1 /* 2 * GPIO driver for AMD 8111 south bridges 3 * 4 * Copyright (c) 2012 Dmitry Eremin-Solenikov 5 * 6 * Based on the AMD RNG driver: 7 * Copyright 2005 (c) MontaVista Software, Inc. 8 * with the majority of the code coming from: 9 * 10 * Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG) 11 * (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com> 12 * 13 * derived from 14 * 15 * Hardware driver for the AMD 768 Random Number Generator (RNG) 16 * (c) Copyright 2001 Red Hat Inc 17 * 18 * derived from 19 * 20 * Hardware driver for Intel i810 Random Number Generator (RNG) 21 * Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com> 22 * Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com> 23 * 24 * This file is licensed under the terms of the GNU General Public 25 * License version 2. This program is licensed "as is" without any 26 * warranty of any kind, whether express or implied. 27 */ 28 #include <linux/module.h> 29 #include <linux/kernel.h> 30 #include <linux/gpio.h> 31 #include <linux/pci.h> 32 #include <linux/spinlock.h> 33 34 #define PMBASE_OFFSET 0xb0 35 #define PMBASE_SIZE 0x30 36 37 #define AMD_REG_GPIO(i) (0x10 + (i)) 38 39 #define AMD_GPIO_LTCH_STS 0x40 /* Latch status, w1 */ 40 #define AMD_GPIO_RTIN 0x20 /* Real Time in, ro */ 41 #define AMD_GPIO_DEBOUNCE 0x10 /* Debounce, rw */ 42 #define AMD_GPIO_MODE_MASK 0x0c /* Pin Mode Select, rw */ 43 #define AMD_GPIO_MODE_IN 0x00 44 #define AMD_GPIO_MODE_OUT 0x04 45 /* Enable alternative (e.g. clkout, IRQ, etc) function of the pin */ 46 #define AMD_GPIO_MODE_ALTFN 0x08 /* Or 0x09 */ 47 #define AMD_GPIO_X_MASK 0x03 /* In/Out specific, rw */ 48 #define AMD_GPIO_X_IN_ACTIVEHI 0x01 /* Active High */ 49 #define AMD_GPIO_X_IN_LATCH 0x02 /* Latched version is selected */ 50 #define AMD_GPIO_X_OUT_LOW 0x00 51 #define AMD_GPIO_X_OUT_HI 0x01 52 #define AMD_GPIO_X_OUT_CLK0 0x02 53 #define AMD_GPIO_X_OUT_CLK1 0x03 54 55 /* 56 * Data for PCI driver interface 57 * 58 * This data only exists for exporting the supported 59 * PCI ids via MODULE_DEVICE_TABLE. We do not actually 60 * register a pci_driver, because someone else might one day 61 * want to register another driver on the same PCI id. 62 */ 63 static const struct pci_device_id pci_tbl[] = { 64 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS), 0 }, 65 { 0, }, /* terminate list */ 66 }; 67 MODULE_DEVICE_TABLE(pci, pci_tbl); 68 69 struct amd_gpio { 70 struct gpio_chip chip; 71 u32 pmbase; 72 void __iomem *pm; 73 struct pci_dev *pdev; 74 spinlock_t lock; /* guards hw registers and orig table */ 75 u8 orig[32]; 76 }; 77 78 static int amd_gpio_request(struct gpio_chip *chip, unsigned offset) 79 { 80 struct amd_gpio *agp = gpiochip_get_data(chip); 81 82 agp->orig[offset] = ioread8(agp->pm + AMD_REG_GPIO(offset)) & 83 (AMD_GPIO_DEBOUNCE | AMD_GPIO_MODE_MASK | AMD_GPIO_X_MASK); 84 85 dev_dbg(&agp->pdev->dev, "Requested gpio %d, data %x\n", offset, agp->orig[offset]); 86 87 return 0; 88 } 89 90 static void amd_gpio_free(struct gpio_chip *chip, unsigned offset) 91 { 92 struct amd_gpio *agp = gpiochip_get_data(chip); 93 94 dev_dbg(&agp->pdev->dev, "Freed gpio %d, data %x\n", offset, agp->orig[offset]); 95 96 iowrite8(agp->orig[offset], agp->pm + AMD_REG_GPIO(offset)); 97 } 98 99 static void amd_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 100 { 101 struct amd_gpio *agp = gpiochip_get_data(chip); 102 u8 temp; 103 unsigned long flags; 104 105 spin_lock_irqsave(&agp->lock, flags); 106 temp = ioread8(agp->pm + AMD_REG_GPIO(offset)); 107 temp = (temp & AMD_GPIO_DEBOUNCE) | AMD_GPIO_MODE_OUT | (value ? AMD_GPIO_X_OUT_HI : AMD_GPIO_X_OUT_LOW); 108 iowrite8(temp, agp->pm + AMD_REG_GPIO(offset)); 109 spin_unlock_irqrestore(&agp->lock, flags); 110 111 dev_dbg(&agp->pdev->dev, "Setting gpio %d, value %d, reg=%02x\n", offset, !!value, temp); 112 } 113 114 static int amd_gpio_get(struct gpio_chip *chip, unsigned offset) 115 { 116 struct amd_gpio *agp = gpiochip_get_data(chip); 117 u8 temp; 118 119 temp = ioread8(agp->pm + AMD_REG_GPIO(offset)); 120 121 dev_dbg(&agp->pdev->dev, "Getting gpio %d, reg=%02x\n", offset, temp); 122 123 return (temp & AMD_GPIO_RTIN) ? 1 : 0; 124 } 125 126 static int amd_gpio_dirout(struct gpio_chip *chip, unsigned offset, int value) 127 { 128 struct amd_gpio *agp = gpiochip_get_data(chip); 129 u8 temp; 130 unsigned long flags; 131 132 spin_lock_irqsave(&agp->lock, flags); 133 temp = ioread8(agp->pm + AMD_REG_GPIO(offset)); 134 temp = (temp & AMD_GPIO_DEBOUNCE) | AMD_GPIO_MODE_OUT | (value ? AMD_GPIO_X_OUT_HI : AMD_GPIO_X_OUT_LOW); 135 iowrite8(temp, agp->pm + AMD_REG_GPIO(offset)); 136 spin_unlock_irqrestore(&agp->lock, flags); 137 138 dev_dbg(&agp->pdev->dev, "Dirout gpio %d, value %d, reg=%02x\n", offset, !!value, temp); 139 140 return 0; 141 } 142 143 static int amd_gpio_dirin(struct gpio_chip *chip, unsigned offset) 144 { 145 struct amd_gpio *agp = gpiochip_get_data(chip); 146 u8 temp; 147 unsigned long flags; 148 149 spin_lock_irqsave(&agp->lock, flags); 150 temp = ioread8(agp->pm + AMD_REG_GPIO(offset)); 151 temp = (temp & AMD_GPIO_DEBOUNCE) | AMD_GPIO_MODE_IN; 152 iowrite8(temp, agp->pm + AMD_REG_GPIO(offset)); 153 spin_unlock_irqrestore(&agp->lock, flags); 154 155 dev_dbg(&agp->pdev->dev, "Dirin gpio %d, reg=%02x\n", offset, temp); 156 157 return 0; 158 } 159 160 static struct amd_gpio gp = { 161 .chip = { 162 .label = "AMD GPIO", 163 .owner = THIS_MODULE, 164 .base = -1, 165 .ngpio = 32, 166 .request = amd_gpio_request, 167 .free = amd_gpio_free, 168 .set = amd_gpio_set, 169 .get = amd_gpio_get, 170 .direction_output = amd_gpio_dirout, 171 .direction_input = amd_gpio_dirin, 172 }, 173 }; 174 175 static int __init amd_gpio_init(void) 176 { 177 int err = -ENODEV; 178 struct pci_dev *pdev = NULL; 179 const struct pci_device_id *ent; 180 181 182 /* We look for our device - AMD South Bridge 183 * I don't know about a system with two such bridges, 184 * so we can assume that there is max. one device. 185 * 186 * We can't use plain pci_driver mechanism, 187 * as the device is really a multiple function device, 188 * main driver that binds to the pci_device is an smbus 189 * driver and have to find & bind to the device this way. 190 */ 191 for_each_pci_dev(pdev) { 192 ent = pci_match_id(pci_tbl, pdev); 193 if (ent) 194 goto found; 195 } 196 /* Device not found. */ 197 goto out; 198 199 found: 200 err = pci_read_config_dword(pdev, 0x58, &gp.pmbase); 201 if (err) 202 goto out; 203 err = -EIO; 204 gp.pmbase &= 0x0000FF00; 205 if (gp.pmbase == 0) 206 goto out; 207 if (!request_region(gp.pmbase + PMBASE_OFFSET, PMBASE_SIZE, "AMD GPIO")) { 208 dev_err(&pdev->dev, "AMD GPIO region 0x%x already in use!\n", 209 gp.pmbase + PMBASE_OFFSET); 210 err = -EBUSY; 211 goto out; 212 } 213 gp.pm = ioport_map(gp.pmbase + PMBASE_OFFSET, PMBASE_SIZE); 214 if (!gp.pm) { 215 dev_err(&pdev->dev, "Couldn't map io port into io memory\n"); 216 release_region(gp.pmbase + PMBASE_OFFSET, PMBASE_SIZE); 217 err = -ENOMEM; 218 goto out; 219 } 220 gp.pdev = pdev; 221 gp.chip.parent = &pdev->dev; 222 223 spin_lock_init(&gp.lock); 224 225 printk(KERN_INFO "AMD-8111 GPIO detected\n"); 226 err = gpiochip_add_data(&gp.chip, &gp); 227 if (err) { 228 printk(KERN_ERR "GPIO registering failed (%d)\n", 229 err); 230 ioport_unmap(gp.pm); 231 release_region(gp.pmbase + PMBASE_OFFSET, PMBASE_SIZE); 232 goto out; 233 } 234 out: 235 return err; 236 } 237 238 static void __exit amd_gpio_exit(void) 239 { 240 gpiochip_remove(&gp.chip); 241 ioport_unmap(gp.pm); 242 release_region(gp.pmbase + PMBASE_OFFSET, PMBASE_SIZE); 243 } 244 245 module_init(amd_gpio_init); 246 module_exit(amd_gpio_exit); 247 248 MODULE_AUTHOR("The Linux Kernel team"); 249 MODULE_DESCRIPTION("GPIO driver for AMD chipsets"); 250 MODULE_LICENSE("GPL"); 251