1 /* 2 * Copyright (C) 2013 Altera Corporation 3 * Based on gpio-mpc8xxx.c 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include <linux/io.h> 20 #include <linux/module.h> 21 #include <linux/gpio/driver.h> 22 #include <linux/of_gpio.h> /* For of_mm_gpio_chip */ 23 #include <linux/platform_device.h> 24 25 #define ALTERA_GPIO_MAX_NGPIO 32 26 #define ALTERA_GPIO_DATA 0x0 27 #define ALTERA_GPIO_DIR 0x4 28 #define ALTERA_GPIO_IRQ_MASK 0x8 29 #define ALTERA_GPIO_EDGE_CAP 0xc 30 31 /** 32 * struct altera_gpio_chip 33 * @mmchip : memory mapped chip structure. 34 * @gpio_lock : synchronization lock so that new irq/set/get requests 35 * will be blocked until the current one completes. 36 * @interrupt_trigger : specifies the hardware configured IRQ trigger type 37 * (rising, falling, both, high) 38 * @mapped_irq : kernel mapped irq number. 39 */ 40 struct altera_gpio_chip { 41 struct of_mm_gpio_chip mmchip; 42 raw_spinlock_t gpio_lock; 43 int interrupt_trigger; 44 int mapped_irq; 45 }; 46 47 static void altera_gpio_irq_unmask(struct irq_data *d) 48 { 49 struct altera_gpio_chip *altera_gc; 50 struct of_mm_gpio_chip *mm_gc; 51 unsigned long flags; 52 u32 intmask; 53 54 altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d)); 55 mm_gc = &altera_gc->mmchip; 56 57 raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags); 58 intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK); 59 /* Set ALTERA_GPIO_IRQ_MASK bit to unmask */ 60 intmask |= BIT(irqd_to_hwirq(d)); 61 writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK); 62 raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags); 63 } 64 65 static void altera_gpio_irq_mask(struct irq_data *d) 66 { 67 struct altera_gpio_chip *altera_gc; 68 struct of_mm_gpio_chip *mm_gc; 69 unsigned long flags; 70 u32 intmask; 71 72 altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d)); 73 mm_gc = &altera_gc->mmchip; 74 75 raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags); 76 intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK); 77 /* Clear ALTERA_GPIO_IRQ_MASK bit to mask */ 78 intmask &= ~BIT(irqd_to_hwirq(d)); 79 writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK); 80 raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags); 81 } 82 83 /** 84 * This controller's IRQ type is synthesized in hardware, so this function 85 * just checks if the requested set_type matches the synthesized IRQ type 86 */ 87 static int altera_gpio_irq_set_type(struct irq_data *d, 88 unsigned int type) 89 { 90 struct altera_gpio_chip *altera_gc; 91 92 altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d)); 93 94 if (type == IRQ_TYPE_NONE) { 95 irq_set_handler_locked(d, handle_bad_irq); 96 return 0; 97 } 98 if (type == altera_gc->interrupt_trigger) { 99 if (type == IRQ_TYPE_LEVEL_HIGH) 100 irq_set_handler_locked(d, handle_level_irq); 101 else 102 irq_set_handler_locked(d, handle_simple_irq); 103 return 0; 104 } 105 irq_set_handler_locked(d, handle_bad_irq); 106 return -EINVAL; 107 } 108 109 static unsigned int altera_gpio_irq_startup(struct irq_data *d) 110 { 111 altera_gpio_irq_unmask(d); 112 113 return 0; 114 } 115 116 static struct irq_chip altera_irq_chip = { 117 .name = "altera-gpio", 118 .irq_mask = altera_gpio_irq_mask, 119 .irq_unmask = altera_gpio_irq_unmask, 120 .irq_set_type = altera_gpio_irq_set_type, 121 .irq_startup = altera_gpio_irq_startup, 122 .irq_shutdown = altera_gpio_irq_mask, 123 }; 124 125 static int altera_gpio_get(struct gpio_chip *gc, unsigned offset) 126 { 127 struct of_mm_gpio_chip *mm_gc; 128 129 mm_gc = to_of_mm_gpio_chip(gc); 130 131 return !!(readl(mm_gc->regs + ALTERA_GPIO_DATA) & BIT(offset)); 132 } 133 134 static void altera_gpio_set(struct gpio_chip *gc, unsigned offset, int value) 135 { 136 struct of_mm_gpio_chip *mm_gc; 137 struct altera_gpio_chip *chip; 138 unsigned long flags; 139 unsigned int data_reg; 140 141 mm_gc = to_of_mm_gpio_chip(gc); 142 chip = gpiochip_get_data(gc); 143 144 raw_spin_lock_irqsave(&chip->gpio_lock, flags); 145 data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA); 146 if (value) 147 data_reg |= BIT(offset); 148 else 149 data_reg &= ~BIT(offset); 150 writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA); 151 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags); 152 } 153 154 static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 155 { 156 struct of_mm_gpio_chip *mm_gc; 157 struct altera_gpio_chip *chip; 158 unsigned long flags; 159 unsigned int gpio_ddr; 160 161 mm_gc = to_of_mm_gpio_chip(gc); 162 chip = gpiochip_get_data(gc); 163 164 raw_spin_lock_irqsave(&chip->gpio_lock, flags); 165 /* Set pin as input, assumes software controlled IP */ 166 gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR); 167 gpio_ddr &= ~BIT(offset); 168 writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR); 169 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags); 170 171 return 0; 172 } 173 174 static int altera_gpio_direction_output(struct gpio_chip *gc, 175 unsigned offset, int value) 176 { 177 struct of_mm_gpio_chip *mm_gc; 178 struct altera_gpio_chip *chip; 179 unsigned long flags; 180 unsigned int data_reg, gpio_ddr; 181 182 mm_gc = to_of_mm_gpio_chip(gc); 183 chip = gpiochip_get_data(gc); 184 185 raw_spin_lock_irqsave(&chip->gpio_lock, flags); 186 /* Sets the GPIO value */ 187 data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA); 188 if (value) 189 data_reg |= BIT(offset); 190 else 191 data_reg &= ~BIT(offset); 192 writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA); 193 194 /* Set pin as output, assumes software controlled IP */ 195 gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR); 196 gpio_ddr |= BIT(offset); 197 writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR); 198 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags); 199 200 return 0; 201 } 202 203 static void altera_gpio_irq_edge_handler(struct irq_desc *desc) 204 { 205 struct altera_gpio_chip *altera_gc; 206 struct irq_chip *chip; 207 struct of_mm_gpio_chip *mm_gc; 208 struct irq_domain *irqdomain; 209 unsigned long status; 210 int i; 211 212 altera_gc = gpiochip_get_data(irq_desc_get_handler_data(desc)); 213 chip = irq_desc_get_chip(desc); 214 mm_gc = &altera_gc->mmchip; 215 irqdomain = altera_gc->mmchip.gc.irq.domain; 216 217 chained_irq_enter(chip, desc); 218 219 while ((status = 220 (readl(mm_gc->regs + ALTERA_GPIO_EDGE_CAP) & 221 readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK)))) { 222 writel(status, mm_gc->regs + ALTERA_GPIO_EDGE_CAP); 223 for_each_set_bit(i, &status, mm_gc->gc.ngpio) { 224 generic_handle_irq(irq_find_mapping(irqdomain, i)); 225 } 226 } 227 228 chained_irq_exit(chip, desc); 229 } 230 231 static void altera_gpio_irq_leveL_high_handler(struct irq_desc *desc) 232 { 233 struct altera_gpio_chip *altera_gc; 234 struct irq_chip *chip; 235 struct of_mm_gpio_chip *mm_gc; 236 struct irq_domain *irqdomain; 237 unsigned long status; 238 int i; 239 240 altera_gc = gpiochip_get_data(irq_desc_get_handler_data(desc)); 241 chip = irq_desc_get_chip(desc); 242 mm_gc = &altera_gc->mmchip; 243 irqdomain = altera_gc->mmchip.gc.irq.domain; 244 245 chained_irq_enter(chip, desc); 246 247 status = readl(mm_gc->regs + ALTERA_GPIO_DATA); 248 status &= readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK); 249 250 for_each_set_bit(i, &status, mm_gc->gc.ngpio) { 251 generic_handle_irq(irq_find_mapping(irqdomain, i)); 252 } 253 chained_irq_exit(chip, desc); 254 } 255 256 static int altera_gpio_probe(struct platform_device *pdev) 257 { 258 struct device_node *node = pdev->dev.of_node; 259 int reg, ret; 260 struct altera_gpio_chip *altera_gc; 261 262 altera_gc = devm_kzalloc(&pdev->dev, sizeof(*altera_gc), GFP_KERNEL); 263 if (!altera_gc) 264 return -ENOMEM; 265 266 raw_spin_lock_init(&altera_gc->gpio_lock); 267 268 if (of_property_read_u32(node, "altr,ngpio", ®)) 269 /* By default assume maximum ngpio */ 270 altera_gc->mmchip.gc.ngpio = ALTERA_GPIO_MAX_NGPIO; 271 else 272 altera_gc->mmchip.gc.ngpio = reg; 273 274 if (altera_gc->mmchip.gc.ngpio > ALTERA_GPIO_MAX_NGPIO) { 275 dev_warn(&pdev->dev, 276 "ngpio is greater than %d, defaulting to %d\n", 277 ALTERA_GPIO_MAX_NGPIO, ALTERA_GPIO_MAX_NGPIO); 278 altera_gc->mmchip.gc.ngpio = ALTERA_GPIO_MAX_NGPIO; 279 } 280 281 altera_gc->mmchip.gc.direction_input = altera_gpio_direction_input; 282 altera_gc->mmchip.gc.direction_output = altera_gpio_direction_output; 283 altera_gc->mmchip.gc.get = altera_gpio_get; 284 altera_gc->mmchip.gc.set = altera_gpio_set; 285 altera_gc->mmchip.gc.owner = THIS_MODULE; 286 altera_gc->mmchip.gc.parent = &pdev->dev; 287 288 ret = of_mm_gpiochip_add_data(node, &altera_gc->mmchip, altera_gc); 289 if (ret) { 290 dev_err(&pdev->dev, "Failed adding memory mapped gpiochip\n"); 291 return ret; 292 } 293 294 platform_set_drvdata(pdev, altera_gc); 295 296 altera_gc->mapped_irq = platform_get_irq(pdev, 0); 297 298 if (altera_gc->mapped_irq < 0) 299 goto skip_irq; 300 301 if (of_property_read_u32(node, "altr,interrupt-type", ®)) { 302 ret = -EINVAL; 303 dev_err(&pdev->dev, 304 "altr,interrupt-type value not set in device tree\n"); 305 goto teardown; 306 } 307 altera_gc->interrupt_trigger = reg; 308 309 ret = gpiochip_irqchip_add(&altera_gc->mmchip.gc, &altera_irq_chip, 0, 310 handle_bad_irq, IRQ_TYPE_NONE); 311 312 if (ret) { 313 dev_err(&pdev->dev, "could not add irqchip\n"); 314 goto teardown; 315 } 316 317 gpiochip_set_chained_irqchip(&altera_gc->mmchip.gc, 318 &altera_irq_chip, 319 altera_gc->mapped_irq, 320 altera_gc->interrupt_trigger == IRQ_TYPE_LEVEL_HIGH ? 321 altera_gpio_irq_leveL_high_handler : 322 altera_gpio_irq_edge_handler); 323 324 skip_irq: 325 return 0; 326 teardown: 327 of_mm_gpiochip_remove(&altera_gc->mmchip); 328 pr_err("%pOF: registration failed with status %d\n", 329 node, ret); 330 331 return ret; 332 } 333 334 static int altera_gpio_remove(struct platform_device *pdev) 335 { 336 struct altera_gpio_chip *altera_gc = platform_get_drvdata(pdev); 337 338 of_mm_gpiochip_remove(&altera_gc->mmchip); 339 340 return 0; 341 } 342 343 static const struct of_device_id altera_gpio_of_match[] = { 344 { .compatible = "altr,pio-1.0", }, 345 {}, 346 }; 347 MODULE_DEVICE_TABLE(of, altera_gpio_of_match); 348 349 static struct platform_driver altera_gpio_driver = { 350 .driver = { 351 .name = "altera_gpio", 352 .of_match_table = of_match_ptr(altera_gpio_of_match), 353 }, 354 .probe = altera_gpio_probe, 355 .remove = altera_gpio_remove, 356 }; 357 358 static int __init altera_gpio_init(void) 359 { 360 return platform_driver_register(&altera_gpio_driver); 361 } 362 subsys_initcall(altera_gpio_init); 363 364 static void __exit altera_gpio_exit(void) 365 { 366 platform_driver_unregister(&altera_gpio_driver); 367 } 368 module_exit(altera_gpio_exit); 369 370 MODULE_AUTHOR("Tien Hock Loh <thloh@altera.com>"); 371 MODULE_DESCRIPTION("Altera GPIO driver"); 372 MODULE_LICENSE("GPL"); 373