1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIO driver for the ACCES 104-DIO-48E series 4 * Copyright (C) 2016 William Breathitt Gray 5 * 6 * This driver supports the following ACCES devices: 104-DIO-48E and 7 * 104-DIO-24E. 8 */ 9 #include <linux/bits.h> 10 #include <linux/device.h> 11 #include <linux/err.h> 12 #include <linux/ioport.h> 13 #include <linux/irq.h> 14 #include <linux/isa.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/moduleparam.h> 18 #include <linux/regmap.h> 19 #include <linux/types.h> 20 21 #include "gpio-i8255.h" 22 23 MODULE_IMPORT_NS(I8255); 24 25 #define DIO48E_EXTENT 16 26 #define MAX_NUM_DIO48E max_num_isa_dev(DIO48E_EXTENT) 27 28 static unsigned int base[MAX_NUM_DIO48E]; 29 static unsigned int num_dio48e; 30 module_param_hw_array(base, uint, ioport, &num_dio48e, 0); 31 MODULE_PARM_DESC(base, "ACCES 104-DIO-48E base addresses"); 32 33 static unsigned int irq[MAX_NUM_DIO48E]; 34 static unsigned int num_irq; 35 module_param_hw_array(irq, uint, irq, &num_irq, 0); 36 MODULE_PARM_DESC(irq, "ACCES 104-DIO-48E interrupt line numbers"); 37 38 #define DIO48E_ENABLE_INTERRUPT 0xB 39 #define DIO48E_DISABLE_INTERRUPT DIO48E_ENABLE_INTERRUPT 40 #define DIO48E_CLEAR_INTERRUPT 0xF 41 42 #define DIO48E_NUM_PPI 2 43 44 static const struct regmap_range dio48e_wr_ranges[] = { 45 regmap_reg_range(0x0, 0x9), regmap_reg_range(0xB, 0xB), 46 regmap_reg_range(0xD, 0xD), regmap_reg_range(0xF, 0xF), 47 }; 48 static const struct regmap_range dio48e_rd_ranges[] = { 49 regmap_reg_range(0x0, 0x2), regmap_reg_range(0x4, 0x6), 50 regmap_reg_range(0xB, 0xB), regmap_reg_range(0xD, 0xD), 51 regmap_reg_range(0xF, 0xF), 52 }; 53 static const struct regmap_range dio48e_volatile_ranges[] = { 54 i8255_volatile_regmap_range(0x0), i8255_volatile_regmap_range(0x4), 55 regmap_reg_range(0xB, 0xB), regmap_reg_range(0xD, 0xD), 56 regmap_reg_range(0xF, 0xF), 57 }; 58 static const struct regmap_range dio48e_precious_ranges[] = { 59 regmap_reg_range(0xB, 0xB), regmap_reg_range(0xD, 0xD), 60 regmap_reg_range(0xF, 0xF), 61 }; 62 static const struct regmap_access_table dio48e_wr_table = { 63 .yes_ranges = dio48e_wr_ranges, 64 .n_yes_ranges = ARRAY_SIZE(dio48e_wr_ranges), 65 }; 66 static const struct regmap_access_table dio48e_rd_table = { 67 .yes_ranges = dio48e_rd_ranges, 68 .n_yes_ranges = ARRAY_SIZE(dio48e_rd_ranges), 69 }; 70 static const struct regmap_access_table dio48e_volatile_table = { 71 .yes_ranges = dio48e_volatile_ranges, 72 .n_yes_ranges = ARRAY_SIZE(dio48e_volatile_ranges), 73 }; 74 static const struct regmap_access_table dio48e_precious_table = { 75 .yes_ranges = dio48e_precious_ranges, 76 .n_yes_ranges = ARRAY_SIZE(dio48e_precious_ranges), 77 }; 78 static const struct regmap_config dio48e_regmap_config = { 79 .reg_bits = 8, 80 .reg_stride = 1, 81 .val_bits = 8, 82 .io_port = true, 83 .max_register = 0xF, 84 .wr_table = &dio48e_wr_table, 85 .rd_table = &dio48e_rd_table, 86 .volatile_table = &dio48e_volatile_table, 87 .precious_table = &dio48e_precious_table, 88 .cache_type = REGCACHE_FLAT, 89 .use_raw_spinlock = true, 90 }; 91 92 /* only bit 3 on each respective Port C supports interrupts */ 93 #define DIO48E_REGMAP_IRQ(_ppi) \ 94 [19 + (_ppi) * 24] = { \ 95 .mask = BIT(_ppi), \ 96 .type = { .types_supported = IRQ_TYPE_EDGE_RISING }, \ 97 } 98 99 static const struct regmap_irq dio48e_regmap_irqs[] = { 100 DIO48E_REGMAP_IRQ(0), DIO48E_REGMAP_IRQ(1), 101 }; 102 103 static int dio48e_handle_mask_sync(struct regmap *const map, const int index, 104 const unsigned int mask_buf_def, 105 const unsigned int mask_buf, 106 void *const irq_drv_data) 107 { 108 unsigned int *const irq_mask = irq_drv_data; 109 const unsigned int prev_mask = *irq_mask; 110 const unsigned int all_masked = GENMASK(1, 0); 111 int err; 112 unsigned int val; 113 114 /* exit early if no change since the previous mask */ 115 if (mask_buf == prev_mask) 116 return 0; 117 118 /* remember the current mask for the next mask sync */ 119 *irq_mask = mask_buf; 120 121 /* if all previously masked, enable interrupts when unmasking */ 122 if (prev_mask == all_masked) { 123 err = regmap_write(map, DIO48E_CLEAR_INTERRUPT, 0x00); 124 if (err) 125 return err; 126 return regmap_write(map, DIO48E_ENABLE_INTERRUPT, 0x00); 127 } 128 129 /* if all are currently masked, disable interrupts */ 130 if (mask_buf == all_masked) 131 return regmap_read(map, DIO48E_DISABLE_INTERRUPT, &val); 132 133 return 0; 134 } 135 136 #define DIO48E_NGPIO 48 137 static const char *dio48e_names[DIO48E_NGPIO] = { 138 "PPI Group 0 Port A 0", "PPI Group 0 Port A 1", "PPI Group 0 Port A 2", 139 "PPI Group 0 Port A 3", "PPI Group 0 Port A 4", "PPI Group 0 Port A 5", 140 "PPI Group 0 Port A 6", "PPI Group 0 Port A 7", "PPI Group 0 Port B 0", 141 "PPI Group 0 Port B 1", "PPI Group 0 Port B 2", "PPI Group 0 Port B 3", 142 "PPI Group 0 Port B 4", "PPI Group 0 Port B 5", "PPI Group 0 Port B 6", 143 "PPI Group 0 Port B 7", "PPI Group 0 Port C 0", "PPI Group 0 Port C 1", 144 "PPI Group 0 Port C 2", "PPI Group 0 Port C 3", "PPI Group 0 Port C 4", 145 "PPI Group 0 Port C 5", "PPI Group 0 Port C 6", "PPI Group 0 Port C 7", 146 "PPI Group 1 Port A 0", "PPI Group 1 Port A 1", "PPI Group 1 Port A 2", 147 "PPI Group 1 Port A 3", "PPI Group 1 Port A 4", "PPI Group 1 Port A 5", 148 "PPI Group 1 Port A 6", "PPI Group 1 Port A 7", "PPI Group 1 Port B 0", 149 "PPI Group 1 Port B 1", "PPI Group 1 Port B 2", "PPI Group 1 Port B 3", 150 "PPI Group 1 Port B 4", "PPI Group 1 Port B 5", "PPI Group 1 Port B 6", 151 "PPI Group 1 Port B 7", "PPI Group 1 Port C 0", "PPI Group 1 Port C 1", 152 "PPI Group 1 Port C 2", "PPI Group 1 Port C 3", "PPI Group 1 Port C 4", 153 "PPI Group 1 Port C 5", "PPI Group 1 Port C 6", "PPI Group 1 Port C 7" 154 }; 155 156 static int dio48e_irq_init_hw(struct regmap *const map) 157 { 158 unsigned int val; 159 160 /* Disable IRQ by default */ 161 return regmap_read(map, DIO48E_DISABLE_INTERRUPT, &val); 162 } 163 164 static int dio48e_probe(struct device *dev, unsigned int id) 165 { 166 const char *const name = dev_name(dev); 167 struct i8255_regmap_config config = {}; 168 void __iomem *regs; 169 struct regmap *map; 170 int err; 171 struct regmap_irq_chip *chip; 172 unsigned int irq_mask; 173 struct regmap_irq_chip_data *chip_data; 174 175 if (!devm_request_region(dev, base[id], DIO48E_EXTENT, name)) { 176 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n", 177 base[id], base[id] + DIO48E_EXTENT); 178 return -EBUSY; 179 } 180 181 regs = devm_ioport_map(dev, base[id], DIO48E_EXTENT); 182 if (!regs) 183 return -ENOMEM; 184 185 map = devm_regmap_init_mmio(dev, regs, &dio48e_regmap_config); 186 if (IS_ERR(map)) 187 return dev_err_probe(dev, PTR_ERR(map), 188 "Unable to initialize register map\n"); 189 190 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 191 if (!chip) 192 return -ENOMEM; 193 194 chip->irq_drv_data = devm_kzalloc(dev, sizeof(irq_mask), GFP_KERNEL); 195 if (!chip->irq_drv_data) 196 return -ENOMEM; 197 198 chip->name = name; 199 /* No IRQ status register so use CLEAR_INTERRUPT register instead */ 200 chip->status_base = DIO48E_CLEAR_INTERRUPT; 201 chip->mask_base = DIO48E_ENABLE_INTERRUPT; 202 chip->ack_base = DIO48E_CLEAR_INTERRUPT; 203 /* CLEAR_INTERRUPT doubles as status register so we need it cleared */ 204 chip->clear_ack = true; 205 chip->status_invert = true; 206 chip->num_regs = 1; 207 chip->irqs = dio48e_regmap_irqs; 208 chip->num_irqs = ARRAY_SIZE(dio48e_regmap_irqs); 209 chip->handle_mask_sync = dio48e_handle_mask_sync; 210 211 /* Initialize to prevent spurious interrupts before we're ready */ 212 err = dio48e_irq_init_hw(map); 213 if (err) 214 return err; 215 216 err = devm_regmap_add_irq_chip(dev, map, irq[id], 0, 0, chip, &chip_data); 217 if (err) 218 return dev_err_probe(dev, err, "IRQ registration failed\n"); 219 220 config.parent = dev; 221 config.map = map; 222 config.num_ppi = DIO48E_NUM_PPI; 223 config.names = dio48e_names; 224 config.domain = regmap_irq_get_domain(chip_data); 225 226 return devm_i8255_regmap_register(dev, &config); 227 } 228 229 static struct isa_driver dio48e_driver = { 230 .probe = dio48e_probe, 231 .driver = { 232 .name = "104-dio-48e" 233 }, 234 }; 235 module_isa_driver_with_irq(dio48e_driver, num_dio48e, num_irq); 236 237 MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>"); 238 MODULE_DESCRIPTION("ACCES 104-DIO-48E GPIO driver"); 239 MODULE_LICENSE("GPL v2"); 240