1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIO driver for the ACCES 104-DIO-48E series 4 * Copyright (C) 2016 William Breathitt Gray 5 * 6 * This driver supports the following ACCES devices: 104-DIO-48E and 7 * 104-DIO-24E. 8 */ 9 #include <linux/bits.h> 10 #include <linux/device.h> 11 #include <linux/errno.h> 12 #include <linux/gpio/driver.h> 13 #include <linux/io.h> 14 #include <linux/ioport.h> 15 #include <linux/interrupt.h> 16 #include <linux/irqdesc.h> 17 #include <linux/isa.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/moduleparam.h> 21 #include <linux/spinlock.h> 22 #include <linux/types.h> 23 24 #include "gpio-i8255.h" 25 26 MODULE_IMPORT_NS(I8255); 27 28 #define DIO48E_EXTENT 16 29 #define MAX_NUM_DIO48E max_num_isa_dev(DIO48E_EXTENT) 30 31 static unsigned int base[MAX_NUM_DIO48E]; 32 static unsigned int num_dio48e; 33 module_param_hw_array(base, uint, ioport, &num_dio48e, 0); 34 MODULE_PARM_DESC(base, "ACCES 104-DIO-48E base addresses"); 35 36 static unsigned int irq[MAX_NUM_DIO48E]; 37 module_param_hw_array(irq, uint, irq, NULL, 0); 38 MODULE_PARM_DESC(irq, "ACCES 104-DIO-48E interrupt line numbers"); 39 40 #define DIO48E_NUM_PPI 2 41 42 /** 43 * struct dio48e_reg - device register structure 44 * @ppi: Programmable Peripheral Interface groups 45 * @enable_buffer: Enable/Disable Buffer groups 46 * @unused1: Unused 47 * @enable_interrupt: Write: Enable Interrupt 48 * Read: Disable Interrupt 49 * @unused2: Unused 50 * @enable_counter: Write: Enable Counter/Timer Addressing 51 * Read: Disable Counter/Timer Addressing 52 * @unused3: Unused 53 * @clear_interrupt: Clear Interrupt 54 */ 55 struct dio48e_reg { 56 struct i8255 ppi[DIO48E_NUM_PPI]; 57 u8 enable_buffer[DIO48E_NUM_PPI]; 58 u8 unused1; 59 u8 enable_interrupt; 60 u8 unused2; 61 u8 enable_counter; 62 u8 unused3; 63 u8 clear_interrupt; 64 }; 65 66 /** 67 * struct dio48e_gpio - GPIO device private data structure 68 * @chip: instance of the gpio_chip 69 * @ppi_state: PPI device states 70 * @lock: synchronization lock to prevent I/O race conditions 71 * @reg: I/O address offset for the device registers 72 * @irq_mask: I/O bits affected by interrupts 73 */ 74 struct dio48e_gpio { 75 struct gpio_chip chip; 76 struct i8255_state ppi_state[DIO48E_NUM_PPI]; 77 raw_spinlock_t lock; 78 struct dio48e_reg __iomem *reg; 79 unsigned char irq_mask; 80 }; 81 82 static int dio48e_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 83 { 84 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); 85 86 if (i8255_get_direction(dio48egpio->ppi_state, offset)) 87 return GPIO_LINE_DIRECTION_IN; 88 89 return GPIO_LINE_DIRECTION_OUT; 90 } 91 92 static int dio48e_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 93 { 94 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); 95 96 i8255_direction_input(dio48egpio->reg->ppi, dio48egpio->ppi_state, 97 offset); 98 99 return 0; 100 } 101 102 static int dio48e_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, 103 int value) 104 { 105 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); 106 107 i8255_direction_output(dio48egpio->reg->ppi, dio48egpio->ppi_state, 108 offset, value); 109 110 return 0; 111 } 112 113 static int dio48e_gpio_get(struct gpio_chip *chip, unsigned int offset) 114 { 115 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); 116 117 return i8255_get(dio48egpio->reg->ppi, offset); 118 } 119 120 static int dio48e_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, 121 unsigned long *bits) 122 { 123 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); 124 125 i8255_get_multiple(dio48egpio->reg->ppi, mask, bits, chip->ngpio); 126 127 return 0; 128 } 129 130 static void dio48e_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 131 { 132 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); 133 134 i8255_set(dio48egpio->reg->ppi, dio48egpio->ppi_state, offset, value); 135 } 136 137 static void dio48e_gpio_set_multiple(struct gpio_chip *chip, 138 unsigned long *mask, unsigned long *bits) 139 { 140 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); 141 142 i8255_set_multiple(dio48egpio->reg->ppi, dio48egpio->ppi_state, mask, 143 bits, chip->ngpio); 144 } 145 146 static void dio48e_irq_ack(struct irq_data *data) 147 { 148 } 149 150 static void dio48e_irq_mask(struct irq_data *data) 151 { 152 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 153 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); 154 const unsigned long offset = irqd_to_hwirq(data); 155 unsigned long flags; 156 157 /* only bit 3 on each respective Port C supports interrupts */ 158 if (offset != 19 && offset != 43) 159 return; 160 161 raw_spin_lock_irqsave(&dio48egpio->lock, flags); 162 163 if (offset == 19) 164 dio48egpio->irq_mask &= ~BIT(0); 165 else 166 dio48egpio->irq_mask &= ~BIT(1); 167 168 if (!dio48egpio->irq_mask) 169 /* disable interrupts */ 170 ioread8(&dio48egpio->reg->enable_interrupt); 171 172 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); 173 } 174 175 static void dio48e_irq_unmask(struct irq_data *data) 176 { 177 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 178 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); 179 const unsigned long offset = irqd_to_hwirq(data); 180 unsigned long flags; 181 182 /* only bit 3 on each respective Port C supports interrupts */ 183 if (offset != 19 && offset != 43) 184 return; 185 186 raw_spin_lock_irqsave(&dio48egpio->lock, flags); 187 188 if (!dio48egpio->irq_mask) { 189 /* enable interrupts */ 190 iowrite8(0x00, &dio48egpio->reg->clear_interrupt); 191 iowrite8(0x00, &dio48egpio->reg->enable_interrupt); 192 } 193 194 if (offset == 19) 195 dio48egpio->irq_mask |= BIT(0); 196 else 197 dio48egpio->irq_mask |= BIT(1); 198 199 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); 200 } 201 202 static int dio48e_irq_set_type(struct irq_data *data, unsigned int flow_type) 203 { 204 const unsigned long offset = irqd_to_hwirq(data); 205 206 /* only bit 3 on each respective Port C supports interrupts */ 207 if (offset != 19 && offset != 43) 208 return -EINVAL; 209 210 if (flow_type != IRQ_TYPE_NONE && flow_type != IRQ_TYPE_EDGE_RISING) 211 return -EINVAL; 212 213 return 0; 214 } 215 216 static struct irq_chip dio48e_irqchip = { 217 .name = "104-dio-48e", 218 .irq_ack = dio48e_irq_ack, 219 .irq_mask = dio48e_irq_mask, 220 .irq_unmask = dio48e_irq_unmask, 221 .irq_set_type = dio48e_irq_set_type 222 }; 223 224 static irqreturn_t dio48e_irq_handler(int irq, void *dev_id) 225 { 226 struct dio48e_gpio *const dio48egpio = dev_id; 227 struct gpio_chip *const chip = &dio48egpio->chip; 228 const unsigned long irq_mask = dio48egpio->irq_mask; 229 unsigned long gpio; 230 231 for_each_set_bit(gpio, &irq_mask, 2) 232 generic_handle_domain_irq(chip->irq.domain, 233 19 + gpio*24); 234 235 raw_spin_lock(&dio48egpio->lock); 236 237 iowrite8(0x00, &dio48egpio->reg->clear_interrupt); 238 239 raw_spin_unlock(&dio48egpio->lock); 240 241 return IRQ_HANDLED; 242 } 243 244 #define DIO48E_NGPIO 48 245 static const char *dio48e_names[DIO48E_NGPIO] = { 246 "PPI Group 0 Port A 0", "PPI Group 0 Port A 1", "PPI Group 0 Port A 2", 247 "PPI Group 0 Port A 3", "PPI Group 0 Port A 4", "PPI Group 0 Port A 5", 248 "PPI Group 0 Port A 6", "PPI Group 0 Port A 7", "PPI Group 0 Port B 0", 249 "PPI Group 0 Port B 1", "PPI Group 0 Port B 2", "PPI Group 0 Port B 3", 250 "PPI Group 0 Port B 4", "PPI Group 0 Port B 5", "PPI Group 0 Port B 6", 251 "PPI Group 0 Port B 7", "PPI Group 0 Port C 0", "PPI Group 0 Port C 1", 252 "PPI Group 0 Port C 2", "PPI Group 0 Port C 3", "PPI Group 0 Port C 4", 253 "PPI Group 0 Port C 5", "PPI Group 0 Port C 6", "PPI Group 0 Port C 7", 254 "PPI Group 1 Port A 0", "PPI Group 1 Port A 1", "PPI Group 1 Port A 2", 255 "PPI Group 1 Port A 3", "PPI Group 1 Port A 4", "PPI Group 1 Port A 5", 256 "PPI Group 1 Port A 6", "PPI Group 1 Port A 7", "PPI Group 1 Port B 0", 257 "PPI Group 1 Port B 1", "PPI Group 1 Port B 2", "PPI Group 1 Port B 3", 258 "PPI Group 1 Port B 4", "PPI Group 1 Port B 5", "PPI Group 1 Port B 6", 259 "PPI Group 1 Port B 7", "PPI Group 1 Port C 0", "PPI Group 1 Port C 1", 260 "PPI Group 1 Port C 2", "PPI Group 1 Port C 3", "PPI Group 1 Port C 4", 261 "PPI Group 1 Port C 5", "PPI Group 1 Port C 6", "PPI Group 1 Port C 7" 262 }; 263 264 static int dio48e_irq_init_hw(struct gpio_chip *gc) 265 { 266 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(gc); 267 268 /* Disable IRQ by default */ 269 ioread8(&dio48egpio->reg->enable_interrupt); 270 271 return 0; 272 } 273 274 static void dio48e_init_ppi(struct i8255 __iomem *const ppi, 275 struct i8255_state *const ppi_state) 276 { 277 const unsigned long ngpio = 24; 278 const unsigned long mask = GENMASK(ngpio - 1, 0); 279 const unsigned long bits = 0; 280 unsigned long i; 281 282 /* Initialize all GPIO to output 0 */ 283 for (i = 0; i < DIO48E_NUM_PPI; i++) { 284 i8255_mode0_output(&ppi[i]); 285 i8255_set_multiple(&ppi[i], &ppi_state[i], &mask, &bits, ngpio); 286 } 287 } 288 289 static int dio48e_probe(struct device *dev, unsigned int id) 290 { 291 struct dio48e_gpio *dio48egpio; 292 const char *const name = dev_name(dev); 293 struct gpio_irq_chip *girq; 294 int err; 295 296 dio48egpio = devm_kzalloc(dev, sizeof(*dio48egpio), GFP_KERNEL); 297 if (!dio48egpio) 298 return -ENOMEM; 299 300 if (!devm_request_region(dev, base[id], DIO48E_EXTENT, name)) { 301 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n", 302 base[id], base[id] + DIO48E_EXTENT); 303 return -EBUSY; 304 } 305 306 dio48egpio->reg = devm_ioport_map(dev, base[id], DIO48E_EXTENT); 307 if (!dio48egpio->reg) 308 return -ENOMEM; 309 310 dio48egpio->chip.label = name; 311 dio48egpio->chip.parent = dev; 312 dio48egpio->chip.owner = THIS_MODULE; 313 dio48egpio->chip.base = -1; 314 dio48egpio->chip.ngpio = DIO48E_NGPIO; 315 dio48egpio->chip.names = dio48e_names; 316 dio48egpio->chip.get_direction = dio48e_gpio_get_direction; 317 dio48egpio->chip.direction_input = dio48e_gpio_direction_input; 318 dio48egpio->chip.direction_output = dio48e_gpio_direction_output; 319 dio48egpio->chip.get = dio48e_gpio_get; 320 dio48egpio->chip.get_multiple = dio48e_gpio_get_multiple; 321 dio48egpio->chip.set = dio48e_gpio_set; 322 dio48egpio->chip.set_multiple = dio48e_gpio_set_multiple; 323 324 girq = &dio48egpio->chip.irq; 325 girq->chip = &dio48e_irqchip; 326 /* This will let us handle the parent IRQ in the driver */ 327 girq->parent_handler = NULL; 328 girq->num_parents = 0; 329 girq->parents = NULL; 330 girq->default_type = IRQ_TYPE_NONE; 331 girq->handler = handle_edge_irq; 332 girq->init_hw = dio48e_irq_init_hw; 333 334 raw_spin_lock_init(&dio48egpio->lock); 335 336 i8255_state_init(dio48egpio->ppi_state, DIO48E_NUM_PPI); 337 dio48e_init_ppi(dio48egpio->reg->ppi, dio48egpio->ppi_state); 338 339 err = devm_gpiochip_add_data(dev, &dio48egpio->chip, dio48egpio); 340 if (err) { 341 dev_err(dev, "GPIO registering failed (%d)\n", err); 342 return err; 343 } 344 345 err = devm_request_irq(dev, irq[id], dio48e_irq_handler, 0, name, 346 dio48egpio); 347 if (err) { 348 dev_err(dev, "IRQ handler registering failed (%d)\n", err); 349 return err; 350 } 351 352 return 0; 353 } 354 355 static struct isa_driver dio48e_driver = { 356 .probe = dio48e_probe, 357 .driver = { 358 .name = "104-dio-48e" 359 }, 360 }; 361 module_isa_driver(dio48e_driver, num_dio48e); 362 363 MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>"); 364 MODULE_DESCRIPTION("ACCES 104-DIO-48E GPIO driver"); 365 MODULE_LICENSE("GPL v2"); 366