1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIO driver for the ACCES 104-DIO-48E series 4 * Copyright (C) 2016 William Breathitt Gray 5 * 6 * This driver supports the following ACCES devices: 104-DIO-48E and 7 * 104-DIO-24E. 8 */ 9 #include <linux/bitmap.h> 10 #include <linux/bitops.h> 11 #include <linux/device.h> 12 #include <linux/errno.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/io.h> 15 #include <linux/ioport.h> 16 #include <linux/interrupt.h> 17 #include <linux/irqdesc.h> 18 #include <linux/isa.h> 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/moduleparam.h> 22 #include <linux/spinlock.h> 23 24 #define DIO48E_EXTENT 16 25 #define MAX_NUM_DIO48E max_num_isa_dev(DIO48E_EXTENT) 26 27 static unsigned int base[MAX_NUM_DIO48E]; 28 static unsigned int num_dio48e; 29 module_param_hw_array(base, uint, ioport, &num_dio48e, 0); 30 MODULE_PARM_DESC(base, "ACCES 104-DIO-48E base addresses"); 31 32 static unsigned int irq[MAX_NUM_DIO48E]; 33 module_param_hw_array(irq, uint, irq, NULL, 0); 34 MODULE_PARM_DESC(irq, "ACCES 104-DIO-48E interrupt line numbers"); 35 36 /** 37 * struct dio48e_gpio - GPIO device private data structure 38 * @chip: instance of the gpio_chip 39 * @io_state: bit I/O state (whether bit is set to input or output) 40 * @out_state: output bits state 41 * @control: Control registers state 42 * @lock: synchronization lock to prevent I/O race conditions 43 * @base: base port address of the GPIO device 44 * @irq_mask: I/O bits affected by interrupts 45 */ 46 struct dio48e_gpio { 47 struct gpio_chip chip; 48 unsigned char io_state[6]; 49 unsigned char out_state[6]; 50 unsigned char control[2]; 51 raw_spinlock_t lock; 52 unsigned base; 53 unsigned char irq_mask; 54 }; 55 56 static int dio48e_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 57 { 58 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); 59 const unsigned port = offset / 8; 60 const unsigned mask = BIT(offset % 8); 61 62 if (dio48egpio->io_state[port] & mask) 63 return GPIO_LINE_DIRECTION_IN; 64 65 return GPIO_LINE_DIRECTION_OUT; 66 } 67 68 static int dio48e_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 69 { 70 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); 71 const unsigned io_port = offset / 8; 72 const unsigned int control_port = io_port / 3; 73 const unsigned control_addr = dio48egpio->base + 3 + control_port*4; 74 unsigned long flags; 75 unsigned control; 76 77 raw_spin_lock_irqsave(&dio48egpio->lock, flags); 78 79 /* Check if configuring Port C */ 80 if (io_port == 2 || io_port == 5) { 81 /* Port C can be configured by nibble */ 82 if (offset % 8 > 3) { 83 dio48egpio->io_state[io_port] |= 0xF0; 84 dio48egpio->control[control_port] |= BIT(3); 85 } else { 86 dio48egpio->io_state[io_port] |= 0x0F; 87 dio48egpio->control[control_port] |= BIT(0); 88 } 89 } else { 90 dio48egpio->io_state[io_port] |= 0xFF; 91 if (io_port == 0 || io_port == 3) 92 dio48egpio->control[control_port] |= BIT(4); 93 else 94 dio48egpio->control[control_port] |= BIT(1); 95 } 96 97 control = BIT(7) | dio48egpio->control[control_port]; 98 outb(control, control_addr); 99 control &= ~BIT(7); 100 outb(control, control_addr); 101 102 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); 103 104 return 0; 105 } 106 107 static int dio48e_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 108 int value) 109 { 110 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); 111 const unsigned io_port = offset / 8; 112 const unsigned int control_port = io_port / 3; 113 const unsigned mask = BIT(offset % 8); 114 const unsigned control_addr = dio48egpio->base + 3 + control_port*4; 115 const unsigned out_port = (io_port > 2) ? io_port + 1 : io_port; 116 unsigned long flags; 117 unsigned control; 118 119 raw_spin_lock_irqsave(&dio48egpio->lock, flags); 120 121 /* Check if configuring Port C */ 122 if (io_port == 2 || io_port == 5) { 123 /* Port C can be configured by nibble */ 124 if (offset % 8 > 3) { 125 dio48egpio->io_state[io_port] &= 0x0F; 126 dio48egpio->control[control_port] &= ~BIT(3); 127 } else { 128 dio48egpio->io_state[io_port] &= 0xF0; 129 dio48egpio->control[control_port] &= ~BIT(0); 130 } 131 } else { 132 dio48egpio->io_state[io_port] &= 0x00; 133 if (io_port == 0 || io_port == 3) 134 dio48egpio->control[control_port] &= ~BIT(4); 135 else 136 dio48egpio->control[control_port] &= ~BIT(1); 137 } 138 139 if (value) 140 dio48egpio->out_state[io_port] |= mask; 141 else 142 dio48egpio->out_state[io_port] &= ~mask; 143 144 control = BIT(7) | dio48egpio->control[control_port]; 145 outb(control, control_addr); 146 147 outb(dio48egpio->out_state[io_port], dio48egpio->base + out_port); 148 149 control &= ~BIT(7); 150 outb(control, control_addr); 151 152 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); 153 154 return 0; 155 } 156 157 static int dio48e_gpio_get(struct gpio_chip *chip, unsigned offset) 158 { 159 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); 160 const unsigned port = offset / 8; 161 const unsigned mask = BIT(offset % 8); 162 const unsigned in_port = (port > 2) ? port + 1 : port; 163 unsigned long flags; 164 unsigned port_state; 165 166 raw_spin_lock_irqsave(&dio48egpio->lock, flags); 167 168 /* ensure that GPIO is set for input */ 169 if (!(dio48egpio->io_state[port] & mask)) { 170 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); 171 return -EINVAL; 172 } 173 174 port_state = inb(dio48egpio->base + in_port); 175 176 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); 177 178 return !!(port_state & mask); 179 } 180 181 static int dio48e_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, 182 unsigned long *bits) 183 { 184 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); 185 size_t i; 186 static const size_t ports[] = { 0, 1, 2, 4, 5, 6 }; 187 const unsigned int gpio_reg_size = 8; 188 unsigned int bits_offset; 189 size_t word_index; 190 unsigned int word_offset; 191 unsigned long word_mask; 192 const unsigned long port_mask = GENMASK(gpio_reg_size - 1, 0); 193 unsigned long port_state; 194 195 /* clear bits array to a clean slate */ 196 bitmap_zero(bits, chip->ngpio); 197 198 /* get bits are evaluated a gpio port register at a time */ 199 for (i = 0; i < ARRAY_SIZE(ports); i++) { 200 /* gpio offset in bits array */ 201 bits_offset = i * gpio_reg_size; 202 203 /* word index for bits array */ 204 word_index = BIT_WORD(bits_offset); 205 206 /* gpio offset within current word of bits array */ 207 word_offset = bits_offset % BITS_PER_LONG; 208 209 /* mask of get bits for current gpio within current word */ 210 word_mask = mask[word_index] & (port_mask << word_offset); 211 if (!word_mask) { 212 /* no get bits in this port so skip to next one */ 213 continue; 214 } 215 216 /* read bits from current gpio port */ 217 port_state = inb(dio48egpio->base + ports[i]); 218 219 /* store acquired bits at respective bits array offset */ 220 bits[word_index] |= (port_state << word_offset) & word_mask; 221 } 222 223 return 0; 224 } 225 226 static void dio48e_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 227 { 228 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); 229 const unsigned port = offset / 8; 230 const unsigned mask = BIT(offset % 8); 231 const unsigned out_port = (port > 2) ? port + 1 : port; 232 unsigned long flags; 233 234 raw_spin_lock_irqsave(&dio48egpio->lock, flags); 235 236 if (value) 237 dio48egpio->out_state[port] |= mask; 238 else 239 dio48egpio->out_state[port] &= ~mask; 240 241 outb(dio48egpio->out_state[port], dio48egpio->base + out_port); 242 243 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); 244 } 245 246 static void dio48e_gpio_set_multiple(struct gpio_chip *chip, 247 unsigned long *mask, unsigned long *bits) 248 { 249 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); 250 unsigned int i; 251 const unsigned int gpio_reg_size = 8; 252 unsigned int port; 253 unsigned int out_port; 254 unsigned int bitmask; 255 unsigned long flags; 256 257 /* set bits are evaluated a gpio register size at a time */ 258 for (i = 0; i < chip->ngpio; i += gpio_reg_size) { 259 /* no more set bits in this mask word; skip to the next word */ 260 if (!mask[BIT_WORD(i)]) { 261 i = (BIT_WORD(i) + 1) * BITS_PER_LONG - gpio_reg_size; 262 continue; 263 } 264 265 port = i / gpio_reg_size; 266 out_port = (port > 2) ? port + 1 : port; 267 bitmask = mask[BIT_WORD(i)] & bits[BIT_WORD(i)]; 268 269 raw_spin_lock_irqsave(&dio48egpio->lock, flags); 270 271 /* update output state data and set device gpio register */ 272 dio48egpio->out_state[port] &= ~mask[BIT_WORD(i)]; 273 dio48egpio->out_state[port] |= bitmask; 274 outb(dio48egpio->out_state[port], dio48egpio->base + out_port); 275 276 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); 277 278 /* prepare for next gpio register set */ 279 mask[BIT_WORD(i)] >>= gpio_reg_size; 280 bits[BIT_WORD(i)] >>= gpio_reg_size; 281 } 282 } 283 284 static void dio48e_irq_ack(struct irq_data *data) 285 { 286 } 287 288 static void dio48e_irq_mask(struct irq_data *data) 289 { 290 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 291 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); 292 const unsigned long offset = irqd_to_hwirq(data); 293 unsigned long flags; 294 295 /* only bit 3 on each respective Port C supports interrupts */ 296 if (offset != 19 && offset != 43) 297 return; 298 299 raw_spin_lock_irqsave(&dio48egpio->lock, flags); 300 301 if (offset == 19) 302 dio48egpio->irq_mask &= ~BIT(0); 303 else 304 dio48egpio->irq_mask &= ~BIT(1); 305 306 if (!dio48egpio->irq_mask) 307 /* disable interrupts */ 308 inb(dio48egpio->base + 0xB); 309 310 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); 311 } 312 313 static void dio48e_irq_unmask(struct irq_data *data) 314 { 315 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 316 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); 317 const unsigned long offset = irqd_to_hwirq(data); 318 unsigned long flags; 319 320 /* only bit 3 on each respective Port C supports interrupts */ 321 if (offset != 19 && offset != 43) 322 return; 323 324 raw_spin_lock_irqsave(&dio48egpio->lock, flags); 325 326 if (!dio48egpio->irq_mask) { 327 /* enable interrupts */ 328 outb(0x00, dio48egpio->base + 0xF); 329 outb(0x00, dio48egpio->base + 0xB); 330 } 331 332 if (offset == 19) 333 dio48egpio->irq_mask |= BIT(0); 334 else 335 dio48egpio->irq_mask |= BIT(1); 336 337 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); 338 } 339 340 static int dio48e_irq_set_type(struct irq_data *data, unsigned flow_type) 341 { 342 const unsigned long offset = irqd_to_hwirq(data); 343 344 /* only bit 3 on each respective Port C supports interrupts */ 345 if (offset != 19 && offset != 43) 346 return -EINVAL; 347 348 if (flow_type != IRQ_TYPE_NONE && flow_type != IRQ_TYPE_EDGE_RISING) 349 return -EINVAL; 350 351 return 0; 352 } 353 354 static struct irq_chip dio48e_irqchip = { 355 .name = "104-dio-48e", 356 .irq_ack = dio48e_irq_ack, 357 .irq_mask = dio48e_irq_mask, 358 .irq_unmask = dio48e_irq_unmask, 359 .irq_set_type = dio48e_irq_set_type 360 }; 361 362 static irqreturn_t dio48e_irq_handler(int irq, void *dev_id) 363 { 364 struct dio48e_gpio *const dio48egpio = dev_id; 365 struct gpio_chip *const chip = &dio48egpio->chip; 366 const unsigned long irq_mask = dio48egpio->irq_mask; 367 unsigned long gpio; 368 369 for_each_set_bit(gpio, &irq_mask, 2) 370 generic_handle_irq(irq_find_mapping(chip->irq.domain, 371 19 + gpio*24)); 372 373 raw_spin_lock(&dio48egpio->lock); 374 375 outb(0x00, dio48egpio->base + 0xF); 376 377 raw_spin_unlock(&dio48egpio->lock); 378 379 return IRQ_HANDLED; 380 } 381 382 #define DIO48E_NGPIO 48 383 static const char *dio48e_names[DIO48E_NGPIO] = { 384 "PPI Group 0 Port A 0", "PPI Group 0 Port A 1", "PPI Group 0 Port A 2", 385 "PPI Group 0 Port A 3", "PPI Group 0 Port A 4", "PPI Group 0 Port A 5", 386 "PPI Group 0 Port A 6", "PPI Group 0 Port A 7", "PPI Group 0 Port B 0", 387 "PPI Group 0 Port B 1", "PPI Group 0 Port B 2", "PPI Group 0 Port B 3", 388 "PPI Group 0 Port B 4", "PPI Group 0 Port B 5", "PPI Group 0 Port B 6", 389 "PPI Group 0 Port B 7", "PPI Group 0 Port C 0", "PPI Group 0 Port C 1", 390 "PPI Group 0 Port C 2", "PPI Group 0 Port C 3", "PPI Group 0 Port C 4", 391 "PPI Group 0 Port C 5", "PPI Group 0 Port C 6", "PPI Group 0 Port C 7", 392 "PPI Group 1 Port A 0", "PPI Group 1 Port A 1", "PPI Group 1 Port A 2", 393 "PPI Group 1 Port A 3", "PPI Group 1 Port A 4", "PPI Group 1 Port A 5", 394 "PPI Group 1 Port A 6", "PPI Group 1 Port A 7", "PPI Group 1 Port B 0", 395 "PPI Group 1 Port B 1", "PPI Group 1 Port B 2", "PPI Group 1 Port B 3", 396 "PPI Group 1 Port B 4", "PPI Group 1 Port B 5", "PPI Group 1 Port B 6", 397 "PPI Group 1 Port B 7", "PPI Group 1 Port C 0", "PPI Group 1 Port C 1", 398 "PPI Group 1 Port C 2", "PPI Group 1 Port C 3", "PPI Group 1 Port C 4", 399 "PPI Group 1 Port C 5", "PPI Group 1 Port C 6", "PPI Group 1 Port C 7" 400 }; 401 402 static int dio48e_probe(struct device *dev, unsigned int id) 403 { 404 struct dio48e_gpio *dio48egpio; 405 const char *const name = dev_name(dev); 406 int err; 407 408 dio48egpio = devm_kzalloc(dev, sizeof(*dio48egpio), GFP_KERNEL); 409 if (!dio48egpio) 410 return -ENOMEM; 411 412 if (!devm_request_region(dev, base[id], DIO48E_EXTENT, name)) { 413 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n", 414 base[id], base[id] + DIO48E_EXTENT); 415 return -EBUSY; 416 } 417 418 dio48egpio->chip.label = name; 419 dio48egpio->chip.parent = dev; 420 dio48egpio->chip.owner = THIS_MODULE; 421 dio48egpio->chip.base = -1; 422 dio48egpio->chip.ngpio = DIO48E_NGPIO; 423 dio48egpio->chip.names = dio48e_names; 424 dio48egpio->chip.get_direction = dio48e_gpio_get_direction; 425 dio48egpio->chip.direction_input = dio48e_gpio_direction_input; 426 dio48egpio->chip.direction_output = dio48e_gpio_direction_output; 427 dio48egpio->chip.get = dio48e_gpio_get; 428 dio48egpio->chip.get_multiple = dio48e_gpio_get_multiple; 429 dio48egpio->chip.set = dio48e_gpio_set; 430 dio48egpio->chip.set_multiple = dio48e_gpio_set_multiple; 431 dio48egpio->base = base[id]; 432 433 raw_spin_lock_init(&dio48egpio->lock); 434 435 err = devm_gpiochip_add_data(dev, &dio48egpio->chip, dio48egpio); 436 if (err) { 437 dev_err(dev, "GPIO registering failed (%d)\n", err); 438 return err; 439 } 440 441 /* initialize all GPIO as output */ 442 outb(0x80, base[id] + 3); 443 outb(0x00, base[id]); 444 outb(0x00, base[id] + 1); 445 outb(0x00, base[id] + 2); 446 outb(0x00, base[id] + 3); 447 outb(0x80, base[id] + 7); 448 outb(0x00, base[id] + 4); 449 outb(0x00, base[id] + 5); 450 outb(0x00, base[id] + 6); 451 outb(0x00, base[id] + 7); 452 453 /* disable IRQ by default */ 454 inb(base[id] + 0xB); 455 456 err = gpiochip_irqchip_add(&dio48egpio->chip, &dio48e_irqchip, 0, 457 handle_edge_irq, IRQ_TYPE_NONE); 458 if (err) { 459 dev_err(dev, "Could not add irqchip (%d)\n", err); 460 return err; 461 } 462 463 err = devm_request_irq(dev, irq[id], dio48e_irq_handler, 0, name, 464 dio48egpio); 465 if (err) { 466 dev_err(dev, "IRQ handler registering failed (%d)\n", err); 467 return err; 468 } 469 470 return 0; 471 } 472 473 static struct isa_driver dio48e_driver = { 474 .probe = dio48e_probe, 475 .driver = { 476 .name = "104-dio-48e" 477 }, 478 }; 479 module_isa_driver(dio48e_driver, num_dio48e); 480 481 MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>"); 482 MODULE_DESCRIPTION("ACCES 104-DIO-48E GPIO driver"); 483 MODULE_LICENSE("GPL v2"); 484