1 /* 2 * FSI hub master driver 3 * 4 * Copyright (C) IBM Corporation 2016 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/delay.h> 17 #include <linux/fsi.h> 18 #include <linux/module.h> 19 #include <linux/slab.h> 20 21 #include "fsi-master.h" 22 23 /* Control Registers */ 24 #define FSI_MMODE 0x0 /* R/W: mode */ 25 #define FSI_MDLYR 0x4 /* R/W: delay */ 26 #define FSI_MCRSP 0x8 /* R/W: clock rate */ 27 #define FSI_MENP0 0x10 /* R/W: enable */ 28 #define FSI_MLEVP0 0x18 /* R: plug detect */ 29 #define FSI_MSENP0 0x18 /* S: Set enable */ 30 #define FSI_MCENP0 0x20 /* C: Clear enable */ 31 #define FSI_MAEB 0x70 /* R: Error address */ 32 #define FSI_MVER 0x74 /* R: master version/type */ 33 #define FSI_MRESP0 0xd0 /* W: Port reset */ 34 #define FSI_MESRB0 0x1d0 /* R: Master error status */ 35 #define FSI_MRESB0 0x1d0 /* W: Reset bridge */ 36 #define FSI_MECTRL 0x2e0 /* W: Error control */ 37 38 /* MMODE: Mode control */ 39 #define FSI_MMODE_EIP 0x80000000 /* Enable interrupt polling */ 40 #define FSI_MMODE_ECRC 0x40000000 /* Enable error recovery */ 41 #define FSI_MMODE_EPC 0x10000000 /* Enable parity checking */ 42 #define FSI_MMODE_P8_TO_LSB 0x00000010 /* Timeout value LSB */ 43 /* MSB=1, LSB=0 is 0.8 ms */ 44 /* MSB=0, LSB=1 is 0.9 ms */ 45 #define FSI_MMODE_CRS0SHFT 18 /* Clk rate selection 0 shift */ 46 #define FSI_MMODE_CRS0MASK 0x3ff /* Clk rate selection 0 mask */ 47 #define FSI_MMODE_CRS1SHFT 8 /* Clk rate selection 1 shift */ 48 #define FSI_MMODE_CRS1MASK 0x3ff /* Clk rate selection 1 mask */ 49 50 /* MRESB: Reset brindge */ 51 #define FSI_MRESB_RST_GEN 0x80000000 /* General reset */ 52 #define FSI_MRESB_RST_ERR 0x40000000 /* Error Reset */ 53 54 /* MRESB: Reset port */ 55 #define FSI_MRESP_RST_ALL_MASTER 0x20000000 /* Reset all FSI masters */ 56 #define FSI_MRESP_RST_ALL_LINK 0x10000000 /* Reset all FSI port contr. */ 57 #define FSI_MRESP_RST_MCR 0x08000000 /* Reset FSI master reg. */ 58 #define FSI_MRESP_RST_PYE 0x04000000 /* Reset FSI parity error */ 59 #define FSI_MRESP_RST_ALL 0xfc000000 /* Reset any error */ 60 61 /* MECTRL: Error control */ 62 #define FSI_MECTRL_EOAE 0x8000 /* Enable machine check when */ 63 /* master 0 in error */ 64 #define FSI_MECTRL_P8_AUTO_TERM 0x4000 /* Auto terminate */ 65 66 #define FSI_ENGID_HUB_MASTER 0x1c 67 #define FSI_HUB_LINK_OFFSET 0x80000 68 #define FSI_HUB_LINK_SIZE 0x80000 69 #define FSI_HUB_MASTER_MAX_LINKS 8 70 71 #define FSI_LINK_ENABLE_SETUP_TIME 10 /* in mS */ 72 73 /* 74 * FSI hub master support 75 * 76 * A hub master increases the number of potential target devices that the 77 * primary FSI master can access. For each link a primary master supports, 78 * each of those links can in turn be chained to a hub master with multiple 79 * links of its own. 80 * 81 * The hub is controlled by a set of control registers exposed as a regular fsi 82 * device (the hub->upstream device), and provides access to the downstream FSI 83 * bus as through an address range on the slave itself (->addr and ->size). 84 * 85 * [This differs from "cascaded" masters, which expose the entire downstream 86 * bus entirely through the fsi device address range, and so have a smaller 87 * accessible address space.] 88 */ 89 struct fsi_master_hub { 90 struct fsi_master master; 91 struct fsi_device *upstream; 92 uint32_t addr, size; /* slave-relative addr of */ 93 /* master address space */ 94 }; 95 96 #define to_fsi_master_hub(m) container_of(m, struct fsi_master_hub, master) 97 98 static int hub_master_read(struct fsi_master *master, int link, 99 uint8_t id, uint32_t addr, void *val, size_t size) 100 { 101 struct fsi_master_hub *hub = to_fsi_master_hub(master); 102 103 if (id != 0) 104 return -EINVAL; 105 106 addr += hub->addr + (link * FSI_HUB_LINK_SIZE); 107 return fsi_slave_read(hub->upstream->slave, addr, val, size); 108 } 109 110 static int hub_master_write(struct fsi_master *master, int link, 111 uint8_t id, uint32_t addr, const void *val, size_t size) 112 { 113 struct fsi_master_hub *hub = to_fsi_master_hub(master); 114 115 if (id != 0) 116 return -EINVAL; 117 118 addr += hub->addr + (link * FSI_HUB_LINK_SIZE); 119 return fsi_slave_write(hub->upstream->slave, addr, val, size); 120 } 121 122 static int hub_master_break(struct fsi_master *master, int link) 123 { 124 uint32_t addr, cmd; 125 126 addr = 0x4; 127 cmd = cpu_to_be32(0xc0de0000); 128 129 return hub_master_write(master, link, 0, addr, &cmd, sizeof(cmd)); 130 } 131 132 static int hub_master_link_enable(struct fsi_master *master, int link) 133 { 134 struct fsi_master_hub *hub = to_fsi_master_hub(master); 135 int idx, bit; 136 __be32 reg; 137 int rc; 138 139 idx = link / 32; 140 bit = link % 32; 141 142 reg = cpu_to_be32(0x80000000 >> bit); 143 144 rc = fsi_device_write(hub->upstream, FSI_MSENP0 + (4 * idx), ®, 4); 145 146 mdelay(FSI_LINK_ENABLE_SETUP_TIME); 147 148 fsi_device_read(hub->upstream, FSI_MENP0 + (4 * idx), ®, 4); 149 150 return rc; 151 } 152 153 static void hub_master_release(struct device *dev) 154 { 155 struct fsi_master_hub *hub = to_fsi_master_hub(dev_to_fsi_master(dev)); 156 157 kfree(hub); 158 } 159 160 /* mmode encoders */ 161 static inline u32 fsi_mmode_crs0(u32 x) 162 { 163 return (x & FSI_MMODE_CRS0MASK) << FSI_MMODE_CRS0SHFT; 164 } 165 166 static inline u32 fsi_mmode_crs1(u32 x) 167 { 168 return (x & FSI_MMODE_CRS1MASK) << FSI_MMODE_CRS1SHFT; 169 } 170 171 static int hub_master_init(struct fsi_master_hub *hub) 172 { 173 struct fsi_device *dev = hub->upstream; 174 __be32 reg; 175 int rc; 176 177 reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK 178 | FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE); 179 rc = fsi_device_write(dev, FSI_MRESP0, ®, sizeof(reg)); 180 if (rc) 181 return rc; 182 183 /* Initialize the MFSI (hub master) engine */ 184 reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK 185 | FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE); 186 rc = fsi_device_write(dev, FSI_MRESP0, ®, sizeof(reg)); 187 if (rc) 188 return rc; 189 190 reg = cpu_to_be32(FSI_MECTRL_EOAE | FSI_MECTRL_P8_AUTO_TERM); 191 rc = fsi_device_write(dev, FSI_MECTRL, ®, sizeof(reg)); 192 if (rc) 193 return rc; 194 195 reg = cpu_to_be32(FSI_MMODE_EIP | FSI_MMODE_ECRC | FSI_MMODE_EPC 196 | fsi_mmode_crs0(1) | fsi_mmode_crs1(1) 197 | FSI_MMODE_P8_TO_LSB); 198 rc = fsi_device_write(dev, FSI_MMODE, ®, sizeof(reg)); 199 if (rc) 200 return rc; 201 202 reg = cpu_to_be32(0xffff0000); 203 rc = fsi_device_write(dev, FSI_MDLYR, ®, sizeof(reg)); 204 if (rc) 205 return rc; 206 207 reg = ~0; 208 rc = fsi_device_write(dev, FSI_MSENP0, ®, sizeof(reg)); 209 if (rc) 210 return rc; 211 212 /* Leave enabled long enough for master logic to set up */ 213 mdelay(FSI_LINK_ENABLE_SETUP_TIME); 214 215 rc = fsi_device_write(dev, FSI_MCENP0, ®, sizeof(reg)); 216 if (rc) 217 return rc; 218 219 rc = fsi_device_read(dev, FSI_MAEB, ®, sizeof(reg)); 220 if (rc) 221 return rc; 222 223 reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK); 224 rc = fsi_device_write(dev, FSI_MRESP0, ®, sizeof(reg)); 225 if (rc) 226 return rc; 227 228 rc = fsi_device_read(dev, FSI_MLEVP0, ®, sizeof(reg)); 229 if (rc) 230 return rc; 231 232 /* Reset the master bridge */ 233 reg = cpu_to_be32(FSI_MRESB_RST_GEN); 234 rc = fsi_device_write(dev, FSI_MRESB0, ®, sizeof(reg)); 235 if (rc) 236 return rc; 237 238 reg = cpu_to_be32(FSI_MRESB_RST_ERR); 239 return fsi_device_write(dev, FSI_MRESB0, ®, sizeof(reg)); 240 } 241 242 static int hub_master_probe(struct device *dev) 243 { 244 struct fsi_device *fsi_dev = to_fsi_dev(dev); 245 struct fsi_master_hub *hub; 246 uint32_t reg, links; 247 __be32 __reg; 248 int rc; 249 250 rc = fsi_device_read(fsi_dev, FSI_MVER, &__reg, sizeof(__reg)); 251 if (rc) 252 return rc; 253 254 reg = be32_to_cpu(__reg); 255 links = (reg >> 8) & 0xff; 256 dev_info(dev, "hub version %08x (%d links)\n", reg, links); 257 258 rc = fsi_slave_claim_range(fsi_dev->slave, FSI_HUB_LINK_OFFSET, 259 FSI_HUB_LINK_SIZE * links); 260 if (rc) { 261 dev_err(dev, "can't claim slave address range for links"); 262 return rc; 263 } 264 265 hub = kzalloc(sizeof(*hub), GFP_KERNEL); 266 if (!hub) { 267 rc = -ENOMEM; 268 goto err_release; 269 } 270 271 hub->addr = FSI_HUB_LINK_OFFSET; 272 hub->size = FSI_HUB_LINK_SIZE * links; 273 hub->upstream = fsi_dev; 274 275 hub->master.dev.parent = dev; 276 hub->master.dev.release = hub_master_release; 277 278 hub->master.n_links = links; 279 hub->master.read = hub_master_read; 280 hub->master.write = hub_master_write; 281 hub->master.send_break = hub_master_break; 282 hub->master.link_enable = hub_master_link_enable; 283 284 dev_set_drvdata(dev, hub); 285 286 hub_master_init(hub); 287 288 rc = fsi_master_register(&hub->master); 289 if (!rc) 290 return 0; 291 292 kfree(hub); 293 err_release: 294 fsi_slave_release_range(fsi_dev->slave, FSI_HUB_LINK_OFFSET, 295 FSI_HUB_LINK_SIZE * links); 296 return rc; 297 } 298 299 static int hub_master_remove(struct device *dev) 300 { 301 struct fsi_master_hub *hub = dev_get_drvdata(dev); 302 303 fsi_master_unregister(&hub->master); 304 fsi_slave_release_range(hub->upstream->slave, hub->addr, hub->size); 305 return 0; 306 } 307 308 static struct fsi_device_id hub_master_ids[] = { 309 { 310 .engine_type = FSI_ENGID_HUB_MASTER, 311 .version = FSI_VERSION_ANY, 312 }, 313 { 0 } 314 }; 315 316 static struct fsi_driver hub_master_driver = { 317 .id_table = hub_master_ids, 318 .drv = { 319 .name = "fsi-master-hub", 320 .bus = &fsi_bus_type, 321 .probe = hub_master_probe, 322 .remove = hub_master_remove, 323 } 324 }; 325 326 module_fsi_driver(hub_master_driver); 327 MODULE_LICENSE("GPL"); 328