1 // SPDX-License-Identifier: GPL-2.0-or-later
2 // Copyright (C) IBM Corporation 2018
3 // FSI master driver for AST2600
4 
5 #include <linux/clk.h>
6 #include <linux/delay.h>
7 #include <linux/fsi.h>
8 #include <linux/io.h>
9 #include <linux/mfd/syscon.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14 #include <linux/slab.h>
15 #include <linux/iopoll.h>
16 #include <linux/gpio/consumer.h>
17 
18 #include "fsi-master.h"
19 
20 struct fsi_master_aspeed {
21 	struct fsi_master	master;
22 	struct device		*dev;
23 	void __iomem		*base;
24 	struct clk		*clk;
25 	struct gpio_desc	*cfam_reset_gpio;
26 };
27 
28 #define to_fsi_master_aspeed(m) \
29 	container_of(m, struct fsi_master_aspeed, master)
30 
31 /* Control register (size 0x400) */
32 static const u32 ctrl_base = 0x80000000;
33 
34 static const u32 fsi_base = 0xa0000000;
35 
36 #define OPB_FSI_VER	0x00
37 #define OPB_TRIGGER	0x04
38 #define OPB_CTRL_BASE	0x08
39 #define OPB_FSI_BASE	0x0c
40 #define OPB_CLK_SYNC	0x3c
41 #define OPB_IRQ_CLEAR	0x40
42 #define OPB_IRQ_MASK	0x44
43 #define OPB_IRQ_STATUS	0x48
44 
45 #define OPB0_SELECT	0x10
46 #define OPB0_RW		0x14
47 #define OPB0_XFER_SIZE	0x18
48 #define OPB0_FSI_ADDR	0x1c
49 #define OPB0_FSI_DATA_W	0x20
50 #define OPB0_STATUS	0x80
51 #define OPB0_FSI_DATA_R	0x84
52 
53 #define OPB0_WRITE_ORDER1	0x4c
54 #define OPB0_WRITE_ORDER2	0x50
55 #define OPB1_WRITE_ORDER1	0x54
56 #define OPB1_WRITE_ORDER2	0x58
57 #define OPB0_READ_ORDER1	0x5c
58 #define OPB1_READ_ORDER2	0x60
59 
60 #define OPB_RETRY_COUNTER	0x64
61 
62 /* OPBn_STATUS */
63 #define STATUS_HALFWORD_ACK	BIT(0)
64 #define STATUS_FULLWORD_ACK	BIT(1)
65 #define STATUS_ERR_ACK		BIT(2)
66 #define STATUS_RETRY		BIT(3)
67 #define STATUS_TIMEOUT		BIT(4)
68 
69 /* OPB_IRQ_MASK */
70 #define OPB1_XFER_ACK_EN BIT(17)
71 #define OPB0_XFER_ACK_EN BIT(16)
72 
73 /* OPB_RW */
74 #define CMD_READ	BIT(0)
75 #define CMD_WRITE	0
76 
77 /* OPBx_XFER_SIZE */
78 #define XFER_FULLWORD	(BIT(1) | BIT(0))
79 #define XFER_HALFWORD	(BIT(0))
80 #define XFER_BYTE	(0)
81 
82 #define CREATE_TRACE_POINTS
83 #include <trace/events/fsi_master_aspeed.h>
84 
85 #define FSI_LINK_ENABLE_SETUP_TIME	10	/* in mS */
86 
87 /* Run the bus at maximum speed by default */
88 #define FSI_DIVISOR_DEFAULT            1
89 #define FSI_DIVISOR_CABLED             2
90 static u16 aspeed_fsi_divisor = FSI_DIVISOR_DEFAULT;
91 module_param_named(bus_div,aspeed_fsi_divisor, ushort, 0);
92 
93 #define OPB_POLL_TIMEOUT		10000
94 
95 static int __opb_write(struct fsi_master_aspeed *aspeed, u32 addr,
96 		       u32 val, u32 transfer_size)
97 {
98 	void __iomem *base = aspeed->base;
99 	u32 reg, status;
100 	int ret;
101 
102 	writel(CMD_WRITE, base + OPB0_RW);
103 	writel(transfer_size, base + OPB0_XFER_SIZE);
104 	writel(addr, base + OPB0_FSI_ADDR);
105 	writel(val, base + OPB0_FSI_DATA_W);
106 	writel(0x1, base + OPB_IRQ_CLEAR);
107 	writel(0x1, base + OPB_TRIGGER);
108 
109 	ret = readl_poll_timeout(base + OPB_IRQ_STATUS, reg,
110 				(reg & OPB0_XFER_ACK_EN) != 0,
111 				0, OPB_POLL_TIMEOUT);
112 
113 	status = readl(base + OPB0_STATUS);
114 
115 	trace_fsi_master_aspeed_opb_write(addr, val, transfer_size, status, reg);
116 
117 	/* Return error when poll timed out */
118 	if (ret)
119 		return ret;
120 
121 	/* Command failed, master will reset */
122 	if (status & STATUS_ERR_ACK)
123 		return -EIO;
124 
125 	return 0;
126 }
127 
128 static int opb_writeb(struct fsi_master_aspeed *aspeed, u32 addr, u8 val)
129 {
130 	return __opb_write(aspeed, addr, val, XFER_BYTE);
131 }
132 
133 static int opb_writew(struct fsi_master_aspeed *aspeed, u32 addr, __be16 val)
134 {
135 	return __opb_write(aspeed, addr, (__force u16)val, XFER_HALFWORD);
136 }
137 
138 static int opb_writel(struct fsi_master_aspeed *aspeed, u32 addr, __be32 val)
139 {
140 	return __opb_write(aspeed, addr, (__force u32)val, XFER_FULLWORD);
141 }
142 
143 static int __opb_read(struct fsi_master_aspeed *aspeed, uint32_t addr,
144 		      u32 transfer_size, void *out)
145 {
146 	void __iomem *base = aspeed->base;
147 	u32 result, reg;
148 	int status, ret;
149 
150 	writel(CMD_READ, base + OPB0_RW);
151 	writel(transfer_size, base + OPB0_XFER_SIZE);
152 	writel(addr, base + OPB0_FSI_ADDR);
153 	writel(0x1, base + OPB_IRQ_CLEAR);
154 	writel(0x1, base + OPB_TRIGGER);
155 
156 	ret = readl_poll_timeout(base + OPB_IRQ_STATUS, reg,
157 			   (reg & OPB0_XFER_ACK_EN) != 0,
158 			   0, OPB_POLL_TIMEOUT);
159 
160 	status = readl(base + OPB0_STATUS);
161 
162 	result = readl(base + OPB0_FSI_DATA_R);
163 
164 	trace_fsi_master_aspeed_opb_read(addr, transfer_size, result,
165 			readl(base + OPB0_STATUS),
166 			reg);
167 
168 	/* Return error when poll timed out */
169 	if (ret)
170 		return ret;
171 
172 	/* Command failed, master will reset */
173 	if (status & STATUS_ERR_ACK)
174 		return -EIO;
175 
176 	if (out) {
177 		switch (transfer_size) {
178 		case XFER_BYTE:
179 			*(u8 *)out = result;
180 			break;
181 		case XFER_HALFWORD:
182 			*(u16 *)out = result;
183 			break;
184 		case XFER_FULLWORD:
185 			*(u32 *)out = result;
186 			break;
187 		default:
188 			return -EINVAL;
189 		}
190 
191 	}
192 
193 	return 0;
194 }
195 
196 static int opb_readl(struct fsi_master_aspeed *aspeed, uint32_t addr, __be32 *out)
197 {
198 	return __opb_read(aspeed, addr, XFER_FULLWORD, out);
199 }
200 
201 static int opb_readw(struct fsi_master_aspeed *aspeed, uint32_t addr, __be16 *out)
202 {
203 	return __opb_read(aspeed, addr, XFER_HALFWORD, (void *)out);
204 }
205 
206 static int opb_readb(struct fsi_master_aspeed *aspeed, uint32_t addr, u8 *out)
207 {
208 	return __opb_read(aspeed, addr, XFER_BYTE, (void *)out);
209 }
210 
211 static int check_errors(struct fsi_master_aspeed *aspeed, int err)
212 {
213 	int ret;
214 
215 	if (trace_fsi_master_aspeed_opb_error_enabled()) {
216 		__be32 mresp0, mstap0, mesrb0;
217 
218 		opb_readl(aspeed, ctrl_base + FSI_MRESP0, &mresp0);
219 		opb_readl(aspeed, ctrl_base + FSI_MSTAP0, &mstap0);
220 		opb_readl(aspeed, ctrl_base + FSI_MESRB0, &mesrb0);
221 
222 		trace_fsi_master_aspeed_opb_error(
223 				be32_to_cpu(mresp0),
224 				be32_to_cpu(mstap0),
225 				be32_to_cpu(mesrb0));
226 	}
227 
228 	if (err == -EIO) {
229 		/* Check MAEB (0x70) ? */
230 
231 		/* Then clear errors in master */
232 		ret = opb_writel(aspeed, ctrl_base + FSI_MRESP0,
233 				cpu_to_be32(FSI_MRESP_RST_ALL_MASTER));
234 		if (ret) {
235 			/* TODO: log? return different code? */
236 			return ret;
237 		}
238 		/* TODO: confirm that 0x70 was okay */
239 	}
240 
241 	/* This will pass through timeout errors */
242 	return err;
243 }
244 
245 static int aspeed_master_read(struct fsi_master *master, int link,
246 			uint8_t id, uint32_t addr, void *val, size_t size)
247 {
248 	struct fsi_master_aspeed *aspeed = to_fsi_master_aspeed(master);
249 	int ret;
250 
251 	if (id > 0x3)
252 		return -EINVAL;
253 
254 	addr |= id << 21;
255 	addr += link * FSI_HUB_LINK_SIZE;
256 
257 	switch (size) {
258 	case 1:
259 		ret = opb_readb(aspeed, fsi_base + addr, val);
260 		break;
261 	case 2:
262 		ret = opb_readw(aspeed, fsi_base + addr, val);
263 		break;
264 	case 4:
265 		ret = opb_readl(aspeed, fsi_base + addr, val);
266 		break;
267 	default:
268 		return -EINVAL;
269 	}
270 
271 	ret = check_errors(aspeed, ret);
272 	if (ret)
273 		return ret;
274 
275 	return 0;
276 }
277 
278 static int aspeed_master_write(struct fsi_master *master, int link,
279 			uint8_t id, uint32_t addr, const void *val, size_t size)
280 {
281 	struct fsi_master_aspeed *aspeed = to_fsi_master_aspeed(master);
282 	int ret;
283 
284 	if (id > 0x3)
285 		return -EINVAL;
286 
287 	addr |= id << 21;
288 	addr += link * FSI_HUB_LINK_SIZE;
289 
290 	switch (size) {
291 	case 1:
292 		ret = opb_writeb(aspeed, fsi_base + addr, *(u8 *)val);
293 		break;
294 	case 2:
295 		ret = opb_writew(aspeed, fsi_base + addr, *(__be16 *)val);
296 		break;
297 	case 4:
298 		ret = opb_writel(aspeed, fsi_base + addr, *(__be32 *)val);
299 		break;
300 	default:
301 		return -EINVAL;
302 	}
303 
304 	ret = check_errors(aspeed, ret);
305 	if (ret)
306 		return ret;
307 
308 	return 0;
309 }
310 
311 static int aspeed_master_link_enable(struct fsi_master *master, int link,
312 				     bool enable)
313 {
314 	struct fsi_master_aspeed *aspeed = to_fsi_master_aspeed(master);
315 	int idx, bit, ret;
316 	__be32 reg;
317 
318 	idx = link / 32;
319 	bit = link % 32;
320 
321 	reg = cpu_to_be32(0x80000000 >> bit);
322 
323 	if (!enable)
324 		return opb_writel(aspeed, ctrl_base + FSI_MCENP0 + (4 * idx),
325 				  reg);
326 
327 	ret = opb_writel(aspeed, ctrl_base + FSI_MSENP0 + (4 * idx), reg);
328 	if (ret)
329 		return ret;
330 
331 	mdelay(FSI_LINK_ENABLE_SETUP_TIME);
332 
333 	return 0;
334 }
335 
336 static int aspeed_master_term(struct fsi_master *master, int link, uint8_t id)
337 {
338 	uint32_t addr;
339 	__be32 cmd;
340 
341 	addr = 0x4;
342 	cmd = cpu_to_be32(0xecc00000);
343 
344 	return aspeed_master_write(master, link, id, addr, &cmd, 4);
345 }
346 
347 static int aspeed_master_break(struct fsi_master *master, int link)
348 {
349 	uint32_t addr;
350 	__be32 cmd;
351 
352 	addr = 0x0;
353 	cmd = cpu_to_be32(0xc0de0000);
354 
355 	return aspeed_master_write(master, link, 0, addr, &cmd, 4);
356 }
357 
358 static void aspeed_master_release(struct device *dev)
359 {
360 	struct fsi_master_aspeed *aspeed =
361 		to_fsi_master_aspeed(dev_to_fsi_master(dev));
362 
363 	kfree(aspeed);
364 }
365 
366 /* mmode encoders */
367 static inline u32 fsi_mmode_crs0(u32 x)
368 {
369 	return (x & FSI_MMODE_CRS0MASK) << FSI_MMODE_CRS0SHFT;
370 }
371 
372 static inline u32 fsi_mmode_crs1(u32 x)
373 {
374 	return (x & FSI_MMODE_CRS1MASK) << FSI_MMODE_CRS1SHFT;
375 }
376 
377 static int aspeed_master_init(struct fsi_master_aspeed *aspeed)
378 {
379 	__be32 reg;
380 
381 	reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK
382 			| FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE);
383 	opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg);
384 
385 	/* Initialize the MFSI (hub master) engine */
386 	reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK
387 			| FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE);
388 	opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg);
389 
390 	reg = cpu_to_be32(FSI_MECTRL_EOAE | FSI_MECTRL_P8_AUTO_TERM);
391 	opb_writel(aspeed, ctrl_base + FSI_MECTRL, reg);
392 
393 	reg = cpu_to_be32(FSI_MMODE_ECRC | FSI_MMODE_EPC | FSI_MMODE_RELA
394 			| fsi_mmode_crs0(aspeed_fsi_divisor)
395 			| fsi_mmode_crs1(aspeed_fsi_divisor)
396 			| FSI_MMODE_P8_TO_LSB);
397 	dev_info(aspeed->dev, "mmode set to %08x (divisor %d)\n",
398 			be32_to_cpu(reg), aspeed_fsi_divisor);
399 	opb_writel(aspeed, ctrl_base + FSI_MMODE, reg);
400 
401 	reg = cpu_to_be32(0xffff0000);
402 	opb_writel(aspeed, ctrl_base + FSI_MDLYR, reg);
403 
404 	reg = cpu_to_be32(~0);
405 	opb_writel(aspeed, ctrl_base + FSI_MSENP0, reg);
406 
407 	/* Leave enabled long enough for master logic to set up */
408 	mdelay(FSI_LINK_ENABLE_SETUP_TIME);
409 
410 	opb_writel(aspeed, ctrl_base + FSI_MCENP0, reg);
411 
412 	opb_readl(aspeed, ctrl_base + FSI_MAEB, NULL);
413 
414 	reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK);
415 	opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg);
416 
417 	opb_readl(aspeed, ctrl_base + FSI_MLEVP0, NULL);
418 
419 	/* Reset the master bridge */
420 	reg = cpu_to_be32(FSI_MRESB_RST_GEN);
421 	opb_writel(aspeed, ctrl_base + FSI_MRESB0, reg);
422 
423 	reg = cpu_to_be32(FSI_MRESB_RST_ERR);
424 	opb_writel(aspeed, ctrl_base + FSI_MRESB0, reg);
425 
426 	return 0;
427 }
428 
429 static ssize_t cfam_reset_store(struct device *dev, struct device_attribute *attr,
430 				const char *buf, size_t count)
431 {
432 	struct fsi_master_aspeed *aspeed = dev_get_drvdata(dev);
433 
434 	gpiod_set_value(aspeed->cfam_reset_gpio, 1);
435 	usleep_range(900, 1000);
436 	gpiod_set_value(aspeed->cfam_reset_gpio, 0);
437 
438 	return count;
439 }
440 
441 static DEVICE_ATTR(cfam_reset, 0200, NULL, cfam_reset_store);
442 
443 static int setup_cfam_reset(struct fsi_master_aspeed *aspeed)
444 {
445 	struct device *dev = aspeed->dev;
446 	struct gpio_desc *gpio;
447 	int rc;
448 
449 	gpio = devm_gpiod_get_optional(dev, "cfam-reset", GPIOD_OUT_LOW);
450 	if (IS_ERR(gpio))
451 		return PTR_ERR(gpio);
452 	if (!gpio)
453 		return 0;
454 
455 	aspeed->cfam_reset_gpio = gpio;
456 
457 	rc = device_create_file(dev, &dev_attr_cfam_reset);
458 	if (rc) {
459 		devm_gpiod_put(dev, gpio);
460 		return rc;
461 	}
462 
463 	return 0;
464 }
465 
466 static int tacoma_cabled_fsi_fixup(struct device *dev)
467 {
468 	struct gpio_desc *routing_gpio, *mux_gpio;
469 	int gpio;
470 
471 	/*
472 	 * The routing GPIO is a jumper indicating we should mux for the
473 	 * externally connected FSI cable.
474 	 */
475 	routing_gpio = devm_gpiod_get_optional(dev, "fsi-routing",
476 			GPIOD_IN | GPIOD_FLAGS_BIT_NONEXCLUSIVE);
477 	if (IS_ERR(routing_gpio))
478 		return PTR_ERR(routing_gpio);
479 	if (!routing_gpio)
480 		return 0;
481 
482 	mux_gpio = devm_gpiod_get_optional(dev, "fsi-mux", GPIOD_ASIS);
483 	if (IS_ERR(mux_gpio))
484 		return PTR_ERR(mux_gpio);
485 	if (!mux_gpio)
486 		return 0;
487 
488 	gpio = gpiod_get_value(routing_gpio);
489 	if (gpio < 0)
490 		return gpio;
491 
492 	/* If the routing GPIO is high we should set the mux to low. */
493 	if (gpio) {
494 		/*
495 		 * Cable signal integrity means we should run the bus
496 		 * slightly slower. Do not override if a kernel param
497 		 * has already overridden.
498 		 */
499 		if (aspeed_fsi_divisor == FSI_DIVISOR_DEFAULT)
500 			aspeed_fsi_divisor = FSI_DIVISOR_CABLED;
501 
502 		gpiod_direction_output(mux_gpio, 0);
503 		dev_info(dev, "FSI configured for external cable\n");
504 	} else {
505 		gpiod_direction_output(mux_gpio, 1);
506 	}
507 
508 	devm_gpiod_put(dev, routing_gpio);
509 
510 	return 0;
511 }
512 
513 static int fsi_master_aspeed_probe(struct platform_device *pdev)
514 {
515 	struct fsi_master_aspeed *aspeed;
516 	struct resource *res;
517 	int rc, links, reg;
518 	__be32 raw;
519 
520 	rc = tacoma_cabled_fsi_fixup(&pdev->dev);
521 	if (rc) {
522 		dev_err(&pdev->dev, "Tacoma FSI cable fixup failed\n");
523 		return rc;
524 	}
525 
526 	aspeed = devm_kzalloc(&pdev->dev, sizeof(*aspeed), GFP_KERNEL);
527 	if (!aspeed)
528 		return -ENOMEM;
529 
530 	aspeed->dev = &pdev->dev;
531 
532 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
533 	aspeed->base = devm_ioremap_resource(&pdev->dev, res);
534 	if (IS_ERR(aspeed->base))
535 		return PTR_ERR(aspeed->base);
536 
537 	aspeed->clk = devm_clk_get(aspeed->dev, NULL);
538 	if (IS_ERR(aspeed->clk)) {
539 		dev_err(aspeed->dev, "couldn't get clock\n");
540 		return PTR_ERR(aspeed->clk);
541 	}
542 	rc = clk_prepare_enable(aspeed->clk);
543 	if (rc) {
544 		dev_err(aspeed->dev, "couldn't enable clock\n");
545 		return rc;
546 	}
547 
548 	rc = setup_cfam_reset(aspeed);
549 	if (rc) {
550 		dev_err(&pdev->dev, "CFAM reset GPIO setup failed\n");
551 	}
552 
553 	writel(0x1, aspeed->base + OPB_CLK_SYNC);
554 	writel(OPB1_XFER_ACK_EN | OPB0_XFER_ACK_EN,
555 			aspeed->base + OPB_IRQ_MASK);
556 
557 	/* TODO: determine an appropriate value */
558 	writel(0x10, aspeed->base + OPB_RETRY_COUNTER);
559 
560 	writel(ctrl_base, aspeed->base + OPB_CTRL_BASE);
561 	writel(fsi_base, aspeed->base + OPB_FSI_BASE);
562 
563 	/* Set read data order */
564 	writel(0x00030b1b, aspeed->base + OPB0_READ_ORDER1);
565 
566 	/* Set write data order */
567 	writel(0x0011101b, aspeed->base + OPB0_WRITE_ORDER1);
568 	writel(0x0c330f3f, aspeed->base + OPB0_WRITE_ORDER2);
569 
570 	/*
571 	 * Select OPB0 for all operations.
572 	 * Will need to be reworked when enabling DMA or anything that uses
573 	 * OPB1.
574 	 */
575 	writel(0x1, aspeed->base + OPB0_SELECT);
576 
577 	rc = opb_readl(aspeed, ctrl_base + FSI_MVER, &raw);
578 	if (rc) {
579 		dev_err(&pdev->dev, "failed to read hub version\n");
580 		return rc;
581 	}
582 
583 	reg = be32_to_cpu(raw);
584 	links = (reg >> 8) & 0xff;
585 	dev_info(&pdev->dev, "hub version %08x (%d links)\n", reg, links);
586 
587 	aspeed->master.dev.parent = &pdev->dev;
588 	aspeed->master.dev.release = aspeed_master_release;
589 	aspeed->master.dev.of_node = of_node_get(dev_of_node(&pdev->dev));
590 
591 	aspeed->master.n_links = links;
592 	aspeed->master.read = aspeed_master_read;
593 	aspeed->master.write = aspeed_master_write;
594 	aspeed->master.send_break = aspeed_master_break;
595 	aspeed->master.term = aspeed_master_term;
596 	aspeed->master.link_enable = aspeed_master_link_enable;
597 
598 	dev_set_drvdata(&pdev->dev, aspeed);
599 
600 	aspeed_master_init(aspeed);
601 
602 	rc = fsi_master_register(&aspeed->master);
603 	if (rc)
604 		goto err_release;
605 
606 	/* At this point, fsi_master_register performs the device_initialize(),
607 	 * and holds the sole reference on master.dev. This means the device
608 	 * will be freed (via ->release) during any subsequent call to
609 	 * fsi_master_unregister.  We add our own reference to it here, so we
610 	 * can perform cleanup (in _remove()) without it being freed before
611 	 * we're ready.
612 	 */
613 	get_device(&aspeed->master.dev);
614 	return 0;
615 
616 err_release:
617 	clk_disable_unprepare(aspeed->clk);
618 	return rc;
619 }
620 
621 static int fsi_master_aspeed_remove(struct platform_device *pdev)
622 {
623 	struct fsi_master_aspeed *aspeed = platform_get_drvdata(pdev);
624 
625 	fsi_master_unregister(&aspeed->master);
626 	clk_disable_unprepare(aspeed->clk);
627 
628 	return 0;
629 }
630 
631 static const struct of_device_id fsi_master_aspeed_match[] = {
632 	{ .compatible = "aspeed,ast2600-fsi-master" },
633 	{ },
634 };
635 
636 static struct platform_driver fsi_master_aspeed_driver = {
637 	.driver = {
638 		.name		= "fsi-master-aspeed",
639 		.of_match_table	= fsi_master_aspeed_match,
640 	},
641 	.probe	= fsi_master_aspeed_probe,
642 	.remove = fsi_master_aspeed_remove,
643 };
644 
645 module_platform_driver(fsi_master_aspeed_driver);
646 MODULE_LICENSE("GPL");
647