1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for FPGA Device Feature List (DFL) PCIe device 4 * 5 * Copyright (C) 2017-2018 Intel Corporation, Inc. 6 * 7 * Authors: 8 * Zhang Yi <Yi.Z.Zhang@intel.com> 9 * Xiao Guangrong <guangrong.xiao@linux.intel.com> 10 * Joseph Grecco <joe.grecco@intel.com> 11 * Enno Luebbers <enno.luebbers@intel.com> 12 * Tim Whisonant <tim.whisonant@intel.com> 13 * Ananda Ravuri <ananda.ravuri@intel.com> 14 * Henry Mitchel <henry.mitchel@intel.com> 15 */ 16 17 #include <linux/pci.h> 18 #include <linux/types.h> 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/stddef.h> 22 #include <linux/errno.h> 23 #include <linux/aer.h> 24 25 #include "dfl.h" 26 27 #define DRV_VERSION "0.8" 28 #define DRV_NAME "dfl-pci" 29 30 struct cci_drvdata { 31 struct dfl_fpga_cdev *cdev; /* container device */ 32 }; 33 34 static void __iomem *cci_pci_ioremap_bar(struct pci_dev *pcidev, int bar) 35 { 36 if (pcim_iomap_regions(pcidev, BIT(bar), DRV_NAME)) 37 return NULL; 38 39 return pcim_iomap_table(pcidev)[bar]; 40 } 41 42 static int cci_pci_alloc_irq(struct pci_dev *pcidev) 43 { 44 int ret, nvec = pci_msix_vec_count(pcidev); 45 46 if (nvec <= 0) { 47 dev_dbg(&pcidev->dev, "fpga interrupt not supported\n"); 48 return 0; 49 } 50 51 ret = pci_alloc_irq_vectors(pcidev, nvec, nvec, PCI_IRQ_MSIX); 52 if (ret < 0) 53 return ret; 54 55 return nvec; 56 } 57 58 static void cci_pci_free_irq(struct pci_dev *pcidev) 59 { 60 pci_free_irq_vectors(pcidev); 61 } 62 63 /* PCI Device ID */ 64 #define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD 65 #define PCIE_DEVICE_ID_PF_INT_6_X 0xBCC0 66 #define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4 67 #define PCIE_DEVICE_ID_INTEL_PAC_N3000 0x0B30 68 /* VF Device */ 69 #define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF 70 #define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1 71 #define PCIE_DEVICE_ID_VF_DSC_1_X 0x09C5 72 73 static struct pci_device_id cci_pcie_id_tbl[] = { 74 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X),}, 75 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X),}, 76 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X),}, 77 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X),}, 78 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X),}, 79 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X),}, 80 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_N3000),}, 81 {0,} 82 }; 83 MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl); 84 85 static int cci_init_drvdata(struct pci_dev *pcidev) 86 { 87 struct cci_drvdata *drvdata; 88 89 drvdata = devm_kzalloc(&pcidev->dev, sizeof(*drvdata), GFP_KERNEL); 90 if (!drvdata) 91 return -ENOMEM; 92 93 pci_set_drvdata(pcidev, drvdata); 94 95 return 0; 96 } 97 98 static void cci_remove_feature_devs(struct pci_dev *pcidev) 99 { 100 struct cci_drvdata *drvdata = pci_get_drvdata(pcidev); 101 102 /* remove all children feature devices */ 103 dfl_fpga_feature_devs_remove(drvdata->cdev); 104 cci_pci_free_irq(pcidev); 105 } 106 107 static int *cci_pci_create_irq_table(struct pci_dev *pcidev, unsigned int nvec) 108 { 109 unsigned int i; 110 int *table; 111 112 table = kcalloc(nvec, sizeof(int), GFP_KERNEL); 113 if (!table) 114 return table; 115 116 for (i = 0; i < nvec; i++) 117 table[i] = pci_irq_vector(pcidev, i); 118 119 return table; 120 } 121 122 /* enumerate feature devices under pci device */ 123 static int cci_enumerate_feature_devs(struct pci_dev *pcidev) 124 { 125 struct cci_drvdata *drvdata = pci_get_drvdata(pcidev); 126 int port_num, bar, i, nvec, ret = 0; 127 struct dfl_fpga_enum_info *info; 128 struct dfl_fpga_cdev *cdev; 129 resource_size_t start, len; 130 void __iomem *base; 131 int *irq_table; 132 u32 offset; 133 u64 v; 134 135 /* allocate enumeration info via pci_dev */ 136 info = dfl_fpga_enum_info_alloc(&pcidev->dev); 137 if (!info) 138 return -ENOMEM; 139 140 /* add irq info for enumeration if the device support irq */ 141 nvec = cci_pci_alloc_irq(pcidev); 142 if (nvec < 0) { 143 dev_err(&pcidev->dev, "Fail to alloc irq %d.\n", nvec); 144 ret = nvec; 145 goto enum_info_free_exit; 146 } else if (nvec) { 147 irq_table = cci_pci_create_irq_table(pcidev, nvec); 148 if (!irq_table) { 149 ret = -ENOMEM; 150 goto irq_free_exit; 151 } 152 153 ret = dfl_fpga_enum_info_add_irq(info, nvec, irq_table); 154 kfree(irq_table); 155 if (ret) 156 goto irq_free_exit; 157 } 158 159 /* start to find Device Feature List from Bar 0 */ 160 base = cci_pci_ioremap_bar(pcidev, 0); 161 if (!base) { 162 ret = -ENOMEM; 163 goto irq_free_exit; 164 } 165 166 /* 167 * PF device has FME and Ports/AFUs, and VF device only has one 168 * Port/AFU. Check them and add related "Device Feature List" info 169 * for the next step enumeration. 170 */ 171 if (dfl_feature_is_fme(base)) { 172 start = pci_resource_start(pcidev, 0); 173 len = pci_resource_len(pcidev, 0); 174 175 dfl_fpga_enum_info_add_dfl(info, start, len, base); 176 177 /* 178 * find more Device Feature Lists (e.g. Ports) per information 179 * indicated by FME module. 180 */ 181 v = readq(base + FME_HDR_CAP); 182 port_num = FIELD_GET(FME_CAP_NUM_PORTS, v); 183 184 WARN_ON(port_num > MAX_DFL_FPGA_PORT_NUM); 185 186 for (i = 0; i < port_num; i++) { 187 v = readq(base + FME_HDR_PORT_OFST(i)); 188 189 /* skip ports which are not implemented. */ 190 if (!(v & FME_PORT_OFST_IMP)) 191 continue; 192 193 /* 194 * add Port's Device Feature List information for next 195 * step enumeration. 196 */ 197 bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v); 198 offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v); 199 base = cci_pci_ioremap_bar(pcidev, bar); 200 if (!base) 201 continue; 202 203 start = pci_resource_start(pcidev, bar) + offset; 204 len = pci_resource_len(pcidev, bar) - offset; 205 206 dfl_fpga_enum_info_add_dfl(info, start, len, 207 base + offset); 208 } 209 } else if (dfl_feature_is_port(base)) { 210 start = pci_resource_start(pcidev, 0); 211 len = pci_resource_len(pcidev, 0); 212 213 dfl_fpga_enum_info_add_dfl(info, start, len, base); 214 } else { 215 ret = -ENODEV; 216 goto irq_free_exit; 217 } 218 219 /* start enumeration with prepared enumeration information */ 220 cdev = dfl_fpga_feature_devs_enumerate(info); 221 if (IS_ERR(cdev)) { 222 dev_err(&pcidev->dev, "Enumeration failure\n"); 223 ret = PTR_ERR(cdev); 224 goto irq_free_exit; 225 } 226 227 drvdata->cdev = cdev; 228 229 irq_free_exit: 230 if (ret) 231 cci_pci_free_irq(pcidev); 232 enum_info_free_exit: 233 dfl_fpga_enum_info_free(info); 234 235 return ret; 236 } 237 238 static 239 int cci_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *pcidevid) 240 { 241 int ret; 242 243 ret = pcim_enable_device(pcidev); 244 if (ret < 0) { 245 dev_err(&pcidev->dev, "Failed to enable device %d.\n", ret); 246 return ret; 247 } 248 249 ret = pci_enable_pcie_error_reporting(pcidev); 250 if (ret && ret != -EINVAL) 251 dev_info(&pcidev->dev, "PCIE AER unavailable %d.\n", ret); 252 253 pci_set_master(pcidev); 254 255 if (!pci_set_dma_mask(pcidev, DMA_BIT_MASK(64))) { 256 ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64)); 257 if (ret) 258 goto disable_error_report_exit; 259 } else if (!pci_set_dma_mask(pcidev, DMA_BIT_MASK(32))) { 260 ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32)); 261 if (ret) 262 goto disable_error_report_exit; 263 } else { 264 ret = -EIO; 265 dev_err(&pcidev->dev, "No suitable DMA support available.\n"); 266 goto disable_error_report_exit; 267 } 268 269 ret = cci_init_drvdata(pcidev); 270 if (ret) { 271 dev_err(&pcidev->dev, "Fail to init drvdata %d.\n", ret); 272 goto disable_error_report_exit; 273 } 274 275 ret = cci_enumerate_feature_devs(pcidev); 276 if (!ret) 277 return ret; 278 279 dev_err(&pcidev->dev, "enumeration failure %d.\n", ret); 280 281 disable_error_report_exit: 282 pci_disable_pcie_error_reporting(pcidev); 283 return ret; 284 } 285 286 static int cci_pci_sriov_configure(struct pci_dev *pcidev, int num_vfs) 287 { 288 struct cci_drvdata *drvdata = pci_get_drvdata(pcidev); 289 struct dfl_fpga_cdev *cdev = drvdata->cdev; 290 291 if (!num_vfs) { 292 /* 293 * disable SRIOV and then put released ports back to default 294 * PF access mode. 295 */ 296 pci_disable_sriov(pcidev); 297 298 dfl_fpga_cdev_config_ports_pf(cdev); 299 300 } else { 301 int ret; 302 303 /* 304 * before enable SRIOV, put released ports into VF access mode 305 * first of all. 306 */ 307 ret = dfl_fpga_cdev_config_ports_vf(cdev, num_vfs); 308 if (ret) 309 return ret; 310 311 ret = pci_enable_sriov(pcidev, num_vfs); 312 if (ret) { 313 dfl_fpga_cdev_config_ports_pf(cdev); 314 return ret; 315 } 316 } 317 318 return num_vfs; 319 } 320 321 static void cci_pci_remove(struct pci_dev *pcidev) 322 { 323 if (dev_is_pf(&pcidev->dev)) 324 cci_pci_sriov_configure(pcidev, 0); 325 326 cci_remove_feature_devs(pcidev); 327 pci_disable_pcie_error_reporting(pcidev); 328 } 329 330 static struct pci_driver cci_pci_driver = { 331 .name = DRV_NAME, 332 .id_table = cci_pcie_id_tbl, 333 .probe = cci_pci_probe, 334 .remove = cci_pci_remove, 335 .sriov_configure = cci_pci_sriov_configure, 336 }; 337 338 module_pci_driver(cci_pci_driver); 339 340 MODULE_DESCRIPTION("FPGA DFL PCIe Device Driver"); 341 MODULE_AUTHOR("Intel Corporation"); 342 MODULE_LICENSE("GPL v2"); 343