1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for FPGA Device Feature List (DFL) PCIe device 4 * 5 * Copyright (C) 2017-2018 Intel Corporation, Inc. 6 * 7 * Authors: 8 * Zhang Yi <Yi.Z.Zhang@intel.com> 9 * Xiao Guangrong <guangrong.xiao@linux.intel.com> 10 * Joseph Grecco <joe.grecco@intel.com> 11 * Enno Luebbers <enno.luebbers@intel.com> 12 * Tim Whisonant <tim.whisonant@intel.com> 13 * Ananda Ravuri <ananda.ravuri@intel.com> 14 * Henry Mitchel <henry.mitchel@intel.com> 15 */ 16 17 #include <linux/pci.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/types.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/stddef.h> 23 #include <linux/errno.h> 24 25 #include "dfl.h" 26 27 #define DRV_VERSION "0.8" 28 #define DRV_NAME "dfl-pci" 29 30 #define PCI_VSEC_ID_INTEL_DFLS 0x43 31 32 #define PCI_VNDR_DFLS_CNT 0x8 33 #define PCI_VNDR_DFLS_RES 0xc 34 35 #define PCI_VNDR_DFLS_RES_BAR_MASK GENMASK(2, 0) 36 #define PCI_VNDR_DFLS_RES_OFF_MASK GENMASK(31, 3) 37 38 struct cci_drvdata { 39 struct dfl_fpga_cdev *cdev; /* container device */ 40 }; 41 42 static void __iomem *cci_pci_ioremap_bar0(struct pci_dev *pcidev) 43 { 44 if (pcim_iomap_regions(pcidev, BIT(0), DRV_NAME)) 45 return NULL; 46 47 return pcim_iomap_table(pcidev)[0]; 48 } 49 50 static int cci_pci_alloc_irq(struct pci_dev *pcidev) 51 { 52 int ret, nvec = pci_msix_vec_count(pcidev); 53 54 if (nvec <= 0) { 55 dev_dbg(&pcidev->dev, "fpga interrupt not supported\n"); 56 return 0; 57 } 58 59 ret = pci_alloc_irq_vectors(pcidev, nvec, nvec, PCI_IRQ_MSIX); 60 if (ret < 0) 61 return ret; 62 63 return nvec; 64 } 65 66 static void cci_pci_free_irq(struct pci_dev *pcidev) 67 { 68 pci_free_irq_vectors(pcidev); 69 } 70 71 /* PCI Device ID */ 72 #define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD 73 #define PCIE_DEVICE_ID_PF_INT_6_X 0xBCC0 74 #define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4 75 #define PCIE_DEVICE_ID_INTEL_PAC_N3000 0x0B30 76 #define PCIE_DEVICE_ID_INTEL_PAC_D5005 0x0B2B 77 #define PCIE_DEVICE_ID_SILICOM_PAC_N5010 0x1000 78 #define PCIE_DEVICE_ID_SILICOM_PAC_N5011 0x1001 79 #define PCIE_DEVICE_ID_INTEL_DFL 0xbcce 80 /* PCI Subdevice ID for PCIE_DEVICE_ID_INTEL_DFL */ 81 #define PCIE_SUBDEVICE_ID_INTEL_D5005 0x138d 82 #define PCIE_SUBDEVICE_ID_INTEL_N6000 0x1770 83 #define PCIE_SUBDEVICE_ID_INTEL_N6001 0x1771 84 #define PCIE_SUBDEVICE_ID_INTEL_C6100 0x17d4 85 86 /* VF Device */ 87 #define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF 88 #define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1 89 #define PCIE_DEVICE_ID_VF_DSC_1_X 0x09C5 90 #define PCIE_DEVICE_ID_INTEL_PAC_D5005_VF 0x0B2C 91 #define PCIE_DEVICE_ID_INTEL_DFL_VF 0xbccf 92 93 static struct pci_device_id cci_pcie_id_tbl[] = { 94 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X),}, 95 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X),}, 96 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X),}, 97 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X),}, 98 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X),}, 99 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X),}, 100 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_N3000),}, 101 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005),}, 102 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005_VF),}, 103 {PCI_DEVICE(PCI_VENDOR_ID_SILICOM_DENMARK, PCIE_DEVICE_ID_SILICOM_PAC_N5010),}, 104 {PCI_DEVICE(PCI_VENDOR_ID_SILICOM_DENMARK, PCIE_DEVICE_ID_SILICOM_PAC_N5011),}, 105 {PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_DFL, 106 PCI_VENDOR_ID_INTEL, PCIE_SUBDEVICE_ID_INTEL_D5005),}, 107 {PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_DFL, 108 PCI_VENDOR_ID_INTEL, PCIE_SUBDEVICE_ID_INTEL_N6000),}, 109 {PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_DFL_VF, 110 PCI_VENDOR_ID_INTEL, PCIE_SUBDEVICE_ID_INTEL_N6000),}, 111 {PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_DFL, 112 PCI_VENDOR_ID_INTEL, PCIE_SUBDEVICE_ID_INTEL_N6001),}, 113 {PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_DFL_VF, 114 PCI_VENDOR_ID_INTEL, PCIE_SUBDEVICE_ID_INTEL_N6001),}, 115 {PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_DFL, 116 PCI_VENDOR_ID_INTEL, PCIE_SUBDEVICE_ID_INTEL_C6100),}, 117 {PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_DFL_VF, 118 PCI_VENDOR_ID_INTEL, PCIE_SUBDEVICE_ID_INTEL_C6100),}, 119 {0,} 120 }; 121 MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl); 122 123 static int cci_init_drvdata(struct pci_dev *pcidev) 124 { 125 struct cci_drvdata *drvdata; 126 127 drvdata = devm_kzalloc(&pcidev->dev, sizeof(*drvdata), GFP_KERNEL); 128 if (!drvdata) 129 return -ENOMEM; 130 131 pci_set_drvdata(pcidev, drvdata); 132 133 return 0; 134 } 135 136 static void cci_remove_feature_devs(struct pci_dev *pcidev) 137 { 138 struct cci_drvdata *drvdata = pci_get_drvdata(pcidev); 139 140 /* remove all children feature devices */ 141 dfl_fpga_feature_devs_remove(drvdata->cdev); 142 cci_pci_free_irq(pcidev); 143 } 144 145 static int *cci_pci_create_irq_table(struct pci_dev *pcidev, unsigned int nvec) 146 { 147 unsigned int i; 148 int *table; 149 150 table = kcalloc(nvec, sizeof(int), GFP_KERNEL); 151 if (!table) 152 return table; 153 154 for (i = 0; i < nvec; i++) 155 table[i] = pci_irq_vector(pcidev, i); 156 157 return table; 158 } 159 160 static int find_dfls_by_vsec(struct pci_dev *pcidev, struct dfl_fpga_enum_info *info) 161 { 162 u32 bir, offset, dfl_cnt, dfl_res; 163 int dfl_res_off, i, bars, voff; 164 resource_size_t start, len; 165 166 voff = pci_find_vsec_capability(pcidev, PCI_VENDOR_ID_INTEL, 167 PCI_VSEC_ID_INTEL_DFLS); 168 if (!voff) { 169 dev_dbg(&pcidev->dev, "%s no DFL VSEC found\n", __func__); 170 return -ENODEV; 171 } 172 173 dfl_cnt = 0; 174 pci_read_config_dword(pcidev, voff + PCI_VNDR_DFLS_CNT, &dfl_cnt); 175 if (dfl_cnt > PCI_STD_NUM_BARS) { 176 dev_err(&pcidev->dev, "%s too many DFLs %d > %d\n", 177 __func__, dfl_cnt, PCI_STD_NUM_BARS); 178 return -EINVAL; 179 } 180 181 dfl_res_off = voff + PCI_VNDR_DFLS_RES; 182 if (dfl_res_off + (dfl_cnt * sizeof(u32)) > PCI_CFG_SPACE_EXP_SIZE) { 183 dev_err(&pcidev->dev, "%s DFL VSEC too big for PCIe config space\n", 184 __func__); 185 return -EINVAL; 186 } 187 188 for (i = 0, bars = 0; i < dfl_cnt; i++, dfl_res_off += sizeof(u32)) { 189 dfl_res = GENMASK(31, 0); 190 pci_read_config_dword(pcidev, dfl_res_off, &dfl_res); 191 192 bir = dfl_res & PCI_VNDR_DFLS_RES_BAR_MASK; 193 if (bir >= PCI_STD_NUM_BARS) { 194 dev_err(&pcidev->dev, "%s bad bir number %d\n", 195 __func__, bir); 196 return -EINVAL; 197 } 198 199 if (bars & BIT(bir)) { 200 dev_err(&pcidev->dev, "%s DFL for BAR %d already specified\n", 201 __func__, bir); 202 return -EINVAL; 203 } 204 205 bars |= BIT(bir); 206 207 len = pci_resource_len(pcidev, bir); 208 offset = dfl_res & PCI_VNDR_DFLS_RES_OFF_MASK; 209 if (offset >= len) { 210 dev_err(&pcidev->dev, "%s bad offset %u >= %pa\n", 211 __func__, offset, &len); 212 return -EINVAL; 213 } 214 215 dev_dbg(&pcidev->dev, "%s BAR %d offset 0x%x\n", __func__, bir, offset); 216 217 len -= offset; 218 219 start = pci_resource_start(pcidev, bir) + offset; 220 221 dfl_fpga_enum_info_add_dfl(info, start, len); 222 } 223 224 return 0; 225 } 226 227 /* default method of finding dfls starting at offset 0 of bar 0 */ 228 static int find_dfls_by_default(struct pci_dev *pcidev, 229 struct dfl_fpga_enum_info *info) 230 { 231 int port_num, bar, i, ret = 0; 232 resource_size_t start, len; 233 void __iomem *base; 234 u32 offset; 235 u64 v; 236 237 /* start to find Device Feature List from Bar 0 */ 238 base = cci_pci_ioremap_bar0(pcidev); 239 if (!base) 240 return -ENOMEM; 241 242 /* 243 * PF device has FME and Ports/AFUs, and VF device only has one 244 * Port/AFU. Check them and add related "Device Feature List" info 245 * for the next step enumeration. 246 */ 247 if (dfl_feature_is_fme(base)) { 248 start = pci_resource_start(pcidev, 0); 249 len = pci_resource_len(pcidev, 0); 250 251 dfl_fpga_enum_info_add_dfl(info, start, len); 252 253 /* 254 * find more Device Feature Lists (e.g. Ports) per information 255 * indicated by FME module. 256 */ 257 v = readq(base + FME_HDR_CAP); 258 port_num = FIELD_GET(FME_CAP_NUM_PORTS, v); 259 260 WARN_ON(port_num > MAX_DFL_FPGA_PORT_NUM); 261 262 for (i = 0; i < port_num; i++) { 263 v = readq(base + FME_HDR_PORT_OFST(i)); 264 265 /* skip ports which are not implemented. */ 266 if (!(v & FME_PORT_OFST_IMP)) 267 continue; 268 269 /* 270 * add Port's Device Feature List information for next 271 * step enumeration. 272 */ 273 bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v); 274 offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v); 275 if (bar == FME_PORT_OFST_BAR_SKIP) { 276 continue; 277 } else if (bar >= PCI_STD_NUM_BARS) { 278 dev_err(&pcidev->dev, "bad BAR %d for port %d\n", 279 bar, i); 280 ret = -EINVAL; 281 break; 282 } 283 284 start = pci_resource_start(pcidev, bar) + offset; 285 len = pci_resource_len(pcidev, bar) - offset; 286 287 dfl_fpga_enum_info_add_dfl(info, start, len); 288 } 289 } else if (dfl_feature_is_port(base)) { 290 start = pci_resource_start(pcidev, 0); 291 len = pci_resource_len(pcidev, 0); 292 293 dfl_fpga_enum_info_add_dfl(info, start, len); 294 } else { 295 ret = -ENODEV; 296 } 297 298 /* release I/O mappings for next step enumeration */ 299 pcim_iounmap_regions(pcidev, BIT(0)); 300 301 return ret; 302 } 303 304 /* enumerate feature devices under pci device */ 305 static int cci_enumerate_feature_devs(struct pci_dev *pcidev) 306 { 307 struct cci_drvdata *drvdata = pci_get_drvdata(pcidev); 308 struct dfl_fpga_enum_info *info; 309 struct dfl_fpga_cdev *cdev; 310 int nvec, ret = 0; 311 int *irq_table; 312 313 /* allocate enumeration info via pci_dev */ 314 info = dfl_fpga_enum_info_alloc(&pcidev->dev); 315 if (!info) 316 return -ENOMEM; 317 318 /* add irq info for enumeration if the device support irq */ 319 nvec = cci_pci_alloc_irq(pcidev); 320 if (nvec < 0) { 321 dev_err(&pcidev->dev, "Fail to alloc irq %d.\n", nvec); 322 ret = nvec; 323 goto enum_info_free_exit; 324 } else if (nvec) { 325 irq_table = cci_pci_create_irq_table(pcidev, nvec); 326 if (!irq_table) { 327 ret = -ENOMEM; 328 goto irq_free_exit; 329 } 330 331 ret = dfl_fpga_enum_info_add_irq(info, nvec, irq_table); 332 kfree(irq_table); 333 if (ret) 334 goto irq_free_exit; 335 } 336 337 ret = find_dfls_by_vsec(pcidev, info); 338 if (ret == -ENODEV) 339 ret = find_dfls_by_default(pcidev, info); 340 341 if (ret) 342 goto irq_free_exit; 343 344 /* start enumeration with prepared enumeration information */ 345 cdev = dfl_fpga_feature_devs_enumerate(info); 346 if (IS_ERR(cdev)) { 347 dev_err(&pcidev->dev, "Enumeration failure\n"); 348 ret = PTR_ERR(cdev); 349 goto irq_free_exit; 350 } 351 352 drvdata->cdev = cdev; 353 354 irq_free_exit: 355 if (ret) 356 cci_pci_free_irq(pcidev); 357 enum_info_free_exit: 358 dfl_fpga_enum_info_free(info); 359 360 return ret; 361 } 362 363 static 364 int cci_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *pcidevid) 365 { 366 int ret; 367 368 ret = pcim_enable_device(pcidev); 369 if (ret < 0) { 370 dev_err(&pcidev->dev, "Failed to enable device %d.\n", ret); 371 return ret; 372 } 373 374 pci_set_master(pcidev); 375 376 ret = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(64)); 377 if (ret) 378 ret = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32)); 379 if (ret) { 380 dev_err(&pcidev->dev, "No suitable DMA support available.\n"); 381 return ret; 382 } 383 384 ret = cci_init_drvdata(pcidev); 385 if (ret) { 386 dev_err(&pcidev->dev, "Fail to init drvdata %d.\n", ret); 387 return ret; 388 } 389 390 ret = cci_enumerate_feature_devs(pcidev); 391 if (ret) { 392 dev_err(&pcidev->dev, "enumeration failure %d.\n", ret); 393 return ret; 394 } 395 396 return 0; 397 } 398 399 static int cci_pci_sriov_configure(struct pci_dev *pcidev, int num_vfs) 400 { 401 struct cci_drvdata *drvdata = pci_get_drvdata(pcidev); 402 struct dfl_fpga_cdev *cdev = drvdata->cdev; 403 404 if (!num_vfs) { 405 /* 406 * disable SRIOV and then put released ports back to default 407 * PF access mode. 408 */ 409 pci_disable_sriov(pcidev); 410 411 dfl_fpga_cdev_config_ports_pf(cdev); 412 413 } else { 414 int ret; 415 416 /* 417 * before enable SRIOV, put released ports into VF access mode 418 * first of all. 419 */ 420 ret = dfl_fpga_cdev_config_ports_vf(cdev, num_vfs); 421 if (ret) 422 return ret; 423 424 ret = pci_enable_sriov(pcidev, num_vfs); 425 if (ret) { 426 dfl_fpga_cdev_config_ports_pf(cdev); 427 return ret; 428 } 429 } 430 431 return num_vfs; 432 } 433 434 static void cci_pci_remove(struct pci_dev *pcidev) 435 { 436 if (dev_is_pf(&pcidev->dev)) 437 cci_pci_sriov_configure(pcidev, 0); 438 439 cci_remove_feature_devs(pcidev); 440 } 441 442 static struct pci_driver cci_pci_driver = { 443 .name = DRV_NAME, 444 .id_table = cci_pcie_id_tbl, 445 .probe = cci_pci_probe, 446 .remove = cci_pci_remove, 447 .sriov_configure = cci_pci_sriov_configure, 448 }; 449 450 module_pci_driver(cci_pci_driver); 451 452 MODULE_DESCRIPTION("FPGA DFL PCIe Device Driver"); 453 MODULE_AUTHOR("Intel Corporation"); 454 MODULE_LICENSE("GPL v2"); 455