1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for FPGA Device Feature List (DFL) PCIe device 4 * 5 * Copyright (C) 2017-2018 Intel Corporation, Inc. 6 * 7 * Authors: 8 * Zhang Yi <Yi.Z.Zhang@intel.com> 9 * Xiao Guangrong <guangrong.xiao@linux.intel.com> 10 * Joseph Grecco <joe.grecco@intel.com> 11 * Enno Luebbers <enno.luebbers@intel.com> 12 * Tim Whisonant <tim.whisonant@intel.com> 13 * Ananda Ravuri <ananda.ravuri@intel.com> 14 * Henry Mitchel <henry.mitchel@intel.com> 15 */ 16 17 #include <linux/pci.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/types.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/stddef.h> 23 #include <linux/errno.h> 24 #include <linux/aer.h> 25 26 #include "dfl.h" 27 28 #define DRV_VERSION "0.8" 29 #define DRV_NAME "dfl-pci" 30 31 #define PCI_VSEC_ID_INTEL_DFLS 0x43 32 33 #define PCI_VNDR_DFLS_CNT 0x8 34 #define PCI_VNDR_DFLS_RES 0xc 35 36 #define PCI_VNDR_DFLS_RES_BAR_MASK GENMASK(2, 0) 37 #define PCI_VNDR_DFLS_RES_OFF_MASK GENMASK(31, 3) 38 39 struct cci_drvdata { 40 struct dfl_fpga_cdev *cdev; /* container device */ 41 }; 42 43 static void __iomem *cci_pci_ioremap_bar0(struct pci_dev *pcidev) 44 { 45 if (pcim_iomap_regions(pcidev, BIT(0), DRV_NAME)) 46 return NULL; 47 48 return pcim_iomap_table(pcidev)[0]; 49 } 50 51 static int cci_pci_alloc_irq(struct pci_dev *pcidev) 52 { 53 int ret, nvec = pci_msix_vec_count(pcidev); 54 55 if (nvec <= 0) { 56 dev_dbg(&pcidev->dev, "fpga interrupt not supported\n"); 57 return 0; 58 } 59 60 ret = pci_alloc_irq_vectors(pcidev, nvec, nvec, PCI_IRQ_MSIX); 61 if (ret < 0) 62 return ret; 63 64 return nvec; 65 } 66 67 static void cci_pci_free_irq(struct pci_dev *pcidev) 68 { 69 pci_free_irq_vectors(pcidev); 70 } 71 72 /* PCI Device ID */ 73 #define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD 74 #define PCIE_DEVICE_ID_PF_INT_6_X 0xBCC0 75 #define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4 76 #define PCIE_DEVICE_ID_INTEL_PAC_N3000 0x0B30 77 #define PCIE_DEVICE_ID_INTEL_PAC_D5005 0x0B2B 78 #define PCIE_DEVICE_ID_SILICOM_PAC_N5010 0x1000 79 #define PCIE_DEVICE_ID_SILICOM_PAC_N5011 0x1001 80 81 /* VF Device */ 82 #define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF 83 #define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1 84 #define PCIE_DEVICE_ID_VF_DSC_1_X 0x09C5 85 #define PCIE_DEVICE_ID_INTEL_PAC_D5005_VF 0x0B2C 86 87 static struct pci_device_id cci_pcie_id_tbl[] = { 88 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X),}, 89 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X),}, 90 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X),}, 91 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X),}, 92 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X),}, 93 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X),}, 94 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_N3000),}, 95 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005),}, 96 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005_VF),}, 97 {PCI_DEVICE(PCI_VENDOR_ID_SILICOM_DENMARK, PCIE_DEVICE_ID_SILICOM_PAC_N5010),}, 98 {PCI_DEVICE(PCI_VENDOR_ID_SILICOM_DENMARK, PCIE_DEVICE_ID_SILICOM_PAC_N5011),}, 99 {0,} 100 }; 101 MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl); 102 103 static int cci_init_drvdata(struct pci_dev *pcidev) 104 { 105 struct cci_drvdata *drvdata; 106 107 drvdata = devm_kzalloc(&pcidev->dev, sizeof(*drvdata), GFP_KERNEL); 108 if (!drvdata) 109 return -ENOMEM; 110 111 pci_set_drvdata(pcidev, drvdata); 112 113 return 0; 114 } 115 116 static void cci_remove_feature_devs(struct pci_dev *pcidev) 117 { 118 struct cci_drvdata *drvdata = pci_get_drvdata(pcidev); 119 120 /* remove all children feature devices */ 121 dfl_fpga_feature_devs_remove(drvdata->cdev); 122 cci_pci_free_irq(pcidev); 123 } 124 125 static int *cci_pci_create_irq_table(struct pci_dev *pcidev, unsigned int nvec) 126 { 127 unsigned int i; 128 int *table; 129 130 table = kcalloc(nvec, sizeof(int), GFP_KERNEL); 131 if (!table) 132 return table; 133 134 for (i = 0; i < nvec; i++) 135 table[i] = pci_irq_vector(pcidev, i); 136 137 return table; 138 } 139 140 static int find_dfls_by_vsec(struct pci_dev *pcidev, struct dfl_fpga_enum_info *info) 141 { 142 u32 bir, offset, vndr_hdr, dfl_cnt, dfl_res; 143 int dfl_res_off, i, bars, voff = 0; 144 resource_size_t start, len; 145 146 while ((voff = pci_find_next_ext_capability(pcidev, voff, PCI_EXT_CAP_ID_VNDR))) { 147 vndr_hdr = 0; 148 pci_read_config_dword(pcidev, voff + PCI_VNDR_HEADER, &vndr_hdr); 149 150 if (PCI_VNDR_HEADER_ID(vndr_hdr) == PCI_VSEC_ID_INTEL_DFLS && 151 pcidev->vendor == PCI_VENDOR_ID_INTEL) 152 break; 153 } 154 155 if (!voff) { 156 dev_dbg(&pcidev->dev, "%s no DFL VSEC found\n", __func__); 157 return -ENODEV; 158 } 159 160 dfl_cnt = 0; 161 pci_read_config_dword(pcidev, voff + PCI_VNDR_DFLS_CNT, &dfl_cnt); 162 if (dfl_cnt > PCI_STD_NUM_BARS) { 163 dev_err(&pcidev->dev, "%s too many DFLs %d > %d\n", 164 __func__, dfl_cnt, PCI_STD_NUM_BARS); 165 return -EINVAL; 166 } 167 168 dfl_res_off = voff + PCI_VNDR_DFLS_RES; 169 if (dfl_res_off + (dfl_cnt * sizeof(u32)) > PCI_CFG_SPACE_EXP_SIZE) { 170 dev_err(&pcidev->dev, "%s DFL VSEC too big for PCIe config space\n", 171 __func__); 172 return -EINVAL; 173 } 174 175 for (i = 0, bars = 0; i < dfl_cnt; i++, dfl_res_off += sizeof(u32)) { 176 dfl_res = GENMASK(31, 0); 177 pci_read_config_dword(pcidev, dfl_res_off, &dfl_res); 178 179 bir = dfl_res & PCI_VNDR_DFLS_RES_BAR_MASK; 180 if (bir >= PCI_STD_NUM_BARS) { 181 dev_err(&pcidev->dev, "%s bad bir number %d\n", 182 __func__, bir); 183 return -EINVAL; 184 } 185 186 if (bars & BIT(bir)) { 187 dev_err(&pcidev->dev, "%s DFL for BAR %d already specified\n", 188 __func__, bir); 189 return -EINVAL; 190 } 191 192 bars |= BIT(bir); 193 194 len = pci_resource_len(pcidev, bir); 195 offset = dfl_res & PCI_VNDR_DFLS_RES_OFF_MASK; 196 if (offset >= len) { 197 dev_err(&pcidev->dev, "%s bad offset %u >= %pa\n", 198 __func__, offset, &len); 199 return -EINVAL; 200 } 201 202 dev_dbg(&pcidev->dev, "%s BAR %d offset 0x%x\n", __func__, bir, offset); 203 204 len -= offset; 205 206 start = pci_resource_start(pcidev, bir) + offset; 207 208 dfl_fpga_enum_info_add_dfl(info, start, len); 209 } 210 211 return 0; 212 } 213 214 /* default method of finding dfls starting at offset 0 of bar 0 */ 215 static int find_dfls_by_default(struct pci_dev *pcidev, 216 struct dfl_fpga_enum_info *info) 217 { 218 int port_num, bar, i, ret = 0; 219 resource_size_t start, len; 220 void __iomem *base; 221 u32 offset; 222 u64 v; 223 224 /* start to find Device Feature List from Bar 0 */ 225 base = cci_pci_ioremap_bar0(pcidev); 226 if (!base) 227 return -ENOMEM; 228 229 /* 230 * PF device has FME and Ports/AFUs, and VF device only has one 231 * Port/AFU. Check them and add related "Device Feature List" info 232 * for the next step enumeration. 233 */ 234 if (dfl_feature_is_fme(base)) { 235 start = pci_resource_start(pcidev, 0); 236 len = pci_resource_len(pcidev, 0); 237 238 dfl_fpga_enum_info_add_dfl(info, start, len); 239 240 /* 241 * find more Device Feature Lists (e.g. Ports) per information 242 * indicated by FME module. 243 */ 244 v = readq(base + FME_HDR_CAP); 245 port_num = FIELD_GET(FME_CAP_NUM_PORTS, v); 246 247 WARN_ON(port_num > MAX_DFL_FPGA_PORT_NUM); 248 249 for (i = 0; i < port_num; i++) { 250 v = readq(base + FME_HDR_PORT_OFST(i)); 251 252 /* skip ports which are not implemented. */ 253 if (!(v & FME_PORT_OFST_IMP)) 254 continue; 255 256 /* 257 * add Port's Device Feature List information for next 258 * step enumeration. 259 */ 260 bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v); 261 offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v); 262 if (bar == FME_PORT_OFST_BAR_SKIP) { 263 continue; 264 } else if (bar >= PCI_STD_NUM_BARS) { 265 dev_err(&pcidev->dev, "bad BAR %d for port %d\n", 266 bar, i); 267 ret = -EINVAL; 268 break; 269 } 270 271 start = pci_resource_start(pcidev, bar) + offset; 272 len = pci_resource_len(pcidev, bar) - offset; 273 274 dfl_fpga_enum_info_add_dfl(info, start, len); 275 } 276 } else if (dfl_feature_is_port(base)) { 277 start = pci_resource_start(pcidev, 0); 278 len = pci_resource_len(pcidev, 0); 279 280 dfl_fpga_enum_info_add_dfl(info, start, len); 281 } else { 282 ret = -ENODEV; 283 } 284 285 /* release I/O mappings for next step enumeration */ 286 pcim_iounmap_regions(pcidev, BIT(0)); 287 288 return ret; 289 } 290 291 /* enumerate feature devices under pci device */ 292 static int cci_enumerate_feature_devs(struct pci_dev *pcidev) 293 { 294 struct cci_drvdata *drvdata = pci_get_drvdata(pcidev); 295 struct dfl_fpga_enum_info *info; 296 struct dfl_fpga_cdev *cdev; 297 int nvec, ret = 0; 298 int *irq_table; 299 300 /* allocate enumeration info via pci_dev */ 301 info = dfl_fpga_enum_info_alloc(&pcidev->dev); 302 if (!info) 303 return -ENOMEM; 304 305 /* add irq info for enumeration if the device support irq */ 306 nvec = cci_pci_alloc_irq(pcidev); 307 if (nvec < 0) { 308 dev_err(&pcidev->dev, "Fail to alloc irq %d.\n", nvec); 309 ret = nvec; 310 goto enum_info_free_exit; 311 } else if (nvec) { 312 irq_table = cci_pci_create_irq_table(pcidev, nvec); 313 if (!irq_table) { 314 ret = -ENOMEM; 315 goto irq_free_exit; 316 } 317 318 ret = dfl_fpga_enum_info_add_irq(info, nvec, irq_table); 319 kfree(irq_table); 320 if (ret) 321 goto irq_free_exit; 322 } 323 324 ret = find_dfls_by_vsec(pcidev, info); 325 if (ret == -ENODEV) 326 ret = find_dfls_by_default(pcidev, info); 327 328 if (ret) 329 goto irq_free_exit; 330 331 /* start enumeration with prepared enumeration information */ 332 cdev = dfl_fpga_feature_devs_enumerate(info); 333 if (IS_ERR(cdev)) { 334 dev_err(&pcidev->dev, "Enumeration failure\n"); 335 ret = PTR_ERR(cdev); 336 goto irq_free_exit; 337 } 338 339 drvdata->cdev = cdev; 340 341 irq_free_exit: 342 if (ret) 343 cci_pci_free_irq(pcidev); 344 enum_info_free_exit: 345 dfl_fpga_enum_info_free(info); 346 347 return ret; 348 } 349 350 static 351 int cci_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *pcidevid) 352 { 353 int ret; 354 355 ret = pcim_enable_device(pcidev); 356 if (ret < 0) { 357 dev_err(&pcidev->dev, "Failed to enable device %d.\n", ret); 358 return ret; 359 } 360 361 ret = pci_enable_pcie_error_reporting(pcidev); 362 if (ret && ret != -EINVAL) 363 dev_info(&pcidev->dev, "PCIE AER unavailable %d.\n", ret); 364 365 pci_set_master(pcidev); 366 367 ret = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(64)); 368 if (ret) 369 ret = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32)); 370 if (ret) { 371 dev_err(&pcidev->dev, "No suitable DMA support available.\n"); 372 goto disable_error_report_exit; 373 } 374 375 ret = cci_init_drvdata(pcidev); 376 if (ret) { 377 dev_err(&pcidev->dev, "Fail to init drvdata %d.\n", ret); 378 goto disable_error_report_exit; 379 } 380 381 ret = cci_enumerate_feature_devs(pcidev); 382 if (!ret) 383 return ret; 384 385 dev_err(&pcidev->dev, "enumeration failure %d.\n", ret); 386 387 disable_error_report_exit: 388 pci_disable_pcie_error_reporting(pcidev); 389 return ret; 390 } 391 392 static int cci_pci_sriov_configure(struct pci_dev *pcidev, int num_vfs) 393 { 394 struct cci_drvdata *drvdata = pci_get_drvdata(pcidev); 395 struct dfl_fpga_cdev *cdev = drvdata->cdev; 396 397 if (!num_vfs) { 398 /* 399 * disable SRIOV and then put released ports back to default 400 * PF access mode. 401 */ 402 pci_disable_sriov(pcidev); 403 404 dfl_fpga_cdev_config_ports_pf(cdev); 405 406 } else { 407 int ret; 408 409 /* 410 * before enable SRIOV, put released ports into VF access mode 411 * first of all. 412 */ 413 ret = dfl_fpga_cdev_config_ports_vf(cdev, num_vfs); 414 if (ret) 415 return ret; 416 417 ret = pci_enable_sriov(pcidev, num_vfs); 418 if (ret) { 419 dfl_fpga_cdev_config_ports_pf(cdev); 420 return ret; 421 } 422 } 423 424 return num_vfs; 425 } 426 427 static void cci_pci_remove(struct pci_dev *pcidev) 428 { 429 if (dev_is_pf(&pcidev->dev)) 430 cci_pci_sriov_configure(pcidev, 0); 431 432 cci_remove_feature_devs(pcidev); 433 pci_disable_pcie_error_reporting(pcidev); 434 } 435 436 static struct pci_driver cci_pci_driver = { 437 .name = DRV_NAME, 438 .id_table = cci_pcie_id_tbl, 439 .probe = cci_pci_probe, 440 .remove = cci_pci_remove, 441 .sriov_configure = cci_pci_sriov_configure, 442 }; 443 444 module_pci_driver(cci_pci_driver); 445 446 MODULE_DESCRIPTION("FPGA DFL PCIe Device Driver"); 447 MODULE_AUTHOR("Intel Corporation"); 448 MODULE_LICENSE("GPL v2"); 449