1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Header file for FPGA Management Engine (FME) Driver 4 * 5 * Copyright (C) 2017-2018 Intel Corporation, Inc. 6 * 7 * Authors: 8 * Kang Luwei <luwei.kang@intel.com> 9 * Xiao Guangrong <guangrong.xiao@linux.intel.com> 10 * Wu Hao <hao.wu@intel.com> 11 * Joseph Grecco <joe.grecco@intel.com> 12 * Enno Luebbers <enno.luebbers@intel.com> 13 * Tim Whisonant <tim.whisonant@intel.com> 14 * Ananda Ravuri <ananda.ravuri@intel.com> 15 * Henry Mitchel <henry.mitchel@intel.com> 16 */ 17 18 #ifndef __DFL_FME_H 19 #define __DFL_FME_H 20 21 /** 22 * struct dfl_fme - dfl fme private data 23 * 24 * @mgr: FME's FPGA manager platform device. 25 * @region_list: linked list of FME's FPGA regions. 26 * @bridge_list: linked list of FME's FPGA bridges. 27 * @pdata: fme platform device's pdata. 28 */ 29 struct dfl_fme { 30 struct platform_device *mgr; 31 struct list_head region_list; 32 struct list_head bridge_list; 33 struct dfl_feature_platform_data *pdata; 34 }; 35 36 extern const struct dfl_feature_ops pr_mgmt_ops; 37 38 #endif /* __DFL_FME_H */ 39