1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for FPGA Accelerated Function Unit (AFU) 4 * 5 * Copyright (C) 2017-2018 Intel Corporation, Inc. 6 * 7 * Authors: 8 * Wu Hao <hao.wu@intel.com> 9 * Xiao Guangrong <guangrong.xiao@linux.intel.com> 10 * Joseph Grecco <joe.grecco@intel.com> 11 * Enno Luebbers <enno.luebbers@intel.com> 12 * Tim Whisonant <tim.whisonant@intel.com> 13 * Ananda Ravuri <ananda.ravuri@intel.com> 14 * Henry Mitchel <henry.mitchel@intel.com> 15 */ 16 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/uaccess.h> 20 #include <linux/fpga-dfl.h> 21 22 #include "dfl-afu.h" 23 24 /** 25 * __afu_port_enable - enable a port by clear reset 26 * @pdev: port platform device. 27 * 28 * Enable Port by clear the port soft reset bit, which is set by default. 29 * The AFU is unable to respond to any MMIO access while in reset. 30 * __afu_port_enable function should only be used after __afu_port_disable 31 * function. 32 * 33 * The caller needs to hold lock for protection. 34 */ 35 void __afu_port_enable(struct platform_device *pdev) 36 { 37 struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev); 38 void __iomem *base; 39 u64 v; 40 41 WARN_ON(!pdata->disable_count); 42 43 if (--pdata->disable_count != 0) 44 return; 45 46 base = dfl_get_feature_ioaddr_by_id(&pdev->dev, PORT_FEATURE_ID_HEADER); 47 48 /* Clear port soft reset */ 49 v = readq(base + PORT_HDR_CTRL); 50 v &= ~PORT_CTRL_SFTRST; 51 writeq(v, base + PORT_HDR_CTRL); 52 } 53 54 #define RST_POLL_INVL 10 /* us */ 55 #define RST_POLL_TIMEOUT 1000 /* us */ 56 57 /** 58 * __afu_port_disable - disable a port by hold reset 59 * @pdev: port platform device. 60 * 61 * Disable Port by setting the port soft reset bit, it puts the port into reset. 62 * 63 * The caller needs to hold lock for protection. 64 */ 65 int __afu_port_disable(struct platform_device *pdev) 66 { 67 struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev); 68 void __iomem *base; 69 u64 v; 70 71 if (pdata->disable_count++ != 0) 72 return 0; 73 74 base = dfl_get_feature_ioaddr_by_id(&pdev->dev, PORT_FEATURE_ID_HEADER); 75 76 /* Set port soft reset */ 77 v = readq(base + PORT_HDR_CTRL); 78 v |= PORT_CTRL_SFTRST; 79 writeq(v, base + PORT_HDR_CTRL); 80 81 /* 82 * HW sets ack bit to 1 when all outstanding requests have been drained 83 * on this port and minimum soft reset pulse width has elapsed. 84 * Driver polls port_soft_reset_ack to determine if reset done by HW. 85 */ 86 if (readq_poll_timeout(base + PORT_HDR_CTRL, v, 87 v & PORT_CTRL_SFTRST_ACK, 88 RST_POLL_INVL, RST_POLL_TIMEOUT)) { 89 dev_err(&pdev->dev, "timeout, fail to reset device\n"); 90 return -ETIMEDOUT; 91 } 92 93 return 0; 94 } 95 96 /* 97 * This function resets the FPGA Port and its accelerator (AFU) by function 98 * __port_disable and __port_enable (set port soft reset bit and then clear 99 * it). Userspace can do Port reset at any time, e.g. during DMA or Partial 100 * Reconfiguration. But it should never cause any system level issue, only 101 * functional failure (e.g. DMA or PR operation failure) and be recoverable 102 * from the failure. 103 * 104 * Note: the accelerator (AFU) is not accessible when its port is in reset 105 * (disabled). Any attempts on MMIO access to AFU while in reset, will 106 * result errors reported via port error reporting sub feature (if present). 107 */ 108 static int __port_reset(struct platform_device *pdev) 109 { 110 int ret; 111 112 ret = __afu_port_disable(pdev); 113 if (!ret) 114 __afu_port_enable(pdev); 115 116 return ret; 117 } 118 119 static int port_reset(struct platform_device *pdev) 120 { 121 struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev); 122 int ret; 123 124 mutex_lock(&pdata->lock); 125 ret = __port_reset(pdev); 126 mutex_unlock(&pdata->lock); 127 128 return ret; 129 } 130 131 static int port_get_id(struct platform_device *pdev) 132 { 133 void __iomem *base; 134 135 base = dfl_get_feature_ioaddr_by_id(&pdev->dev, PORT_FEATURE_ID_HEADER); 136 137 return FIELD_GET(PORT_CAP_PORT_NUM, readq(base + PORT_HDR_CAP)); 138 } 139 140 static ssize_t 141 id_show(struct device *dev, struct device_attribute *attr, char *buf) 142 { 143 int id = port_get_id(to_platform_device(dev)); 144 145 return scnprintf(buf, PAGE_SIZE, "%d\n", id); 146 } 147 static DEVICE_ATTR_RO(id); 148 149 static ssize_t 150 ltr_show(struct device *dev, struct device_attribute *attr, char *buf) 151 { 152 struct dfl_feature_platform_data *pdata = dev_get_platdata(dev); 153 void __iomem *base; 154 u64 v; 155 156 base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER); 157 158 mutex_lock(&pdata->lock); 159 v = readq(base + PORT_HDR_CTRL); 160 mutex_unlock(&pdata->lock); 161 162 return sprintf(buf, "%x\n", (u8)FIELD_GET(PORT_CTRL_LATENCY, v)); 163 } 164 165 static ssize_t 166 ltr_store(struct device *dev, struct device_attribute *attr, 167 const char *buf, size_t count) 168 { 169 struct dfl_feature_platform_data *pdata = dev_get_platdata(dev); 170 void __iomem *base; 171 bool ltr; 172 u64 v; 173 174 if (kstrtobool(buf, <r)) 175 return -EINVAL; 176 177 base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER); 178 179 mutex_lock(&pdata->lock); 180 v = readq(base + PORT_HDR_CTRL); 181 v &= ~PORT_CTRL_LATENCY; 182 v |= FIELD_PREP(PORT_CTRL_LATENCY, ltr ? 1 : 0); 183 writeq(v, base + PORT_HDR_CTRL); 184 mutex_unlock(&pdata->lock); 185 186 return count; 187 } 188 static DEVICE_ATTR_RW(ltr); 189 190 static ssize_t 191 ap1_event_show(struct device *dev, struct device_attribute *attr, char *buf) 192 { 193 struct dfl_feature_platform_data *pdata = dev_get_platdata(dev); 194 void __iomem *base; 195 u64 v; 196 197 base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER); 198 199 mutex_lock(&pdata->lock); 200 v = readq(base + PORT_HDR_STS); 201 mutex_unlock(&pdata->lock); 202 203 return sprintf(buf, "%x\n", (u8)FIELD_GET(PORT_STS_AP1_EVT, v)); 204 } 205 206 static ssize_t 207 ap1_event_store(struct device *dev, struct device_attribute *attr, 208 const char *buf, size_t count) 209 { 210 struct dfl_feature_platform_data *pdata = dev_get_platdata(dev); 211 void __iomem *base; 212 bool clear; 213 214 if (kstrtobool(buf, &clear) || !clear) 215 return -EINVAL; 216 217 base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER); 218 219 mutex_lock(&pdata->lock); 220 writeq(PORT_STS_AP1_EVT, base + PORT_HDR_STS); 221 mutex_unlock(&pdata->lock); 222 223 return count; 224 } 225 static DEVICE_ATTR_RW(ap1_event); 226 227 static ssize_t 228 ap2_event_show(struct device *dev, struct device_attribute *attr, 229 char *buf) 230 { 231 struct dfl_feature_platform_data *pdata = dev_get_platdata(dev); 232 void __iomem *base; 233 u64 v; 234 235 base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER); 236 237 mutex_lock(&pdata->lock); 238 v = readq(base + PORT_HDR_STS); 239 mutex_unlock(&pdata->lock); 240 241 return sprintf(buf, "%x\n", (u8)FIELD_GET(PORT_STS_AP2_EVT, v)); 242 } 243 244 static ssize_t 245 ap2_event_store(struct device *dev, struct device_attribute *attr, 246 const char *buf, size_t count) 247 { 248 struct dfl_feature_platform_data *pdata = dev_get_platdata(dev); 249 void __iomem *base; 250 bool clear; 251 252 if (kstrtobool(buf, &clear) || !clear) 253 return -EINVAL; 254 255 base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER); 256 257 mutex_lock(&pdata->lock); 258 writeq(PORT_STS_AP2_EVT, base + PORT_HDR_STS); 259 mutex_unlock(&pdata->lock); 260 261 return count; 262 } 263 static DEVICE_ATTR_RW(ap2_event); 264 265 static ssize_t 266 power_state_show(struct device *dev, struct device_attribute *attr, char *buf) 267 { 268 struct dfl_feature_platform_data *pdata = dev_get_platdata(dev); 269 void __iomem *base; 270 u64 v; 271 272 base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER); 273 274 mutex_lock(&pdata->lock); 275 v = readq(base + PORT_HDR_STS); 276 mutex_unlock(&pdata->lock); 277 278 return sprintf(buf, "0x%x\n", (u8)FIELD_GET(PORT_STS_PWR_STATE, v)); 279 } 280 static DEVICE_ATTR_RO(power_state); 281 282 static ssize_t 283 userclk_freqcmd_store(struct device *dev, struct device_attribute *attr, 284 const char *buf, size_t count) 285 { 286 struct dfl_feature_platform_data *pdata = dev_get_platdata(dev); 287 u64 userclk_freq_cmd; 288 void __iomem *base; 289 290 if (kstrtou64(buf, 0, &userclk_freq_cmd)) 291 return -EINVAL; 292 293 base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER); 294 295 mutex_lock(&pdata->lock); 296 writeq(userclk_freq_cmd, base + PORT_HDR_USRCLK_CMD0); 297 mutex_unlock(&pdata->lock); 298 299 return count; 300 } 301 static DEVICE_ATTR_WO(userclk_freqcmd); 302 303 static ssize_t 304 userclk_freqcntrcmd_store(struct device *dev, struct device_attribute *attr, 305 const char *buf, size_t count) 306 { 307 struct dfl_feature_platform_data *pdata = dev_get_platdata(dev); 308 u64 userclk_freqcntr_cmd; 309 void __iomem *base; 310 311 if (kstrtou64(buf, 0, &userclk_freqcntr_cmd)) 312 return -EINVAL; 313 314 base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER); 315 316 mutex_lock(&pdata->lock); 317 writeq(userclk_freqcntr_cmd, base + PORT_HDR_USRCLK_CMD1); 318 mutex_unlock(&pdata->lock); 319 320 return count; 321 } 322 static DEVICE_ATTR_WO(userclk_freqcntrcmd); 323 324 static ssize_t 325 userclk_freqsts_show(struct device *dev, struct device_attribute *attr, 326 char *buf) 327 { 328 struct dfl_feature_platform_data *pdata = dev_get_platdata(dev); 329 u64 userclk_freqsts; 330 void __iomem *base; 331 332 base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER); 333 334 mutex_lock(&pdata->lock); 335 userclk_freqsts = readq(base + PORT_HDR_USRCLK_STS0); 336 mutex_unlock(&pdata->lock); 337 338 return sprintf(buf, "0x%llx\n", (unsigned long long)userclk_freqsts); 339 } 340 static DEVICE_ATTR_RO(userclk_freqsts); 341 342 static ssize_t 343 userclk_freqcntrsts_show(struct device *dev, struct device_attribute *attr, 344 char *buf) 345 { 346 struct dfl_feature_platform_data *pdata = dev_get_platdata(dev); 347 u64 userclk_freqcntrsts; 348 void __iomem *base; 349 350 base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER); 351 352 mutex_lock(&pdata->lock); 353 userclk_freqcntrsts = readq(base + PORT_HDR_USRCLK_STS1); 354 mutex_unlock(&pdata->lock); 355 356 return sprintf(buf, "0x%llx\n", 357 (unsigned long long)userclk_freqcntrsts); 358 } 359 static DEVICE_ATTR_RO(userclk_freqcntrsts); 360 361 static struct attribute *port_hdr_attrs[] = { 362 &dev_attr_id.attr, 363 &dev_attr_ltr.attr, 364 &dev_attr_ap1_event.attr, 365 &dev_attr_ap2_event.attr, 366 &dev_attr_power_state.attr, 367 &dev_attr_userclk_freqcmd.attr, 368 &dev_attr_userclk_freqcntrcmd.attr, 369 &dev_attr_userclk_freqsts.attr, 370 &dev_attr_userclk_freqcntrsts.attr, 371 NULL, 372 }; 373 374 static umode_t port_hdr_attrs_visible(struct kobject *kobj, 375 struct attribute *attr, int n) 376 { 377 struct device *dev = kobj_to_dev(kobj); 378 umode_t mode = attr->mode; 379 void __iomem *base; 380 381 base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER); 382 383 if (dfl_feature_revision(base) > 0) { 384 /* 385 * userclk sysfs interfaces are only visible in case port 386 * revision is 0, as hardware with revision >0 doesn't 387 * support this. 388 */ 389 if (attr == &dev_attr_userclk_freqcmd.attr || 390 attr == &dev_attr_userclk_freqcntrcmd.attr || 391 attr == &dev_attr_userclk_freqsts.attr || 392 attr == &dev_attr_userclk_freqcntrsts.attr) 393 mode = 0; 394 } 395 396 return mode; 397 } 398 399 static const struct attribute_group port_hdr_group = { 400 .attrs = port_hdr_attrs, 401 .is_visible = port_hdr_attrs_visible, 402 }; 403 404 static int port_hdr_init(struct platform_device *pdev, 405 struct dfl_feature *feature) 406 { 407 port_reset(pdev); 408 409 return 0; 410 } 411 412 static long 413 port_hdr_ioctl(struct platform_device *pdev, struct dfl_feature *feature, 414 unsigned int cmd, unsigned long arg) 415 { 416 long ret; 417 418 switch (cmd) { 419 case DFL_FPGA_PORT_RESET: 420 if (!arg) 421 ret = port_reset(pdev); 422 else 423 ret = -EINVAL; 424 break; 425 default: 426 dev_dbg(&pdev->dev, "%x cmd not handled", cmd); 427 ret = -ENODEV; 428 } 429 430 return ret; 431 } 432 433 static const struct dfl_feature_id port_hdr_id_table[] = { 434 {.id = PORT_FEATURE_ID_HEADER,}, 435 {0,} 436 }; 437 438 static const struct dfl_feature_ops port_hdr_ops = { 439 .init = port_hdr_init, 440 .ioctl = port_hdr_ioctl, 441 }; 442 443 static ssize_t 444 afu_id_show(struct device *dev, struct device_attribute *attr, char *buf) 445 { 446 struct dfl_feature_platform_data *pdata = dev_get_platdata(dev); 447 void __iomem *base; 448 u64 guidl, guidh; 449 450 base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_AFU); 451 452 mutex_lock(&pdata->lock); 453 if (pdata->disable_count) { 454 mutex_unlock(&pdata->lock); 455 return -EBUSY; 456 } 457 458 guidl = readq(base + GUID_L); 459 guidh = readq(base + GUID_H); 460 mutex_unlock(&pdata->lock); 461 462 return scnprintf(buf, PAGE_SIZE, "%016llx%016llx\n", guidh, guidl); 463 } 464 static DEVICE_ATTR_RO(afu_id); 465 466 static struct attribute *port_afu_attrs[] = { 467 &dev_attr_afu_id.attr, 468 NULL 469 }; 470 471 static umode_t port_afu_attrs_visible(struct kobject *kobj, 472 struct attribute *attr, int n) 473 { 474 struct device *dev = kobj_to_dev(kobj); 475 476 /* 477 * sysfs entries are visible only if related private feature is 478 * enumerated. 479 */ 480 if (!dfl_get_feature_by_id(dev, PORT_FEATURE_ID_AFU)) 481 return 0; 482 483 return attr->mode; 484 } 485 486 static const struct attribute_group port_afu_group = { 487 .attrs = port_afu_attrs, 488 .is_visible = port_afu_attrs_visible, 489 }; 490 491 static int port_afu_init(struct platform_device *pdev, 492 struct dfl_feature *feature) 493 { 494 struct resource *res = &pdev->resource[feature->resource_index]; 495 496 return afu_mmio_region_add(dev_get_platdata(&pdev->dev), 497 DFL_PORT_REGION_INDEX_AFU, 498 resource_size(res), res->start, 499 DFL_PORT_REGION_MMAP | DFL_PORT_REGION_READ | 500 DFL_PORT_REGION_WRITE); 501 } 502 503 static const struct dfl_feature_id port_afu_id_table[] = { 504 {.id = PORT_FEATURE_ID_AFU,}, 505 {0,} 506 }; 507 508 static const struct dfl_feature_ops port_afu_ops = { 509 .init = port_afu_init, 510 }; 511 512 static int port_stp_init(struct platform_device *pdev, 513 struct dfl_feature *feature) 514 { 515 struct resource *res = &pdev->resource[feature->resource_index]; 516 517 return afu_mmio_region_add(dev_get_platdata(&pdev->dev), 518 DFL_PORT_REGION_INDEX_STP, 519 resource_size(res), res->start, 520 DFL_PORT_REGION_MMAP | DFL_PORT_REGION_READ | 521 DFL_PORT_REGION_WRITE); 522 } 523 524 static const struct dfl_feature_id port_stp_id_table[] = { 525 {.id = PORT_FEATURE_ID_STP,}, 526 {0,} 527 }; 528 529 static const struct dfl_feature_ops port_stp_ops = { 530 .init = port_stp_init, 531 }; 532 533 static struct dfl_feature_driver port_feature_drvs[] = { 534 { 535 .id_table = port_hdr_id_table, 536 .ops = &port_hdr_ops, 537 }, 538 { 539 .id_table = port_afu_id_table, 540 .ops = &port_afu_ops, 541 }, 542 { 543 .id_table = port_err_id_table, 544 .ops = &port_err_ops, 545 }, 546 { 547 .id_table = port_stp_id_table, 548 .ops = &port_stp_ops, 549 }, 550 { 551 .ops = NULL, 552 } 553 }; 554 555 static int afu_open(struct inode *inode, struct file *filp) 556 { 557 struct platform_device *fdev = dfl_fpga_inode_to_feature_dev(inode); 558 struct dfl_feature_platform_data *pdata; 559 int ret; 560 561 pdata = dev_get_platdata(&fdev->dev); 562 if (WARN_ON(!pdata)) 563 return -ENODEV; 564 565 mutex_lock(&pdata->lock); 566 ret = dfl_feature_dev_use_begin(pdata, filp->f_flags & O_EXCL); 567 if (!ret) { 568 dev_dbg(&fdev->dev, "Device File Opened %d Times\n", 569 dfl_feature_dev_use_count(pdata)); 570 filp->private_data = fdev; 571 } 572 mutex_unlock(&pdata->lock); 573 574 return ret; 575 } 576 577 static int afu_release(struct inode *inode, struct file *filp) 578 { 579 struct platform_device *pdev = filp->private_data; 580 struct dfl_feature_platform_data *pdata; 581 582 dev_dbg(&pdev->dev, "Device File Release\n"); 583 584 pdata = dev_get_platdata(&pdev->dev); 585 586 mutex_lock(&pdata->lock); 587 dfl_feature_dev_use_end(pdata); 588 589 if (!dfl_feature_dev_use_count(pdata)) { 590 __port_reset(pdev); 591 afu_dma_region_destroy(pdata); 592 } 593 mutex_unlock(&pdata->lock); 594 595 return 0; 596 } 597 598 static long afu_ioctl_check_extension(struct dfl_feature_platform_data *pdata, 599 unsigned long arg) 600 { 601 /* No extension support for now */ 602 return 0; 603 } 604 605 static long 606 afu_ioctl_get_info(struct dfl_feature_platform_data *pdata, void __user *arg) 607 { 608 struct dfl_fpga_port_info info; 609 struct dfl_afu *afu; 610 unsigned long minsz; 611 612 minsz = offsetofend(struct dfl_fpga_port_info, num_umsgs); 613 614 if (copy_from_user(&info, arg, minsz)) 615 return -EFAULT; 616 617 if (info.argsz < minsz) 618 return -EINVAL; 619 620 mutex_lock(&pdata->lock); 621 afu = dfl_fpga_pdata_get_private(pdata); 622 info.flags = 0; 623 info.num_regions = afu->num_regions; 624 info.num_umsgs = afu->num_umsgs; 625 mutex_unlock(&pdata->lock); 626 627 if (copy_to_user(arg, &info, sizeof(info))) 628 return -EFAULT; 629 630 return 0; 631 } 632 633 static long afu_ioctl_get_region_info(struct dfl_feature_platform_data *pdata, 634 void __user *arg) 635 { 636 struct dfl_fpga_port_region_info rinfo; 637 struct dfl_afu_mmio_region region; 638 unsigned long minsz; 639 long ret; 640 641 minsz = offsetofend(struct dfl_fpga_port_region_info, offset); 642 643 if (copy_from_user(&rinfo, arg, minsz)) 644 return -EFAULT; 645 646 if (rinfo.argsz < minsz || rinfo.padding) 647 return -EINVAL; 648 649 ret = afu_mmio_region_get_by_index(pdata, rinfo.index, ®ion); 650 if (ret) 651 return ret; 652 653 rinfo.flags = region.flags; 654 rinfo.size = region.size; 655 rinfo.offset = region.offset; 656 657 if (copy_to_user(arg, &rinfo, sizeof(rinfo))) 658 return -EFAULT; 659 660 return 0; 661 } 662 663 static long 664 afu_ioctl_dma_map(struct dfl_feature_platform_data *pdata, void __user *arg) 665 { 666 struct dfl_fpga_port_dma_map map; 667 unsigned long minsz; 668 long ret; 669 670 minsz = offsetofend(struct dfl_fpga_port_dma_map, iova); 671 672 if (copy_from_user(&map, arg, minsz)) 673 return -EFAULT; 674 675 if (map.argsz < minsz || map.flags) 676 return -EINVAL; 677 678 ret = afu_dma_map_region(pdata, map.user_addr, map.length, &map.iova); 679 if (ret) 680 return ret; 681 682 if (copy_to_user(arg, &map, sizeof(map))) { 683 afu_dma_unmap_region(pdata, map.iova); 684 return -EFAULT; 685 } 686 687 dev_dbg(&pdata->dev->dev, "dma map: ua=%llx, len=%llx, iova=%llx\n", 688 (unsigned long long)map.user_addr, 689 (unsigned long long)map.length, 690 (unsigned long long)map.iova); 691 692 return 0; 693 } 694 695 static long 696 afu_ioctl_dma_unmap(struct dfl_feature_platform_data *pdata, void __user *arg) 697 { 698 struct dfl_fpga_port_dma_unmap unmap; 699 unsigned long minsz; 700 701 minsz = offsetofend(struct dfl_fpga_port_dma_unmap, iova); 702 703 if (copy_from_user(&unmap, arg, minsz)) 704 return -EFAULT; 705 706 if (unmap.argsz < minsz || unmap.flags) 707 return -EINVAL; 708 709 return afu_dma_unmap_region(pdata, unmap.iova); 710 } 711 712 static long afu_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) 713 { 714 struct platform_device *pdev = filp->private_data; 715 struct dfl_feature_platform_data *pdata; 716 struct dfl_feature *f; 717 long ret; 718 719 dev_dbg(&pdev->dev, "%s cmd 0x%x\n", __func__, cmd); 720 721 pdata = dev_get_platdata(&pdev->dev); 722 723 switch (cmd) { 724 case DFL_FPGA_GET_API_VERSION: 725 return DFL_FPGA_API_VERSION; 726 case DFL_FPGA_CHECK_EXTENSION: 727 return afu_ioctl_check_extension(pdata, arg); 728 case DFL_FPGA_PORT_GET_INFO: 729 return afu_ioctl_get_info(pdata, (void __user *)arg); 730 case DFL_FPGA_PORT_GET_REGION_INFO: 731 return afu_ioctl_get_region_info(pdata, (void __user *)arg); 732 case DFL_FPGA_PORT_DMA_MAP: 733 return afu_ioctl_dma_map(pdata, (void __user *)arg); 734 case DFL_FPGA_PORT_DMA_UNMAP: 735 return afu_ioctl_dma_unmap(pdata, (void __user *)arg); 736 default: 737 /* 738 * Let sub-feature's ioctl function to handle the cmd 739 * Sub-feature's ioctl returns -ENODEV when cmd is not 740 * handled in this sub feature, and returns 0 and other 741 * error code if cmd is handled. 742 */ 743 dfl_fpga_dev_for_each_feature(pdata, f) 744 if (f->ops && f->ops->ioctl) { 745 ret = f->ops->ioctl(pdev, f, cmd, arg); 746 if (ret != -ENODEV) 747 return ret; 748 } 749 } 750 751 return -EINVAL; 752 } 753 754 static const struct vm_operations_struct afu_vma_ops = { 755 #ifdef CONFIG_HAVE_IOREMAP_PROT 756 .access = generic_access_phys, 757 #endif 758 }; 759 760 static int afu_mmap(struct file *filp, struct vm_area_struct *vma) 761 { 762 struct platform_device *pdev = filp->private_data; 763 struct dfl_feature_platform_data *pdata; 764 u64 size = vma->vm_end - vma->vm_start; 765 struct dfl_afu_mmio_region region; 766 u64 offset; 767 int ret; 768 769 if (!(vma->vm_flags & VM_SHARED)) 770 return -EINVAL; 771 772 pdata = dev_get_platdata(&pdev->dev); 773 774 offset = vma->vm_pgoff << PAGE_SHIFT; 775 ret = afu_mmio_region_get_by_offset(pdata, offset, size, ®ion); 776 if (ret) 777 return ret; 778 779 if (!(region.flags & DFL_PORT_REGION_MMAP)) 780 return -EINVAL; 781 782 if ((vma->vm_flags & VM_READ) && !(region.flags & DFL_PORT_REGION_READ)) 783 return -EPERM; 784 785 if ((vma->vm_flags & VM_WRITE) && 786 !(region.flags & DFL_PORT_REGION_WRITE)) 787 return -EPERM; 788 789 /* Support debug access to the mapping */ 790 vma->vm_ops = &afu_vma_ops; 791 792 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 793 794 return remap_pfn_range(vma, vma->vm_start, 795 (region.phys + (offset - region.offset)) >> PAGE_SHIFT, 796 size, vma->vm_page_prot); 797 } 798 799 static const struct file_operations afu_fops = { 800 .owner = THIS_MODULE, 801 .open = afu_open, 802 .release = afu_release, 803 .unlocked_ioctl = afu_ioctl, 804 .mmap = afu_mmap, 805 }; 806 807 static int afu_dev_init(struct platform_device *pdev) 808 { 809 struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev); 810 struct dfl_afu *afu; 811 812 afu = devm_kzalloc(&pdev->dev, sizeof(*afu), GFP_KERNEL); 813 if (!afu) 814 return -ENOMEM; 815 816 afu->pdata = pdata; 817 818 mutex_lock(&pdata->lock); 819 dfl_fpga_pdata_set_private(pdata, afu); 820 afu_mmio_region_init(pdata); 821 afu_dma_region_init(pdata); 822 mutex_unlock(&pdata->lock); 823 824 return 0; 825 } 826 827 static int afu_dev_destroy(struct platform_device *pdev) 828 { 829 struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev); 830 831 mutex_lock(&pdata->lock); 832 afu_mmio_region_destroy(pdata); 833 afu_dma_region_destroy(pdata); 834 dfl_fpga_pdata_set_private(pdata, NULL); 835 mutex_unlock(&pdata->lock); 836 837 return 0; 838 } 839 840 static int port_enable_set(struct platform_device *pdev, bool enable) 841 { 842 struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev); 843 int ret = 0; 844 845 mutex_lock(&pdata->lock); 846 if (enable) 847 __afu_port_enable(pdev); 848 else 849 ret = __afu_port_disable(pdev); 850 mutex_unlock(&pdata->lock); 851 852 return ret; 853 } 854 855 static struct dfl_fpga_port_ops afu_port_ops = { 856 .name = DFL_FPGA_FEATURE_DEV_PORT, 857 .owner = THIS_MODULE, 858 .get_id = port_get_id, 859 .enable_set = port_enable_set, 860 }; 861 862 static int afu_probe(struct platform_device *pdev) 863 { 864 int ret; 865 866 dev_dbg(&pdev->dev, "%s\n", __func__); 867 868 ret = afu_dev_init(pdev); 869 if (ret) 870 goto exit; 871 872 ret = dfl_fpga_dev_feature_init(pdev, port_feature_drvs); 873 if (ret) 874 goto dev_destroy; 875 876 ret = dfl_fpga_dev_ops_register(pdev, &afu_fops, THIS_MODULE); 877 if (ret) { 878 dfl_fpga_dev_feature_uinit(pdev); 879 goto dev_destroy; 880 } 881 882 return 0; 883 884 dev_destroy: 885 afu_dev_destroy(pdev); 886 exit: 887 return ret; 888 } 889 890 static int afu_remove(struct platform_device *pdev) 891 { 892 dev_dbg(&pdev->dev, "%s\n", __func__); 893 894 dfl_fpga_dev_ops_unregister(pdev); 895 dfl_fpga_dev_feature_uinit(pdev); 896 afu_dev_destroy(pdev); 897 898 return 0; 899 } 900 901 static const struct attribute_group *afu_dev_groups[] = { 902 &port_hdr_group, 903 &port_afu_group, 904 &port_err_group, 905 NULL 906 }; 907 908 static struct platform_driver afu_driver = { 909 .driver = { 910 .name = DFL_FPGA_FEATURE_DEV_PORT, 911 .dev_groups = afu_dev_groups, 912 }, 913 .probe = afu_probe, 914 .remove = afu_remove, 915 }; 916 917 static int __init afu_init(void) 918 { 919 int ret; 920 921 dfl_fpga_port_ops_add(&afu_port_ops); 922 923 ret = platform_driver_register(&afu_driver); 924 if (ret) 925 dfl_fpga_port_ops_del(&afu_port_ops); 926 927 return ret; 928 } 929 930 static void __exit afu_exit(void) 931 { 932 platform_driver_unregister(&afu_driver); 933 934 dfl_fpga_port_ops_del(&afu_port_ops); 935 } 936 937 module_init(afu_init); 938 module_exit(afu_exit); 939 940 MODULE_DESCRIPTION("FPGA Accelerated Function Unit driver"); 941 MODULE_AUTHOR("Intel Corporation"); 942 MODULE_LICENSE("GPL v2"); 943 MODULE_ALIAS("platform:dfl-port"); 944