1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * FPGA Manager Driver for Altera Arria/Cyclone/Stratix CvP 4 * 5 * Copyright (C) 2017 DENX Software Engineering 6 * 7 * Anatolij Gustschin <agust@denx.de> 8 * 9 * Manage Altera FPGA firmware using PCIe CvP. 10 * Firmware must be in binary "rbf" format. 11 */ 12 13 #include <linux/delay.h> 14 #include <linux/device.h> 15 #include <linux/fpga/fpga-mgr.h> 16 #include <linux/module.h> 17 #include <linux/pci.h> 18 #include <linux/sizes.h> 19 20 #define CVP_BAR 0 /* BAR used for data transfer in memory mode */ 21 #define CVP_DUMMY_WR 244 /* dummy writes to clear CvP state machine */ 22 #define TIMEOUT_US 2000 /* CVP STATUS timeout for USERMODE polling */ 23 24 /* Vendor Specific Extended Capability Registers */ 25 #define VSE_PCIE_EXT_CAP_ID 0x200 26 #define VSE_PCIE_EXT_CAP_ID_VAL 0x000b /* 16bit */ 27 28 #define VSE_CVP_STATUS 0x21c /* 32bit */ 29 #define VSE_CVP_STATUS_CFG_RDY BIT(18) /* CVP_CONFIG_READY */ 30 #define VSE_CVP_STATUS_CFG_ERR BIT(19) /* CVP_CONFIG_ERROR */ 31 #define VSE_CVP_STATUS_CVP_EN BIT(20) /* ctrl block is enabling CVP */ 32 #define VSE_CVP_STATUS_USERMODE BIT(21) /* USERMODE */ 33 #define VSE_CVP_STATUS_CFG_DONE BIT(23) /* CVP_CONFIG_DONE */ 34 #define VSE_CVP_STATUS_PLD_CLK_IN_USE BIT(24) /* PLD_CLK_IN_USE */ 35 36 #define VSE_CVP_MODE_CTRL 0x220 /* 32bit */ 37 #define VSE_CVP_MODE_CTRL_CVP_MODE BIT(0) /* CVP (1) or normal mode (0) */ 38 #define VSE_CVP_MODE_CTRL_HIP_CLK_SEL BIT(1) /* PMA (1) or fabric clock (0) */ 39 #define VSE_CVP_MODE_CTRL_NUMCLKS_OFF 8 /* NUMCLKS bits offset */ 40 #define VSE_CVP_MODE_CTRL_NUMCLKS_MASK GENMASK(15, 8) 41 42 #define VSE_CVP_DATA 0x228 /* 32bit */ 43 #define VSE_CVP_PROG_CTRL 0x22c /* 32bit */ 44 #define VSE_CVP_PROG_CTRL_CONFIG BIT(0) 45 #define VSE_CVP_PROG_CTRL_START_XFER BIT(1) 46 47 #define VSE_UNCOR_ERR_STATUS 0x234 /* 32bit */ 48 #define VSE_UNCOR_ERR_CVP_CFG_ERR BIT(5) /* CVP_CONFIG_ERROR_LATCHED */ 49 50 #define DRV_NAME "altera-cvp" 51 #define ALTERA_CVP_MGR_NAME "Altera CvP FPGA Manager" 52 53 /* Optional CvP config error status check for debugging */ 54 static bool altera_cvp_chkcfg; 55 56 struct altera_cvp_conf { 57 struct fpga_manager *mgr; 58 struct pci_dev *pci_dev; 59 void __iomem *map; 60 void (*write_data)(struct altera_cvp_conf *conf, 61 u32 data); 62 char mgr_name[64]; 63 u8 numclks; 64 }; 65 66 static enum fpga_mgr_states altera_cvp_state(struct fpga_manager *mgr) 67 { 68 struct altera_cvp_conf *conf = mgr->priv; 69 u32 status; 70 71 pci_read_config_dword(conf->pci_dev, VSE_CVP_STATUS, &status); 72 73 if (status & VSE_CVP_STATUS_CFG_DONE) 74 return FPGA_MGR_STATE_OPERATING; 75 76 if (status & VSE_CVP_STATUS_CVP_EN) 77 return FPGA_MGR_STATE_POWER_UP; 78 79 return FPGA_MGR_STATE_UNKNOWN; 80 } 81 82 static void altera_cvp_write_data_iomem(struct altera_cvp_conf *conf, u32 val) 83 { 84 writel(val, conf->map); 85 } 86 87 static void altera_cvp_write_data_config(struct altera_cvp_conf *conf, u32 val) 88 { 89 pci_write_config_dword(conf->pci_dev, VSE_CVP_DATA, val); 90 } 91 92 /* switches between CvP clock and internal clock */ 93 static void altera_cvp_dummy_write(struct altera_cvp_conf *conf) 94 { 95 unsigned int i; 96 u32 val; 97 98 /* set 1 CVP clock cycle for every CVP Data Register Write */ 99 pci_read_config_dword(conf->pci_dev, VSE_CVP_MODE_CTRL, &val); 100 val &= ~VSE_CVP_MODE_CTRL_NUMCLKS_MASK; 101 val |= 1 << VSE_CVP_MODE_CTRL_NUMCLKS_OFF; 102 pci_write_config_dword(conf->pci_dev, VSE_CVP_MODE_CTRL, val); 103 104 for (i = 0; i < CVP_DUMMY_WR; i++) 105 conf->write_data(conf, 0); /* dummy data, could be any value */ 106 } 107 108 static int altera_cvp_wait_status(struct altera_cvp_conf *conf, u32 status_mask, 109 u32 status_val, int timeout_us) 110 { 111 unsigned int retries; 112 u32 val; 113 114 retries = timeout_us / 10; 115 if (timeout_us % 10) 116 retries++; 117 118 do { 119 pci_read_config_dword(conf->pci_dev, VSE_CVP_STATUS, &val); 120 if ((val & status_mask) == status_val) 121 return 0; 122 123 /* use small usleep value to re-check and break early */ 124 usleep_range(10, 11); 125 } while (--retries); 126 127 return -ETIMEDOUT; 128 } 129 130 static int altera_cvp_teardown(struct fpga_manager *mgr, 131 struct fpga_image_info *info) 132 { 133 struct altera_cvp_conf *conf = mgr->priv; 134 struct pci_dev *pdev = conf->pci_dev; 135 int ret; 136 u32 val; 137 138 /* STEP 12 - reset START_XFER bit */ 139 pci_read_config_dword(pdev, VSE_CVP_PROG_CTRL, &val); 140 val &= ~VSE_CVP_PROG_CTRL_START_XFER; 141 pci_write_config_dword(pdev, VSE_CVP_PROG_CTRL, val); 142 143 /* STEP 13 - reset CVP_CONFIG bit */ 144 val &= ~VSE_CVP_PROG_CTRL_CONFIG; 145 pci_write_config_dword(pdev, VSE_CVP_PROG_CTRL, val); 146 147 /* 148 * STEP 14 149 * - set CVP_NUMCLKS to 1 and then issue CVP_DUMMY_WR dummy 150 * writes to the HIP 151 */ 152 altera_cvp_dummy_write(conf); /* from CVP clock to internal clock */ 153 154 /* STEP 15 - poll CVP_CONFIG_READY bit for 0 with 10us timeout */ 155 ret = altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY, 0, 10); 156 if (ret) 157 dev_err(&mgr->dev, "CFG_RDY == 0 timeout\n"); 158 159 return ret; 160 } 161 162 static int altera_cvp_write_init(struct fpga_manager *mgr, 163 struct fpga_image_info *info, 164 const char *buf, size_t count) 165 { 166 struct altera_cvp_conf *conf = mgr->priv; 167 struct pci_dev *pdev = conf->pci_dev; 168 u32 iflags, val; 169 int ret; 170 171 iflags = info ? info->flags : 0; 172 173 if (iflags & FPGA_MGR_PARTIAL_RECONFIG) { 174 dev_err(&mgr->dev, "Partial reconfiguration not supported.\n"); 175 return -EINVAL; 176 } 177 178 /* Determine allowed clock to data ratio */ 179 if (iflags & FPGA_MGR_COMPRESSED_BITSTREAM) 180 conf->numclks = 8; /* ratio for all compressed images */ 181 else if (iflags & FPGA_MGR_ENCRYPTED_BITSTREAM) 182 conf->numclks = 4; /* for uncompressed and encrypted images */ 183 else 184 conf->numclks = 1; /* for uncompressed and unencrypted images */ 185 186 /* STEP 1 - read CVP status and check CVP_EN flag */ 187 pci_read_config_dword(pdev, VSE_CVP_STATUS, &val); 188 if (!(val & VSE_CVP_STATUS_CVP_EN)) { 189 dev_err(&mgr->dev, "CVP mode off: 0x%04x\n", val); 190 return -ENODEV; 191 } 192 193 if (val & VSE_CVP_STATUS_CFG_RDY) { 194 dev_warn(&mgr->dev, "CvP already started, teardown first\n"); 195 ret = altera_cvp_teardown(mgr, info); 196 if (ret) 197 return ret; 198 } 199 200 /* 201 * STEP 2 202 * - set HIP_CLK_SEL and CVP_MODE (must be set in the order mentioned) 203 */ 204 /* switch from fabric to PMA clock */ 205 pci_read_config_dword(pdev, VSE_CVP_MODE_CTRL, &val); 206 val |= VSE_CVP_MODE_CTRL_HIP_CLK_SEL; 207 pci_write_config_dword(pdev, VSE_CVP_MODE_CTRL, val); 208 209 /* set CVP mode */ 210 pci_read_config_dword(pdev, VSE_CVP_MODE_CTRL, &val); 211 val |= VSE_CVP_MODE_CTRL_CVP_MODE; 212 pci_write_config_dword(pdev, VSE_CVP_MODE_CTRL, val); 213 214 /* 215 * STEP 3 216 * - set CVP_NUMCLKS to 1 and issue CVP_DUMMY_WR dummy writes to the HIP 217 */ 218 altera_cvp_dummy_write(conf); 219 220 /* STEP 4 - set CVP_CONFIG bit */ 221 pci_read_config_dword(pdev, VSE_CVP_PROG_CTRL, &val); 222 /* request control block to begin transfer using CVP */ 223 val |= VSE_CVP_PROG_CTRL_CONFIG; 224 pci_write_config_dword(pdev, VSE_CVP_PROG_CTRL, val); 225 226 /* STEP 5 - poll CVP_CONFIG READY for 1 with 10us timeout */ 227 ret = altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY, 228 VSE_CVP_STATUS_CFG_RDY, 10); 229 if (ret) { 230 dev_warn(&mgr->dev, "CFG_RDY == 1 timeout\n"); 231 return ret; 232 } 233 234 /* 235 * STEP 6 236 * - set CVP_NUMCLKS to 1 and issue CVP_DUMMY_WR dummy writes to the HIP 237 */ 238 altera_cvp_dummy_write(conf); 239 240 /* STEP 7 - set START_XFER */ 241 pci_read_config_dword(pdev, VSE_CVP_PROG_CTRL, &val); 242 val |= VSE_CVP_PROG_CTRL_START_XFER; 243 pci_write_config_dword(pdev, VSE_CVP_PROG_CTRL, val); 244 245 /* STEP 8 - start transfer (set CVP_NUMCLKS for bitstream) */ 246 pci_read_config_dword(pdev, VSE_CVP_MODE_CTRL, &val); 247 val &= ~VSE_CVP_MODE_CTRL_NUMCLKS_MASK; 248 val |= conf->numclks << VSE_CVP_MODE_CTRL_NUMCLKS_OFF; 249 pci_write_config_dword(pdev, VSE_CVP_MODE_CTRL, val); 250 251 return 0; 252 } 253 254 static inline int altera_cvp_chk_error(struct fpga_manager *mgr, size_t bytes) 255 { 256 struct altera_cvp_conf *conf = mgr->priv; 257 u32 val; 258 259 /* STEP 10 (optional) - check CVP_CONFIG_ERROR flag */ 260 pci_read_config_dword(conf->pci_dev, VSE_CVP_STATUS, &val); 261 if (val & VSE_CVP_STATUS_CFG_ERR) { 262 dev_err(&mgr->dev, "CVP_CONFIG_ERROR after %zu bytes!\n", 263 bytes); 264 return -EPROTO; 265 } 266 return 0; 267 } 268 269 static int altera_cvp_write(struct fpga_manager *mgr, const char *buf, 270 size_t count) 271 { 272 struct altera_cvp_conf *conf = mgr->priv; 273 const u32 *data; 274 size_t done, remaining; 275 int status = 0; 276 u32 mask; 277 278 /* STEP 9 - write 32-bit data from RBF file to CVP data register */ 279 data = (u32 *)buf; 280 remaining = count; 281 done = 0; 282 283 while (remaining >= 4) { 284 conf->write_data(conf, *data++); 285 done += 4; 286 remaining -= 4; 287 288 /* 289 * STEP 10 (optional) and STEP 11 290 * - check error flag 291 * - loop until data transfer completed 292 * Config images can be huge (more than 40 MiB), so 293 * only check after a new 4k data block has been written. 294 * This reduces the number of checks and speeds up the 295 * configuration process. 296 */ 297 if (altera_cvp_chkcfg && !(done % SZ_4K)) { 298 status = altera_cvp_chk_error(mgr, done); 299 if (status < 0) 300 return status; 301 } 302 } 303 304 /* write up to 3 trailing bytes, if any */ 305 mask = BIT(remaining * 8) - 1; 306 if (mask) 307 conf->write_data(conf, *data & mask); 308 309 if (altera_cvp_chkcfg) 310 status = altera_cvp_chk_error(mgr, count); 311 312 return status; 313 } 314 315 static int altera_cvp_write_complete(struct fpga_manager *mgr, 316 struct fpga_image_info *info) 317 { 318 struct altera_cvp_conf *conf = mgr->priv; 319 struct pci_dev *pdev = conf->pci_dev; 320 int ret; 321 u32 mask; 322 u32 val; 323 324 ret = altera_cvp_teardown(mgr, info); 325 if (ret) 326 return ret; 327 328 /* STEP 16 - check CVP_CONFIG_ERROR_LATCHED bit */ 329 pci_read_config_dword(pdev, VSE_UNCOR_ERR_STATUS, &val); 330 if (val & VSE_UNCOR_ERR_CVP_CFG_ERR) { 331 dev_err(&mgr->dev, "detected CVP_CONFIG_ERROR_LATCHED!\n"); 332 return -EPROTO; 333 } 334 335 /* STEP 17 - reset CVP_MODE and HIP_CLK_SEL bit */ 336 pci_read_config_dword(pdev, VSE_CVP_MODE_CTRL, &val); 337 val &= ~VSE_CVP_MODE_CTRL_HIP_CLK_SEL; 338 val &= ~VSE_CVP_MODE_CTRL_CVP_MODE; 339 pci_write_config_dword(pdev, VSE_CVP_MODE_CTRL, val); 340 341 /* STEP 18 - poll PLD_CLK_IN_USE and USER_MODE bits */ 342 mask = VSE_CVP_STATUS_PLD_CLK_IN_USE | VSE_CVP_STATUS_USERMODE; 343 ret = altera_cvp_wait_status(conf, mask, mask, TIMEOUT_US); 344 if (ret) 345 dev_err(&mgr->dev, "PLD_CLK_IN_USE|USERMODE timeout\n"); 346 347 return ret; 348 } 349 350 static const struct fpga_manager_ops altera_cvp_ops = { 351 .state = altera_cvp_state, 352 .write_init = altera_cvp_write_init, 353 .write = altera_cvp_write, 354 .write_complete = altera_cvp_write_complete, 355 }; 356 357 static ssize_t chkcfg_show(struct device_driver *dev, char *buf) 358 { 359 return snprintf(buf, 3, "%d\n", altera_cvp_chkcfg); 360 } 361 362 static ssize_t chkcfg_store(struct device_driver *drv, const char *buf, 363 size_t count) 364 { 365 int ret; 366 367 ret = kstrtobool(buf, &altera_cvp_chkcfg); 368 if (ret) 369 return ret; 370 371 return count; 372 } 373 374 static DRIVER_ATTR_RW(chkcfg); 375 376 static int altera_cvp_probe(struct pci_dev *pdev, 377 const struct pci_device_id *dev_id); 378 static void altera_cvp_remove(struct pci_dev *pdev); 379 380 static struct pci_device_id altera_cvp_id_tbl[] = { 381 { PCI_VDEVICE(ALTERA, PCI_ANY_ID) }, 382 { } 383 }; 384 MODULE_DEVICE_TABLE(pci, altera_cvp_id_tbl); 385 386 static struct pci_driver altera_cvp_driver = { 387 .name = DRV_NAME, 388 .id_table = altera_cvp_id_tbl, 389 .probe = altera_cvp_probe, 390 .remove = altera_cvp_remove, 391 }; 392 393 static int altera_cvp_probe(struct pci_dev *pdev, 394 const struct pci_device_id *dev_id) 395 { 396 struct altera_cvp_conf *conf; 397 struct fpga_manager *mgr; 398 u16 cmd, val; 399 u32 regval; 400 int ret; 401 402 /* 403 * First check if this is the expected FPGA device. PCI config 404 * space access works without enabling the PCI device, memory 405 * space access is enabled further down. 406 */ 407 pci_read_config_word(pdev, VSE_PCIE_EXT_CAP_ID, &val); 408 if (val != VSE_PCIE_EXT_CAP_ID_VAL) { 409 dev_err(&pdev->dev, "Wrong EXT_CAP_ID value 0x%x\n", val); 410 return -ENODEV; 411 } 412 413 pci_read_config_dword(pdev, VSE_CVP_STATUS, ®val); 414 if (!(regval & VSE_CVP_STATUS_CVP_EN)) { 415 dev_err(&pdev->dev, 416 "CVP is disabled for this device: CVP_STATUS Reg 0x%x\n", 417 regval); 418 return -ENODEV; 419 } 420 421 conf = devm_kzalloc(&pdev->dev, sizeof(*conf), GFP_KERNEL); 422 if (!conf) 423 return -ENOMEM; 424 425 /* 426 * Enable memory BAR access. We cannot use pci_enable_device() here 427 * because it will make the driver unusable with FPGA devices that 428 * have additional big IOMEM resources (e.g. 4GiB BARs) on 32-bit 429 * platform. Such BARs will not have an assigned address range and 430 * pci_enable_device() will fail, complaining about not claimed BAR, 431 * even if the concerned BAR is not needed for FPGA configuration 432 * at all. Thus, enable the device via PCI config space command. 433 */ 434 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 435 if (!(cmd & PCI_COMMAND_MEMORY)) { 436 cmd |= PCI_COMMAND_MEMORY; 437 pci_write_config_word(pdev, PCI_COMMAND, cmd); 438 } 439 440 ret = pci_request_region(pdev, CVP_BAR, "CVP"); 441 if (ret) { 442 dev_err(&pdev->dev, "Requesting CVP BAR region failed\n"); 443 goto err_disable; 444 } 445 446 conf->pci_dev = pdev; 447 conf->write_data = altera_cvp_write_data_iomem; 448 449 conf->map = pci_iomap(pdev, CVP_BAR, 0); 450 if (!conf->map) { 451 dev_warn(&pdev->dev, "Mapping CVP BAR failed\n"); 452 conf->write_data = altera_cvp_write_data_config; 453 } 454 455 snprintf(conf->mgr_name, sizeof(conf->mgr_name), "%s @%s", 456 ALTERA_CVP_MGR_NAME, pci_name(pdev)); 457 458 mgr = devm_fpga_mgr_create(&pdev->dev, conf->mgr_name, 459 &altera_cvp_ops, conf); 460 if (!mgr) { 461 ret = -ENOMEM; 462 goto err_unmap; 463 } 464 465 pci_set_drvdata(pdev, mgr); 466 467 ret = fpga_mgr_register(mgr); 468 if (ret) 469 goto err_unmap; 470 471 return 0; 472 473 err_unmap: 474 if (conf->map) 475 pci_iounmap(pdev, conf->map); 476 pci_release_region(pdev, CVP_BAR); 477 err_disable: 478 cmd &= ~PCI_COMMAND_MEMORY; 479 pci_write_config_word(pdev, PCI_COMMAND, cmd); 480 return ret; 481 } 482 483 static void altera_cvp_remove(struct pci_dev *pdev) 484 { 485 struct fpga_manager *mgr = pci_get_drvdata(pdev); 486 struct altera_cvp_conf *conf = mgr->priv; 487 u16 cmd; 488 489 fpga_mgr_unregister(mgr); 490 if (conf->map) 491 pci_iounmap(pdev, conf->map); 492 pci_release_region(pdev, CVP_BAR); 493 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 494 cmd &= ~PCI_COMMAND_MEMORY; 495 pci_write_config_word(pdev, PCI_COMMAND, cmd); 496 } 497 498 static int __init altera_cvp_init(void) 499 { 500 int ret; 501 502 ret = pci_register_driver(&altera_cvp_driver); 503 if (ret) 504 return ret; 505 506 ret = driver_create_file(&altera_cvp_driver.driver, 507 &driver_attr_chkcfg); 508 if (ret) 509 pr_warn("Can't create sysfs chkcfg file\n"); 510 511 return 0; 512 } 513 514 static void __exit altera_cvp_exit(void) 515 { 516 driver_remove_file(&altera_cvp_driver.driver, &driver_attr_chkcfg); 517 pci_unregister_driver(&altera_cvp_driver); 518 } 519 520 module_init(altera_cvp_init); 521 module_exit(altera_cvp_exit); 522 523 MODULE_LICENSE("GPL v2"); 524 MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>"); 525 MODULE_DESCRIPTION("Module to load Altera FPGA over CvP"); 526