1b2441318SGreg Kroah-Hartman# SPDX-License-Identifier: GPL-2.0 26a8c3be7SAlan Tull# 36a8c3be7SAlan Tull# Makefile for the fpga framework and fpga manager drivers. 46a8c3be7SAlan Tull# 56a8c3be7SAlan Tull 66a8c3be7SAlan Tull# Core FPGA Manager Framework 76a8c3be7SAlan Tullobj-$(CONFIG_FPGA) += fpga-mgr.o 86a8c3be7SAlan Tull 96a8c3be7SAlan Tull# FPGA Manager Drivers 1034d1dc17SAnatolij Gustschinobj-$(CONFIG_FPGA_MGR_ALTERA_CVP) += altera-cvp.o 115692fae0SJoshua Claytonobj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI) += altera-ps-spi.o 1221f8ba2eSJoel Holdsworthobj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o 13fab6266eSAlan Tullobj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o 14acbb910aSAlan Tullobj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o 154348f7e2SFlorian Fainelliobj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o 16061c97d1SAnatolij Gustschinobj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o 1737784706SMoritz Fischerobj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o 18d201cc17SMatthew Gerlachobj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o 195b73cb5bSMatthew Gerlachobj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o 2021aeda95SAlan Tull 2121aeda95SAlan Tull# FPGA Bridge Drivers 2221aeda95SAlan Tullobj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o 23e5f8efa5SAlan Tullobj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o 24ca24a648SAlan Tullobj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o 257e961c12SMoritz Fischerobj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o 260fa20cdfSAlan Tull 270fa20cdfSAlan Tull# High Level Interfaces 280fa20cdfSAlan Tullobj-$(CONFIG_FPGA_REGION) += fpga-region.o 29