16a8c3be7SAlan Tull# 26a8c3be7SAlan Tull# Makefile for the fpga framework and fpga manager drivers. 36a8c3be7SAlan Tull# 46a8c3be7SAlan Tull 56a8c3be7SAlan Tull# Core FPGA Manager Framework 66a8c3be7SAlan Tullobj-$(CONFIG_FPGA) += fpga-mgr.o 76a8c3be7SAlan Tull 86a8c3be7SAlan Tull# FPGA Manager Drivers 934d1dc17SAnatolij Gustschinobj-$(CONFIG_FPGA_MGR_ALTERA_CVP) += altera-cvp.o 105692fae0SJoshua Claytonobj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI) += altera-ps-spi.o 1121f8ba2eSJoel Holdsworthobj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o 12fab6266eSAlan Tullobj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o 13acbb910aSAlan Tullobj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o 144348f7e2SFlorian Fainelliobj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o 15061c97d1SAnatolij Gustschinobj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o 1637784706SMoritz Fischerobj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o 17d201cc17SMatthew Gerlachobj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o 185b73cb5bSMatthew Gerlachobj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o 1921aeda95SAlan Tull 2021aeda95SAlan Tull# FPGA Bridge Drivers 2121aeda95SAlan Tullobj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o 22e5f8efa5SAlan Tullobj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o 23ca24a648SAlan Tullobj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o 247e961c12SMoritz Fischerobj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o 250fa20cdfSAlan Tull 260fa20cdfSAlan Tull# High Level Interfaces 270fa20cdfSAlan Tullobj-$(CONFIG_FPGA_REGION) += fpga-region.o 28