1# 2# FPGA framework configuration 3# 4 5menuconfig FPGA 6 tristate "FPGA Configuration Framework" 7 help 8 Say Y here if you want support for configuring FPGAs from the 9 kernel. The FPGA framework adds a FPGA manager class and FPGA 10 manager drivers. 11 12if FPGA 13 14config FPGA_MGR_SOCFPGA 15 tristate "Altera SOCFPGA FPGA Manager" 16 depends on ARCH_SOCFPGA || COMPILE_TEST 17 help 18 FPGA manager driver support for Altera SOCFPGA. 19 20config FPGA_MGR_SOCFPGA_A10 21 tristate "Altera SoCFPGA Arria10" 22 depends on ARCH_SOCFPGA || COMPILE_TEST 23 select REGMAP_MMIO 24 help 25 FPGA manager driver support for Altera Arria10 SoCFPGA. 26 27config ALTERA_PR_IP_CORE 28 tristate "Altera Partial Reconfiguration IP Core" 29 help 30 Core driver support for Altera Partial Reconfiguration IP component 31 32config ALTERA_PR_IP_CORE_PLAT 33 tristate "Platform support of Altera Partial Reconfiguration IP Core" 34 depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM 35 help 36 Platform driver support for Altera Partial Reconfiguration IP 37 component 38 39config FPGA_MGR_ALTERA_PS_SPI 40 tristate "Altera FPGA Passive Serial over SPI" 41 depends on SPI 42 help 43 FPGA manager driver support for Altera Arria/Cyclone/Stratix 44 using the passive serial interface over SPI. 45 46config FPGA_MGR_ALTERA_CVP 47 tristate "Altera Arria-V/Cyclone-V/Stratix-V CvP FPGA Manager" 48 depends on PCI 49 help 50 FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V 51 and Arria 10 Altera FPGAs using the CvP interface over PCIe. 52 53config FPGA_MGR_ZYNQ_FPGA 54 tristate "Xilinx Zynq FPGA" 55 depends on ARCH_ZYNQ || COMPILE_TEST 56 help 57 FPGA manager driver support for Xilinx Zynq FPGAs. 58 59config FPGA_MGR_STRATIX10_SOC 60 tristate "Intel Stratix10 SoC FPGA Manager" 61 depends on (ARCH_STRATIX10 && INTEL_STRATIX10_SERVICE) 62 help 63 FPGA manager driver support for the Intel Stratix10 SoC. 64 65config FPGA_MGR_XILINX_SPI 66 tristate "Xilinx Configuration over Slave Serial (SPI)" 67 depends on SPI 68 help 69 FPGA manager driver support for Xilinx FPGA configuration 70 over slave serial interface. 71 72config FPGA_MGR_ICE40_SPI 73 tristate "Lattice iCE40 SPI" 74 depends on OF && SPI 75 help 76 FPGA manager driver support for Lattice iCE40 FPGAs over SPI. 77 78config FPGA_MGR_MACHXO2_SPI 79 tristate "Lattice MachXO2 SPI" 80 depends on SPI 81 help 82 FPGA manager driver support for Lattice MachXO2 configuration 83 over slave SPI interface. 84 85config FPGA_MGR_TS73XX 86 tristate "Technologic Systems TS-73xx SBC FPGA Manager" 87 depends on ARCH_EP93XX && MACH_TS72XX 88 help 89 FPGA manager driver support for the Altera Cyclone II FPGA 90 present on the TS-73xx SBC boards. 91 92config FPGA_BRIDGE 93 tristate "FPGA Bridge Framework" 94 help 95 Say Y here if you want to support bridges connected between host 96 processors and FPGAs or between FPGAs. 97 98config SOCFPGA_FPGA_BRIDGE 99 tristate "Altera SoCFPGA FPGA Bridges" 100 depends on ARCH_SOCFPGA && FPGA_BRIDGE 101 help 102 Say Y to enable drivers for FPGA bridges for Altera SOCFPGA 103 devices. 104 105config ALTERA_FREEZE_BRIDGE 106 tristate "Altera FPGA Freeze Bridge" 107 depends on ARCH_SOCFPGA && FPGA_BRIDGE 108 help 109 Say Y to enable drivers for Altera FPGA Freeze bridges. A 110 freeze bridge is a bridge that exists in the FPGA fabric to 111 isolate one region of the FPGA from the busses while that 112 region is being reprogrammed. 113 114config XILINX_PR_DECOUPLER 115 tristate "Xilinx LogiCORE PR Decoupler" 116 depends on FPGA_BRIDGE 117 depends on HAS_IOMEM 118 help 119 Say Y to enable drivers for Xilinx LogiCORE PR Decoupler. 120 The PR Decoupler exists in the FPGA fabric to isolate one 121 region of the FPGA from the busses while that region is 122 being reprogrammed during partial reconfig. 123 124config FPGA_REGION 125 tristate "FPGA Region" 126 depends on FPGA_BRIDGE 127 help 128 FPGA Region common code. A FPGA Region controls a FPGA Manager 129 and the FPGA Bridges associated with either a reconfigurable 130 region of an FPGA or a whole FPGA. 131 132config OF_FPGA_REGION 133 tristate "FPGA Region Device Tree Overlay Support" 134 depends on OF && FPGA_REGION 135 help 136 Support for loading FPGA images by applying a Device Tree 137 overlay. 138 139config FPGA_DFL 140 tristate "FPGA Device Feature List (DFL) support" 141 select FPGA_BRIDGE 142 select FPGA_REGION 143 help 144 Device Feature List (DFL) defines a feature list structure that 145 creates a linked list of feature headers within the MMIO space 146 to provide an extensible way of adding features for FPGA. 147 Driver can walk through the feature headers to enumerate feature 148 devices (e.g. FPGA Management Engine, Port and Accelerator 149 Function Unit) and their private features for target FPGA devices. 150 151 Select this option to enable common support for Field-Programmable 152 Gate Array (FPGA) solutions which implement Device Feature List. 153 It provides enumeration APIs and feature device infrastructure. 154 155config FPGA_DFL_FME 156 tristate "FPGA DFL FME Driver" 157 depends on FPGA_DFL 158 help 159 The FPGA Management Engine (FME) is a feature device implemented 160 under Device Feature List (DFL) framework. Select this option to 161 enable the platform device driver for FME which implements all 162 FPGA platform level management features. There shall be one FME 163 per DFL based FPGA device. 164 165config FPGA_DFL_FME_MGR 166 tristate "FPGA DFL FME Manager Driver" 167 depends on FPGA_DFL_FME && HAS_IOMEM 168 help 169 Say Y to enable FPGA Manager driver for FPGA Management Engine. 170 171config FPGA_DFL_FME_BRIDGE 172 tristate "FPGA DFL FME Bridge Driver" 173 depends on FPGA_DFL_FME && HAS_IOMEM 174 help 175 Say Y to enable FPGA Bridge driver for FPGA Management Engine. 176 177config FPGA_DFL_FME_REGION 178 tristate "FPGA DFL FME Region Driver" 179 depends on FPGA_DFL_FME && HAS_IOMEM 180 help 181 Say Y to enable FPGA Region driver for FPGA Management Engine. 182 183config FPGA_DFL_AFU 184 tristate "FPGA DFL AFU Driver" 185 depends on FPGA_DFL 186 help 187 This is the driver for FPGA Accelerated Function Unit (AFU) which 188 implements AFU and Port management features. A User AFU connects 189 to the FPGA infrastructure via a Port. There may be more than one 190 Port/AFU per DFL based FPGA device. 191 192config FPGA_DFL_PCI 193 tristate "FPGA DFL PCIe Device Driver" 194 depends on PCI && FPGA_DFL 195 help 196 Select this option to enable PCIe driver for PCIe-based 197 Field-Programmable Gate Array (FPGA) solutions which implement 198 the Device Feature List (DFL). This driver provides interfaces 199 for userspace applications to configure, enumerate, open and access 200 FPGA accelerators on the FPGA DFL devices, enables system level 201 management functions such as FPGA partial reconfiguration, power 202 management and virtualization with DFL framework and DFL feature 203 device drivers. 204 205 To compile this as a module, choose M here. 206 207endif # FPGA 208