1# 2# FPGA framework configuration 3# 4 5menuconfig FPGA 6 tristate "FPGA Configuration Framework" 7 help 8 Say Y here if you want support for configuring FPGAs from the 9 kernel. The FPGA framework adds a FPGA manager class and FPGA 10 manager drivers. 11 12if FPGA 13 14config FPGA_MGR_SOCFPGA 15 tristate "Altera SOCFPGA FPGA Manager" 16 depends on ARCH_SOCFPGA || COMPILE_TEST 17 help 18 FPGA manager driver support for Altera SOCFPGA. 19 20config FPGA_MGR_SOCFPGA_A10 21 tristate "Altera SoCFPGA Arria10" 22 depends on ARCH_SOCFPGA || COMPILE_TEST 23 select REGMAP_MMIO 24 help 25 FPGA manager driver support for Altera Arria10 SoCFPGA. 26 27config ALTERA_PR_IP_CORE 28 tristate "Altera Partial Reconfiguration IP Core" 29 help 30 Core driver support for Altera Partial Reconfiguration IP component 31 32config ALTERA_PR_IP_CORE_PLAT 33 tristate "Platform support of Altera Partial Reconfiguration IP Core" 34 depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM 35 help 36 Platform driver support for Altera Partial Reconfiguration IP 37 component 38 39config FPGA_MGR_ALTERA_PS_SPI 40 tristate "Altera FPGA Passive Serial over SPI" 41 depends on SPI 42 help 43 FPGA manager driver support for Altera Arria/Cyclone/Stratix 44 using the passive serial interface over SPI. 45 46config FPGA_MGR_ALTERA_CVP 47 tristate "Altera Arria-V/Cyclone-V/Stratix-V CvP FPGA Manager" 48 depends on PCI 49 help 50 FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V 51 and Arria 10 Altera FPGAs using the CvP interface over PCIe. 52 53config FPGA_MGR_ZYNQ_FPGA 54 tristate "Xilinx Zynq FPGA" 55 depends on ARCH_ZYNQ || COMPILE_TEST 56 help 57 FPGA manager driver support for Xilinx Zynq FPGAs. 58 59config FPGA_MGR_XILINX_SPI 60 tristate "Xilinx Configuration over Slave Serial (SPI)" 61 depends on SPI 62 help 63 FPGA manager driver support for Xilinx FPGA configuration 64 over slave serial interface. 65 66config FPGA_MGR_ICE40_SPI 67 tristate "Lattice iCE40 SPI" 68 depends on OF && SPI 69 help 70 FPGA manager driver support for Lattice iCE40 FPGAs over SPI. 71 72config FPGA_MGR_MACHXO2_SPI 73 tristate "Lattice MachXO2 SPI" 74 depends on SPI 75 help 76 FPGA manager driver support for Lattice MachXO2 configuration 77 over slave SPI interface. 78 79config FPGA_MGR_TS73XX 80 tristate "Technologic Systems TS-73xx SBC FPGA Manager" 81 depends on ARCH_EP93XX && MACH_TS72XX 82 help 83 FPGA manager driver support for the Altera Cyclone II FPGA 84 present on the TS-73xx SBC boards. 85 86config FPGA_BRIDGE 87 tristate "FPGA Bridge Framework" 88 help 89 Say Y here if you want to support bridges connected between host 90 processors and FPGAs or between FPGAs. 91 92config SOCFPGA_FPGA_BRIDGE 93 tristate "Altera SoCFPGA FPGA Bridges" 94 depends on ARCH_SOCFPGA && FPGA_BRIDGE 95 help 96 Say Y to enable drivers for FPGA bridges for Altera SOCFPGA 97 devices. 98 99config ALTERA_FREEZE_BRIDGE 100 tristate "Altera FPGA Freeze Bridge" 101 depends on ARCH_SOCFPGA && FPGA_BRIDGE 102 help 103 Say Y to enable drivers for Altera FPGA Freeze bridges. A 104 freeze bridge is a bridge that exists in the FPGA fabric to 105 isolate one region of the FPGA from the busses while that 106 region is being reprogrammed. 107 108config XILINX_PR_DECOUPLER 109 tristate "Xilinx LogiCORE PR Decoupler" 110 depends on FPGA_BRIDGE 111 depends on HAS_IOMEM 112 help 113 Say Y to enable drivers for Xilinx LogiCORE PR Decoupler. 114 The PR Decoupler exists in the FPGA fabric to isolate one 115 region of the FPGA from the busses while that region is 116 being reprogrammed during partial reconfig. 117 118config FPGA_REGION 119 tristate "FPGA Region" 120 depends on FPGA_BRIDGE 121 help 122 FPGA Region common code. A FPGA Region controls a FPGA Manager 123 and the FPGA Bridges associated with either a reconfigurable 124 region of an FPGA or a whole FPGA. 125 126config OF_FPGA_REGION 127 tristate "FPGA Region Device Tree Overlay Support" 128 depends on OF && FPGA_REGION 129 help 130 Support for loading FPGA images by applying a Device Tree 131 overlay. 132 133config FPGA_DFL 134 tristate "FPGA Device Feature List (DFL) support" 135 select FPGA_BRIDGE 136 select FPGA_REGION 137 help 138 Device Feature List (DFL) defines a feature list structure that 139 creates a linked list of feature headers within the MMIO space 140 to provide an extensible way of adding features for FPGA. 141 Driver can walk through the feature headers to enumerate feature 142 devices (e.g. FPGA Management Engine, Port and Accelerator 143 Function Unit) and their private features for target FPGA devices. 144 145 Select this option to enable common support for Field-Programmable 146 Gate Array (FPGA) solutions which implement Device Feature List. 147 It provides enumeration APIs and feature device infrastructure. 148 149config FPGA_DFL_FME 150 tristate "FPGA DFL FME Driver" 151 depends on FPGA_DFL 152 help 153 The FPGA Management Engine (FME) is a feature device implemented 154 under Device Feature List (DFL) framework. Select this option to 155 enable the platform device driver for FME which implements all 156 FPGA platform level management features. There shall be one FME 157 per DFL based FPGA device. 158 159config FPGA_DFL_FME_MGR 160 tristate "FPGA DFL FME Manager Driver" 161 depends on FPGA_DFL_FME && HAS_IOMEM 162 help 163 Say Y to enable FPGA Manager driver for FPGA Management Engine. 164 165config FPGA_DFL_FME_BRIDGE 166 tristate "FPGA DFL FME Bridge Driver" 167 depends on FPGA_DFL_FME && HAS_IOMEM 168 help 169 Say Y to enable FPGA Bridge driver for FPGA Management Engine. 170 171config FPGA_DFL_FME_REGION 172 tristate "FPGA DFL FME Region Driver" 173 depends on FPGA_DFL_FME && HAS_IOMEM 174 help 175 Say Y to enable FPGA Region driver for FPGA Management Engine. 176 177config FPGA_DFL_AFU 178 tristate "FPGA DFL AFU Driver" 179 depends on FPGA_DFL 180 help 181 This is the driver for FPGA Accelerated Function Unit (AFU) which 182 implements AFU and Port management features. A User AFU connects 183 to the FPGA infrastructure via a Port. There may be more than one 184 Port/AFU per DFL based FPGA device. 185 186config FPGA_DFL_PCI 187 tristate "FPGA DFL PCIe Device Driver" 188 depends on PCI && FPGA_DFL 189 help 190 Select this option to enable PCIe driver for PCIe-based 191 Field-Programmable Gate Array (FPGA) solutions which implement 192 the Device Feature List (DFL). This driver provides interfaces 193 for userspace applications to configure, enumerate, open and access 194 FPGA accelerators on the FPGA DFL devices, enables system level 195 management functions such as FPGA partial reconfiguration, power 196 management and virtualization with DFL framework and DFL feature 197 device drivers. 198 199 To compile this as a module, choose M here. 200 201endif # FPGA 202