xref: /openbmc/linux/drivers/fpga/Kconfig (revision 0c94efab) 
1# SPDX-License-Identifier: GPL-2.0-only
2#
3# FPGA framework configuration
4#
5
6menuconfig FPGA
7	tristate "FPGA Configuration Framework"
8	help
9	  Say Y here if you want support for configuring FPGAs from the
10	  kernel.  The FPGA framework adds a FPGA manager class and FPGA
11	  manager drivers.
12
13if FPGA
14
15config FPGA_MGR_SOCFPGA
16	tristate "Altera SOCFPGA FPGA Manager"
17	depends on ARCH_SOCFPGA || COMPILE_TEST
18	help
19	  FPGA manager driver support for Altera SOCFPGA.
20
21config FPGA_MGR_SOCFPGA_A10
22	tristate "Altera SoCFPGA Arria10"
23	depends on ARCH_SOCFPGA || COMPILE_TEST
24	select REGMAP_MMIO
25	help
26	  FPGA manager driver support for Altera Arria10 SoCFPGA.
27
28config ALTERA_PR_IP_CORE
29        tristate "Altera Partial Reconfiguration IP Core"
30        help
31          Core driver support for Altera Partial Reconfiguration IP component
32
33config ALTERA_PR_IP_CORE_PLAT
34	tristate "Platform support of Altera Partial Reconfiguration IP Core"
35	depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM
36	help
37	  Platform driver support for Altera Partial Reconfiguration IP
38	  component
39
40config FPGA_MGR_ALTERA_PS_SPI
41	tristate "Altera FPGA Passive Serial over SPI"
42	depends on SPI
43	help
44	  FPGA manager driver support for Altera Arria/Cyclone/Stratix
45	  using the passive serial interface over SPI.
46
47config FPGA_MGR_ALTERA_CVP
48	tristate "Altera Arria-V/Cyclone-V/Stratix-V CvP FPGA Manager"
49	depends on PCI
50	help
51	  FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V
52	  and Arria 10 Altera FPGAs using the CvP interface over PCIe.
53
54config FPGA_MGR_ZYNQ_FPGA
55	tristate "Xilinx Zynq FPGA"
56	depends on ARCH_ZYNQ || COMPILE_TEST
57	help
58	  FPGA manager driver support for Xilinx Zynq FPGAs.
59
60config FPGA_MGR_STRATIX10_SOC
61	tristate "Intel Stratix10 SoC FPGA Manager"
62	depends on (ARCH_STRATIX10 && INTEL_STRATIX10_SERVICE)
63	help
64	  FPGA manager driver support for the Intel Stratix10 SoC.
65
66config FPGA_MGR_XILINX_SPI
67	tristate "Xilinx Configuration over Slave Serial (SPI)"
68	depends on SPI
69	help
70	  FPGA manager driver support for Xilinx FPGA configuration
71	  over slave serial interface.
72
73config FPGA_MGR_ICE40_SPI
74	tristate "Lattice iCE40 SPI"
75	depends on OF && SPI
76	help
77	  FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
78
79config FPGA_MGR_MACHXO2_SPI
80	tristate "Lattice MachXO2 SPI"
81	depends on SPI
82	help
83	  FPGA manager driver support for Lattice MachXO2 configuration
84	  over slave SPI interface.
85
86config FPGA_MGR_TS73XX
87	tristate "Technologic Systems TS-73xx SBC FPGA Manager"
88	depends on ARCH_EP93XX && MACH_TS72XX
89	help
90	  FPGA manager driver support for the Altera Cyclone II FPGA
91	  present on the TS-73xx SBC boards.
92
93config FPGA_BRIDGE
94	tristate "FPGA Bridge Framework"
95	help
96	  Say Y here if you want to support bridges connected between host
97	  processors and FPGAs or between FPGAs.
98
99config SOCFPGA_FPGA_BRIDGE
100	tristate "Altera SoCFPGA FPGA Bridges"
101	depends on ARCH_SOCFPGA && FPGA_BRIDGE
102	help
103	  Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
104	  devices.
105
106config ALTERA_FREEZE_BRIDGE
107	tristate "Altera FPGA Freeze Bridge"
108	depends on FPGA_BRIDGE && HAS_IOMEM
109	help
110	  Say Y to enable drivers for Altera FPGA Freeze bridges.  A
111	  freeze bridge is a bridge that exists in the FPGA fabric to
112	  isolate one region of the FPGA from the busses while that
113	  region is being reprogrammed.
114
115config XILINX_PR_DECOUPLER
116	tristate "Xilinx LogiCORE PR Decoupler"
117	depends on FPGA_BRIDGE
118	depends on HAS_IOMEM
119	help
120	  Say Y to enable drivers for Xilinx LogiCORE PR Decoupler.
121	  The PR Decoupler exists in the FPGA fabric to isolate one
122	  region of the FPGA from the busses while that region is
123	  being reprogrammed during partial reconfig.
124
125config FPGA_REGION
126	tristate "FPGA Region"
127	depends on FPGA_BRIDGE
128	help
129	  FPGA Region common code.  A FPGA Region controls a FPGA Manager
130	  and the FPGA Bridges associated with either a reconfigurable
131	  region of an FPGA or a whole FPGA.
132
133config OF_FPGA_REGION
134	tristate "FPGA Region Device Tree Overlay Support"
135	depends on OF && FPGA_REGION
136	help
137	  Support for loading FPGA images by applying a Device Tree
138	  overlay.
139
140config FPGA_DFL
141	tristate "FPGA Device Feature List (DFL) support"
142	select FPGA_BRIDGE
143	select FPGA_REGION
144	help
145	  Device Feature List (DFL) defines a feature list structure that
146	  creates a linked list of feature headers within the MMIO space
147	  to provide an extensible way of adding features for FPGA.
148	  Driver can walk through the feature headers to enumerate feature
149	  devices (e.g. FPGA Management Engine, Port and Accelerator
150	  Function Unit) and their private features for target FPGA devices.
151
152	  Select this option to enable common support for Field-Programmable
153	  Gate Array (FPGA) solutions which implement Device Feature List.
154	  It provides enumeration APIs and feature device infrastructure.
155
156config FPGA_DFL_FME
157	tristate "FPGA DFL FME Driver"
158	depends on FPGA_DFL
159	help
160	  The FPGA Management Engine (FME) is a feature device implemented
161	  under Device Feature List (DFL) framework. Select this option to
162	  enable the platform device driver for FME which implements all
163	  FPGA platform level management features. There shall be one FME
164	  per DFL based FPGA device.
165
166config FPGA_DFL_FME_MGR
167	tristate "FPGA DFL FME Manager Driver"
168	depends on FPGA_DFL_FME && HAS_IOMEM
169	help
170	  Say Y to enable FPGA Manager driver for FPGA Management Engine.
171
172config FPGA_DFL_FME_BRIDGE
173	tristate "FPGA DFL FME Bridge Driver"
174	depends on FPGA_DFL_FME && HAS_IOMEM
175	help
176	  Say Y to enable FPGA Bridge driver for FPGA Management Engine.
177
178config FPGA_DFL_FME_REGION
179	tristate "FPGA DFL FME Region Driver"
180	depends on FPGA_DFL_FME && HAS_IOMEM
181	help
182	  Say Y to enable FPGA Region driver for FPGA Management Engine.
183
184config FPGA_DFL_AFU
185	tristate "FPGA DFL AFU Driver"
186	depends on FPGA_DFL
187	help
188	  This is the driver for FPGA Accelerated Function Unit (AFU) which
189	  implements AFU and Port management features. A User AFU connects
190	  to the FPGA infrastructure via a Port. There may be more than one
191	  Port/AFU per DFL based FPGA device.
192
193config FPGA_DFL_PCI
194	tristate "FPGA DFL PCIe Device Driver"
195	depends on PCI && FPGA_DFL
196	help
197	  Select this option to enable PCIe driver for PCIe-based
198	  Field-Programmable Gate Array (FPGA) solutions which implement
199	  the Device Feature List (DFL). This driver provides interfaces
200	  for userspace applications to configure, enumerate, open and access
201	  FPGA accelerators on the FPGA DFL devices, enables system level
202	  management functions such as FPGA partial reconfiguration, power
203	  management and virtualization with DFL framework and DFL feature
204	  device drivers.
205
206	  To compile this as a module, choose M here.
207
208config FPGA_MGR_ZYNQMP_FPGA
209	tristate "Xilinx ZynqMP FPGA"
210	depends on ARCH_ZYNQMP || COMPILE_TEST
211	help
212	  FPGA manager driver support for Xilinx ZynqMP FPGAs.
213	  This driver uses the processor configuration port(PCAP)
214	  to configure the programmable logic(PL) through PS
215	  on ZynqMP SoC.
216
217endif # FPGA
218