1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2010,2015,2019 The Linux Foundation. All rights reserved. 3 * Copyright (C) 2015 Linaro Ltd. 4 */ 5 #include <linux/platform_device.h> 6 #include <linux/init.h> 7 #include <linux/interrupt.h> 8 #include <linux/completion.h> 9 #include <linux/cpumask.h> 10 #include <linux/export.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/interconnect.h> 13 #include <linux/module.h> 14 #include <linux/types.h> 15 #include <linux/firmware/qcom/qcom_scm.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/of_irq.h> 19 #include <linux/of_platform.h> 20 #include <linux/clk.h> 21 #include <linux/reset-controller.h> 22 #include <linux/arm-smccc.h> 23 24 #include "qcom_scm.h" 25 26 static bool download_mode = IS_ENABLED(CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT); 27 module_param(download_mode, bool, 0); 28 29 #define SCM_HAS_CORE_CLK BIT(0) 30 #define SCM_HAS_IFACE_CLK BIT(1) 31 #define SCM_HAS_BUS_CLK BIT(2) 32 33 struct qcom_scm { 34 struct device *dev; 35 struct clk *core_clk; 36 struct clk *iface_clk; 37 struct clk *bus_clk; 38 struct icc_path *path; 39 struct completion waitq_comp; 40 struct reset_controller_dev reset; 41 42 /* control access to the interconnect path */ 43 struct mutex scm_bw_lock; 44 int scm_vote_count; 45 46 u64 dload_mode_addr; 47 }; 48 49 struct qcom_scm_current_perm_info { 50 __le32 vmid; 51 __le32 perm; 52 __le64 ctx; 53 __le32 ctx_size; 54 __le32 unused; 55 }; 56 57 struct qcom_scm_mem_map_info { 58 __le64 mem_addr; 59 __le64 mem_size; 60 }; 61 62 /* Each bit configures cold/warm boot address for one of the 4 CPUs */ 63 static const u8 qcom_scm_cpu_cold_bits[QCOM_SCM_BOOT_MAX_CPUS] = { 64 0, BIT(0), BIT(3), BIT(5) 65 }; 66 static const u8 qcom_scm_cpu_warm_bits[QCOM_SCM_BOOT_MAX_CPUS] = { 67 BIT(2), BIT(1), BIT(4), BIT(6) 68 }; 69 70 #define QCOM_SMC_WAITQ_FLAG_WAKE_ONE BIT(0) 71 #define QCOM_SMC_WAITQ_FLAG_WAKE_ALL BIT(1) 72 73 static const char * const qcom_scm_convention_names[] = { 74 [SMC_CONVENTION_UNKNOWN] = "unknown", 75 [SMC_CONVENTION_ARM_32] = "smc arm 32", 76 [SMC_CONVENTION_ARM_64] = "smc arm 64", 77 [SMC_CONVENTION_LEGACY] = "smc legacy", 78 }; 79 80 static struct qcom_scm *__scm; 81 82 static int qcom_scm_clk_enable(void) 83 { 84 int ret; 85 86 ret = clk_prepare_enable(__scm->core_clk); 87 if (ret) 88 goto bail; 89 90 ret = clk_prepare_enable(__scm->iface_clk); 91 if (ret) 92 goto disable_core; 93 94 ret = clk_prepare_enable(__scm->bus_clk); 95 if (ret) 96 goto disable_iface; 97 98 return 0; 99 100 disable_iface: 101 clk_disable_unprepare(__scm->iface_clk); 102 disable_core: 103 clk_disable_unprepare(__scm->core_clk); 104 bail: 105 return ret; 106 } 107 108 static void qcom_scm_clk_disable(void) 109 { 110 clk_disable_unprepare(__scm->core_clk); 111 clk_disable_unprepare(__scm->iface_clk); 112 clk_disable_unprepare(__scm->bus_clk); 113 } 114 115 static int qcom_scm_bw_enable(void) 116 { 117 int ret = 0; 118 119 if (!__scm->path) 120 return 0; 121 122 if (IS_ERR(__scm->path)) 123 return -EINVAL; 124 125 mutex_lock(&__scm->scm_bw_lock); 126 if (!__scm->scm_vote_count) { 127 ret = icc_set_bw(__scm->path, 0, UINT_MAX); 128 if (ret < 0) { 129 dev_err(__scm->dev, "failed to set bandwidth request\n"); 130 goto err_bw; 131 } 132 } 133 __scm->scm_vote_count++; 134 err_bw: 135 mutex_unlock(&__scm->scm_bw_lock); 136 137 return ret; 138 } 139 140 static void qcom_scm_bw_disable(void) 141 { 142 if (IS_ERR_OR_NULL(__scm->path)) 143 return; 144 145 mutex_lock(&__scm->scm_bw_lock); 146 if (__scm->scm_vote_count-- == 1) 147 icc_set_bw(__scm->path, 0, 0); 148 mutex_unlock(&__scm->scm_bw_lock); 149 } 150 151 enum qcom_scm_convention qcom_scm_convention = SMC_CONVENTION_UNKNOWN; 152 static DEFINE_SPINLOCK(scm_query_lock); 153 154 static enum qcom_scm_convention __get_convention(void) 155 { 156 unsigned long flags; 157 struct qcom_scm_desc desc = { 158 .svc = QCOM_SCM_SVC_INFO, 159 .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL, 160 .args[0] = SCM_SMC_FNID(QCOM_SCM_SVC_INFO, 161 QCOM_SCM_INFO_IS_CALL_AVAIL) | 162 (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT), 163 .arginfo = QCOM_SCM_ARGS(1), 164 .owner = ARM_SMCCC_OWNER_SIP, 165 }; 166 struct qcom_scm_res res; 167 enum qcom_scm_convention probed_convention; 168 int ret; 169 bool forced = false; 170 171 if (likely(qcom_scm_convention != SMC_CONVENTION_UNKNOWN)) 172 return qcom_scm_convention; 173 174 /* 175 * Device isn't required as there is only one argument - no device 176 * needed to dma_map_single to secure world 177 */ 178 probed_convention = SMC_CONVENTION_ARM_64; 179 ret = __scm_smc_call(NULL, &desc, probed_convention, &res, true); 180 if (!ret && res.result[0] == 1) 181 goto found; 182 183 /* 184 * Some SC7180 firmwares didn't implement the 185 * QCOM_SCM_INFO_IS_CALL_AVAIL call, so we fallback to forcing ARM_64 186 * calling conventions on these firmwares. Luckily we don't make any 187 * early calls into the firmware on these SoCs so the device pointer 188 * will be valid here to check if the compatible matches. 189 */ 190 if (of_device_is_compatible(__scm ? __scm->dev->of_node : NULL, "qcom,scm-sc7180")) { 191 forced = true; 192 goto found; 193 } 194 195 probed_convention = SMC_CONVENTION_ARM_32; 196 ret = __scm_smc_call(NULL, &desc, probed_convention, &res, true); 197 if (!ret && res.result[0] == 1) 198 goto found; 199 200 probed_convention = SMC_CONVENTION_LEGACY; 201 found: 202 spin_lock_irqsave(&scm_query_lock, flags); 203 if (probed_convention != qcom_scm_convention) { 204 qcom_scm_convention = probed_convention; 205 pr_info("qcom_scm: convention: %s%s\n", 206 qcom_scm_convention_names[qcom_scm_convention], 207 forced ? " (forced)" : ""); 208 } 209 spin_unlock_irqrestore(&scm_query_lock, flags); 210 211 return qcom_scm_convention; 212 } 213 214 /** 215 * qcom_scm_call() - Invoke a syscall in the secure world 216 * @dev: device 217 * @desc: Descriptor structure containing arguments and return values 218 * @res: Structure containing results from SMC/HVC call 219 * 220 * Sends a command to the SCM and waits for the command to finish processing. 221 * This should *only* be called in pre-emptible context. 222 */ 223 static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc, 224 struct qcom_scm_res *res) 225 { 226 might_sleep(); 227 switch (__get_convention()) { 228 case SMC_CONVENTION_ARM_32: 229 case SMC_CONVENTION_ARM_64: 230 return scm_smc_call(dev, desc, res, false); 231 case SMC_CONVENTION_LEGACY: 232 return scm_legacy_call(dev, desc, res); 233 default: 234 pr_err("Unknown current SCM calling convention.\n"); 235 return -EINVAL; 236 } 237 } 238 239 /** 240 * qcom_scm_call_atomic() - atomic variation of qcom_scm_call() 241 * @dev: device 242 * @desc: Descriptor structure containing arguments and return values 243 * @res: Structure containing results from SMC/HVC call 244 * 245 * Sends a command to the SCM and waits for the command to finish processing. 246 * This can be called in atomic context. 247 */ 248 static int qcom_scm_call_atomic(struct device *dev, 249 const struct qcom_scm_desc *desc, 250 struct qcom_scm_res *res) 251 { 252 switch (__get_convention()) { 253 case SMC_CONVENTION_ARM_32: 254 case SMC_CONVENTION_ARM_64: 255 return scm_smc_call(dev, desc, res, true); 256 case SMC_CONVENTION_LEGACY: 257 return scm_legacy_call_atomic(dev, desc, res); 258 default: 259 pr_err("Unknown current SCM calling convention.\n"); 260 return -EINVAL; 261 } 262 } 263 264 static bool __qcom_scm_is_call_available(struct device *dev, u32 svc_id, 265 u32 cmd_id) 266 { 267 int ret; 268 struct qcom_scm_desc desc = { 269 .svc = QCOM_SCM_SVC_INFO, 270 .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL, 271 .owner = ARM_SMCCC_OWNER_SIP, 272 }; 273 struct qcom_scm_res res; 274 275 desc.arginfo = QCOM_SCM_ARGS(1); 276 switch (__get_convention()) { 277 case SMC_CONVENTION_ARM_32: 278 case SMC_CONVENTION_ARM_64: 279 desc.args[0] = SCM_SMC_FNID(svc_id, cmd_id) | 280 (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT); 281 break; 282 case SMC_CONVENTION_LEGACY: 283 desc.args[0] = SCM_LEGACY_FNID(svc_id, cmd_id); 284 break; 285 default: 286 pr_err("Unknown SMC convention being used\n"); 287 return false; 288 } 289 290 ret = qcom_scm_call(dev, &desc, &res); 291 292 return ret ? false : !!res.result[0]; 293 } 294 295 static int qcom_scm_set_boot_addr(void *entry, const u8 *cpu_bits) 296 { 297 int cpu; 298 unsigned int flags = 0; 299 struct qcom_scm_desc desc = { 300 .svc = QCOM_SCM_SVC_BOOT, 301 .cmd = QCOM_SCM_BOOT_SET_ADDR, 302 .arginfo = QCOM_SCM_ARGS(2), 303 .owner = ARM_SMCCC_OWNER_SIP, 304 }; 305 306 for_each_present_cpu(cpu) { 307 if (cpu >= QCOM_SCM_BOOT_MAX_CPUS) 308 return -EINVAL; 309 flags |= cpu_bits[cpu]; 310 } 311 312 desc.args[0] = flags; 313 desc.args[1] = virt_to_phys(entry); 314 315 return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL); 316 } 317 318 static int qcom_scm_set_boot_addr_mc(void *entry, unsigned int flags) 319 { 320 struct qcom_scm_desc desc = { 321 .svc = QCOM_SCM_SVC_BOOT, 322 .cmd = QCOM_SCM_BOOT_SET_ADDR_MC, 323 .owner = ARM_SMCCC_OWNER_SIP, 324 .arginfo = QCOM_SCM_ARGS(6), 325 .args = { 326 virt_to_phys(entry), 327 /* Apply to all CPUs in all affinity levels */ 328 ~0ULL, ~0ULL, ~0ULL, ~0ULL, 329 flags, 330 }, 331 }; 332 333 /* Need a device for DMA of the additional arguments */ 334 if (!__scm || __get_convention() == SMC_CONVENTION_LEGACY) 335 return -EOPNOTSUPP; 336 337 return qcom_scm_call(__scm->dev, &desc, NULL); 338 } 339 340 /** 341 * qcom_scm_set_warm_boot_addr() - Set the warm boot address for all cpus 342 * @entry: Entry point function for the cpus 343 * 344 * Set the Linux entry point for the SCM to transfer control to when coming 345 * out of a power down. CPU power down may be executed on cpuidle or hotplug. 346 */ 347 int qcom_scm_set_warm_boot_addr(void *entry) 348 { 349 if (qcom_scm_set_boot_addr_mc(entry, QCOM_SCM_BOOT_MC_FLAG_WARMBOOT)) 350 /* Fallback to old SCM call */ 351 return qcom_scm_set_boot_addr(entry, qcom_scm_cpu_warm_bits); 352 return 0; 353 } 354 EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr); 355 356 /** 357 * qcom_scm_set_cold_boot_addr() - Set the cold boot address for all cpus 358 * @entry: Entry point function for the cpus 359 */ 360 int qcom_scm_set_cold_boot_addr(void *entry) 361 { 362 if (qcom_scm_set_boot_addr_mc(entry, QCOM_SCM_BOOT_MC_FLAG_COLDBOOT)) 363 /* Fallback to old SCM call */ 364 return qcom_scm_set_boot_addr(entry, qcom_scm_cpu_cold_bits); 365 return 0; 366 } 367 EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr); 368 369 /** 370 * qcom_scm_cpu_power_down() - Power down the cpu 371 * @flags: Flags to flush cache 372 * 373 * This is an end point to power down cpu. If there was a pending interrupt, 374 * the control would return from this function, otherwise, the cpu jumps to the 375 * warm boot entry point set for this cpu upon reset. 376 */ 377 void qcom_scm_cpu_power_down(u32 flags) 378 { 379 struct qcom_scm_desc desc = { 380 .svc = QCOM_SCM_SVC_BOOT, 381 .cmd = QCOM_SCM_BOOT_TERMINATE_PC, 382 .args[0] = flags & QCOM_SCM_FLUSH_FLAG_MASK, 383 .arginfo = QCOM_SCM_ARGS(1), 384 .owner = ARM_SMCCC_OWNER_SIP, 385 }; 386 387 qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL); 388 } 389 EXPORT_SYMBOL(qcom_scm_cpu_power_down); 390 391 int qcom_scm_set_remote_state(u32 state, u32 id) 392 { 393 struct qcom_scm_desc desc = { 394 .svc = QCOM_SCM_SVC_BOOT, 395 .cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE, 396 .arginfo = QCOM_SCM_ARGS(2), 397 .args[0] = state, 398 .args[1] = id, 399 .owner = ARM_SMCCC_OWNER_SIP, 400 }; 401 struct qcom_scm_res res; 402 int ret; 403 404 ret = qcom_scm_call(__scm->dev, &desc, &res); 405 406 return ret ? : res.result[0]; 407 } 408 EXPORT_SYMBOL(qcom_scm_set_remote_state); 409 410 static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) 411 { 412 struct qcom_scm_desc desc = { 413 .svc = QCOM_SCM_SVC_BOOT, 414 .cmd = QCOM_SCM_BOOT_SET_DLOAD_MODE, 415 .arginfo = QCOM_SCM_ARGS(2), 416 .args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE, 417 .owner = ARM_SMCCC_OWNER_SIP, 418 }; 419 420 desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0; 421 422 return qcom_scm_call_atomic(__scm->dev, &desc, NULL); 423 } 424 425 static void qcom_scm_set_download_mode(bool enable) 426 { 427 bool avail; 428 int ret = 0; 429 430 avail = __qcom_scm_is_call_available(__scm->dev, 431 QCOM_SCM_SVC_BOOT, 432 QCOM_SCM_BOOT_SET_DLOAD_MODE); 433 if (avail) { 434 ret = __qcom_scm_set_dload_mode(__scm->dev, enable); 435 } else if (__scm->dload_mode_addr) { 436 ret = qcom_scm_io_writel(__scm->dload_mode_addr, 437 enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0); 438 } else { 439 dev_err(__scm->dev, 440 "No available mechanism for setting download mode\n"); 441 } 442 443 if (ret) 444 dev_err(__scm->dev, "failed to set download mode: %d\n", ret); 445 } 446 447 /** 448 * qcom_scm_pas_init_image() - Initialize peripheral authentication service 449 * state machine for a given peripheral, using the 450 * metadata 451 * @peripheral: peripheral id 452 * @metadata: pointer to memory containing ELF header, program header table 453 * and optional blob of data used for authenticating the metadata 454 * and the rest of the firmware 455 * @size: size of the metadata 456 * @ctx: optional metadata context 457 * 458 * Return: 0 on success. 459 * 460 * Upon successful return, the PAS metadata context (@ctx) will be used to 461 * track the metadata allocation, this needs to be released by invoking 462 * qcom_scm_pas_metadata_release() by the caller. 463 */ 464 int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size, 465 struct qcom_scm_pas_metadata *ctx) 466 { 467 dma_addr_t mdata_phys; 468 void *mdata_buf; 469 int ret; 470 struct qcom_scm_desc desc = { 471 .svc = QCOM_SCM_SVC_PIL, 472 .cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE, 473 .arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW), 474 .args[0] = peripheral, 475 .owner = ARM_SMCCC_OWNER_SIP, 476 }; 477 struct qcom_scm_res res; 478 479 /* 480 * During the scm call memory protection will be enabled for the meta 481 * data blob, so make sure it's physically contiguous, 4K aligned and 482 * non-cachable to avoid XPU violations. 483 */ 484 mdata_buf = dma_alloc_coherent(__scm->dev, size, &mdata_phys, 485 GFP_KERNEL); 486 if (!mdata_buf) { 487 dev_err(__scm->dev, "Allocation of metadata buffer failed.\n"); 488 return -ENOMEM; 489 } 490 memcpy(mdata_buf, metadata, size); 491 492 ret = qcom_scm_clk_enable(); 493 if (ret) 494 goto out; 495 496 ret = qcom_scm_bw_enable(); 497 if (ret) 498 return ret; 499 500 desc.args[1] = mdata_phys; 501 502 ret = qcom_scm_call(__scm->dev, &desc, &res); 503 504 qcom_scm_bw_disable(); 505 qcom_scm_clk_disable(); 506 507 out: 508 if (ret < 0 || !ctx) { 509 dma_free_coherent(__scm->dev, size, mdata_buf, mdata_phys); 510 } else if (ctx) { 511 ctx->ptr = mdata_buf; 512 ctx->phys = mdata_phys; 513 ctx->size = size; 514 } 515 516 return ret ? : res.result[0]; 517 } 518 EXPORT_SYMBOL(qcom_scm_pas_init_image); 519 520 /** 521 * qcom_scm_pas_metadata_release() - release metadata context 522 * @ctx: metadata context 523 */ 524 void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx) 525 { 526 if (!ctx->ptr) 527 return; 528 529 dma_free_coherent(__scm->dev, ctx->size, ctx->ptr, ctx->phys); 530 531 ctx->ptr = NULL; 532 ctx->phys = 0; 533 ctx->size = 0; 534 } 535 EXPORT_SYMBOL(qcom_scm_pas_metadata_release); 536 537 /** 538 * qcom_scm_pas_mem_setup() - Prepare the memory related to a given peripheral 539 * for firmware loading 540 * @peripheral: peripheral id 541 * @addr: start address of memory area to prepare 542 * @size: size of the memory area to prepare 543 * 544 * Returns 0 on success. 545 */ 546 int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size) 547 { 548 int ret; 549 struct qcom_scm_desc desc = { 550 .svc = QCOM_SCM_SVC_PIL, 551 .cmd = QCOM_SCM_PIL_PAS_MEM_SETUP, 552 .arginfo = QCOM_SCM_ARGS(3), 553 .args[0] = peripheral, 554 .args[1] = addr, 555 .args[2] = size, 556 .owner = ARM_SMCCC_OWNER_SIP, 557 }; 558 struct qcom_scm_res res; 559 560 ret = qcom_scm_clk_enable(); 561 if (ret) 562 return ret; 563 564 ret = qcom_scm_bw_enable(); 565 if (ret) 566 return ret; 567 568 ret = qcom_scm_call(__scm->dev, &desc, &res); 569 qcom_scm_bw_disable(); 570 qcom_scm_clk_disable(); 571 572 return ret ? : res.result[0]; 573 } 574 EXPORT_SYMBOL(qcom_scm_pas_mem_setup); 575 576 /** 577 * qcom_scm_pas_auth_and_reset() - Authenticate the given peripheral firmware 578 * and reset the remote processor 579 * @peripheral: peripheral id 580 * 581 * Return 0 on success. 582 */ 583 int qcom_scm_pas_auth_and_reset(u32 peripheral) 584 { 585 int ret; 586 struct qcom_scm_desc desc = { 587 .svc = QCOM_SCM_SVC_PIL, 588 .cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET, 589 .arginfo = QCOM_SCM_ARGS(1), 590 .args[0] = peripheral, 591 .owner = ARM_SMCCC_OWNER_SIP, 592 }; 593 struct qcom_scm_res res; 594 595 ret = qcom_scm_clk_enable(); 596 if (ret) 597 return ret; 598 599 ret = qcom_scm_bw_enable(); 600 if (ret) 601 return ret; 602 603 ret = qcom_scm_call(__scm->dev, &desc, &res); 604 qcom_scm_bw_disable(); 605 qcom_scm_clk_disable(); 606 607 return ret ? : res.result[0]; 608 } 609 EXPORT_SYMBOL(qcom_scm_pas_auth_and_reset); 610 611 /** 612 * qcom_scm_pas_shutdown() - Shut down the remote processor 613 * @peripheral: peripheral id 614 * 615 * Returns 0 on success. 616 */ 617 int qcom_scm_pas_shutdown(u32 peripheral) 618 { 619 int ret; 620 struct qcom_scm_desc desc = { 621 .svc = QCOM_SCM_SVC_PIL, 622 .cmd = QCOM_SCM_PIL_PAS_SHUTDOWN, 623 .arginfo = QCOM_SCM_ARGS(1), 624 .args[0] = peripheral, 625 .owner = ARM_SMCCC_OWNER_SIP, 626 }; 627 struct qcom_scm_res res; 628 629 ret = qcom_scm_clk_enable(); 630 if (ret) 631 return ret; 632 633 ret = qcom_scm_bw_enable(); 634 if (ret) 635 return ret; 636 637 ret = qcom_scm_call(__scm->dev, &desc, &res); 638 639 qcom_scm_bw_disable(); 640 qcom_scm_clk_disable(); 641 642 return ret ? : res.result[0]; 643 } 644 EXPORT_SYMBOL(qcom_scm_pas_shutdown); 645 646 /** 647 * qcom_scm_pas_supported() - Check if the peripheral authentication service is 648 * available for the given peripherial 649 * @peripheral: peripheral id 650 * 651 * Returns true if PAS is supported for this peripheral, otherwise false. 652 */ 653 bool qcom_scm_pas_supported(u32 peripheral) 654 { 655 int ret; 656 struct qcom_scm_desc desc = { 657 .svc = QCOM_SCM_SVC_PIL, 658 .cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED, 659 .arginfo = QCOM_SCM_ARGS(1), 660 .args[0] = peripheral, 661 .owner = ARM_SMCCC_OWNER_SIP, 662 }; 663 struct qcom_scm_res res; 664 665 if (!__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL, 666 QCOM_SCM_PIL_PAS_IS_SUPPORTED)) 667 return false; 668 669 ret = qcom_scm_call(__scm->dev, &desc, &res); 670 671 return ret ? false : !!res.result[0]; 672 } 673 EXPORT_SYMBOL(qcom_scm_pas_supported); 674 675 static int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) 676 { 677 struct qcom_scm_desc desc = { 678 .svc = QCOM_SCM_SVC_PIL, 679 .cmd = QCOM_SCM_PIL_PAS_MSS_RESET, 680 .arginfo = QCOM_SCM_ARGS(2), 681 .args[0] = reset, 682 .args[1] = 0, 683 .owner = ARM_SMCCC_OWNER_SIP, 684 }; 685 struct qcom_scm_res res; 686 int ret; 687 688 ret = qcom_scm_call(__scm->dev, &desc, &res); 689 690 return ret ? : res.result[0]; 691 } 692 693 static int qcom_scm_pas_reset_assert(struct reset_controller_dev *rcdev, 694 unsigned long idx) 695 { 696 if (idx != 0) 697 return -EINVAL; 698 699 return __qcom_scm_pas_mss_reset(__scm->dev, 1); 700 } 701 702 static int qcom_scm_pas_reset_deassert(struct reset_controller_dev *rcdev, 703 unsigned long idx) 704 { 705 if (idx != 0) 706 return -EINVAL; 707 708 return __qcom_scm_pas_mss_reset(__scm->dev, 0); 709 } 710 711 static const struct reset_control_ops qcom_scm_pas_reset_ops = { 712 .assert = qcom_scm_pas_reset_assert, 713 .deassert = qcom_scm_pas_reset_deassert, 714 }; 715 716 int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) 717 { 718 struct qcom_scm_desc desc = { 719 .svc = QCOM_SCM_SVC_IO, 720 .cmd = QCOM_SCM_IO_READ, 721 .arginfo = QCOM_SCM_ARGS(1), 722 .args[0] = addr, 723 .owner = ARM_SMCCC_OWNER_SIP, 724 }; 725 struct qcom_scm_res res; 726 int ret; 727 728 729 ret = qcom_scm_call_atomic(__scm->dev, &desc, &res); 730 if (ret >= 0) 731 *val = res.result[0]; 732 733 return ret < 0 ? ret : 0; 734 } 735 EXPORT_SYMBOL(qcom_scm_io_readl); 736 737 int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) 738 { 739 struct qcom_scm_desc desc = { 740 .svc = QCOM_SCM_SVC_IO, 741 .cmd = QCOM_SCM_IO_WRITE, 742 .arginfo = QCOM_SCM_ARGS(2), 743 .args[0] = addr, 744 .args[1] = val, 745 .owner = ARM_SMCCC_OWNER_SIP, 746 }; 747 748 return qcom_scm_call_atomic(__scm->dev, &desc, NULL); 749 } 750 EXPORT_SYMBOL(qcom_scm_io_writel); 751 752 /** 753 * qcom_scm_restore_sec_cfg_available() - Check if secure environment 754 * supports restore security config interface. 755 * 756 * Return true if restore-cfg interface is supported, false if not. 757 */ 758 bool qcom_scm_restore_sec_cfg_available(void) 759 { 760 return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_MP, 761 QCOM_SCM_MP_RESTORE_SEC_CFG); 762 } 763 EXPORT_SYMBOL(qcom_scm_restore_sec_cfg_available); 764 765 int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) 766 { 767 struct qcom_scm_desc desc = { 768 .svc = QCOM_SCM_SVC_MP, 769 .cmd = QCOM_SCM_MP_RESTORE_SEC_CFG, 770 .arginfo = QCOM_SCM_ARGS(2), 771 .args[0] = device_id, 772 .args[1] = spare, 773 .owner = ARM_SMCCC_OWNER_SIP, 774 }; 775 struct qcom_scm_res res; 776 int ret; 777 778 ret = qcom_scm_call(__scm->dev, &desc, &res); 779 780 return ret ? : res.result[0]; 781 } 782 EXPORT_SYMBOL(qcom_scm_restore_sec_cfg); 783 784 int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) 785 { 786 struct qcom_scm_desc desc = { 787 .svc = QCOM_SCM_SVC_MP, 788 .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE, 789 .arginfo = QCOM_SCM_ARGS(1), 790 .args[0] = spare, 791 .owner = ARM_SMCCC_OWNER_SIP, 792 }; 793 struct qcom_scm_res res; 794 int ret; 795 796 ret = qcom_scm_call(__scm->dev, &desc, &res); 797 798 if (size) 799 *size = res.result[0]; 800 801 return ret ? : res.result[1]; 802 } 803 EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_size); 804 805 int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) 806 { 807 struct qcom_scm_desc desc = { 808 .svc = QCOM_SCM_SVC_MP, 809 .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT, 810 .arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL, 811 QCOM_SCM_VAL), 812 .args[0] = addr, 813 .args[1] = size, 814 .args[2] = spare, 815 .owner = ARM_SMCCC_OWNER_SIP, 816 }; 817 int ret; 818 819 ret = qcom_scm_call(__scm->dev, &desc, NULL); 820 821 /* the pg table has been initialized already, ignore the error */ 822 if (ret == -EPERM) 823 ret = 0; 824 825 return ret; 826 } 827 EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_init); 828 829 int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size) 830 { 831 struct qcom_scm_desc desc = { 832 .svc = QCOM_SCM_SVC_MP, 833 .cmd = QCOM_SCM_MP_IOMMU_SET_CP_POOL_SIZE, 834 .arginfo = QCOM_SCM_ARGS(2), 835 .args[0] = size, 836 .args[1] = spare, 837 .owner = ARM_SMCCC_OWNER_SIP, 838 }; 839 840 return qcom_scm_call(__scm->dev, &desc, NULL); 841 } 842 EXPORT_SYMBOL(qcom_scm_iommu_set_cp_pool_size); 843 844 int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size, 845 u32 cp_nonpixel_start, 846 u32 cp_nonpixel_size) 847 { 848 int ret; 849 struct qcom_scm_desc desc = { 850 .svc = QCOM_SCM_SVC_MP, 851 .cmd = QCOM_SCM_MP_VIDEO_VAR, 852 .arginfo = QCOM_SCM_ARGS(4, QCOM_SCM_VAL, QCOM_SCM_VAL, 853 QCOM_SCM_VAL, QCOM_SCM_VAL), 854 .args[0] = cp_start, 855 .args[1] = cp_size, 856 .args[2] = cp_nonpixel_start, 857 .args[3] = cp_nonpixel_size, 858 .owner = ARM_SMCCC_OWNER_SIP, 859 }; 860 struct qcom_scm_res res; 861 862 ret = qcom_scm_call(__scm->dev, &desc, &res); 863 864 return ret ? : res.result[0]; 865 } 866 EXPORT_SYMBOL(qcom_scm_mem_protect_video_var); 867 868 static int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region, 869 size_t mem_sz, phys_addr_t src, size_t src_sz, 870 phys_addr_t dest, size_t dest_sz) 871 { 872 int ret; 873 struct qcom_scm_desc desc = { 874 .svc = QCOM_SCM_SVC_MP, 875 .cmd = QCOM_SCM_MP_ASSIGN, 876 .arginfo = QCOM_SCM_ARGS(7, QCOM_SCM_RO, QCOM_SCM_VAL, 877 QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_RO, 878 QCOM_SCM_VAL, QCOM_SCM_VAL), 879 .args[0] = mem_region, 880 .args[1] = mem_sz, 881 .args[2] = src, 882 .args[3] = src_sz, 883 .args[4] = dest, 884 .args[5] = dest_sz, 885 .args[6] = 0, 886 .owner = ARM_SMCCC_OWNER_SIP, 887 }; 888 struct qcom_scm_res res; 889 890 ret = qcom_scm_call(dev, &desc, &res); 891 892 return ret ? : res.result[0]; 893 } 894 895 /** 896 * qcom_scm_assign_mem() - Make a secure call to reassign memory ownership 897 * @mem_addr: mem region whose ownership need to be reassigned 898 * @mem_sz: size of the region. 899 * @srcvm: vmid for current set of owners, each set bit in 900 * flag indicate a unique owner 901 * @newvm: array having new owners and corresponding permission 902 * flags 903 * @dest_cnt: number of owners in next set. 904 * 905 * Return negative errno on failure or 0 on success with @srcvm updated. 906 */ 907 int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, 908 unsigned int *srcvm, 909 const struct qcom_scm_vmperm *newvm, 910 unsigned int dest_cnt) 911 { 912 struct qcom_scm_current_perm_info *destvm; 913 struct qcom_scm_mem_map_info *mem_to_map; 914 phys_addr_t mem_to_map_phys; 915 phys_addr_t dest_phys; 916 dma_addr_t ptr_phys; 917 size_t mem_to_map_sz; 918 size_t dest_sz; 919 size_t src_sz; 920 size_t ptr_sz; 921 int next_vm; 922 __le32 *src; 923 void *ptr; 924 int ret, i, b; 925 unsigned long srcvm_bits = *srcvm; 926 927 src_sz = hweight_long(srcvm_bits) * sizeof(*src); 928 mem_to_map_sz = sizeof(*mem_to_map); 929 dest_sz = dest_cnt * sizeof(*destvm); 930 ptr_sz = ALIGN(src_sz, SZ_64) + ALIGN(mem_to_map_sz, SZ_64) + 931 ALIGN(dest_sz, SZ_64); 932 933 ptr = dma_alloc_coherent(__scm->dev, ptr_sz, &ptr_phys, GFP_KERNEL); 934 if (!ptr) 935 return -ENOMEM; 936 937 /* Fill source vmid detail */ 938 src = ptr; 939 i = 0; 940 for_each_set_bit(b, &srcvm_bits, BITS_PER_LONG) 941 src[i++] = cpu_to_le32(b); 942 943 /* Fill details of mem buff to map */ 944 mem_to_map = ptr + ALIGN(src_sz, SZ_64); 945 mem_to_map_phys = ptr_phys + ALIGN(src_sz, SZ_64); 946 mem_to_map->mem_addr = cpu_to_le64(mem_addr); 947 mem_to_map->mem_size = cpu_to_le64(mem_sz); 948 949 next_vm = 0; 950 /* Fill details of next vmid detail */ 951 destvm = ptr + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64); 952 dest_phys = ptr_phys + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64); 953 for (i = 0; i < dest_cnt; i++, destvm++, newvm++) { 954 destvm->vmid = cpu_to_le32(newvm->vmid); 955 destvm->perm = cpu_to_le32(newvm->perm); 956 destvm->ctx = 0; 957 destvm->ctx_size = 0; 958 next_vm |= BIT(newvm->vmid); 959 } 960 961 ret = __qcom_scm_assign_mem(__scm->dev, mem_to_map_phys, mem_to_map_sz, 962 ptr_phys, src_sz, dest_phys, dest_sz); 963 dma_free_coherent(__scm->dev, ptr_sz, ptr, ptr_phys); 964 if (ret) { 965 dev_err(__scm->dev, 966 "Assign memory protection call failed %d\n", ret); 967 return -EINVAL; 968 } 969 970 *srcvm = next_vm; 971 return 0; 972 } 973 EXPORT_SYMBOL(qcom_scm_assign_mem); 974 975 /** 976 * qcom_scm_ocmem_lock_available() - is OCMEM lock/unlock interface available 977 */ 978 bool qcom_scm_ocmem_lock_available(void) 979 { 980 return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_OCMEM, 981 QCOM_SCM_OCMEM_LOCK_CMD); 982 } 983 EXPORT_SYMBOL(qcom_scm_ocmem_lock_available); 984 985 /** 986 * qcom_scm_ocmem_lock() - call OCMEM lock interface to assign an OCMEM 987 * region to the specified initiator 988 * 989 * @id: tz initiator id 990 * @offset: OCMEM offset 991 * @size: OCMEM size 992 * @mode: access mode (WIDE/NARROW) 993 */ 994 int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset, u32 size, 995 u32 mode) 996 { 997 struct qcom_scm_desc desc = { 998 .svc = QCOM_SCM_SVC_OCMEM, 999 .cmd = QCOM_SCM_OCMEM_LOCK_CMD, 1000 .args[0] = id, 1001 .args[1] = offset, 1002 .args[2] = size, 1003 .args[3] = mode, 1004 .arginfo = QCOM_SCM_ARGS(4), 1005 }; 1006 1007 return qcom_scm_call(__scm->dev, &desc, NULL); 1008 } 1009 EXPORT_SYMBOL(qcom_scm_ocmem_lock); 1010 1011 /** 1012 * qcom_scm_ocmem_unlock() - call OCMEM unlock interface to release an OCMEM 1013 * region from the specified initiator 1014 * 1015 * @id: tz initiator id 1016 * @offset: OCMEM offset 1017 * @size: OCMEM size 1018 */ 1019 int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, u32 size) 1020 { 1021 struct qcom_scm_desc desc = { 1022 .svc = QCOM_SCM_SVC_OCMEM, 1023 .cmd = QCOM_SCM_OCMEM_UNLOCK_CMD, 1024 .args[0] = id, 1025 .args[1] = offset, 1026 .args[2] = size, 1027 .arginfo = QCOM_SCM_ARGS(3), 1028 }; 1029 1030 return qcom_scm_call(__scm->dev, &desc, NULL); 1031 } 1032 EXPORT_SYMBOL(qcom_scm_ocmem_unlock); 1033 1034 /** 1035 * qcom_scm_ice_available() - Is the ICE key programming interface available? 1036 * 1037 * Return: true iff the SCM calls wrapped by qcom_scm_ice_invalidate_key() and 1038 * qcom_scm_ice_set_key() are available. 1039 */ 1040 bool qcom_scm_ice_available(void) 1041 { 1042 return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_ES, 1043 QCOM_SCM_ES_INVALIDATE_ICE_KEY) && 1044 __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_ES, 1045 QCOM_SCM_ES_CONFIG_SET_ICE_KEY); 1046 } 1047 EXPORT_SYMBOL(qcom_scm_ice_available); 1048 1049 /** 1050 * qcom_scm_ice_invalidate_key() - Invalidate an inline encryption key 1051 * @index: the keyslot to invalidate 1052 * 1053 * The UFSHCI and eMMC standards define a standard way to do this, but it 1054 * doesn't work on these SoCs; only this SCM call does. 1055 * 1056 * It is assumed that the SoC has only one ICE instance being used, as this SCM 1057 * call doesn't specify which ICE instance the keyslot belongs to. 1058 * 1059 * Return: 0 on success; -errno on failure. 1060 */ 1061 int qcom_scm_ice_invalidate_key(u32 index) 1062 { 1063 struct qcom_scm_desc desc = { 1064 .svc = QCOM_SCM_SVC_ES, 1065 .cmd = QCOM_SCM_ES_INVALIDATE_ICE_KEY, 1066 .arginfo = QCOM_SCM_ARGS(1), 1067 .args[0] = index, 1068 .owner = ARM_SMCCC_OWNER_SIP, 1069 }; 1070 1071 return qcom_scm_call(__scm->dev, &desc, NULL); 1072 } 1073 EXPORT_SYMBOL(qcom_scm_ice_invalidate_key); 1074 1075 /** 1076 * qcom_scm_ice_set_key() - Set an inline encryption key 1077 * @index: the keyslot into which to set the key 1078 * @key: the key to program 1079 * @key_size: the size of the key in bytes 1080 * @cipher: the encryption algorithm the key is for 1081 * @data_unit_size: the encryption data unit size, i.e. the size of each 1082 * individual plaintext and ciphertext. Given in 512-byte 1083 * units, e.g. 1 = 512 bytes, 8 = 4096 bytes, etc. 1084 * 1085 * Program a key into a keyslot of Qualcomm ICE (Inline Crypto Engine), where it 1086 * can then be used to encrypt/decrypt UFS or eMMC I/O requests inline. 1087 * 1088 * The UFSHCI and eMMC standards define a standard way to do this, but it 1089 * doesn't work on these SoCs; only this SCM call does. 1090 * 1091 * It is assumed that the SoC has only one ICE instance being used, as this SCM 1092 * call doesn't specify which ICE instance the keyslot belongs to. 1093 * 1094 * Return: 0 on success; -errno on failure. 1095 */ 1096 int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size, 1097 enum qcom_scm_ice_cipher cipher, u32 data_unit_size) 1098 { 1099 struct qcom_scm_desc desc = { 1100 .svc = QCOM_SCM_SVC_ES, 1101 .cmd = QCOM_SCM_ES_CONFIG_SET_ICE_KEY, 1102 .arginfo = QCOM_SCM_ARGS(5, QCOM_SCM_VAL, QCOM_SCM_RW, 1103 QCOM_SCM_VAL, QCOM_SCM_VAL, 1104 QCOM_SCM_VAL), 1105 .args[0] = index, 1106 .args[2] = key_size, 1107 .args[3] = cipher, 1108 .args[4] = data_unit_size, 1109 .owner = ARM_SMCCC_OWNER_SIP, 1110 }; 1111 void *keybuf; 1112 dma_addr_t key_phys; 1113 int ret; 1114 1115 /* 1116 * 'key' may point to vmalloc()'ed memory, but we need to pass a 1117 * physical address that's been properly flushed. The sanctioned way to 1118 * do this is by using the DMA API. But as is best practice for crypto 1119 * keys, we also must wipe the key after use. This makes kmemdup() + 1120 * dma_map_single() not clearly correct, since the DMA API can use 1121 * bounce buffers. Instead, just use dma_alloc_coherent(). Programming 1122 * keys is normally rare and thus not performance-critical. 1123 */ 1124 1125 keybuf = dma_alloc_coherent(__scm->dev, key_size, &key_phys, 1126 GFP_KERNEL); 1127 if (!keybuf) 1128 return -ENOMEM; 1129 memcpy(keybuf, key, key_size); 1130 desc.args[1] = key_phys; 1131 1132 ret = qcom_scm_call(__scm->dev, &desc, NULL); 1133 1134 memzero_explicit(keybuf, key_size); 1135 1136 dma_free_coherent(__scm->dev, key_size, keybuf, key_phys); 1137 return ret; 1138 } 1139 EXPORT_SYMBOL(qcom_scm_ice_set_key); 1140 1141 /** 1142 * qcom_scm_hdcp_available() - Check if secure environment supports HDCP. 1143 * 1144 * Return true if HDCP is supported, false if not. 1145 */ 1146 bool qcom_scm_hdcp_available(void) 1147 { 1148 bool avail; 1149 int ret = qcom_scm_clk_enable(); 1150 1151 if (ret) 1152 return ret; 1153 1154 avail = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_HDCP, 1155 QCOM_SCM_HDCP_INVOKE); 1156 1157 qcom_scm_clk_disable(); 1158 1159 return avail; 1160 } 1161 EXPORT_SYMBOL(qcom_scm_hdcp_available); 1162 1163 /** 1164 * qcom_scm_hdcp_req() - Send HDCP request. 1165 * @req: HDCP request array 1166 * @req_cnt: HDCP request array count 1167 * @resp: response buffer passed to SCM 1168 * 1169 * Write HDCP register(s) through SCM. 1170 */ 1171 int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp) 1172 { 1173 int ret; 1174 struct qcom_scm_desc desc = { 1175 .svc = QCOM_SCM_SVC_HDCP, 1176 .cmd = QCOM_SCM_HDCP_INVOKE, 1177 .arginfo = QCOM_SCM_ARGS(10), 1178 .args = { 1179 req[0].addr, 1180 req[0].val, 1181 req[1].addr, 1182 req[1].val, 1183 req[2].addr, 1184 req[2].val, 1185 req[3].addr, 1186 req[3].val, 1187 req[4].addr, 1188 req[4].val 1189 }, 1190 .owner = ARM_SMCCC_OWNER_SIP, 1191 }; 1192 struct qcom_scm_res res; 1193 1194 if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT) 1195 return -ERANGE; 1196 1197 ret = qcom_scm_clk_enable(); 1198 if (ret) 1199 return ret; 1200 1201 ret = qcom_scm_call(__scm->dev, &desc, &res); 1202 *resp = res.result[0]; 1203 1204 qcom_scm_clk_disable(); 1205 1206 return ret; 1207 } 1208 EXPORT_SYMBOL(qcom_scm_hdcp_req); 1209 1210 int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt) 1211 { 1212 struct qcom_scm_desc desc = { 1213 .svc = QCOM_SCM_SVC_SMMU_PROGRAM, 1214 .cmd = QCOM_SCM_SMMU_PT_FORMAT, 1215 .arginfo = QCOM_SCM_ARGS(3), 1216 .args[0] = sec_id, 1217 .args[1] = ctx_num, 1218 .args[2] = pt_fmt, /* 0: LPAE AArch32 - 1: AArch64 */ 1219 .owner = ARM_SMCCC_OWNER_SIP, 1220 }; 1221 1222 return qcom_scm_call(__scm->dev, &desc, NULL); 1223 } 1224 EXPORT_SYMBOL(qcom_scm_iommu_set_pt_format); 1225 1226 int qcom_scm_qsmmu500_wait_safe_toggle(bool en) 1227 { 1228 struct qcom_scm_desc desc = { 1229 .svc = QCOM_SCM_SVC_SMMU_PROGRAM, 1230 .cmd = QCOM_SCM_SMMU_CONFIG_ERRATA1, 1231 .arginfo = QCOM_SCM_ARGS(2), 1232 .args[0] = QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL, 1233 .args[1] = en, 1234 .owner = ARM_SMCCC_OWNER_SIP, 1235 }; 1236 1237 1238 return qcom_scm_call_atomic(__scm->dev, &desc, NULL); 1239 } 1240 EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle); 1241 1242 bool qcom_scm_lmh_dcvsh_available(void) 1243 { 1244 return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_LMH, QCOM_SCM_LMH_LIMIT_DCVSH); 1245 } 1246 EXPORT_SYMBOL(qcom_scm_lmh_dcvsh_available); 1247 1248 int qcom_scm_lmh_profile_change(u32 profile_id) 1249 { 1250 struct qcom_scm_desc desc = { 1251 .svc = QCOM_SCM_SVC_LMH, 1252 .cmd = QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE, 1253 .arginfo = QCOM_SCM_ARGS(1, QCOM_SCM_VAL), 1254 .args[0] = profile_id, 1255 .owner = ARM_SMCCC_OWNER_SIP, 1256 }; 1257 1258 return qcom_scm_call(__scm->dev, &desc, NULL); 1259 } 1260 EXPORT_SYMBOL(qcom_scm_lmh_profile_change); 1261 1262 int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val, 1263 u64 limit_node, u32 node_id, u64 version) 1264 { 1265 dma_addr_t payload_phys; 1266 u32 *payload_buf; 1267 int ret, payload_size = 5 * sizeof(u32); 1268 1269 struct qcom_scm_desc desc = { 1270 .svc = QCOM_SCM_SVC_LMH, 1271 .cmd = QCOM_SCM_LMH_LIMIT_DCVSH, 1272 .arginfo = QCOM_SCM_ARGS(5, QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_VAL, 1273 QCOM_SCM_VAL, QCOM_SCM_VAL), 1274 .args[1] = payload_size, 1275 .args[2] = limit_node, 1276 .args[3] = node_id, 1277 .args[4] = version, 1278 .owner = ARM_SMCCC_OWNER_SIP, 1279 }; 1280 1281 payload_buf = dma_alloc_coherent(__scm->dev, payload_size, &payload_phys, GFP_KERNEL); 1282 if (!payload_buf) 1283 return -ENOMEM; 1284 1285 payload_buf[0] = payload_fn; 1286 payload_buf[1] = 0; 1287 payload_buf[2] = payload_reg; 1288 payload_buf[3] = 1; 1289 payload_buf[4] = payload_val; 1290 1291 desc.args[0] = payload_phys; 1292 1293 ret = qcom_scm_call(__scm->dev, &desc, NULL); 1294 1295 dma_free_coherent(__scm->dev, payload_size, payload_buf, payload_phys); 1296 return ret; 1297 } 1298 EXPORT_SYMBOL(qcom_scm_lmh_dcvsh); 1299 1300 static int qcom_scm_find_dload_address(struct device *dev, u64 *addr) 1301 { 1302 struct device_node *tcsr; 1303 struct device_node *np = dev->of_node; 1304 struct resource res; 1305 u32 offset; 1306 int ret; 1307 1308 tcsr = of_parse_phandle(np, "qcom,dload-mode", 0); 1309 if (!tcsr) 1310 return 0; 1311 1312 ret = of_address_to_resource(tcsr, 0, &res); 1313 of_node_put(tcsr); 1314 if (ret) 1315 return ret; 1316 1317 ret = of_property_read_u32_index(np, "qcom,dload-mode", 1, &offset); 1318 if (ret < 0) 1319 return ret; 1320 1321 *addr = res.start + offset; 1322 1323 return 0; 1324 } 1325 1326 /** 1327 * qcom_scm_is_available() - Checks if SCM is available 1328 */ 1329 bool qcom_scm_is_available(void) 1330 { 1331 return !!__scm; 1332 } 1333 EXPORT_SYMBOL(qcom_scm_is_available); 1334 1335 static int qcom_scm_assert_valid_wq_ctx(u32 wq_ctx) 1336 { 1337 /* FW currently only supports a single wq_ctx (zero). 1338 * TODO: Update this logic to include dynamic allocation and lookup of 1339 * completion structs when FW supports more wq_ctx values. 1340 */ 1341 if (wq_ctx != 0) { 1342 dev_err(__scm->dev, "Firmware unexpectedly passed non-zero wq_ctx\n"); 1343 return -EINVAL; 1344 } 1345 1346 return 0; 1347 } 1348 1349 int qcom_scm_wait_for_wq_completion(u32 wq_ctx) 1350 { 1351 int ret; 1352 1353 ret = qcom_scm_assert_valid_wq_ctx(wq_ctx); 1354 if (ret) 1355 return ret; 1356 1357 wait_for_completion(&__scm->waitq_comp); 1358 1359 return 0; 1360 } 1361 1362 static int qcom_scm_waitq_wakeup(struct qcom_scm *scm, unsigned int wq_ctx) 1363 { 1364 int ret; 1365 1366 ret = qcom_scm_assert_valid_wq_ctx(wq_ctx); 1367 if (ret) 1368 return ret; 1369 1370 complete(&__scm->waitq_comp); 1371 1372 return 0; 1373 } 1374 1375 static irqreturn_t qcom_scm_irq_handler(int irq, void *data) 1376 { 1377 int ret; 1378 struct qcom_scm *scm = data; 1379 u32 wq_ctx, flags, more_pending = 0; 1380 1381 do { 1382 ret = scm_get_wq_ctx(&wq_ctx, &flags, &more_pending); 1383 if (ret) { 1384 dev_err(scm->dev, "GET_WQ_CTX SMC call failed: %d\n", ret); 1385 goto out; 1386 } 1387 1388 if (flags != QCOM_SMC_WAITQ_FLAG_WAKE_ONE && 1389 flags != QCOM_SMC_WAITQ_FLAG_WAKE_ALL) { 1390 dev_err(scm->dev, "Invalid flags found for wq_ctx: %u\n", flags); 1391 goto out; 1392 } 1393 1394 ret = qcom_scm_waitq_wakeup(scm, wq_ctx); 1395 if (ret) 1396 goto out; 1397 } while (more_pending); 1398 1399 out: 1400 return IRQ_HANDLED; 1401 } 1402 1403 static int qcom_scm_probe(struct platform_device *pdev) 1404 { 1405 struct qcom_scm *scm; 1406 unsigned long clks; 1407 int irq, ret; 1408 1409 scm = devm_kzalloc(&pdev->dev, sizeof(*scm), GFP_KERNEL); 1410 if (!scm) 1411 return -ENOMEM; 1412 1413 ret = qcom_scm_find_dload_address(&pdev->dev, &scm->dload_mode_addr); 1414 if (ret < 0) 1415 return ret; 1416 1417 mutex_init(&scm->scm_bw_lock); 1418 1419 clks = (unsigned long)of_device_get_match_data(&pdev->dev); 1420 1421 scm->path = devm_of_icc_get(&pdev->dev, NULL); 1422 if (IS_ERR(scm->path)) 1423 return dev_err_probe(&pdev->dev, PTR_ERR(scm->path), 1424 "failed to acquire interconnect path\n"); 1425 1426 scm->core_clk = devm_clk_get(&pdev->dev, "core"); 1427 if (IS_ERR(scm->core_clk)) { 1428 if (PTR_ERR(scm->core_clk) == -EPROBE_DEFER) 1429 return PTR_ERR(scm->core_clk); 1430 1431 if (clks & SCM_HAS_CORE_CLK) { 1432 dev_err(&pdev->dev, "failed to acquire core clk\n"); 1433 return PTR_ERR(scm->core_clk); 1434 } 1435 1436 scm->core_clk = NULL; 1437 } 1438 1439 scm->iface_clk = devm_clk_get(&pdev->dev, "iface"); 1440 if (IS_ERR(scm->iface_clk)) { 1441 if (PTR_ERR(scm->iface_clk) == -EPROBE_DEFER) 1442 return PTR_ERR(scm->iface_clk); 1443 1444 if (clks & SCM_HAS_IFACE_CLK) { 1445 dev_err(&pdev->dev, "failed to acquire iface clk\n"); 1446 return PTR_ERR(scm->iface_clk); 1447 } 1448 1449 scm->iface_clk = NULL; 1450 } 1451 1452 scm->bus_clk = devm_clk_get(&pdev->dev, "bus"); 1453 if (IS_ERR(scm->bus_clk)) { 1454 if (PTR_ERR(scm->bus_clk) == -EPROBE_DEFER) 1455 return PTR_ERR(scm->bus_clk); 1456 1457 if (clks & SCM_HAS_BUS_CLK) { 1458 dev_err(&pdev->dev, "failed to acquire bus clk\n"); 1459 return PTR_ERR(scm->bus_clk); 1460 } 1461 1462 scm->bus_clk = NULL; 1463 } 1464 1465 scm->reset.ops = &qcom_scm_pas_reset_ops; 1466 scm->reset.nr_resets = 1; 1467 scm->reset.of_node = pdev->dev.of_node; 1468 ret = devm_reset_controller_register(&pdev->dev, &scm->reset); 1469 if (ret) 1470 return ret; 1471 1472 /* vote for max clk rate for highest performance */ 1473 ret = clk_set_rate(scm->core_clk, INT_MAX); 1474 if (ret) 1475 return ret; 1476 1477 __scm = scm; 1478 __scm->dev = &pdev->dev; 1479 1480 init_completion(&__scm->waitq_comp); 1481 1482 irq = platform_get_irq(pdev, 0); 1483 if (irq < 0) { 1484 if (irq != -ENXIO) 1485 return irq; 1486 } else { 1487 ret = devm_request_threaded_irq(__scm->dev, irq, NULL, qcom_scm_irq_handler, 1488 IRQF_ONESHOT, "qcom-scm", __scm); 1489 if (ret < 0) 1490 return dev_err_probe(scm->dev, ret, "Failed to request qcom-scm irq\n"); 1491 } 1492 1493 __get_convention(); 1494 1495 /* 1496 * If requested enable "download mode", from this point on warmboot 1497 * will cause the boot stages to enter download mode, unless 1498 * disabled below by a clean shutdown/reboot. 1499 */ 1500 if (download_mode) 1501 qcom_scm_set_download_mode(true); 1502 1503 return 0; 1504 } 1505 1506 static void qcom_scm_shutdown(struct platform_device *pdev) 1507 { 1508 /* Clean shutdown, disable download mode to allow normal restart */ 1509 if (download_mode) 1510 qcom_scm_set_download_mode(false); 1511 } 1512 1513 static const struct of_device_id qcom_scm_dt_match[] = { 1514 { .compatible = "qcom,scm-apq8064", 1515 /* FIXME: This should have .data = (void *) SCM_HAS_CORE_CLK */ 1516 }, 1517 { .compatible = "qcom,scm-apq8084", .data = (void *)(SCM_HAS_CORE_CLK | 1518 SCM_HAS_IFACE_CLK | 1519 SCM_HAS_BUS_CLK) 1520 }, 1521 { .compatible = "qcom,scm-ipq4019" }, 1522 { .compatible = "qcom,scm-mdm9607", .data = (void *)(SCM_HAS_CORE_CLK | 1523 SCM_HAS_IFACE_CLK | 1524 SCM_HAS_BUS_CLK) }, 1525 { .compatible = "qcom,scm-msm8660", .data = (void *) SCM_HAS_CORE_CLK }, 1526 { .compatible = "qcom,scm-msm8960", .data = (void *) SCM_HAS_CORE_CLK }, 1527 { .compatible = "qcom,scm-msm8916", .data = (void *)(SCM_HAS_CORE_CLK | 1528 SCM_HAS_IFACE_CLK | 1529 SCM_HAS_BUS_CLK) 1530 }, 1531 { .compatible = "qcom,scm-msm8953", .data = (void *)(SCM_HAS_CORE_CLK | 1532 SCM_HAS_IFACE_CLK | 1533 SCM_HAS_BUS_CLK) 1534 }, 1535 { .compatible = "qcom,scm-msm8974", .data = (void *)(SCM_HAS_CORE_CLK | 1536 SCM_HAS_IFACE_CLK | 1537 SCM_HAS_BUS_CLK) 1538 }, 1539 { .compatible = "qcom,scm-msm8976", .data = (void *)(SCM_HAS_CORE_CLK | 1540 SCM_HAS_IFACE_CLK | 1541 SCM_HAS_BUS_CLK) 1542 }, 1543 { .compatible = "qcom,scm-msm8994" }, 1544 { .compatible = "qcom,scm-msm8996" }, 1545 { .compatible = "qcom,scm" }, 1546 {} 1547 }; 1548 MODULE_DEVICE_TABLE(of, qcom_scm_dt_match); 1549 1550 static struct platform_driver qcom_scm_driver = { 1551 .driver = { 1552 .name = "qcom_scm", 1553 .of_match_table = qcom_scm_dt_match, 1554 .suppress_bind_attrs = true, 1555 }, 1556 .probe = qcom_scm_probe, 1557 .shutdown = qcom_scm_shutdown, 1558 }; 1559 1560 static int __init qcom_scm_init(void) 1561 { 1562 return platform_driver_register(&qcom_scm_driver); 1563 } 1564 subsys_initcall(qcom_scm_init); 1565 1566 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. SCM driver"); 1567 MODULE_LICENSE("GPL v2"); 1568