1*cb1c9e02SArd Biesheuvel // SPDX-License-Identifier: GPL-2.0-only
2*cb1c9e02SArd Biesheuvel #include <linux/efi.h>
3*cb1c9e02SArd Biesheuvel
4*cb1c9e02SArd Biesheuvel #include <asm/boot.h>
5*cb1c9e02SArd Biesheuvel #include <asm/desc.h>
6*cb1c9e02SArd Biesheuvel #include <asm/efi.h>
7*cb1c9e02SArd Biesheuvel
8*cb1c9e02SArd Biesheuvel #include "efistub.h"
9*cb1c9e02SArd Biesheuvel #include "x86-stub.h"
10*cb1c9e02SArd Biesheuvel
11*cb1c9e02SArd Biesheuvel bool efi_no5lvl;
12*cb1c9e02SArd Biesheuvel
13*cb1c9e02SArd Biesheuvel static void (*la57_toggle)(void *cr3);
14*cb1c9e02SArd Biesheuvel
15*cb1c9e02SArd Biesheuvel static const struct desc_struct gdt[] = {
16*cb1c9e02SArd Biesheuvel [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
17*cb1c9e02SArd Biesheuvel [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
18*cb1c9e02SArd Biesheuvel };
19*cb1c9e02SArd Biesheuvel
20*cb1c9e02SArd Biesheuvel /*
21*cb1c9e02SArd Biesheuvel * Enabling (or disabling) 5 level paging is tricky, because it can only be
22*cb1c9e02SArd Biesheuvel * done from 32-bit mode with paging disabled. This means not only that the
23*cb1c9e02SArd Biesheuvel * code itself must be running from 32-bit addressable physical memory, but
24*cb1c9e02SArd Biesheuvel * also that the root page table must be 32-bit addressable, as programming
25*cb1c9e02SArd Biesheuvel * a 64-bit value into CR3 when running in 32-bit mode is not supported.
26*cb1c9e02SArd Biesheuvel */
efi_setup_5level_paging(void)27*cb1c9e02SArd Biesheuvel efi_status_t efi_setup_5level_paging(void)
28*cb1c9e02SArd Biesheuvel {
29*cb1c9e02SArd Biesheuvel u8 tmpl_size = (u8 *)&trampoline_ljmp_imm_offset - (u8 *)&trampoline_32bit_src;
30*cb1c9e02SArd Biesheuvel efi_status_t status;
31*cb1c9e02SArd Biesheuvel u8 *la57_code;
32*cb1c9e02SArd Biesheuvel
33*cb1c9e02SArd Biesheuvel if (!efi_is_64bit())
34*cb1c9e02SArd Biesheuvel return EFI_SUCCESS;
35*cb1c9e02SArd Biesheuvel
36*cb1c9e02SArd Biesheuvel /* check for 5 level paging support */
37*cb1c9e02SArd Biesheuvel if (native_cpuid_eax(0) < 7 ||
38*cb1c9e02SArd Biesheuvel !(native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31))))
39*cb1c9e02SArd Biesheuvel return EFI_SUCCESS;
40*cb1c9e02SArd Biesheuvel
41*cb1c9e02SArd Biesheuvel /* allocate some 32-bit addressable memory for code and a page table */
42*cb1c9e02SArd Biesheuvel status = efi_allocate_pages(2 * PAGE_SIZE, (unsigned long *)&la57_code,
43*cb1c9e02SArd Biesheuvel U32_MAX);
44*cb1c9e02SArd Biesheuvel if (status != EFI_SUCCESS)
45*cb1c9e02SArd Biesheuvel return status;
46*cb1c9e02SArd Biesheuvel
47*cb1c9e02SArd Biesheuvel la57_toggle = memcpy(la57_code, trampoline_32bit_src, tmpl_size);
48*cb1c9e02SArd Biesheuvel memset(la57_code + tmpl_size, 0x90, PAGE_SIZE - tmpl_size);
49*cb1c9e02SArd Biesheuvel
50*cb1c9e02SArd Biesheuvel /*
51*cb1c9e02SArd Biesheuvel * To avoid the need to allocate a 32-bit addressable stack, the
52*cb1c9e02SArd Biesheuvel * trampoline uses a LJMP instruction to switch back to long mode.
53*cb1c9e02SArd Biesheuvel * LJMP takes an absolute destination address, which needs to be
54*cb1c9e02SArd Biesheuvel * fixed up at runtime.
55*cb1c9e02SArd Biesheuvel */
56*cb1c9e02SArd Biesheuvel *(u32 *)&la57_code[trampoline_ljmp_imm_offset] += (unsigned long)la57_code;
57*cb1c9e02SArd Biesheuvel
58*cb1c9e02SArd Biesheuvel efi_adjust_memory_range_protection((unsigned long)la57_toggle, PAGE_SIZE);
59*cb1c9e02SArd Biesheuvel
60*cb1c9e02SArd Biesheuvel return EFI_SUCCESS;
61*cb1c9e02SArd Biesheuvel }
62*cb1c9e02SArd Biesheuvel
efi_5level_switch(void)63*cb1c9e02SArd Biesheuvel void efi_5level_switch(void)
64*cb1c9e02SArd Biesheuvel {
65*cb1c9e02SArd Biesheuvel bool want_la57 = IS_ENABLED(CONFIG_X86_5LEVEL) && !efi_no5lvl;
66*cb1c9e02SArd Biesheuvel bool have_la57 = native_read_cr4() & X86_CR4_LA57;
67*cb1c9e02SArd Biesheuvel bool need_toggle = want_la57 ^ have_la57;
68*cb1c9e02SArd Biesheuvel u64 *pgt = (void *)la57_toggle + PAGE_SIZE;
69*cb1c9e02SArd Biesheuvel u64 *cr3 = (u64 *)__native_read_cr3();
70*cb1c9e02SArd Biesheuvel u64 *new_cr3;
71*cb1c9e02SArd Biesheuvel
72*cb1c9e02SArd Biesheuvel if (!la57_toggle || !need_toggle)
73*cb1c9e02SArd Biesheuvel return;
74*cb1c9e02SArd Biesheuvel
75*cb1c9e02SArd Biesheuvel if (!have_la57) {
76*cb1c9e02SArd Biesheuvel /*
77*cb1c9e02SArd Biesheuvel * 5 level paging will be enabled, so a root level page needs
78*cb1c9e02SArd Biesheuvel * to be allocated from the 32-bit addressable physical region,
79*cb1c9e02SArd Biesheuvel * with its first entry referring to the existing hierarchy.
80*cb1c9e02SArd Biesheuvel */
81*cb1c9e02SArd Biesheuvel new_cr3 = memset(pgt, 0, PAGE_SIZE);
82*cb1c9e02SArd Biesheuvel new_cr3[0] = (u64)cr3 | _PAGE_TABLE_NOENC;
83*cb1c9e02SArd Biesheuvel } else {
84*cb1c9e02SArd Biesheuvel /* take the new root table pointer from the current entry #0 */
85*cb1c9e02SArd Biesheuvel new_cr3 = (u64 *)(cr3[0] & PAGE_MASK);
86*cb1c9e02SArd Biesheuvel
87*cb1c9e02SArd Biesheuvel /* copy the new root table if it is not 32-bit addressable */
88*cb1c9e02SArd Biesheuvel if ((u64)new_cr3 > U32_MAX)
89*cb1c9e02SArd Biesheuvel new_cr3 = memcpy(pgt, new_cr3, PAGE_SIZE);
90*cb1c9e02SArd Biesheuvel }
91*cb1c9e02SArd Biesheuvel
92*cb1c9e02SArd Biesheuvel native_load_gdt(&(struct desc_ptr){ sizeof(gdt) - 1, (u64)gdt });
93*cb1c9e02SArd Biesheuvel
94*cb1c9e02SArd Biesheuvel la57_toggle(new_cr3);
95*cb1c9e02SArd Biesheuvel }
96