1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * cs_dsp.c -- Cirrus Logic DSP firmware support 4 * 5 * Based on sound/soc/codecs/wm_adsp.c 6 * 7 * Copyright 2012 Wolfson Microelectronics plc 8 * Copyright (C) 2015-2021 Cirrus Logic, Inc. and 9 * Cirrus Logic International Semiconductor Ltd. 10 */ 11 12 #include <linux/ctype.h> 13 #include <linux/debugfs.h> 14 #include <linux/delay.h> 15 #include <linux/module.h> 16 #include <linux/moduleparam.h> 17 #include <linux/seq_file.h> 18 #include <linux/slab.h> 19 #include <linux/vmalloc.h> 20 21 #include <linux/firmware/cirrus/cs_dsp.h> 22 #include <linux/firmware/cirrus/wmfw.h> 23 24 #define cs_dsp_err(_dsp, fmt, ...) \ 25 dev_err(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) 26 #define cs_dsp_warn(_dsp, fmt, ...) \ 27 dev_warn(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) 28 #define cs_dsp_info(_dsp, fmt, ...) \ 29 dev_info(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) 30 #define cs_dsp_dbg(_dsp, fmt, ...) \ 31 dev_dbg(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) 32 33 #define ADSP1_CONTROL_1 0x00 34 #define ADSP1_CONTROL_2 0x02 35 #define ADSP1_CONTROL_3 0x03 36 #define ADSP1_CONTROL_4 0x04 37 #define ADSP1_CONTROL_5 0x06 38 #define ADSP1_CONTROL_6 0x07 39 #define ADSP1_CONTROL_7 0x08 40 #define ADSP1_CONTROL_8 0x09 41 #define ADSP1_CONTROL_9 0x0A 42 #define ADSP1_CONTROL_10 0x0B 43 #define ADSP1_CONTROL_11 0x0C 44 #define ADSP1_CONTROL_12 0x0D 45 #define ADSP1_CONTROL_13 0x0F 46 #define ADSP1_CONTROL_14 0x10 47 #define ADSP1_CONTROL_15 0x11 48 #define ADSP1_CONTROL_16 0x12 49 #define ADSP1_CONTROL_17 0x13 50 #define ADSP1_CONTROL_18 0x14 51 #define ADSP1_CONTROL_19 0x16 52 #define ADSP1_CONTROL_20 0x17 53 #define ADSP1_CONTROL_21 0x18 54 #define ADSP1_CONTROL_22 0x1A 55 #define ADSP1_CONTROL_23 0x1B 56 #define ADSP1_CONTROL_24 0x1C 57 #define ADSP1_CONTROL_25 0x1E 58 #define ADSP1_CONTROL_26 0x20 59 #define ADSP1_CONTROL_27 0x21 60 #define ADSP1_CONTROL_28 0x22 61 #define ADSP1_CONTROL_29 0x23 62 #define ADSP1_CONTROL_30 0x24 63 #define ADSP1_CONTROL_31 0x26 64 65 /* 66 * ADSP1 Control 19 67 */ 68 #define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ 69 #define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ 70 #define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ 71 72 /* 73 * ADSP1 Control 30 74 */ 75 #define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */ 76 #define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */ 77 #define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */ 78 #define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */ 79 #define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */ 80 #define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */ 81 #define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */ 82 #define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */ 83 #define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */ 84 #define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */ 85 #define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */ 86 #define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */ 87 #define ADSP1_START 0x0001 /* DSP1_START */ 88 #define ADSP1_START_MASK 0x0001 /* DSP1_START */ 89 #define ADSP1_START_SHIFT 0 /* DSP1_START */ 90 #define ADSP1_START_WIDTH 1 /* DSP1_START */ 91 92 /* 93 * ADSP1 Control 31 94 */ 95 #define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */ 96 #define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */ 97 #define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */ 98 99 #define ADSP2_CONTROL 0x0 100 #define ADSP2_CLOCKING 0x1 101 #define ADSP2V2_CLOCKING 0x2 102 #define ADSP2_STATUS1 0x4 103 #define ADSP2_WDMA_CONFIG_1 0x30 104 #define ADSP2_WDMA_CONFIG_2 0x31 105 #define ADSP2V2_WDMA_CONFIG_2 0x32 106 #define ADSP2_RDMA_CONFIG_1 0x34 107 108 #define ADSP2_SCRATCH0 0x40 109 #define ADSP2_SCRATCH1 0x41 110 #define ADSP2_SCRATCH2 0x42 111 #define ADSP2_SCRATCH3 0x43 112 113 #define ADSP2V2_SCRATCH0_1 0x40 114 #define ADSP2V2_SCRATCH2_3 0x42 115 116 /* 117 * ADSP2 Control 118 */ 119 #define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */ 120 #define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */ 121 #define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */ 122 #define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */ 123 #define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */ 124 #define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */ 125 #define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */ 126 #define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */ 127 #define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */ 128 #define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */ 129 #define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */ 130 #define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */ 131 #define ADSP2_START 0x0001 /* DSP1_START */ 132 #define ADSP2_START_MASK 0x0001 /* DSP1_START */ 133 #define ADSP2_START_SHIFT 0 /* DSP1_START */ 134 #define ADSP2_START_WIDTH 1 /* DSP1_START */ 135 136 /* 137 * ADSP2 clocking 138 */ 139 #define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */ 140 #define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */ 141 #define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */ 142 143 /* 144 * ADSP2V2 clocking 145 */ 146 #define ADSP2V2_CLK_SEL_MASK 0x70000 /* CLK_SEL_ENA */ 147 #define ADSP2V2_CLK_SEL_SHIFT 16 /* CLK_SEL_ENA */ 148 #define ADSP2V2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */ 149 150 #define ADSP2V2_RATE_MASK 0x7800 /* DSP_RATE */ 151 #define ADSP2V2_RATE_SHIFT 11 /* DSP_RATE */ 152 #define ADSP2V2_RATE_WIDTH 4 /* DSP_RATE */ 153 154 /* 155 * ADSP2 Status 1 156 */ 157 #define ADSP2_RAM_RDY 0x0001 158 #define ADSP2_RAM_RDY_MASK 0x0001 159 #define ADSP2_RAM_RDY_SHIFT 0 160 #define ADSP2_RAM_RDY_WIDTH 1 161 162 /* 163 * ADSP2 Lock support 164 */ 165 #define ADSP2_LOCK_CODE_0 0x5555 166 #define ADSP2_LOCK_CODE_1 0xAAAA 167 168 #define ADSP2_WATCHDOG 0x0A 169 #define ADSP2_BUS_ERR_ADDR 0x52 170 #define ADSP2_REGION_LOCK_STATUS 0x64 171 #define ADSP2_LOCK_REGION_1_LOCK_REGION_0 0x66 172 #define ADSP2_LOCK_REGION_3_LOCK_REGION_2 0x68 173 #define ADSP2_LOCK_REGION_5_LOCK_REGION_4 0x6A 174 #define ADSP2_LOCK_REGION_7_LOCK_REGION_6 0x6C 175 #define ADSP2_LOCK_REGION_9_LOCK_REGION_8 0x6E 176 #define ADSP2_LOCK_REGION_CTRL 0x7A 177 #define ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR 0x7C 178 179 #define ADSP2_REGION_LOCK_ERR_MASK 0x8000 180 #define ADSP2_ADDR_ERR_MASK 0x4000 181 #define ADSP2_WDT_TIMEOUT_STS_MASK 0x2000 182 #define ADSP2_CTRL_ERR_PAUSE_ENA 0x0002 183 #define ADSP2_CTRL_ERR_EINT 0x0001 184 185 #define ADSP2_BUS_ERR_ADDR_MASK 0x00FFFFFF 186 #define ADSP2_XMEM_ERR_ADDR_MASK 0x0000FFFF 187 #define ADSP2_PMEM_ERR_ADDR_MASK 0x7FFF0000 188 #define ADSP2_PMEM_ERR_ADDR_SHIFT 16 189 #define ADSP2_WDT_ENA_MASK 0xFFFFFFFD 190 191 #define ADSP2_LOCK_REGION_SHIFT 16 192 193 /* 194 * Event control messages 195 */ 196 #define CS_DSP_FW_EVENT_SHUTDOWN 0x000001 197 198 /* 199 * HALO system info 200 */ 201 #define HALO_AHBM_WINDOW_DEBUG_0 0x02040 202 #define HALO_AHBM_WINDOW_DEBUG_1 0x02044 203 204 /* 205 * HALO core 206 */ 207 #define HALO_SCRATCH1 0x005c0 208 #define HALO_SCRATCH2 0x005c8 209 #define HALO_SCRATCH3 0x005d0 210 #define HALO_SCRATCH4 0x005d8 211 #define HALO_CCM_CORE_CONTROL 0x41000 212 #define HALO_CORE_SOFT_RESET 0x00010 213 #define HALO_WDT_CONTROL 0x47000 214 215 /* 216 * HALO MPU banks 217 */ 218 #define HALO_MPU_XMEM_ACCESS_0 0x43000 219 #define HALO_MPU_YMEM_ACCESS_0 0x43004 220 #define HALO_MPU_WINDOW_ACCESS_0 0x43008 221 #define HALO_MPU_XREG_ACCESS_0 0x4300C 222 #define HALO_MPU_YREG_ACCESS_0 0x43014 223 #define HALO_MPU_XMEM_ACCESS_1 0x43018 224 #define HALO_MPU_YMEM_ACCESS_1 0x4301C 225 #define HALO_MPU_WINDOW_ACCESS_1 0x43020 226 #define HALO_MPU_XREG_ACCESS_1 0x43024 227 #define HALO_MPU_YREG_ACCESS_1 0x4302C 228 #define HALO_MPU_XMEM_ACCESS_2 0x43030 229 #define HALO_MPU_YMEM_ACCESS_2 0x43034 230 #define HALO_MPU_WINDOW_ACCESS_2 0x43038 231 #define HALO_MPU_XREG_ACCESS_2 0x4303C 232 #define HALO_MPU_YREG_ACCESS_2 0x43044 233 #define HALO_MPU_XMEM_ACCESS_3 0x43048 234 #define HALO_MPU_YMEM_ACCESS_3 0x4304C 235 #define HALO_MPU_WINDOW_ACCESS_3 0x43050 236 #define HALO_MPU_XREG_ACCESS_3 0x43054 237 #define HALO_MPU_YREG_ACCESS_3 0x4305C 238 #define HALO_MPU_XM_VIO_ADDR 0x43100 239 #define HALO_MPU_XM_VIO_STATUS 0x43104 240 #define HALO_MPU_YM_VIO_ADDR 0x43108 241 #define HALO_MPU_YM_VIO_STATUS 0x4310C 242 #define HALO_MPU_PM_VIO_ADDR 0x43110 243 #define HALO_MPU_PM_VIO_STATUS 0x43114 244 #define HALO_MPU_LOCK_CONFIG 0x43140 245 246 /* 247 * HALO_AHBM_WINDOW_DEBUG_1 248 */ 249 #define HALO_AHBM_CORE_ERR_ADDR_MASK 0x0fffff00 250 #define HALO_AHBM_CORE_ERR_ADDR_SHIFT 8 251 #define HALO_AHBM_FLAGS_ERR_MASK 0x000000ff 252 253 /* 254 * HALO_CCM_CORE_CONTROL 255 */ 256 #define HALO_CORE_RESET 0x00000200 257 #define HALO_CORE_EN 0x00000001 258 259 /* 260 * HALO_CORE_SOFT_RESET 261 */ 262 #define HALO_CORE_SOFT_RESET_MASK 0x00000001 263 264 /* 265 * HALO_WDT_CONTROL 266 */ 267 #define HALO_WDT_EN_MASK 0x00000001 268 269 /* 270 * HALO_MPU_?M_VIO_STATUS 271 */ 272 #define HALO_MPU_VIO_STS_MASK 0x007e0000 273 #define HALO_MPU_VIO_STS_SHIFT 17 274 #define HALO_MPU_VIO_ERR_WR_MASK 0x00008000 275 #define HALO_MPU_VIO_ERR_SRC_MASK 0x00007fff 276 #define HALO_MPU_VIO_ERR_SRC_SHIFT 0 277 278 struct cs_dsp_ops { 279 bool (*validate_version)(struct cs_dsp *dsp, unsigned int version); 280 unsigned int (*parse_sizes)(struct cs_dsp *dsp, 281 const char * const file, 282 unsigned int pos, 283 const struct firmware *firmware); 284 int (*setup_algs)(struct cs_dsp *dsp); 285 unsigned int (*region_to_reg)(struct cs_dsp_region const *mem, 286 unsigned int offset); 287 288 void (*show_fw_status)(struct cs_dsp *dsp); 289 void (*stop_watchdog)(struct cs_dsp *dsp); 290 291 int (*enable_memory)(struct cs_dsp *dsp); 292 void (*disable_memory)(struct cs_dsp *dsp); 293 int (*lock_memory)(struct cs_dsp *dsp, unsigned int lock_regions); 294 295 int (*enable_core)(struct cs_dsp *dsp); 296 void (*disable_core)(struct cs_dsp *dsp); 297 298 int (*start_core)(struct cs_dsp *dsp); 299 void (*stop_core)(struct cs_dsp *dsp); 300 }; 301 302 static const struct cs_dsp_ops cs_dsp_adsp1_ops; 303 static const struct cs_dsp_ops cs_dsp_adsp2_ops[]; 304 static const struct cs_dsp_ops cs_dsp_halo_ops; 305 static const struct cs_dsp_ops cs_dsp_halo_ao_ops; 306 307 struct cs_dsp_buf { 308 struct list_head list; 309 void *buf; 310 }; 311 312 static struct cs_dsp_buf *cs_dsp_buf_alloc(const void *src, size_t len, 313 struct list_head *list) 314 { 315 struct cs_dsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL); 316 317 if (buf == NULL) 318 return NULL; 319 320 buf->buf = vmalloc(len); 321 if (!buf->buf) { 322 kfree(buf); 323 return NULL; 324 } 325 memcpy(buf->buf, src, len); 326 327 if (list) 328 list_add_tail(&buf->list, list); 329 330 return buf; 331 } 332 333 static void cs_dsp_buf_free(struct list_head *list) 334 { 335 while (!list_empty(list)) { 336 struct cs_dsp_buf *buf = list_first_entry(list, 337 struct cs_dsp_buf, 338 list); 339 list_del(&buf->list); 340 vfree(buf->buf); 341 kfree(buf); 342 } 343 } 344 345 /** 346 * cs_dsp_mem_region_name() - Return a name string for a memory type 347 * @type: the memory type to match 348 * 349 * Return: A const string identifying the memory region. 350 */ 351 const char *cs_dsp_mem_region_name(unsigned int type) 352 { 353 switch (type) { 354 case WMFW_ADSP1_PM: 355 return "PM"; 356 case WMFW_HALO_PM_PACKED: 357 return "PM_PACKED"; 358 case WMFW_ADSP1_DM: 359 return "DM"; 360 case WMFW_ADSP2_XM: 361 return "XM"; 362 case WMFW_HALO_XM_PACKED: 363 return "XM_PACKED"; 364 case WMFW_ADSP2_YM: 365 return "YM"; 366 case WMFW_HALO_YM_PACKED: 367 return "YM_PACKED"; 368 case WMFW_ADSP1_ZM: 369 return "ZM"; 370 default: 371 return NULL; 372 } 373 } 374 EXPORT_SYMBOL_NS_GPL(cs_dsp_mem_region_name, FW_CS_DSP); 375 376 #ifdef CONFIG_DEBUG_FS 377 static void cs_dsp_debugfs_save_wmfwname(struct cs_dsp *dsp, const char *s) 378 { 379 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s); 380 381 kfree(dsp->wmfw_file_name); 382 dsp->wmfw_file_name = tmp; 383 } 384 385 static void cs_dsp_debugfs_save_binname(struct cs_dsp *dsp, const char *s) 386 { 387 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s); 388 389 kfree(dsp->bin_file_name); 390 dsp->bin_file_name = tmp; 391 } 392 393 static void cs_dsp_debugfs_clear(struct cs_dsp *dsp) 394 { 395 kfree(dsp->wmfw_file_name); 396 kfree(dsp->bin_file_name); 397 dsp->wmfw_file_name = NULL; 398 dsp->bin_file_name = NULL; 399 } 400 401 static ssize_t cs_dsp_debugfs_wmfw_read(struct file *file, 402 char __user *user_buf, 403 size_t count, loff_t *ppos) 404 { 405 struct cs_dsp *dsp = file->private_data; 406 ssize_t ret; 407 408 mutex_lock(&dsp->pwr_lock); 409 410 if (!dsp->wmfw_file_name || !dsp->booted) 411 ret = 0; 412 else 413 ret = simple_read_from_buffer(user_buf, count, ppos, 414 dsp->wmfw_file_name, 415 strlen(dsp->wmfw_file_name)); 416 417 mutex_unlock(&dsp->pwr_lock); 418 return ret; 419 } 420 421 static ssize_t cs_dsp_debugfs_bin_read(struct file *file, 422 char __user *user_buf, 423 size_t count, loff_t *ppos) 424 { 425 struct cs_dsp *dsp = file->private_data; 426 ssize_t ret; 427 428 mutex_lock(&dsp->pwr_lock); 429 430 if (!dsp->bin_file_name || !dsp->booted) 431 ret = 0; 432 else 433 ret = simple_read_from_buffer(user_buf, count, ppos, 434 dsp->bin_file_name, 435 strlen(dsp->bin_file_name)); 436 437 mutex_unlock(&dsp->pwr_lock); 438 return ret; 439 } 440 441 static const struct { 442 const char *name; 443 const struct file_operations fops; 444 } cs_dsp_debugfs_fops[] = { 445 { 446 .name = "wmfw_file_name", 447 .fops = { 448 .open = simple_open, 449 .read = cs_dsp_debugfs_wmfw_read, 450 }, 451 }, 452 { 453 .name = "bin_file_name", 454 .fops = { 455 .open = simple_open, 456 .read = cs_dsp_debugfs_bin_read, 457 }, 458 }, 459 }; 460 461 static int cs_dsp_coeff_base_reg(struct cs_dsp_coeff_ctl *ctl, unsigned int *reg, 462 unsigned int off); 463 464 static int cs_dsp_debugfs_read_controls_show(struct seq_file *s, void *ignored) 465 { 466 struct cs_dsp *dsp = s->private; 467 struct cs_dsp_coeff_ctl *ctl; 468 unsigned int reg; 469 470 list_for_each_entry(ctl, &dsp->ctl_list, list) { 471 cs_dsp_coeff_base_reg(ctl, ®, 0); 472 seq_printf(s, "%22.*s: %#8zx %s:%08x %#8x %s %#8x %#4x %c%c%c%c %s %s\n", 473 ctl->subname_len, ctl->subname, ctl->len, 474 cs_dsp_mem_region_name(ctl->alg_region.type), 475 ctl->offset, reg, ctl->fw_name, ctl->alg_region.alg, ctl->type, 476 ctl->flags & WMFW_CTL_FLAG_VOLATILE ? 'V' : '-', 477 ctl->flags & WMFW_CTL_FLAG_SYS ? 'S' : '-', 478 ctl->flags & WMFW_CTL_FLAG_READABLE ? 'R' : '-', 479 ctl->flags & WMFW_CTL_FLAG_WRITEABLE ? 'W' : '-', 480 ctl->enabled ? "enabled" : "disabled", 481 ctl->set ? "dirty" : "clean"); 482 } 483 484 return 0; 485 } 486 DEFINE_SHOW_ATTRIBUTE(cs_dsp_debugfs_read_controls); 487 488 /** 489 * cs_dsp_init_debugfs() - Create and populate DSP representation in debugfs 490 * @dsp: pointer to DSP structure 491 * @debugfs_root: pointer to debugfs directory in which to create this DSP 492 * representation 493 */ 494 void cs_dsp_init_debugfs(struct cs_dsp *dsp, struct dentry *debugfs_root) 495 { 496 struct dentry *root = NULL; 497 int i; 498 499 root = debugfs_create_dir(dsp->name, debugfs_root); 500 501 debugfs_create_bool("booted", 0444, root, &dsp->booted); 502 debugfs_create_bool("running", 0444, root, &dsp->running); 503 debugfs_create_x32("fw_id", 0444, root, &dsp->fw_id); 504 debugfs_create_x32("fw_version", 0444, root, &dsp->fw_id_version); 505 506 for (i = 0; i < ARRAY_SIZE(cs_dsp_debugfs_fops); ++i) 507 debugfs_create_file(cs_dsp_debugfs_fops[i].name, 0444, root, 508 dsp, &cs_dsp_debugfs_fops[i].fops); 509 510 debugfs_create_file("controls", 0444, root, dsp, 511 &cs_dsp_debugfs_read_controls_fops); 512 513 dsp->debugfs_root = root; 514 } 515 EXPORT_SYMBOL_NS_GPL(cs_dsp_init_debugfs, FW_CS_DSP); 516 517 /** 518 * cs_dsp_cleanup_debugfs() - Removes DSP representation from debugfs 519 * @dsp: pointer to DSP structure 520 */ 521 void cs_dsp_cleanup_debugfs(struct cs_dsp *dsp) 522 { 523 cs_dsp_debugfs_clear(dsp); 524 debugfs_remove_recursive(dsp->debugfs_root); 525 dsp->debugfs_root = NULL; 526 } 527 EXPORT_SYMBOL_NS_GPL(cs_dsp_cleanup_debugfs, FW_CS_DSP); 528 #else 529 void cs_dsp_init_debugfs(struct cs_dsp *dsp, struct dentry *debugfs_root) 530 { 531 } 532 EXPORT_SYMBOL_NS_GPL(cs_dsp_init_debugfs, FW_CS_DSP); 533 534 void cs_dsp_cleanup_debugfs(struct cs_dsp *dsp) 535 { 536 } 537 EXPORT_SYMBOL_NS_GPL(cs_dsp_cleanup_debugfs, FW_CS_DSP); 538 539 static inline void cs_dsp_debugfs_save_wmfwname(struct cs_dsp *dsp, 540 const char *s) 541 { 542 } 543 544 static inline void cs_dsp_debugfs_save_binname(struct cs_dsp *dsp, 545 const char *s) 546 { 547 } 548 549 static inline void cs_dsp_debugfs_clear(struct cs_dsp *dsp) 550 { 551 } 552 #endif 553 554 static const struct cs_dsp_region *cs_dsp_find_region(struct cs_dsp *dsp, 555 int type) 556 { 557 int i; 558 559 for (i = 0; i < dsp->num_mems; i++) 560 if (dsp->mem[i].type == type) 561 return &dsp->mem[i]; 562 563 return NULL; 564 } 565 566 static unsigned int cs_dsp_region_to_reg(struct cs_dsp_region const *mem, 567 unsigned int offset) 568 { 569 switch (mem->type) { 570 case WMFW_ADSP1_PM: 571 return mem->base + (offset * 3); 572 case WMFW_ADSP1_DM: 573 case WMFW_ADSP2_XM: 574 case WMFW_ADSP2_YM: 575 case WMFW_ADSP1_ZM: 576 return mem->base + (offset * 2); 577 default: 578 WARN(1, "Unknown memory region type"); 579 return offset; 580 } 581 } 582 583 static unsigned int cs_dsp_halo_region_to_reg(struct cs_dsp_region const *mem, 584 unsigned int offset) 585 { 586 switch (mem->type) { 587 case WMFW_ADSP2_XM: 588 case WMFW_ADSP2_YM: 589 return mem->base + (offset * 4); 590 case WMFW_HALO_XM_PACKED: 591 case WMFW_HALO_YM_PACKED: 592 return (mem->base + (offset * 3)) & ~0x3; 593 case WMFW_HALO_PM_PACKED: 594 return mem->base + (offset * 5); 595 default: 596 WARN(1, "Unknown memory region type"); 597 return offset; 598 } 599 } 600 601 static void cs_dsp_read_fw_status(struct cs_dsp *dsp, 602 int noffs, unsigned int *offs) 603 { 604 unsigned int i; 605 int ret; 606 607 for (i = 0; i < noffs; ++i) { 608 ret = regmap_read(dsp->regmap, dsp->base + offs[i], &offs[i]); 609 if (ret) { 610 cs_dsp_err(dsp, "Failed to read SCRATCH%u: %d\n", i, ret); 611 return; 612 } 613 } 614 } 615 616 static void cs_dsp_adsp2_show_fw_status(struct cs_dsp *dsp) 617 { 618 unsigned int offs[] = { 619 ADSP2_SCRATCH0, ADSP2_SCRATCH1, ADSP2_SCRATCH2, ADSP2_SCRATCH3, 620 }; 621 622 cs_dsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs); 623 624 cs_dsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", 625 offs[0], offs[1], offs[2], offs[3]); 626 } 627 628 static void cs_dsp_adsp2v2_show_fw_status(struct cs_dsp *dsp) 629 { 630 unsigned int offs[] = { ADSP2V2_SCRATCH0_1, ADSP2V2_SCRATCH2_3 }; 631 632 cs_dsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs); 633 634 cs_dsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", 635 offs[0] & 0xFFFF, offs[0] >> 16, 636 offs[1] & 0xFFFF, offs[1] >> 16); 637 } 638 639 static void cs_dsp_halo_show_fw_status(struct cs_dsp *dsp) 640 { 641 unsigned int offs[] = { 642 HALO_SCRATCH1, HALO_SCRATCH2, HALO_SCRATCH3, HALO_SCRATCH4, 643 }; 644 645 cs_dsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs); 646 647 cs_dsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", 648 offs[0], offs[1], offs[2], offs[3]); 649 } 650 651 static int cs_dsp_coeff_base_reg(struct cs_dsp_coeff_ctl *ctl, unsigned int *reg, 652 unsigned int off) 653 { 654 const struct cs_dsp_alg_region *alg_region = &ctl->alg_region; 655 struct cs_dsp *dsp = ctl->dsp; 656 const struct cs_dsp_region *mem; 657 658 mem = cs_dsp_find_region(dsp, alg_region->type); 659 if (!mem) { 660 cs_dsp_err(dsp, "No base for region %x\n", 661 alg_region->type); 662 return -EINVAL; 663 } 664 665 *reg = dsp->ops->region_to_reg(mem, ctl->alg_region.base + ctl->offset + off); 666 667 return 0; 668 } 669 670 /** 671 * cs_dsp_coeff_write_acked_control() - Sends event_id to the acked control 672 * @ctl: pointer to acked coefficient control 673 * @event_id: the value to write to the given acked control 674 * 675 * Once the value has been written to the control the function shall block 676 * until the running firmware acknowledges the write or timeout is exceeded. 677 * 678 * Must be called with pwr_lock held. 679 * 680 * Return: Zero for success, a negative number on error. 681 */ 682 int cs_dsp_coeff_write_acked_control(struct cs_dsp_coeff_ctl *ctl, unsigned int event_id) 683 { 684 struct cs_dsp *dsp = ctl->dsp; 685 __be32 val = cpu_to_be32(event_id); 686 unsigned int reg; 687 int i, ret; 688 689 lockdep_assert_held(&dsp->pwr_lock); 690 691 if (!dsp->running) 692 return -EPERM; 693 694 ret = cs_dsp_coeff_base_reg(ctl, ®, 0); 695 if (ret) 696 return ret; 697 698 cs_dsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n", 699 event_id, ctl->alg_region.alg, 700 cs_dsp_mem_region_name(ctl->alg_region.type), ctl->offset); 701 702 ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val)); 703 if (ret) { 704 cs_dsp_err(dsp, "Failed to write %x: %d\n", reg, ret); 705 return ret; 706 } 707 708 /* 709 * Poll for ack, we initially poll at ~1ms intervals for firmwares 710 * that respond quickly, then go to ~10ms polls. A firmware is unlikely 711 * to ack instantly so we do the first 1ms delay before reading the 712 * control to avoid a pointless bus transaction 713 */ 714 for (i = 0; i < CS_DSP_ACKED_CTL_TIMEOUT_MS;) { 715 switch (i) { 716 case 0 ... CS_DSP_ACKED_CTL_N_QUICKPOLLS - 1: 717 usleep_range(1000, 2000); 718 i++; 719 break; 720 default: 721 usleep_range(10000, 20000); 722 i += 10; 723 break; 724 } 725 726 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val)); 727 if (ret) { 728 cs_dsp_err(dsp, "Failed to read %x: %d\n", reg, ret); 729 return ret; 730 } 731 732 if (val == 0) { 733 cs_dsp_dbg(dsp, "Acked control ACKED at poll %u\n", i); 734 return 0; 735 } 736 } 737 738 cs_dsp_warn(dsp, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n", 739 reg, ctl->alg_region.alg, 740 cs_dsp_mem_region_name(ctl->alg_region.type), 741 ctl->offset); 742 743 return -ETIMEDOUT; 744 } 745 EXPORT_SYMBOL_NS_GPL(cs_dsp_coeff_write_acked_control, FW_CS_DSP); 746 747 static int cs_dsp_coeff_write_ctrl_raw(struct cs_dsp_coeff_ctl *ctl, 748 unsigned int off, const void *buf, size_t len) 749 { 750 struct cs_dsp *dsp = ctl->dsp; 751 void *scratch; 752 int ret; 753 unsigned int reg; 754 755 ret = cs_dsp_coeff_base_reg(ctl, ®, off); 756 if (ret) 757 return ret; 758 759 scratch = kmemdup(buf, len, GFP_KERNEL | GFP_DMA); 760 if (!scratch) 761 return -ENOMEM; 762 763 ret = regmap_raw_write(dsp->regmap, reg, scratch, 764 len); 765 if (ret) { 766 cs_dsp_err(dsp, "Failed to write %zu bytes to %x: %d\n", 767 len, reg, ret); 768 kfree(scratch); 769 return ret; 770 } 771 cs_dsp_dbg(dsp, "Wrote %zu bytes to %x\n", len, reg); 772 773 kfree(scratch); 774 775 return 0; 776 } 777 778 /** 779 * cs_dsp_coeff_write_ctrl() - Writes the given buffer to the given coefficient control 780 * @ctl: pointer to coefficient control 781 * @off: word offset at which data should be written 782 * @buf: the buffer to write to the given control 783 * @len: the length of the buffer in bytes 784 * 785 * Must be called with pwr_lock held. 786 * 787 * Return: < 0 on error, 1 when the control value changed and 0 when it has not. 788 */ 789 int cs_dsp_coeff_write_ctrl(struct cs_dsp_coeff_ctl *ctl, 790 unsigned int off, const void *buf, size_t len) 791 { 792 int ret = 0; 793 794 if (!ctl) 795 return -ENOENT; 796 797 lockdep_assert_held(&ctl->dsp->pwr_lock); 798 799 if (len + off * sizeof(u32) > ctl->len) 800 return -EINVAL; 801 802 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) { 803 ret = -EPERM; 804 } else if (buf != ctl->cache) { 805 if (memcmp(ctl->cache + off * sizeof(u32), buf, len)) 806 memcpy(ctl->cache + off * sizeof(u32), buf, len); 807 else 808 return 0; 809 } 810 811 ctl->set = 1; 812 if (ctl->enabled && ctl->dsp->running) 813 ret = cs_dsp_coeff_write_ctrl_raw(ctl, off, buf, len); 814 815 if (ret < 0) 816 return ret; 817 818 return 1; 819 } 820 EXPORT_SYMBOL_NS_GPL(cs_dsp_coeff_write_ctrl, FW_CS_DSP); 821 822 static int cs_dsp_coeff_read_ctrl_raw(struct cs_dsp_coeff_ctl *ctl, 823 unsigned int off, void *buf, size_t len) 824 { 825 struct cs_dsp *dsp = ctl->dsp; 826 void *scratch; 827 int ret; 828 unsigned int reg; 829 830 ret = cs_dsp_coeff_base_reg(ctl, ®, off); 831 if (ret) 832 return ret; 833 834 scratch = kmalloc(len, GFP_KERNEL | GFP_DMA); 835 if (!scratch) 836 return -ENOMEM; 837 838 ret = regmap_raw_read(dsp->regmap, reg, scratch, len); 839 if (ret) { 840 cs_dsp_err(dsp, "Failed to read %zu bytes from %x: %d\n", 841 len, reg, ret); 842 kfree(scratch); 843 return ret; 844 } 845 cs_dsp_dbg(dsp, "Read %zu bytes from %x\n", len, reg); 846 847 memcpy(buf, scratch, len); 848 kfree(scratch); 849 850 return 0; 851 } 852 853 /** 854 * cs_dsp_coeff_read_ctrl() - Reads the given coefficient control into the given buffer 855 * @ctl: pointer to coefficient control 856 * @off: word offset at which data should be read 857 * @buf: the buffer to store to the given control 858 * @len: the length of the buffer in bytes 859 * 860 * Must be called with pwr_lock held. 861 * 862 * Return: Zero for success, a negative number on error. 863 */ 864 int cs_dsp_coeff_read_ctrl(struct cs_dsp_coeff_ctl *ctl, 865 unsigned int off, void *buf, size_t len) 866 { 867 int ret = 0; 868 869 if (!ctl) 870 return -ENOENT; 871 872 lockdep_assert_held(&ctl->dsp->pwr_lock); 873 874 if (len + off * sizeof(u32) > ctl->len) 875 return -EINVAL; 876 877 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) { 878 if (ctl->enabled && ctl->dsp->running) 879 return cs_dsp_coeff_read_ctrl_raw(ctl, off, buf, len); 880 else 881 return -EPERM; 882 } else { 883 if (!ctl->flags && ctl->enabled && ctl->dsp->running) 884 ret = cs_dsp_coeff_read_ctrl_raw(ctl, 0, ctl->cache, ctl->len); 885 886 if (buf != ctl->cache) 887 memcpy(buf, ctl->cache + off * sizeof(u32), len); 888 } 889 890 return ret; 891 } 892 EXPORT_SYMBOL_NS_GPL(cs_dsp_coeff_read_ctrl, FW_CS_DSP); 893 894 static int cs_dsp_coeff_init_control_caches(struct cs_dsp *dsp) 895 { 896 struct cs_dsp_coeff_ctl *ctl; 897 int ret; 898 899 list_for_each_entry(ctl, &dsp->ctl_list, list) { 900 if (!ctl->enabled || ctl->set) 901 continue; 902 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) 903 continue; 904 905 /* 906 * For readable controls populate the cache from the DSP memory. 907 * For non-readable controls the cache was zero-filled when 908 * created so we don't need to do anything. 909 */ 910 if (!ctl->flags || (ctl->flags & WMFW_CTL_FLAG_READABLE)) { 911 ret = cs_dsp_coeff_read_ctrl_raw(ctl, 0, ctl->cache, ctl->len); 912 if (ret < 0) 913 return ret; 914 } 915 } 916 917 return 0; 918 } 919 920 static int cs_dsp_coeff_sync_controls(struct cs_dsp *dsp) 921 { 922 struct cs_dsp_coeff_ctl *ctl; 923 int ret; 924 925 list_for_each_entry(ctl, &dsp->ctl_list, list) { 926 if (!ctl->enabled) 927 continue; 928 if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) { 929 ret = cs_dsp_coeff_write_ctrl_raw(ctl, 0, ctl->cache, 930 ctl->len); 931 if (ret < 0) 932 return ret; 933 } 934 } 935 936 return 0; 937 } 938 939 static void cs_dsp_signal_event_controls(struct cs_dsp *dsp, 940 unsigned int event) 941 { 942 struct cs_dsp_coeff_ctl *ctl; 943 int ret; 944 945 list_for_each_entry(ctl, &dsp->ctl_list, list) { 946 if (ctl->type != WMFW_CTL_TYPE_HOSTEVENT) 947 continue; 948 949 if (!ctl->enabled) 950 continue; 951 952 ret = cs_dsp_coeff_write_acked_control(ctl, event); 953 if (ret) 954 cs_dsp_warn(dsp, 955 "Failed to send 0x%x event to alg 0x%x (%d)\n", 956 event, ctl->alg_region.alg, ret); 957 } 958 } 959 960 static void cs_dsp_free_ctl_blk(struct cs_dsp_coeff_ctl *ctl) 961 { 962 kfree(ctl->cache); 963 kfree(ctl->subname); 964 kfree(ctl); 965 } 966 967 static int cs_dsp_create_control(struct cs_dsp *dsp, 968 const struct cs_dsp_alg_region *alg_region, 969 unsigned int offset, unsigned int len, 970 const char *subname, unsigned int subname_len, 971 unsigned int flags, unsigned int type) 972 { 973 struct cs_dsp_coeff_ctl *ctl; 974 int ret; 975 976 list_for_each_entry(ctl, &dsp->ctl_list, list) { 977 if (ctl->fw_name == dsp->fw_name && 978 ctl->alg_region.alg == alg_region->alg && 979 ctl->alg_region.type == alg_region->type) { 980 if ((!subname && !ctl->subname) || 981 (subname && !strncmp(ctl->subname, subname, ctl->subname_len))) { 982 if (!ctl->enabled) 983 ctl->enabled = 1; 984 return 0; 985 } 986 } 987 } 988 989 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL); 990 if (!ctl) 991 return -ENOMEM; 992 993 ctl->fw_name = dsp->fw_name; 994 ctl->alg_region = *alg_region; 995 if (subname && dsp->fw_ver >= 2) { 996 ctl->subname_len = subname_len; 997 ctl->subname = kasprintf(GFP_KERNEL, "%.*s", subname_len, subname); 998 if (!ctl->subname) { 999 ret = -ENOMEM; 1000 goto err_ctl; 1001 } 1002 } 1003 ctl->enabled = 1; 1004 ctl->set = 0; 1005 ctl->dsp = dsp; 1006 1007 ctl->flags = flags; 1008 ctl->type = type; 1009 ctl->offset = offset; 1010 ctl->len = len; 1011 ctl->cache = kzalloc(ctl->len, GFP_KERNEL); 1012 if (!ctl->cache) { 1013 ret = -ENOMEM; 1014 goto err_ctl_subname; 1015 } 1016 1017 list_add(&ctl->list, &dsp->ctl_list); 1018 1019 if (dsp->client_ops->control_add) { 1020 ret = dsp->client_ops->control_add(ctl); 1021 if (ret) 1022 goto err_list_del; 1023 } 1024 1025 return 0; 1026 1027 err_list_del: 1028 list_del(&ctl->list); 1029 kfree(ctl->cache); 1030 err_ctl_subname: 1031 kfree(ctl->subname); 1032 err_ctl: 1033 kfree(ctl); 1034 1035 return ret; 1036 } 1037 1038 struct cs_dsp_coeff_parsed_alg { 1039 int id; 1040 const u8 *name; 1041 int name_len; 1042 int ncoeff; 1043 }; 1044 1045 struct cs_dsp_coeff_parsed_coeff { 1046 int offset; 1047 int mem_type; 1048 const u8 *name; 1049 int name_len; 1050 unsigned int ctl_type; 1051 int flags; 1052 int len; 1053 }; 1054 1055 static int cs_dsp_coeff_parse_string(int bytes, const u8 **pos, const u8 **str) 1056 { 1057 int length; 1058 1059 switch (bytes) { 1060 case 1: 1061 length = **pos; 1062 break; 1063 case 2: 1064 length = le16_to_cpu(*((__le16 *)*pos)); 1065 break; 1066 default: 1067 return 0; 1068 } 1069 1070 if (str) 1071 *str = *pos + bytes; 1072 1073 *pos += ((length + bytes) + 3) & ~0x03; 1074 1075 return length; 1076 } 1077 1078 static int cs_dsp_coeff_parse_int(int bytes, const u8 **pos) 1079 { 1080 int val = 0; 1081 1082 switch (bytes) { 1083 case 2: 1084 val = le16_to_cpu(*((__le16 *)*pos)); 1085 break; 1086 case 4: 1087 val = le32_to_cpu(*((__le32 *)*pos)); 1088 break; 1089 default: 1090 break; 1091 } 1092 1093 *pos += bytes; 1094 1095 return val; 1096 } 1097 1098 static inline void cs_dsp_coeff_parse_alg(struct cs_dsp *dsp, const u8 **data, 1099 struct cs_dsp_coeff_parsed_alg *blk) 1100 { 1101 const struct wmfw_adsp_alg_data *raw; 1102 1103 switch (dsp->fw_ver) { 1104 case 0: 1105 case 1: 1106 raw = (const struct wmfw_adsp_alg_data *)*data; 1107 *data = raw->data; 1108 1109 blk->id = le32_to_cpu(raw->id); 1110 blk->name = raw->name; 1111 blk->name_len = strlen(raw->name); 1112 blk->ncoeff = le32_to_cpu(raw->ncoeff); 1113 break; 1114 default: 1115 blk->id = cs_dsp_coeff_parse_int(sizeof(raw->id), data); 1116 blk->name_len = cs_dsp_coeff_parse_string(sizeof(u8), data, 1117 &blk->name); 1118 cs_dsp_coeff_parse_string(sizeof(u16), data, NULL); 1119 blk->ncoeff = cs_dsp_coeff_parse_int(sizeof(raw->ncoeff), data); 1120 break; 1121 } 1122 1123 cs_dsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id); 1124 cs_dsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name); 1125 cs_dsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff); 1126 } 1127 1128 static inline void cs_dsp_coeff_parse_coeff(struct cs_dsp *dsp, const u8 **data, 1129 struct cs_dsp_coeff_parsed_coeff *blk) 1130 { 1131 const struct wmfw_adsp_coeff_data *raw; 1132 const u8 *tmp; 1133 int length; 1134 1135 switch (dsp->fw_ver) { 1136 case 0: 1137 case 1: 1138 raw = (const struct wmfw_adsp_coeff_data *)*data; 1139 *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size); 1140 1141 blk->offset = le16_to_cpu(raw->hdr.offset); 1142 blk->mem_type = le16_to_cpu(raw->hdr.type); 1143 blk->name = raw->name; 1144 blk->name_len = strlen(raw->name); 1145 blk->ctl_type = le16_to_cpu(raw->ctl_type); 1146 blk->flags = le16_to_cpu(raw->flags); 1147 blk->len = le32_to_cpu(raw->len); 1148 break; 1149 default: 1150 tmp = *data; 1151 blk->offset = cs_dsp_coeff_parse_int(sizeof(raw->hdr.offset), &tmp); 1152 blk->mem_type = cs_dsp_coeff_parse_int(sizeof(raw->hdr.type), &tmp); 1153 length = cs_dsp_coeff_parse_int(sizeof(raw->hdr.size), &tmp); 1154 blk->name_len = cs_dsp_coeff_parse_string(sizeof(u8), &tmp, 1155 &blk->name); 1156 cs_dsp_coeff_parse_string(sizeof(u8), &tmp, NULL); 1157 cs_dsp_coeff_parse_string(sizeof(u16), &tmp, NULL); 1158 blk->ctl_type = cs_dsp_coeff_parse_int(sizeof(raw->ctl_type), &tmp); 1159 blk->flags = cs_dsp_coeff_parse_int(sizeof(raw->flags), &tmp); 1160 blk->len = cs_dsp_coeff_parse_int(sizeof(raw->len), &tmp); 1161 1162 *data = *data + sizeof(raw->hdr) + length; 1163 break; 1164 } 1165 1166 cs_dsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type); 1167 cs_dsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset); 1168 cs_dsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name); 1169 cs_dsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags); 1170 cs_dsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type); 1171 cs_dsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len); 1172 } 1173 1174 static int cs_dsp_check_coeff_flags(struct cs_dsp *dsp, 1175 const struct cs_dsp_coeff_parsed_coeff *coeff_blk, 1176 unsigned int f_required, 1177 unsigned int f_illegal) 1178 { 1179 if ((coeff_blk->flags & f_illegal) || 1180 ((coeff_blk->flags & f_required) != f_required)) { 1181 cs_dsp_err(dsp, "Illegal flags 0x%x for control type 0x%x\n", 1182 coeff_blk->flags, coeff_blk->ctl_type); 1183 return -EINVAL; 1184 } 1185 1186 return 0; 1187 } 1188 1189 static int cs_dsp_parse_coeff(struct cs_dsp *dsp, 1190 const struct wmfw_region *region) 1191 { 1192 struct cs_dsp_alg_region alg_region = {}; 1193 struct cs_dsp_coeff_parsed_alg alg_blk; 1194 struct cs_dsp_coeff_parsed_coeff coeff_blk; 1195 const u8 *data = region->data; 1196 int i, ret; 1197 1198 cs_dsp_coeff_parse_alg(dsp, &data, &alg_blk); 1199 for (i = 0; i < alg_blk.ncoeff; i++) { 1200 cs_dsp_coeff_parse_coeff(dsp, &data, &coeff_blk); 1201 1202 switch (coeff_blk.ctl_type) { 1203 case WMFW_CTL_TYPE_BYTES: 1204 break; 1205 case WMFW_CTL_TYPE_ACKED: 1206 if (coeff_blk.flags & WMFW_CTL_FLAG_SYS) 1207 continue; /* ignore */ 1208 1209 ret = cs_dsp_check_coeff_flags(dsp, &coeff_blk, 1210 WMFW_CTL_FLAG_VOLATILE | 1211 WMFW_CTL_FLAG_WRITEABLE | 1212 WMFW_CTL_FLAG_READABLE, 1213 0); 1214 if (ret) 1215 return -EINVAL; 1216 break; 1217 case WMFW_CTL_TYPE_HOSTEVENT: 1218 case WMFW_CTL_TYPE_FWEVENT: 1219 ret = cs_dsp_check_coeff_flags(dsp, &coeff_blk, 1220 WMFW_CTL_FLAG_SYS | 1221 WMFW_CTL_FLAG_VOLATILE | 1222 WMFW_CTL_FLAG_WRITEABLE | 1223 WMFW_CTL_FLAG_READABLE, 1224 0); 1225 if (ret) 1226 return -EINVAL; 1227 break; 1228 case WMFW_CTL_TYPE_HOST_BUFFER: 1229 ret = cs_dsp_check_coeff_flags(dsp, &coeff_blk, 1230 WMFW_CTL_FLAG_SYS | 1231 WMFW_CTL_FLAG_VOLATILE | 1232 WMFW_CTL_FLAG_READABLE, 1233 0); 1234 if (ret) 1235 return -EINVAL; 1236 break; 1237 default: 1238 cs_dsp_err(dsp, "Unknown control type: %d\n", 1239 coeff_blk.ctl_type); 1240 return -EINVAL; 1241 } 1242 1243 alg_region.type = coeff_blk.mem_type; 1244 alg_region.alg = alg_blk.id; 1245 1246 ret = cs_dsp_create_control(dsp, &alg_region, 1247 coeff_blk.offset, 1248 coeff_blk.len, 1249 coeff_blk.name, 1250 coeff_blk.name_len, 1251 coeff_blk.flags, 1252 coeff_blk.ctl_type); 1253 if (ret < 0) 1254 cs_dsp_err(dsp, "Failed to create control: %.*s, %d\n", 1255 coeff_blk.name_len, coeff_blk.name, ret); 1256 } 1257 1258 return 0; 1259 } 1260 1261 static unsigned int cs_dsp_adsp1_parse_sizes(struct cs_dsp *dsp, 1262 const char * const file, 1263 unsigned int pos, 1264 const struct firmware *firmware) 1265 { 1266 const struct wmfw_adsp1_sizes *adsp1_sizes; 1267 1268 adsp1_sizes = (void *)&firmware->data[pos]; 1269 1270 cs_dsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n", file, 1271 le32_to_cpu(adsp1_sizes->dm), le32_to_cpu(adsp1_sizes->pm), 1272 le32_to_cpu(adsp1_sizes->zm)); 1273 1274 return pos + sizeof(*adsp1_sizes); 1275 } 1276 1277 static unsigned int cs_dsp_adsp2_parse_sizes(struct cs_dsp *dsp, 1278 const char * const file, 1279 unsigned int pos, 1280 const struct firmware *firmware) 1281 { 1282 const struct wmfw_adsp2_sizes *adsp2_sizes; 1283 1284 adsp2_sizes = (void *)&firmware->data[pos]; 1285 1286 cs_dsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n", file, 1287 le32_to_cpu(adsp2_sizes->xm), le32_to_cpu(adsp2_sizes->ym), 1288 le32_to_cpu(adsp2_sizes->pm), le32_to_cpu(adsp2_sizes->zm)); 1289 1290 return pos + sizeof(*adsp2_sizes); 1291 } 1292 1293 static bool cs_dsp_validate_version(struct cs_dsp *dsp, unsigned int version) 1294 { 1295 switch (version) { 1296 case 0: 1297 cs_dsp_warn(dsp, "Deprecated file format %d\n", version); 1298 return true; 1299 case 1: 1300 case 2: 1301 return true; 1302 default: 1303 return false; 1304 } 1305 } 1306 1307 static bool cs_dsp_halo_validate_version(struct cs_dsp *dsp, unsigned int version) 1308 { 1309 switch (version) { 1310 case 3: 1311 return true; 1312 default: 1313 return false; 1314 } 1315 } 1316 1317 static int cs_dsp_load(struct cs_dsp *dsp, const struct firmware *firmware, 1318 const char *file) 1319 { 1320 LIST_HEAD(buf_list); 1321 struct regmap *regmap = dsp->regmap; 1322 unsigned int pos = 0; 1323 const struct wmfw_header *header; 1324 const struct wmfw_adsp1_sizes *adsp1_sizes; 1325 const struct wmfw_footer *footer; 1326 const struct wmfw_region *region; 1327 const struct cs_dsp_region *mem; 1328 const char *region_name; 1329 char *text = NULL; 1330 struct cs_dsp_buf *buf; 1331 unsigned int reg; 1332 int regions = 0; 1333 int ret, offset, type; 1334 1335 if (!firmware) 1336 return 0; 1337 1338 ret = -EINVAL; 1339 1340 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer); 1341 if (pos >= firmware->size) { 1342 cs_dsp_err(dsp, "%s: file too short, %zu bytes\n", 1343 file, firmware->size); 1344 goto out_fw; 1345 } 1346 1347 header = (void *)&firmware->data[0]; 1348 1349 if (memcmp(&header->magic[0], "WMFW", 4) != 0) { 1350 cs_dsp_err(dsp, "%s: invalid magic\n", file); 1351 goto out_fw; 1352 } 1353 1354 if (!dsp->ops->validate_version(dsp, header->ver)) { 1355 cs_dsp_err(dsp, "%s: unknown file format %d\n", 1356 file, header->ver); 1357 goto out_fw; 1358 } 1359 1360 cs_dsp_info(dsp, "Firmware version: %d\n", header->ver); 1361 dsp->fw_ver = header->ver; 1362 1363 if (header->core != dsp->type) { 1364 cs_dsp_err(dsp, "%s: invalid core %d != %d\n", 1365 file, header->core, dsp->type); 1366 goto out_fw; 1367 } 1368 1369 pos = sizeof(*header); 1370 pos = dsp->ops->parse_sizes(dsp, file, pos, firmware); 1371 1372 footer = (void *)&firmware->data[pos]; 1373 pos += sizeof(*footer); 1374 1375 if (le32_to_cpu(header->len) != pos) { 1376 cs_dsp_err(dsp, "%s: unexpected header length %d\n", 1377 file, le32_to_cpu(header->len)); 1378 goto out_fw; 1379 } 1380 1381 cs_dsp_dbg(dsp, "%s: timestamp %llu\n", file, 1382 le64_to_cpu(footer->timestamp)); 1383 1384 while (pos < firmware->size && 1385 sizeof(*region) < firmware->size - pos) { 1386 region = (void *)&(firmware->data[pos]); 1387 region_name = "Unknown"; 1388 reg = 0; 1389 text = NULL; 1390 offset = le32_to_cpu(region->offset) & 0xffffff; 1391 type = be32_to_cpu(region->type) & 0xff; 1392 1393 switch (type) { 1394 case WMFW_NAME_TEXT: 1395 region_name = "Firmware name"; 1396 text = kzalloc(le32_to_cpu(region->len) + 1, 1397 GFP_KERNEL); 1398 break; 1399 case WMFW_ALGORITHM_DATA: 1400 region_name = "Algorithm"; 1401 ret = cs_dsp_parse_coeff(dsp, region); 1402 if (ret != 0) 1403 goto out_fw; 1404 break; 1405 case WMFW_INFO_TEXT: 1406 region_name = "Information"; 1407 text = kzalloc(le32_to_cpu(region->len) + 1, 1408 GFP_KERNEL); 1409 break; 1410 case WMFW_ABSOLUTE: 1411 region_name = "Absolute"; 1412 reg = offset; 1413 break; 1414 case WMFW_ADSP1_PM: 1415 case WMFW_ADSP1_DM: 1416 case WMFW_ADSP2_XM: 1417 case WMFW_ADSP2_YM: 1418 case WMFW_ADSP1_ZM: 1419 case WMFW_HALO_PM_PACKED: 1420 case WMFW_HALO_XM_PACKED: 1421 case WMFW_HALO_YM_PACKED: 1422 mem = cs_dsp_find_region(dsp, type); 1423 if (!mem) { 1424 cs_dsp_err(dsp, "No region of type: %x\n", type); 1425 ret = -EINVAL; 1426 goto out_fw; 1427 } 1428 1429 region_name = cs_dsp_mem_region_name(type); 1430 reg = dsp->ops->region_to_reg(mem, offset); 1431 break; 1432 default: 1433 cs_dsp_warn(dsp, 1434 "%s.%d: Unknown region type %x at %d(%x)\n", 1435 file, regions, type, pos, pos); 1436 break; 1437 } 1438 1439 cs_dsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file, 1440 regions, le32_to_cpu(region->len), offset, 1441 region_name); 1442 1443 if (le32_to_cpu(region->len) > 1444 firmware->size - pos - sizeof(*region)) { 1445 cs_dsp_err(dsp, 1446 "%s.%d: %s region len %d bytes exceeds file length %zu\n", 1447 file, regions, region_name, 1448 le32_to_cpu(region->len), firmware->size); 1449 ret = -EINVAL; 1450 goto out_fw; 1451 } 1452 1453 if (text) { 1454 memcpy(text, region->data, le32_to_cpu(region->len)); 1455 cs_dsp_info(dsp, "%s: %s\n", file, text); 1456 kfree(text); 1457 text = NULL; 1458 } 1459 1460 if (reg) { 1461 buf = cs_dsp_buf_alloc(region->data, 1462 le32_to_cpu(region->len), 1463 &buf_list); 1464 if (!buf) { 1465 cs_dsp_err(dsp, "Out of memory\n"); 1466 ret = -ENOMEM; 1467 goto out_fw; 1468 } 1469 1470 ret = regmap_raw_write_async(regmap, reg, buf->buf, 1471 le32_to_cpu(region->len)); 1472 if (ret != 0) { 1473 cs_dsp_err(dsp, 1474 "%s.%d: Failed to write %d bytes at %d in %s: %d\n", 1475 file, regions, 1476 le32_to_cpu(region->len), offset, 1477 region_name, ret); 1478 goto out_fw; 1479 } 1480 } 1481 1482 pos += le32_to_cpu(region->len) + sizeof(*region); 1483 regions++; 1484 } 1485 1486 ret = regmap_async_complete(regmap); 1487 if (ret != 0) { 1488 cs_dsp_err(dsp, "Failed to complete async write: %d\n", ret); 1489 goto out_fw; 1490 } 1491 1492 if (pos > firmware->size) 1493 cs_dsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", 1494 file, regions, pos - firmware->size); 1495 1496 cs_dsp_debugfs_save_wmfwname(dsp, file); 1497 1498 out_fw: 1499 regmap_async_complete(regmap); 1500 cs_dsp_buf_free(&buf_list); 1501 kfree(text); 1502 1503 return ret; 1504 } 1505 1506 /** 1507 * cs_dsp_get_ctl() - Finds a matching coefficient control 1508 * @dsp: pointer to DSP structure 1509 * @name: pointer to string to match with a control's subname 1510 * @type: the algorithm type to match 1511 * @alg: the algorithm id to match 1512 * 1513 * Find cs_dsp_coeff_ctl with input name as its subname 1514 * 1515 * Return: pointer to the control on success, NULL if not found 1516 */ 1517 struct cs_dsp_coeff_ctl *cs_dsp_get_ctl(struct cs_dsp *dsp, const char *name, int type, 1518 unsigned int alg) 1519 { 1520 struct cs_dsp_coeff_ctl *pos, *rslt = NULL; 1521 1522 lockdep_assert_held(&dsp->pwr_lock); 1523 1524 list_for_each_entry(pos, &dsp->ctl_list, list) { 1525 if (!pos->subname) 1526 continue; 1527 if (strncmp(pos->subname, name, pos->subname_len) == 0 && 1528 pos->fw_name == dsp->fw_name && 1529 pos->alg_region.alg == alg && 1530 pos->alg_region.type == type) { 1531 rslt = pos; 1532 break; 1533 } 1534 } 1535 1536 return rslt; 1537 } 1538 EXPORT_SYMBOL_NS_GPL(cs_dsp_get_ctl, FW_CS_DSP); 1539 1540 static void cs_dsp_ctl_fixup_base(struct cs_dsp *dsp, 1541 const struct cs_dsp_alg_region *alg_region) 1542 { 1543 struct cs_dsp_coeff_ctl *ctl; 1544 1545 list_for_each_entry(ctl, &dsp->ctl_list, list) { 1546 if (ctl->fw_name == dsp->fw_name && 1547 alg_region->alg == ctl->alg_region.alg && 1548 alg_region->type == ctl->alg_region.type) { 1549 ctl->alg_region.base = alg_region->base; 1550 } 1551 } 1552 } 1553 1554 static void *cs_dsp_read_algs(struct cs_dsp *dsp, size_t n_algs, 1555 const struct cs_dsp_region *mem, 1556 unsigned int pos, unsigned int len) 1557 { 1558 void *alg; 1559 unsigned int reg; 1560 int ret; 1561 __be32 val; 1562 1563 if (n_algs == 0) { 1564 cs_dsp_err(dsp, "No algorithms\n"); 1565 return ERR_PTR(-EINVAL); 1566 } 1567 1568 if (n_algs > 1024) { 1569 cs_dsp_err(dsp, "Algorithm count %zx excessive\n", n_algs); 1570 return ERR_PTR(-EINVAL); 1571 } 1572 1573 /* Read the terminator first to validate the length */ 1574 reg = dsp->ops->region_to_reg(mem, pos + len); 1575 1576 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val)); 1577 if (ret != 0) { 1578 cs_dsp_err(dsp, "Failed to read algorithm list end: %d\n", 1579 ret); 1580 return ERR_PTR(ret); 1581 } 1582 1583 if (be32_to_cpu(val) != 0xbedead) 1584 cs_dsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbedead\n", 1585 reg, be32_to_cpu(val)); 1586 1587 /* Convert length from DSP words to bytes */ 1588 len *= sizeof(u32); 1589 1590 alg = kzalloc(len, GFP_KERNEL | GFP_DMA); 1591 if (!alg) 1592 return ERR_PTR(-ENOMEM); 1593 1594 reg = dsp->ops->region_to_reg(mem, pos); 1595 1596 ret = regmap_raw_read(dsp->regmap, reg, alg, len); 1597 if (ret != 0) { 1598 cs_dsp_err(dsp, "Failed to read algorithm list: %d\n", ret); 1599 kfree(alg); 1600 return ERR_PTR(ret); 1601 } 1602 1603 return alg; 1604 } 1605 1606 /** 1607 * cs_dsp_find_alg_region() - Finds a matching algorithm region 1608 * @dsp: pointer to DSP structure 1609 * @type: the algorithm type to match 1610 * @id: the algorithm id to match 1611 * 1612 * Return: Pointer to matching algorithm region, or NULL if not found. 1613 */ 1614 struct cs_dsp_alg_region *cs_dsp_find_alg_region(struct cs_dsp *dsp, 1615 int type, unsigned int id) 1616 { 1617 struct cs_dsp_alg_region *alg_region; 1618 1619 lockdep_assert_held(&dsp->pwr_lock); 1620 1621 list_for_each_entry(alg_region, &dsp->alg_regions, list) { 1622 if (id == alg_region->alg && type == alg_region->type) 1623 return alg_region; 1624 } 1625 1626 return NULL; 1627 } 1628 EXPORT_SYMBOL_NS_GPL(cs_dsp_find_alg_region, FW_CS_DSP); 1629 1630 static struct cs_dsp_alg_region *cs_dsp_create_region(struct cs_dsp *dsp, 1631 int type, __be32 id, 1632 __be32 ver, __be32 base) 1633 { 1634 struct cs_dsp_alg_region *alg_region; 1635 1636 alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL); 1637 if (!alg_region) 1638 return ERR_PTR(-ENOMEM); 1639 1640 alg_region->type = type; 1641 alg_region->alg = be32_to_cpu(id); 1642 alg_region->ver = be32_to_cpu(ver); 1643 alg_region->base = be32_to_cpu(base); 1644 1645 list_add_tail(&alg_region->list, &dsp->alg_regions); 1646 1647 if (dsp->fw_ver > 0) 1648 cs_dsp_ctl_fixup_base(dsp, alg_region); 1649 1650 return alg_region; 1651 } 1652 1653 static void cs_dsp_free_alg_regions(struct cs_dsp *dsp) 1654 { 1655 struct cs_dsp_alg_region *alg_region; 1656 1657 while (!list_empty(&dsp->alg_regions)) { 1658 alg_region = list_first_entry(&dsp->alg_regions, 1659 struct cs_dsp_alg_region, 1660 list); 1661 list_del(&alg_region->list); 1662 kfree(alg_region); 1663 } 1664 } 1665 1666 static void cs_dsp_parse_wmfw_id_header(struct cs_dsp *dsp, 1667 struct wmfw_id_hdr *fw, int nalgs) 1668 { 1669 dsp->fw_id = be32_to_cpu(fw->id); 1670 dsp->fw_id_version = be32_to_cpu(fw->ver); 1671 1672 cs_dsp_info(dsp, "Firmware: %x v%d.%d.%d, %d algorithms\n", 1673 dsp->fw_id, (dsp->fw_id_version & 0xff0000) >> 16, 1674 (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff, 1675 nalgs); 1676 } 1677 1678 static void cs_dsp_parse_wmfw_v3_id_header(struct cs_dsp *dsp, 1679 struct wmfw_v3_id_hdr *fw, int nalgs) 1680 { 1681 dsp->fw_id = be32_to_cpu(fw->id); 1682 dsp->fw_id_version = be32_to_cpu(fw->ver); 1683 dsp->fw_vendor_id = be32_to_cpu(fw->vendor_id); 1684 1685 cs_dsp_info(dsp, "Firmware: %x vendor: 0x%x v%d.%d.%d, %d algorithms\n", 1686 dsp->fw_id, dsp->fw_vendor_id, 1687 (dsp->fw_id_version & 0xff0000) >> 16, 1688 (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff, 1689 nalgs); 1690 } 1691 1692 static int cs_dsp_create_regions(struct cs_dsp *dsp, __be32 id, __be32 ver, 1693 int nregions, const int *type, __be32 *base) 1694 { 1695 struct cs_dsp_alg_region *alg_region; 1696 int i; 1697 1698 for (i = 0; i < nregions; i++) { 1699 alg_region = cs_dsp_create_region(dsp, type[i], id, ver, base[i]); 1700 if (IS_ERR(alg_region)) 1701 return PTR_ERR(alg_region); 1702 } 1703 1704 return 0; 1705 } 1706 1707 static int cs_dsp_adsp1_setup_algs(struct cs_dsp *dsp) 1708 { 1709 struct wmfw_adsp1_id_hdr adsp1_id; 1710 struct wmfw_adsp1_alg_hdr *adsp1_alg; 1711 struct cs_dsp_alg_region *alg_region; 1712 const struct cs_dsp_region *mem; 1713 unsigned int pos, len; 1714 size_t n_algs; 1715 int i, ret; 1716 1717 mem = cs_dsp_find_region(dsp, WMFW_ADSP1_DM); 1718 if (WARN_ON(!mem)) 1719 return -EINVAL; 1720 1721 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id, 1722 sizeof(adsp1_id)); 1723 if (ret != 0) { 1724 cs_dsp_err(dsp, "Failed to read algorithm info: %d\n", 1725 ret); 1726 return ret; 1727 } 1728 1729 n_algs = be32_to_cpu(adsp1_id.n_algs); 1730 1731 cs_dsp_parse_wmfw_id_header(dsp, &adsp1_id.fw, n_algs); 1732 1733 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP1_ZM, 1734 adsp1_id.fw.id, adsp1_id.fw.ver, 1735 adsp1_id.zm); 1736 if (IS_ERR(alg_region)) 1737 return PTR_ERR(alg_region); 1738 1739 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP1_DM, 1740 adsp1_id.fw.id, adsp1_id.fw.ver, 1741 adsp1_id.dm); 1742 if (IS_ERR(alg_region)) 1743 return PTR_ERR(alg_region); 1744 1745 /* Calculate offset and length in DSP words */ 1746 pos = sizeof(adsp1_id) / sizeof(u32); 1747 len = (sizeof(*adsp1_alg) * n_algs) / sizeof(u32); 1748 1749 adsp1_alg = cs_dsp_read_algs(dsp, n_algs, mem, pos, len); 1750 if (IS_ERR(adsp1_alg)) 1751 return PTR_ERR(adsp1_alg); 1752 1753 for (i = 0; i < n_algs; i++) { 1754 cs_dsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n", 1755 i, be32_to_cpu(adsp1_alg[i].alg.id), 1756 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16, 1757 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8, 1758 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff, 1759 be32_to_cpu(adsp1_alg[i].dm), 1760 be32_to_cpu(adsp1_alg[i].zm)); 1761 1762 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP1_DM, 1763 adsp1_alg[i].alg.id, 1764 adsp1_alg[i].alg.ver, 1765 adsp1_alg[i].dm); 1766 if (IS_ERR(alg_region)) { 1767 ret = PTR_ERR(alg_region); 1768 goto out; 1769 } 1770 if (dsp->fw_ver == 0) { 1771 if (i + 1 < n_algs) { 1772 len = be32_to_cpu(adsp1_alg[i + 1].dm); 1773 len -= be32_to_cpu(adsp1_alg[i].dm); 1774 len *= 4; 1775 cs_dsp_create_control(dsp, alg_region, 0, 1776 len, NULL, 0, 0, 1777 WMFW_CTL_TYPE_BYTES); 1778 } else { 1779 cs_dsp_warn(dsp, "Missing length info for region DM with ID %x\n", 1780 be32_to_cpu(adsp1_alg[i].alg.id)); 1781 } 1782 } 1783 1784 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP1_ZM, 1785 adsp1_alg[i].alg.id, 1786 adsp1_alg[i].alg.ver, 1787 adsp1_alg[i].zm); 1788 if (IS_ERR(alg_region)) { 1789 ret = PTR_ERR(alg_region); 1790 goto out; 1791 } 1792 if (dsp->fw_ver == 0) { 1793 if (i + 1 < n_algs) { 1794 len = be32_to_cpu(adsp1_alg[i + 1].zm); 1795 len -= be32_to_cpu(adsp1_alg[i].zm); 1796 len *= 4; 1797 cs_dsp_create_control(dsp, alg_region, 0, 1798 len, NULL, 0, 0, 1799 WMFW_CTL_TYPE_BYTES); 1800 } else { 1801 cs_dsp_warn(dsp, "Missing length info for region ZM with ID %x\n", 1802 be32_to_cpu(adsp1_alg[i].alg.id)); 1803 } 1804 } 1805 } 1806 1807 out: 1808 kfree(adsp1_alg); 1809 return ret; 1810 } 1811 1812 static int cs_dsp_adsp2_setup_algs(struct cs_dsp *dsp) 1813 { 1814 struct wmfw_adsp2_id_hdr adsp2_id; 1815 struct wmfw_adsp2_alg_hdr *adsp2_alg; 1816 struct cs_dsp_alg_region *alg_region; 1817 const struct cs_dsp_region *mem; 1818 unsigned int pos, len; 1819 size_t n_algs; 1820 int i, ret; 1821 1822 mem = cs_dsp_find_region(dsp, WMFW_ADSP2_XM); 1823 if (WARN_ON(!mem)) 1824 return -EINVAL; 1825 1826 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id, 1827 sizeof(adsp2_id)); 1828 if (ret != 0) { 1829 cs_dsp_err(dsp, "Failed to read algorithm info: %d\n", 1830 ret); 1831 return ret; 1832 } 1833 1834 n_algs = be32_to_cpu(adsp2_id.n_algs); 1835 1836 cs_dsp_parse_wmfw_id_header(dsp, &adsp2_id.fw, n_algs); 1837 1838 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_XM, 1839 adsp2_id.fw.id, adsp2_id.fw.ver, 1840 adsp2_id.xm); 1841 if (IS_ERR(alg_region)) 1842 return PTR_ERR(alg_region); 1843 1844 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_YM, 1845 adsp2_id.fw.id, adsp2_id.fw.ver, 1846 adsp2_id.ym); 1847 if (IS_ERR(alg_region)) 1848 return PTR_ERR(alg_region); 1849 1850 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_ZM, 1851 adsp2_id.fw.id, adsp2_id.fw.ver, 1852 adsp2_id.zm); 1853 if (IS_ERR(alg_region)) 1854 return PTR_ERR(alg_region); 1855 1856 /* Calculate offset and length in DSP words */ 1857 pos = sizeof(adsp2_id) / sizeof(u32); 1858 len = (sizeof(*adsp2_alg) * n_algs) / sizeof(u32); 1859 1860 adsp2_alg = cs_dsp_read_algs(dsp, n_algs, mem, pos, len); 1861 if (IS_ERR(adsp2_alg)) 1862 return PTR_ERR(adsp2_alg); 1863 1864 for (i = 0; i < n_algs; i++) { 1865 cs_dsp_info(dsp, 1866 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n", 1867 i, be32_to_cpu(adsp2_alg[i].alg.id), 1868 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16, 1869 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8, 1870 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff, 1871 be32_to_cpu(adsp2_alg[i].xm), 1872 be32_to_cpu(adsp2_alg[i].ym), 1873 be32_to_cpu(adsp2_alg[i].zm)); 1874 1875 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_XM, 1876 adsp2_alg[i].alg.id, 1877 adsp2_alg[i].alg.ver, 1878 adsp2_alg[i].xm); 1879 if (IS_ERR(alg_region)) { 1880 ret = PTR_ERR(alg_region); 1881 goto out; 1882 } 1883 if (dsp->fw_ver == 0) { 1884 if (i + 1 < n_algs) { 1885 len = be32_to_cpu(adsp2_alg[i + 1].xm); 1886 len -= be32_to_cpu(adsp2_alg[i].xm); 1887 len *= 4; 1888 cs_dsp_create_control(dsp, alg_region, 0, 1889 len, NULL, 0, 0, 1890 WMFW_CTL_TYPE_BYTES); 1891 } else { 1892 cs_dsp_warn(dsp, "Missing length info for region XM with ID %x\n", 1893 be32_to_cpu(adsp2_alg[i].alg.id)); 1894 } 1895 } 1896 1897 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_YM, 1898 adsp2_alg[i].alg.id, 1899 adsp2_alg[i].alg.ver, 1900 adsp2_alg[i].ym); 1901 if (IS_ERR(alg_region)) { 1902 ret = PTR_ERR(alg_region); 1903 goto out; 1904 } 1905 if (dsp->fw_ver == 0) { 1906 if (i + 1 < n_algs) { 1907 len = be32_to_cpu(adsp2_alg[i + 1].ym); 1908 len -= be32_to_cpu(adsp2_alg[i].ym); 1909 len *= 4; 1910 cs_dsp_create_control(dsp, alg_region, 0, 1911 len, NULL, 0, 0, 1912 WMFW_CTL_TYPE_BYTES); 1913 } else { 1914 cs_dsp_warn(dsp, "Missing length info for region YM with ID %x\n", 1915 be32_to_cpu(adsp2_alg[i].alg.id)); 1916 } 1917 } 1918 1919 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_ZM, 1920 adsp2_alg[i].alg.id, 1921 adsp2_alg[i].alg.ver, 1922 adsp2_alg[i].zm); 1923 if (IS_ERR(alg_region)) { 1924 ret = PTR_ERR(alg_region); 1925 goto out; 1926 } 1927 if (dsp->fw_ver == 0) { 1928 if (i + 1 < n_algs) { 1929 len = be32_to_cpu(adsp2_alg[i + 1].zm); 1930 len -= be32_to_cpu(adsp2_alg[i].zm); 1931 len *= 4; 1932 cs_dsp_create_control(dsp, alg_region, 0, 1933 len, NULL, 0, 0, 1934 WMFW_CTL_TYPE_BYTES); 1935 } else { 1936 cs_dsp_warn(dsp, "Missing length info for region ZM with ID %x\n", 1937 be32_to_cpu(adsp2_alg[i].alg.id)); 1938 } 1939 } 1940 } 1941 1942 out: 1943 kfree(adsp2_alg); 1944 return ret; 1945 } 1946 1947 static int cs_dsp_halo_create_regions(struct cs_dsp *dsp, __be32 id, __be32 ver, 1948 __be32 xm_base, __be32 ym_base) 1949 { 1950 static const int types[] = { 1951 WMFW_ADSP2_XM, WMFW_HALO_XM_PACKED, 1952 WMFW_ADSP2_YM, WMFW_HALO_YM_PACKED 1953 }; 1954 __be32 bases[] = { xm_base, xm_base, ym_base, ym_base }; 1955 1956 return cs_dsp_create_regions(dsp, id, ver, ARRAY_SIZE(types), types, bases); 1957 } 1958 1959 static int cs_dsp_halo_setup_algs(struct cs_dsp *dsp) 1960 { 1961 struct wmfw_halo_id_hdr halo_id; 1962 struct wmfw_halo_alg_hdr *halo_alg; 1963 const struct cs_dsp_region *mem; 1964 unsigned int pos, len; 1965 size_t n_algs; 1966 int i, ret; 1967 1968 mem = cs_dsp_find_region(dsp, WMFW_ADSP2_XM); 1969 if (WARN_ON(!mem)) 1970 return -EINVAL; 1971 1972 ret = regmap_raw_read(dsp->regmap, mem->base, &halo_id, 1973 sizeof(halo_id)); 1974 if (ret != 0) { 1975 cs_dsp_err(dsp, "Failed to read algorithm info: %d\n", 1976 ret); 1977 return ret; 1978 } 1979 1980 n_algs = be32_to_cpu(halo_id.n_algs); 1981 1982 cs_dsp_parse_wmfw_v3_id_header(dsp, &halo_id.fw, n_algs); 1983 1984 ret = cs_dsp_halo_create_regions(dsp, halo_id.fw.id, halo_id.fw.ver, 1985 halo_id.xm_base, halo_id.ym_base); 1986 if (ret) 1987 return ret; 1988 1989 /* Calculate offset and length in DSP words */ 1990 pos = sizeof(halo_id) / sizeof(u32); 1991 len = (sizeof(*halo_alg) * n_algs) / sizeof(u32); 1992 1993 halo_alg = cs_dsp_read_algs(dsp, n_algs, mem, pos, len); 1994 if (IS_ERR(halo_alg)) 1995 return PTR_ERR(halo_alg); 1996 1997 for (i = 0; i < n_algs; i++) { 1998 cs_dsp_info(dsp, 1999 "%d: ID %x v%d.%d.%d XM@%x YM@%x\n", 2000 i, be32_to_cpu(halo_alg[i].alg.id), 2001 (be32_to_cpu(halo_alg[i].alg.ver) & 0xff0000) >> 16, 2002 (be32_to_cpu(halo_alg[i].alg.ver) & 0xff00) >> 8, 2003 be32_to_cpu(halo_alg[i].alg.ver) & 0xff, 2004 be32_to_cpu(halo_alg[i].xm_base), 2005 be32_to_cpu(halo_alg[i].ym_base)); 2006 2007 ret = cs_dsp_halo_create_regions(dsp, halo_alg[i].alg.id, 2008 halo_alg[i].alg.ver, 2009 halo_alg[i].xm_base, 2010 halo_alg[i].ym_base); 2011 if (ret) 2012 goto out; 2013 } 2014 2015 out: 2016 kfree(halo_alg); 2017 return ret; 2018 } 2019 2020 static int cs_dsp_load_coeff(struct cs_dsp *dsp, const struct firmware *firmware, 2021 const char *file) 2022 { 2023 LIST_HEAD(buf_list); 2024 struct regmap *regmap = dsp->regmap; 2025 struct wmfw_coeff_hdr *hdr; 2026 struct wmfw_coeff_item *blk; 2027 const struct cs_dsp_region *mem; 2028 struct cs_dsp_alg_region *alg_region; 2029 const char *region_name; 2030 int ret, pos, blocks, type, offset, reg, version; 2031 char *text = NULL; 2032 struct cs_dsp_buf *buf; 2033 2034 if (!firmware) 2035 return 0; 2036 2037 ret = -EINVAL; 2038 2039 if (sizeof(*hdr) >= firmware->size) { 2040 cs_dsp_err(dsp, "%s: coefficient file too short, %zu bytes\n", 2041 file, firmware->size); 2042 goto out_fw; 2043 } 2044 2045 hdr = (void *)&firmware->data[0]; 2046 if (memcmp(hdr->magic, "WMDR", 4) != 0) { 2047 cs_dsp_err(dsp, "%s: invalid coefficient magic\n", file); 2048 goto out_fw; 2049 } 2050 2051 switch (be32_to_cpu(hdr->rev) & 0xff) { 2052 case 1: 2053 case 2: 2054 break; 2055 default: 2056 cs_dsp_err(dsp, "%s: Unsupported coefficient file format %d\n", 2057 file, be32_to_cpu(hdr->rev) & 0xff); 2058 ret = -EINVAL; 2059 goto out_fw; 2060 } 2061 2062 cs_dsp_info(dsp, "%s: v%d.%d.%d\n", file, 2063 (le32_to_cpu(hdr->ver) >> 16) & 0xff, 2064 (le32_to_cpu(hdr->ver) >> 8) & 0xff, 2065 le32_to_cpu(hdr->ver) & 0xff); 2066 2067 pos = le32_to_cpu(hdr->len); 2068 2069 blocks = 0; 2070 while (pos < firmware->size && 2071 sizeof(*blk) < firmware->size - pos) { 2072 blk = (void *)(&firmware->data[pos]); 2073 2074 type = le16_to_cpu(blk->type); 2075 offset = le16_to_cpu(blk->offset); 2076 version = le32_to_cpu(blk->ver) >> 8; 2077 2078 cs_dsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n", 2079 file, blocks, le32_to_cpu(blk->id), 2080 (le32_to_cpu(blk->ver) >> 16) & 0xff, 2081 (le32_to_cpu(blk->ver) >> 8) & 0xff, 2082 le32_to_cpu(blk->ver) & 0xff); 2083 cs_dsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n", 2084 file, blocks, le32_to_cpu(blk->len), offset, type); 2085 2086 reg = 0; 2087 region_name = "Unknown"; 2088 switch (type) { 2089 case (WMFW_NAME_TEXT << 8): 2090 text = kzalloc(le32_to_cpu(blk->len) + 1, GFP_KERNEL); 2091 break; 2092 case (WMFW_INFO_TEXT << 8): 2093 case (WMFW_METADATA << 8): 2094 break; 2095 case (WMFW_ABSOLUTE << 8): 2096 /* 2097 * Old files may use this for global 2098 * coefficients. 2099 */ 2100 if (le32_to_cpu(blk->id) == dsp->fw_id && 2101 offset == 0) { 2102 region_name = "global coefficients"; 2103 mem = cs_dsp_find_region(dsp, type); 2104 if (!mem) { 2105 cs_dsp_err(dsp, "No ZM\n"); 2106 break; 2107 } 2108 reg = dsp->ops->region_to_reg(mem, 0); 2109 2110 } else { 2111 region_name = "register"; 2112 reg = offset; 2113 } 2114 break; 2115 2116 case WMFW_ADSP1_DM: 2117 case WMFW_ADSP1_ZM: 2118 case WMFW_ADSP2_XM: 2119 case WMFW_ADSP2_YM: 2120 case WMFW_HALO_XM_PACKED: 2121 case WMFW_HALO_YM_PACKED: 2122 case WMFW_HALO_PM_PACKED: 2123 cs_dsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n", 2124 file, blocks, le32_to_cpu(blk->len), 2125 type, le32_to_cpu(blk->id)); 2126 2127 region_name = cs_dsp_mem_region_name(type); 2128 mem = cs_dsp_find_region(dsp, type); 2129 if (!mem) { 2130 cs_dsp_err(dsp, "No base for region %x\n", type); 2131 break; 2132 } 2133 2134 alg_region = cs_dsp_find_alg_region(dsp, type, 2135 le32_to_cpu(blk->id)); 2136 if (alg_region) { 2137 if (version != alg_region->ver) 2138 cs_dsp_warn(dsp, 2139 "Algorithm coefficient version %d.%d.%d but expected %d.%d.%d\n", 2140 (version >> 16) & 0xFF, 2141 (version >> 8) & 0xFF, 2142 version & 0xFF, 2143 (alg_region->ver >> 16) & 0xFF, 2144 (alg_region->ver >> 8) & 0xFF, 2145 alg_region->ver & 0xFF); 2146 2147 reg = alg_region->base; 2148 reg = dsp->ops->region_to_reg(mem, reg); 2149 reg += offset; 2150 } else { 2151 cs_dsp_err(dsp, "No %s for algorithm %x\n", 2152 region_name, le32_to_cpu(blk->id)); 2153 } 2154 break; 2155 2156 default: 2157 cs_dsp_err(dsp, "%s.%d: Unknown region type %x at %d\n", 2158 file, blocks, type, pos); 2159 break; 2160 } 2161 2162 if (text) { 2163 memcpy(text, blk->data, le32_to_cpu(blk->len)); 2164 cs_dsp_info(dsp, "%s: %s\n", dsp->fw_name, text); 2165 kfree(text); 2166 text = NULL; 2167 } 2168 2169 if (reg) { 2170 if (le32_to_cpu(blk->len) > 2171 firmware->size - pos - sizeof(*blk)) { 2172 cs_dsp_err(dsp, 2173 "%s.%d: %s region len %d bytes exceeds file length %zu\n", 2174 file, blocks, region_name, 2175 le32_to_cpu(blk->len), 2176 firmware->size); 2177 ret = -EINVAL; 2178 goto out_fw; 2179 } 2180 2181 buf = cs_dsp_buf_alloc(blk->data, 2182 le32_to_cpu(blk->len), 2183 &buf_list); 2184 if (!buf) { 2185 cs_dsp_err(dsp, "Out of memory\n"); 2186 ret = -ENOMEM; 2187 goto out_fw; 2188 } 2189 2190 cs_dsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n", 2191 file, blocks, le32_to_cpu(blk->len), 2192 reg); 2193 ret = regmap_raw_write_async(regmap, reg, buf->buf, 2194 le32_to_cpu(blk->len)); 2195 if (ret != 0) { 2196 cs_dsp_err(dsp, 2197 "%s.%d: Failed to write to %x in %s: %d\n", 2198 file, blocks, reg, region_name, ret); 2199 } 2200 } 2201 2202 pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03; 2203 blocks++; 2204 } 2205 2206 ret = regmap_async_complete(regmap); 2207 if (ret != 0) 2208 cs_dsp_err(dsp, "Failed to complete async write: %d\n", ret); 2209 2210 if (pos > firmware->size) 2211 cs_dsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", 2212 file, blocks, pos - firmware->size); 2213 2214 cs_dsp_debugfs_save_binname(dsp, file); 2215 2216 out_fw: 2217 regmap_async_complete(regmap); 2218 cs_dsp_buf_free(&buf_list); 2219 kfree(text); 2220 return ret; 2221 } 2222 2223 static int cs_dsp_create_name(struct cs_dsp *dsp) 2224 { 2225 if (!dsp->name) { 2226 dsp->name = devm_kasprintf(dsp->dev, GFP_KERNEL, "DSP%d", 2227 dsp->num); 2228 if (!dsp->name) 2229 return -ENOMEM; 2230 } 2231 2232 return 0; 2233 } 2234 2235 static int cs_dsp_common_init(struct cs_dsp *dsp) 2236 { 2237 int ret; 2238 2239 ret = cs_dsp_create_name(dsp); 2240 if (ret) 2241 return ret; 2242 2243 INIT_LIST_HEAD(&dsp->alg_regions); 2244 INIT_LIST_HEAD(&dsp->ctl_list); 2245 2246 mutex_init(&dsp->pwr_lock); 2247 2248 return 0; 2249 } 2250 2251 /** 2252 * cs_dsp_adsp1_init() - Initialise a cs_dsp structure representing a ADSP1 device 2253 * @dsp: pointer to DSP structure 2254 * 2255 * Return: Zero for success, a negative number on error. 2256 */ 2257 int cs_dsp_adsp1_init(struct cs_dsp *dsp) 2258 { 2259 dsp->ops = &cs_dsp_adsp1_ops; 2260 2261 return cs_dsp_common_init(dsp); 2262 } 2263 EXPORT_SYMBOL_NS_GPL(cs_dsp_adsp1_init, FW_CS_DSP); 2264 2265 /** 2266 * cs_dsp_adsp1_power_up() - Load and start the named firmware 2267 * @dsp: pointer to DSP structure 2268 * @wmfw_firmware: the firmware to be sent 2269 * @wmfw_filename: file name of firmware to be sent 2270 * @coeff_firmware: the coefficient data to be sent 2271 * @coeff_filename: file name of coefficient to data be sent 2272 * @fw_name: the user-friendly firmware name 2273 * 2274 * Return: Zero for success, a negative number on error. 2275 */ 2276 int cs_dsp_adsp1_power_up(struct cs_dsp *dsp, 2277 const struct firmware *wmfw_firmware, char *wmfw_filename, 2278 const struct firmware *coeff_firmware, char *coeff_filename, 2279 const char *fw_name) 2280 { 2281 unsigned int val; 2282 int ret; 2283 2284 mutex_lock(&dsp->pwr_lock); 2285 2286 dsp->fw_name = fw_name; 2287 2288 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, 2289 ADSP1_SYS_ENA, ADSP1_SYS_ENA); 2290 2291 /* 2292 * For simplicity set the DSP clock rate to be the 2293 * SYSCLK rate rather than making it configurable. 2294 */ 2295 if (dsp->sysclk_reg) { 2296 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val); 2297 if (ret != 0) { 2298 cs_dsp_err(dsp, "Failed to read SYSCLK state: %d\n", ret); 2299 goto err_mutex; 2300 } 2301 2302 val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift; 2303 2304 ret = regmap_update_bits(dsp->regmap, 2305 dsp->base + ADSP1_CONTROL_31, 2306 ADSP1_CLK_SEL_MASK, val); 2307 if (ret != 0) { 2308 cs_dsp_err(dsp, "Failed to set clock rate: %d\n", ret); 2309 goto err_mutex; 2310 } 2311 } 2312 2313 ret = cs_dsp_load(dsp, wmfw_firmware, wmfw_filename); 2314 if (ret != 0) 2315 goto err_ena; 2316 2317 ret = cs_dsp_adsp1_setup_algs(dsp); 2318 if (ret != 0) 2319 goto err_ena; 2320 2321 ret = cs_dsp_load_coeff(dsp, coeff_firmware, coeff_filename); 2322 if (ret != 0) 2323 goto err_ena; 2324 2325 /* Initialize caches for enabled and unset controls */ 2326 ret = cs_dsp_coeff_init_control_caches(dsp); 2327 if (ret != 0) 2328 goto err_ena; 2329 2330 /* Sync set controls */ 2331 ret = cs_dsp_coeff_sync_controls(dsp); 2332 if (ret != 0) 2333 goto err_ena; 2334 2335 dsp->booted = true; 2336 2337 /* Start the core running */ 2338 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, 2339 ADSP1_CORE_ENA | ADSP1_START, 2340 ADSP1_CORE_ENA | ADSP1_START); 2341 2342 dsp->running = true; 2343 2344 mutex_unlock(&dsp->pwr_lock); 2345 2346 return 0; 2347 2348 err_ena: 2349 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, 2350 ADSP1_SYS_ENA, 0); 2351 err_mutex: 2352 mutex_unlock(&dsp->pwr_lock); 2353 return ret; 2354 } 2355 EXPORT_SYMBOL_NS_GPL(cs_dsp_adsp1_power_up, FW_CS_DSP); 2356 2357 /** 2358 * cs_dsp_adsp1_power_down() - Halts the DSP 2359 * @dsp: pointer to DSP structure 2360 */ 2361 void cs_dsp_adsp1_power_down(struct cs_dsp *dsp) 2362 { 2363 struct cs_dsp_coeff_ctl *ctl; 2364 2365 mutex_lock(&dsp->pwr_lock); 2366 2367 dsp->running = false; 2368 dsp->booted = false; 2369 2370 /* Halt the core */ 2371 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, 2372 ADSP1_CORE_ENA | ADSP1_START, 0); 2373 2374 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19, 2375 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0); 2376 2377 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, 2378 ADSP1_SYS_ENA, 0); 2379 2380 list_for_each_entry(ctl, &dsp->ctl_list, list) 2381 ctl->enabled = 0; 2382 2383 cs_dsp_free_alg_regions(dsp); 2384 2385 mutex_unlock(&dsp->pwr_lock); 2386 } 2387 EXPORT_SYMBOL_NS_GPL(cs_dsp_adsp1_power_down, FW_CS_DSP); 2388 2389 static int cs_dsp_adsp2v2_enable_core(struct cs_dsp *dsp) 2390 { 2391 unsigned int val; 2392 int ret, count; 2393 2394 /* Wait for the RAM to start, should be near instantaneous */ 2395 for (count = 0; count < 10; ++count) { 2396 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val); 2397 if (ret != 0) 2398 return ret; 2399 2400 if (val & ADSP2_RAM_RDY) 2401 break; 2402 2403 usleep_range(250, 500); 2404 } 2405 2406 if (!(val & ADSP2_RAM_RDY)) { 2407 cs_dsp_err(dsp, "Failed to start DSP RAM\n"); 2408 return -EBUSY; 2409 } 2410 2411 cs_dsp_dbg(dsp, "RAM ready after %d polls\n", count); 2412 2413 return 0; 2414 } 2415 2416 static int cs_dsp_adsp2_enable_core(struct cs_dsp *dsp) 2417 { 2418 int ret; 2419 2420 ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL, 2421 ADSP2_SYS_ENA, ADSP2_SYS_ENA); 2422 if (ret != 0) 2423 return ret; 2424 2425 return cs_dsp_adsp2v2_enable_core(dsp); 2426 } 2427 2428 static int cs_dsp_adsp2_lock(struct cs_dsp *dsp, unsigned int lock_regions) 2429 { 2430 struct regmap *regmap = dsp->regmap; 2431 unsigned int code0, code1, lock_reg; 2432 2433 if (!(lock_regions & CS_ADSP2_REGION_ALL)) 2434 return 0; 2435 2436 lock_regions &= CS_ADSP2_REGION_ALL; 2437 lock_reg = dsp->base + ADSP2_LOCK_REGION_1_LOCK_REGION_0; 2438 2439 while (lock_regions) { 2440 code0 = code1 = 0; 2441 if (lock_regions & BIT(0)) { 2442 code0 = ADSP2_LOCK_CODE_0; 2443 code1 = ADSP2_LOCK_CODE_1; 2444 } 2445 if (lock_regions & BIT(1)) { 2446 code0 |= ADSP2_LOCK_CODE_0 << ADSP2_LOCK_REGION_SHIFT; 2447 code1 |= ADSP2_LOCK_CODE_1 << ADSP2_LOCK_REGION_SHIFT; 2448 } 2449 regmap_write(regmap, lock_reg, code0); 2450 regmap_write(regmap, lock_reg, code1); 2451 lock_regions >>= 2; 2452 lock_reg += 2; 2453 } 2454 2455 return 0; 2456 } 2457 2458 static int cs_dsp_adsp2_enable_memory(struct cs_dsp *dsp) 2459 { 2460 return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, 2461 ADSP2_MEM_ENA, ADSP2_MEM_ENA); 2462 } 2463 2464 static void cs_dsp_adsp2_disable_memory(struct cs_dsp *dsp) 2465 { 2466 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, 2467 ADSP2_MEM_ENA, 0); 2468 } 2469 2470 static void cs_dsp_adsp2_disable_core(struct cs_dsp *dsp) 2471 { 2472 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0); 2473 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0); 2474 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0); 2475 2476 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, 2477 ADSP2_SYS_ENA, 0); 2478 } 2479 2480 static void cs_dsp_adsp2v2_disable_core(struct cs_dsp *dsp) 2481 { 2482 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0); 2483 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0); 2484 regmap_write(dsp->regmap, dsp->base + ADSP2V2_WDMA_CONFIG_2, 0); 2485 } 2486 2487 static int cs_dsp_halo_configure_mpu(struct cs_dsp *dsp, unsigned int lock_regions) 2488 { 2489 struct reg_sequence config[] = { 2490 { dsp->base + HALO_MPU_LOCK_CONFIG, 0x5555 }, 2491 { dsp->base + HALO_MPU_LOCK_CONFIG, 0xAAAA }, 2492 { dsp->base + HALO_MPU_XMEM_ACCESS_0, 0xFFFFFFFF }, 2493 { dsp->base + HALO_MPU_YMEM_ACCESS_0, 0xFFFFFFFF }, 2494 { dsp->base + HALO_MPU_WINDOW_ACCESS_0, lock_regions }, 2495 { dsp->base + HALO_MPU_XREG_ACCESS_0, lock_regions }, 2496 { dsp->base + HALO_MPU_YREG_ACCESS_0, lock_regions }, 2497 { dsp->base + HALO_MPU_XMEM_ACCESS_1, 0xFFFFFFFF }, 2498 { dsp->base + HALO_MPU_YMEM_ACCESS_1, 0xFFFFFFFF }, 2499 { dsp->base + HALO_MPU_WINDOW_ACCESS_1, lock_regions }, 2500 { dsp->base + HALO_MPU_XREG_ACCESS_1, lock_regions }, 2501 { dsp->base + HALO_MPU_YREG_ACCESS_1, lock_regions }, 2502 { dsp->base + HALO_MPU_XMEM_ACCESS_2, 0xFFFFFFFF }, 2503 { dsp->base + HALO_MPU_YMEM_ACCESS_2, 0xFFFFFFFF }, 2504 { dsp->base + HALO_MPU_WINDOW_ACCESS_2, lock_regions }, 2505 { dsp->base + HALO_MPU_XREG_ACCESS_2, lock_regions }, 2506 { dsp->base + HALO_MPU_YREG_ACCESS_2, lock_regions }, 2507 { dsp->base + HALO_MPU_XMEM_ACCESS_3, 0xFFFFFFFF }, 2508 { dsp->base + HALO_MPU_YMEM_ACCESS_3, 0xFFFFFFFF }, 2509 { dsp->base + HALO_MPU_WINDOW_ACCESS_3, lock_regions }, 2510 { dsp->base + HALO_MPU_XREG_ACCESS_3, lock_regions }, 2511 { dsp->base + HALO_MPU_YREG_ACCESS_3, lock_regions }, 2512 { dsp->base + HALO_MPU_LOCK_CONFIG, 0 }, 2513 }; 2514 2515 return regmap_multi_reg_write(dsp->regmap, config, ARRAY_SIZE(config)); 2516 } 2517 2518 /** 2519 * cs_dsp_set_dspclk() - Applies the given frequency to the given cs_dsp 2520 * @dsp: pointer to DSP structure 2521 * @freq: clock rate to set 2522 * 2523 * This is only for use on ADSP2 cores. 2524 * 2525 * Return: Zero for success, a negative number on error. 2526 */ 2527 int cs_dsp_set_dspclk(struct cs_dsp *dsp, unsigned int freq) 2528 { 2529 int ret; 2530 2531 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CLOCKING, 2532 ADSP2_CLK_SEL_MASK, 2533 freq << ADSP2_CLK_SEL_SHIFT); 2534 if (ret) 2535 cs_dsp_err(dsp, "Failed to set clock rate: %d\n", ret); 2536 2537 return ret; 2538 } 2539 EXPORT_SYMBOL_NS_GPL(cs_dsp_set_dspclk, FW_CS_DSP); 2540 2541 static void cs_dsp_stop_watchdog(struct cs_dsp *dsp) 2542 { 2543 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_WATCHDOG, 2544 ADSP2_WDT_ENA_MASK, 0); 2545 } 2546 2547 static void cs_dsp_halo_stop_watchdog(struct cs_dsp *dsp) 2548 { 2549 regmap_update_bits(dsp->regmap, dsp->base + HALO_WDT_CONTROL, 2550 HALO_WDT_EN_MASK, 0); 2551 } 2552 2553 /** 2554 * cs_dsp_power_up() - Downloads firmware to the DSP 2555 * @dsp: pointer to DSP structure 2556 * @wmfw_firmware: the firmware to be sent 2557 * @wmfw_filename: file name of firmware to be sent 2558 * @coeff_firmware: the coefficient data to be sent 2559 * @coeff_filename: file name of coefficient to data be sent 2560 * @fw_name: the user-friendly firmware name 2561 * 2562 * This function is used on ADSP2 and Halo DSP cores, it powers-up the DSP core 2563 * and downloads the firmware but does not start the firmware running. The 2564 * cs_dsp booted flag will be set once completed and if the core has a low-power 2565 * memory retention mode it will be put into this state after the firmware is 2566 * downloaded. 2567 * 2568 * Return: Zero for success, a negative number on error. 2569 */ 2570 int cs_dsp_power_up(struct cs_dsp *dsp, 2571 const struct firmware *wmfw_firmware, char *wmfw_filename, 2572 const struct firmware *coeff_firmware, char *coeff_filename, 2573 const char *fw_name) 2574 { 2575 int ret; 2576 2577 mutex_lock(&dsp->pwr_lock); 2578 2579 dsp->fw_name = fw_name; 2580 2581 if (dsp->ops->enable_memory) { 2582 ret = dsp->ops->enable_memory(dsp); 2583 if (ret != 0) 2584 goto err_mutex; 2585 } 2586 2587 if (dsp->ops->enable_core) { 2588 ret = dsp->ops->enable_core(dsp); 2589 if (ret != 0) 2590 goto err_mem; 2591 } 2592 2593 ret = cs_dsp_load(dsp, wmfw_firmware, wmfw_filename); 2594 if (ret != 0) 2595 goto err_ena; 2596 2597 ret = dsp->ops->setup_algs(dsp); 2598 if (ret != 0) 2599 goto err_ena; 2600 2601 ret = cs_dsp_load_coeff(dsp, coeff_firmware, coeff_filename); 2602 if (ret != 0) 2603 goto err_ena; 2604 2605 /* Initialize caches for enabled and unset controls */ 2606 ret = cs_dsp_coeff_init_control_caches(dsp); 2607 if (ret != 0) 2608 goto err_ena; 2609 2610 if (dsp->ops->disable_core) 2611 dsp->ops->disable_core(dsp); 2612 2613 dsp->booted = true; 2614 2615 mutex_unlock(&dsp->pwr_lock); 2616 2617 return 0; 2618 err_ena: 2619 if (dsp->ops->disable_core) 2620 dsp->ops->disable_core(dsp); 2621 err_mem: 2622 if (dsp->ops->disable_memory) 2623 dsp->ops->disable_memory(dsp); 2624 err_mutex: 2625 mutex_unlock(&dsp->pwr_lock); 2626 2627 return ret; 2628 } 2629 EXPORT_SYMBOL_NS_GPL(cs_dsp_power_up, FW_CS_DSP); 2630 2631 /** 2632 * cs_dsp_power_down() - Powers-down the DSP 2633 * @dsp: pointer to DSP structure 2634 * 2635 * cs_dsp_stop() must have been called before this function. The core will be 2636 * fully powered down and so the memory will not be retained. 2637 */ 2638 void cs_dsp_power_down(struct cs_dsp *dsp) 2639 { 2640 struct cs_dsp_coeff_ctl *ctl; 2641 2642 mutex_lock(&dsp->pwr_lock); 2643 2644 cs_dsp_debugfs_clear(dsp); 2645 2646 dsp->fw_id = 0; 2647 dsp->fw_id_version = 0; 2648 2649 dsp->booted = false; 2650 2651 if (dsp->ops->disable_memory) 2652 dsp->ops->disable_memory(dsp); 2653 2654 list_for_each_entry(ctl, &dsp->ctl_list, list) 2655 ctl->enabled = 0; 2656 2657 cs_dsp_free_alg_regions(dsp); 2658 2659 mutex_unlock(&dsp->pwr_lock); 2660 2661 cs_dsp_dbg(dsp, "Shutdown complete\n"); 2662 } 2663 EXPORT_SYMBOL_NS_GPL(cs_dsp_power_down, FW_CS_DSP); 2664 2665 static int cs_dsp_adsp2_start_core(struct cs_dsp *dsp) 2666 { 2667 return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, 2668 ADSP2_CORE_ENA | ADSP2_START, 2669 ADSP2_CORE_ENA | ADSP2_START); 2670 } 2671 2672 static void cs_dsp_adsp2_stop_core(struct cs_dsp *dsp) 2673 { 2674 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, 2675 ADSP2_CORE_ENA | ADSP2_START, 0); 2676 } 2677 2678 /** 2679 * cs_dsp_run() - Starts the firmware running 2680 * @dsp: pointer to DSP structure 2681 * 2682 * cs_dsp_power_up() must have previously been called successfully. 2683 * 2684 * Return: Zero for success, a negative number on error. 2685 */ 2686 int cs_dsp_run(struct cs_dsp *dsp) 2687 { 2688 int ret; 2689 2690 mutex_lock(&dsp->pwr_lock); 2691 2692 if (!dsp->booted) { 2693 ret = -EIO; 2694 goto err; 2695 } 2696 2697 if (dsp->ops->enable_core) { 2698 ret = dsp->ops->enable_core(dsp); 2699 if (ret != 0) 2700 goto err; 2701 } 2702 2703 if (dsp->client_ops->pre_run) { 2704 ret = dsp->client_ops->pre_run(dsp); 2705 if (ret) 2706 goto err; 2707 } 2708 2709 /* Sync set controls */ 2710 ret = cs_dsp_coeff_sync_controls(dsp); 2711 if (ret != 0) 2712 goto err; 2713 2714 if (dsp->ops->lock_memory) { 2715 ret = dsp->ops->lock_memory(dsp, dsp->lock_regions); 2716 if (ret != 0) { 2717 cs_dsp_err(dsp, "Error configuring MPU: %d\n", ret); 2718 goto err; 2719 } 2720 } 2721 2722 if (dsp->ops->start_core) { 2723 ret = dsp->ops->start_core(dsp); 2724 if (ret != 0) 2725 goto err; 2726 } 2727 2728 dsp->running = true; 2729 2730 if (dsp->client_ops->post_run) { 2731 ret = dsp->client_ops->post_run(dsp); 2732 if (ret) 2733 goto err; 2734 } 2735 2736 mutex_unlock(&dsp->pwr_lock); 2737 2738 return 0; 2739 2740 err: 2741 if (dsp->ops->stop_core) 2742 dsp->ops->stop_core(dsp); 2743 if (dsp->ops->disable_core) 2744 dsp->ops->disable_core(dsp); 2745 mutex_unlock(&dsp->pwr_lock); 2746 2747 return ret; 2748 } 2749 EXPORT_SYMBOL_NS_GPL(cs_dsp_run, FW_CS_DSP); 2750 2751 /** 2752 * cs_dsp_stop() - Stops the firmware 2753 * @dsp: pointer to DSP structure 2754 * 2755 * Memory will not be disabled so firmware will remain loaded. 2756 */ 2757 void cs_dsp_stop(struct cs_dsp *dsp) 2758 { 2759 /* Tell the firmware to cleanup */ 2760 cs_dsp_signal_event_controls(dsp, CS_DSP_FW_EVENT_SHUTDOWN); 2761 2762 if (dsp->ops->stop_watchdog) 2763 dsp->ops->stop_watchdog(dsp); 2764 2765 /* Log firmware state, it can be useful for analysis */ 2766 if (dsp->ops->show_fw_status) 2767 dsp->ops->show_fw_status(dsp); 2768 2769 mutex_lock(&dsp->pwr_lock); 2770 2771 if (dsp->client_ops->pre_stop) 2772 dsp->client_ops->pre_stop(dsp); 2773 2774 dsp->running = false; 2775 2776 if (dsp->ops->stop_core) 2777 dsp->ops->stop_core(dsp); 2778 if (dsp->ops->disable_core) 2779 dsp->ops->disable_core(dsp); 2780 2781 if (dsp->client_ops->post_stop) 2782 dsp->client_ops->post_stop(dsp); 2783 2784 mutex_unlock(&dsp->pwr_lock); 2785 2786 cs_dsp_dbg(dsp, "Execution stopped\n"); 2787 } 2788 EXPORT_SYMBOL_NS_GPL(cs_dsp_stop, FW_CS_DSP); 2789 2790 static int cs_dsp_halo_start_core(struct cs_dsp *dsp) 2791 { 2792 int ret; 2793 2794 ret = regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL, 2795 HALO_CORE_RESET | HALO_CORE_EN, 2796 HALO_CORE_RESET | HALO_CORE_EN); 2797 if (ret) 2798 return ret; 2799 2800 return regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL, 2801 HALO_CORE_RESET, 0); 2802 } 2803 2804 static void cs_dsp_halo_stop_core(struct cs_dsp *dsp) 2805 { 2806 regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL, 2807 HALO_CORE_EN, 0); 2808 2809 /* reset halo core with CORE_SOFT_RESET */ 2810 regmap_update_bits(dsp->regmap, dsp->base + HALO_CORE_SOFT_RESET, 2811 HALO_CORE_SOFT_RESET_MASK, 1); 2812 } 2813 2814 /** 2815 * cs_dsp_adsp2_init() - Initialise a cs_dsp structure representing a ADSP2 core 2816 * @dsp: pointer to DSP structure 2817 * 2818 * Return: Zero for success, a negative number on error. 2819 */ 2820 int cs_dsp_adsp2_init(struct cs_dsp *dsp) 2821 { 2822 int ret; 2823 2824 switch (dsp->rev) { 2825 case 0: 2826 /* 2827 * Disable the DSP memory by default when in reset for a small 2828 * power saving. 2829 */ 2830 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, 2831 ADSP2_MEM_ENA, 0); 2832 if (ret) { 2833 cs_dsp_err(dsp, 2834 "Failed to clear memory retention: %d\n", ret); 2835 return ret; 2836 } 2837 2838 dsp->ops = &cs_dsp_adsp2_ops[0]; 2839 break; 2840 case 1: 2841 dsp->ops = &cs_dsp_adsp2_ops[1]; 2842 break; 2843 default: 2844 dsp->ops = &cs_dsp_adsp2_ops[2]; 2845 break; 2846 } 2847 2848 return cs_dsp_common_init(dsp); 2849 } 2850 EXPORT_SYMBOL_NS_GPL(cs_dsp_adsp2_init, FW_CS_DSP); 2851 2852 /** 2853 * cs_dsp_halo_init() - Initialise a cs_dsp structure representing a HALO Core DSP 2854 * @dsp: pointer to DSP structure 2855 * 2856 * Return: Zero for success, a negative number on error. 2857 */ 2858 int cs_dsp_halo_init(struct cs_dsp *dsp) 2859 { 2860 if (dsp->no_core_startstop) 2861 dsp->ops = &cs_dsp_halo_ao_ops; 2862 else 2863 dsp->ops = &cs_dsp_halo_ops; 2864 2865 return cs_dsp_common_init(dsp); 2866 } 2867 EXPORT_SYMBOL_NS_GPL(cs_dsp_halo_init, FW_CS_DSP); 2868 2869 /** 2870 * cs_dsp_remove() - Clean a cs_dsp before deletion 2871 * @dsp: pointer to DSP structure 2872 */ 2873 void cs_dsp_remove(struct cs_dsp *dsp) 2874 { 2875 struct cs_dsp_coeff_ctl *ctl; 2876 2877 while (!list_empty(&dsp->ctl_list)) { 2878 ctl = list_first_entry(&dsp->ctl_list, struct cs_dsp_coeff_ctl, list); 2879 2880 if (dsp->client_ops->control_remove) 2881 dsp->client_ops->control_remove(ctl); 2882 2883 list_del(&ctl->list); 2884 cs_dsp_free_ctl_blk(ctl); 2885 } 2886 } 2887 EXPORT_SYMBOL_NS_GPL(cs_dsp_remove, FW_CS_DSP); 2888 2889 /** 2890 * cs_dsp_read_raw_data_block() - Reads a block of data from DSP memory 2891 * @dsp: pointer to DSP structure 2892 * @mem_type: the type of DSP memory containing the data to be read 2893 * @mem_addr: the address of the data within the memory region 2894 * @num_words: the length of the data to read 2895 * @data: a buffer to store the fetched data 2896 * 2897 * If this is used to read unpacked 24-bit memory, each 24-bit DSP word will 2898 * occupy 32-bits in data (MSbyte will be 0). This padding can be removed using 2899 * cs_dsp_remove_padding() 2900 * 2901 * Return: Zero for success, a negative number on error. 2902 */ 2903 int cs_dsp_read_raw_data_block(struct cs_dsp *dsp, int mem_type, unsigned int mem_addr, 2904 unsigned int num_words, __be32 *data) 2905 { 2906 struct cs_dsp_region const *mem = cs_dsp_find_region(dsp, mem_type); 2907 unsigned int reg; 2908 int ret; 2909 2910 lockdep_assert_held(&dsp->pwr_lock); 2911 2912 if (!mem) 2913 return -EINVAL; 2914 2915 reg = dsp->ops->region_to_reg(mem, mem_addr); 2916 2917 ret = regmap_raw_read(dsp->regmap, reg, data, 2918 sizeof(*data) * num_words); 2919 if (ret < 0) 2920 return ret; 2921 2922 return 0; 2923 } 2924 EXPORT_SYMBOL_NS_GPL(cs_dsp_read_raw_data_block, FW_CS_DSP); 2925 2926 /** 2927 * cs_dsp_read_data_word() - Reads a word from DSP memory 2928 * @dsp: pointer to DSP structure 2929 * @mem_type: the type of DSP memory containing the data to be read 2930 * @mem_addr: the address of the data within the memory region 2931 * @data: a buffer to store the fetched data 2932 * 2933 * Return: Zero for success, a negative number on error. 2934 */ 2935 int cs_dsp_read_data_word(struct cs_dsp *dsp, int mem_type, unsigned int mem_addr, u32 *data) 2936 { 2937 __be32 raw; 2938 int ret; 2939 2940 ret = cs_dsp_read_raw_data_block(dsp, mem_type, mem_addr, 1, &raw); 2941 if (ret < 0) 2942 return ret; 2943 2944 *data = be32_to_cpu(raw) & 0x00ffffffu; 2945 2946 return 0; 2947 } 2948 EXPORT_SYMBOL_NS_GPL(cs_dsp_read_data_word, FW_CS_DSP); 2949 2950 /** 2951 * cs_dsp_write_data_word() - Writes a word to DSP memory 2952 * @dsp: pointer to DSP structure 2953 * @mem_type: the type of DSP memory containing the data to be written 2954 * @mem_addr: the address of the data within the memory region 2955 * @data: the data to be written 2956 * 2957 * Return: Zero for success, a negative number on error. 2958 */ 2959 int cs_dsp_write_data_word(struct cs_dsp *dsp, int mem_type, unsigned int mem_addr, u32 data) 2960 { 2961 struct cs_dsp_region const *mem = cs_dsp_find_region(dsp, mem_type); 2962 __be32 val = cpu_to_be32(data & 0x00ffffffu); 2963 unsigned int reg; 2964 2965 lockdep_assert_held(&dsp->pwr_lock); 2966 2967 if (!mem) 2968 return -EINVAL; 2969 2970 reg = dsp->ops->region_to_reg(mem, mem_addr); 2971 2972 return regmap_raw_write(dsp->regmap, reg, &val, sizeof(val)); 2973 } 2974 EXPORT_SYMBOL_NS_GPL(cs_dsp_write_data_word, FW_CS_DSP); 2975 2976 /** 2977 * cs_dsp_remove_padding() - Convert unpacked words to packed bytes 2978 * @buf: buffer containing DSP words read from DSP memory 2979 * @nwords: number of words to convert 2980 * 2981 * DSP words from the register map have pad bytes and the data bytes 2982 * are in swapped order. This swaps to the native endian order and 2983 * strips the pad bytes. 2984 */ 2985 void cs_dsp_remove_padding(u32 *buf, int nwords) 2986 { 2987 const __be32 *pack_in = (__be32 *)buf; 2988 u8 *pack_out = (u8 *)buf; 2989 int i; 2990 2991 for (i = 0; i < nwords; i++) { 2992 u32 word = be32_to_cpu(*pack_in++); 2993 *pack_out++ = (u8)word; 2994 *pack_out++ = (u8)(word >> 8); 2995 *pack_out++ = (u8)(word >> 16); 2996 } 2997 } 2998 EXPORT_SYMBOL_NS_GPL(cs_dsp_remove_padding, FW_CS_DSP); 2999 3000 /** 3001 * cs_dsp_adsp2_bus_error() - Handle a DSP bus error interrupt 3002 * @dsp: pointer to DSP structure 3003 * 3004 * The firmware and DSP state will be logged for future analysis. 3005 */ 3006 void cs_dsp_adsp2_bus_error(struct cs_dsp *dsp) 3007 { 3008 unsigned int val; 3009 struct regmap *regmap = dsp->regmap; 3010 int ret = 0; 3011 3012 mutex_lock(&dsp->pwr_lock); 3013 3014 ret = regmap_read(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, &val); 3015 if (ret) { 3016 cs_dsp_err(dsp, 3017 "Failed to read Region Lock Ctrl register: %d\n", ret); 3018 goto error; 3019 } 3020 3021 if (val & ADSP2_WDT_TIMEOUT_STS_MASK) { 3022 cs_dsp_err(dsp, "watchdog timeout error\n"); 3023 dsp->ops->stop_watchdog(dsp); 3024 if (dsp->client_ops->watchdog_expired) 3025 dsp->client_ops->watchdog_expired(dsp); 3026 } 3027 3028 if (val & (ADSP2_ADDR_ERR_MASK | ADSP2_REGION_LOCK_ERR_MASK)) { 3029 if (val & ADSP2_ADDR_ERR_MASK) 3030 cs_dsp_err(dsp, "bus error: address error\n"); 3031 else 3032 cs_dsp_err(dsp, "bus error: region lock error\n"); 3033 3034 ret = regmap_read(regmap, dsp->base + ADSP2_BUS_ERR_ADDR, &val); 3035 if (ret) { 3036 cs_dsp_err(dsp, 3037 "Failed to read Bus Err Addr register: %d\n", 3038 ret); 3039 goto error; 3040 } 3041 3042 cs_dsp_err(dsp, "bus error address = 0x%x\n", 3043 val & ADSP2_BUS_ERR_ADDR_MASK); 3044 3045 ret = regmap_read(regmap, 3046 dsp->base + ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR, 3047 &val); 3048 if (ret) { 3049 cs_dsp_err(dsp, 3050 "Failed to read Pmem Xmem Err Addr register: %d\n", 3051 ret); 3052 goto error; 3053 } 3054 3055 cs_dsp_err(dsp, "xmem error address = 0x%x\n", 3056 val & ADSP2_XMEM_ERR_ADDR_MASK); 3057 cs_dsp_err(dsp, "pmem error address = 0x%x\n", 3058 (val & ADSP2_PMEM_ERR_ADDR_MASK) >> 3059 ADSP2_PMEM_ERR_ADDR_SHIFT); 3060 } 3061 3062 regmap_update_bits(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, 3063 ADSP2_CTRL_ERR_EINT, ADSP2_CTRL_ERR_EINT); 3064 3065 error: 3066 mutex_unlock(&dsp->pwr_lock); 3067 } 3068 EXPORT_SYMBOL_NS_GPL(cs_dsp_adsp2_bus_error, FW_CS_DSP); 3069 3070 /** 3071 * cs_dsp_halo_bus_error() - Handle a DSP bus error interrupt 3072 * @dsp: pointer to DSP structure 3073 * 3074 * The firmware and DSP state will be logged for future analysis. 3075 */ 3076 void cs_dsp_halo_bus_error(struct cs_dsp *dsp) 3077 { 3078 struct regmap *regmap = dsp->regmap; 3079 unsigned int fault[6]; 3080 struct reg_sequence clear[] = { 3081 { dsp->base + HALO_MPU_XM_VIO_STATUS, 0x0 }, 3082 { dsp->base + HALO_MPU_YM_VIO_STATUS, 0x0 }, 3083 { dsp->base + HALO_MPU_PM_VIO_STATUS, 0x0 }, 3084 }; 3085 int ret; 3086 3087 mutex_lock(&dsp->pwr_lock); 3088 3089 ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_1, 3090 fault); 3091 if (ret) { 3092 cs_dsp_warn(dsp, "Failed to read AHB DEBUG_1: %d\n", ret); 3093 goto exit_unlock; 3094 } 3095 3096 cs_dsp_warn(dsp, "AHB: STATUS: 0x%x ADDR: 0x%x\n", 3097 *fault & HALO_AHBM_FLAGS_ERR_MASK, 3098 (*fault & HALO_AHBM_CORE_ERR_ADDR_MASK) >> 3099 HALO_AHBM_CORE_ERR_ADDR_SHIFT); 3100 3101 ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_0, 3102 fault); 3103 if (ret) { 3104 cs_dsp_warn(dsp, "Failed to read AHB DEBUG_0: %d\n", ret); 3105 goto exit_unlock; 3106 } 3107 3108 cs_dsp_warn(dsp, "AHB: SYS_ADDR: 0x%x\n", *fault); 3109 3110 ret = regmap_bulk_read(regmap, dsp->base + HALO_MPU_XM_VIO_ADDR, 3111 fault, ARRAY_SIZE(fault)); 3112 if (ret) { 3113 cs_dsp_warn(dsp, "Failed to read MPU fault info: %d\n", ret); 3114 goto exit_unlock; 3115 } 3116 3117 cs_dsp_warn(dsp, "XM: STATUS:0x%x ADDR:0x%x\n", fault[1], fault[0]); 3118 cs_dsp_warn(dsp, "YM: STATUS:0x%x ADDR:0x%x\n", fault[3], fault[2]); 3119 cs_dsp_warn(dsp, "PM: STATUS:0x%x ADDR:0x%x\n", fault[5], fault[4]); 3120 3121 ret = regmap_multi_reg_write(dsp->regmap, clear, ARRAY_SIZE(clear)); 3122 if (ret) 3123 cs_dsp_warn(dsp, "Failed to clear MPU status: %d\n", ret); 3124 3125 exit_unlock: 3126 mutex_unlock(&dsp->pwr_lock); 3127 } 3128 EXPORT_SYMBOL_NS_GPL(cs_dsp_halo_bus_error, FW_CS_DSP); 3129 3130 /** 3131 * cs_dsp_halo_wdt_expire() - Handle DSP watchdog expiry 3132 * @dsp: pointer to DSP structure 3133 * 3134 * This is logged for future analysis. 3135 */ 3136 void cs_dsp_halo_wdt_expire(struct cs_dsp *dsp) 3137 { 3138 mutex_lock(&dsp->pwr_lock); 3139 3140 cs_dsp_warn(dsp, "WDT Expiry Fault\n"); 3141 3142 dsp->ops->stop_watchdog(dsp); 3143 if (dsp->client_ops->watchdog_expired) 3144 dsp->client_ops->watchdog_expired(dsp); 3145 3146 mutex_unlock(&dsp->pwr_lock); 3147 } 3148 EXPORT_SYMBOL_NS_GPL(cs_dsp_halo_wdt_expire, FW_CS_DSP); 3149 3150 static const struct cs_dsp_ops cs_dsp_adsp1_ops = { 3151 .validate_version = cs_dsp_validate_version, 3152 .parse_sizes = cs_dsp_adsp1_parse_sizes, 3153 .region_to_reg = cs_dsp_region_to_reg, 3154 }; 3155 3156 static const struct cs_dsp_ops cs_dsp_adsp2_ops[] = { 3157 { 3158 .parse_sizes = cs_dsp_adsp2_parse_sizes, 3159 .validate_version = cs_dsp_validate_version, 3160 .setup_algs = cs_dsp_adsp2_setup_algs, 3161 .region_to_reg = cs_dsp_region_to_reg, 3162 3163 .show_fw_status = cs_dsp_adsp2_show_fw_status, 3164 3165 .enable_memory = cs_dsp_adsp2_enable_memory, 3166 .disable_memory = cs_dsp_adsp2_disable_memory, 3167 3168 .enable_core = cs_dsp_adsp2_enable_core, 3169 .disable_core = cs_dsp_adsp2_disable_core, 3170 3171 .start_core = cs_dsp_adsp2_start_core, 3172 .stop_core = cs_dsp_adsp2_stop_core, 3173 3174 }, 3175 { 3176 .parse_sizes = cs_dsp_adsp2_parse_sizes, 3177 .validate_version = cs_dsp_validate_version, 3178 .setup_algs = cs_dsp_adsp2_setup_algs, 3179 .region_to_reg = cs_dsp_region_to_reg, 3180 3181 .show_fw_status = cs_dsp_adsp2v2_show_fw_status, 3182 3183 .enable_memory = cs_dsp_adsp2_enable_memory, 3184 .disable_memory = cs_dsp_adsp2_disable_memory, 3185 .lock_memory = cs_dsp_adsp2_lock, 3186 3187 .enable_core = cs_dsp_adsp2v2_enable_core, 3188 .disable_core = cs_dsp_adsp2v2_disable_core, 3189 3190 .start_core = cs_dsp_adsp2_start_core, 3191 .stop_core = cs_dsp_adsp2_stop_core, 3192 }, 3193 { 3194 .parse_sizes = cs_dsp_adsp2_parse_sizes, 3195 .validate_version = cs_dsp_validate_version, 3196 .setup_algs = cs_dsp_adsp2_setup_algs, 3197 .region_to_reg = cs_dsp_region_to_reg, 3198 3199 .show_fw_status = cs_dsp_adsp2v2_show_fw_status, 3200 .stop_watchdog = cs_dsp_stop_watchdog, 3201 3202 .enable_memory = cs_dsp_adsp2_enable_memory, 3203 .disable_memory = cs_dsp_adsp2_disable_memory, 3204 .lock_memory = cs_dsp_adsp2_lock, 3205 3206 .enable_core = cs_dsp_adsp2v2_enable_core, 3207 .disable_core = cs_dsp_adsp2v2_disable_core, 3208 3209 .start_core = cs_dsp_adsp2_start_core, 3210 .stop_core = cs_dsp_adsp2_stop_core, 3211 }, 3212 }; 3213 3214 static const struct cs_dsp_ops cs_dsp_halo_ops = { 3215 .parse_sizes = cs_dsp_adsp2_parse_sizes, 3216 .validate_version = cs_dsp_halo_validate_version, 3217 .setup_algs = cs_dsp_halo_setup_algs, 3218 .region_to_reg = cs_dsp_halo_region_to_reg, 3219 3220 .show_fw_status = cs_dsp_halo_show_fw_status, 3221 .stop_watchdog = cs_dsp_halo_stop_watchdog, 3222 3223 .lock_memory = cs_dsp_halo_configure_mpu, 3224 3225 .start_core = cs_dsp_halo_start_core, 3226 .stop_core = cs_dsp_halo_stop_core, 3227 }; 3228 3229 static const struct cs_dsp_ops cs_dsp_halo_ao_ops = { 3230 .parse_sizes = cs_dsp_adsp2_parse_sizes, 3231 .validate_version = cs_dsp_halo_validate_version, 3232 .setup_algs = cs_dsp_halo_setup_algs, 3233 .region_to_reg = cs_dsp_halo_region_to_reg, 3234 .show_fw_status = cs_dsp_halo_show_fw_status, 3235 }; 3236 3237 /** 3238 * cs_dsp_chunk_write() - Format data to a DSP memory chunk 3239 * @ch: Pointer to the chunk structure 3240 * @nbits: Number of bits to write 3241 * @val: Value to write 3242 * 3243 * This function sequentially writes values into the format required for DSP 3244 * memory, it handles both inserting of the padding bytes and converting to 3245 * big endian. Note that data is only committed to the chunk when a whole DSP 3246 * words worth of data is available. 3247 * 3248 * Return: Zero for success, a negative number on error. 3249 */ 3250 int cs_dsp_chunk_write(struct cs_dsp_chunk *ch, int nbits, u32 val) 3251 { 3252 int nwrite, i; 3253 3254 nwrite = min(CS_DSP_DATA_WORD_BITS - ch->cachebits, nbits); 3255 3256 ch->cache <<= nwrite; 3257 ch->cache |= val >> (nbits - nwrite); 3258 ch->cachebits += nwrite; 3259 nbits -= nwrite; 3260 3261 if (ch->cachebits == CS_DSP_DATA_WORD_BITS) { 3262 if (cs_dsp_chunk_end(ch)) 3263 return -ENOSPC; 3264 3265 ch->cache &= 0xFFFFFF; 3266 for (i = 0; i < sizeof(ch->cache); i++, ch->cache <<= BITS_PER_BYTE) 3267 *ch->data++ = (ch->cache & 0xFF000000) >> CS_DSP_DATA_WORD_BITS; 3268 3269 ch->bytes += sizeof(ch->cache); 3270 ch->cachebits = 0; 3271 } 3272 3273 if (nbits) 3274 return cs_dsp_chunk_write(ch, nbits, val); 3275 3276 return 0; 3277 } 3278 EXPORT_SYMBOL_NS_GPL(cs_dsp_chunk_write, FW_CS_DSP); 3279 3280 /** 3281 * cs_dsp_chunk_flush() - Pad remaining data with zero and commit to chunk 3282 * @ch: Pointer to the chunk structure 3283 * 3284 * As cs_dsp_chunk_write only writes data when a whole DSP word is ready to 3285 * be written out it is possible that some data will remain in the cache, this 3286 * function will pad that data with zeros upto a whole DSP word and write out. 3287 * 3288 * Return: Zero for success, a negative number on error. 3289 */ 3290 int cs_dsp_chunk_flush(struct cs_dsp_chunk *ch) 3291 { 3292 if (!ch->cachebits) 3293 return 0; 3294 3295 return cs_dsp_chunk_write(ch, CS_DSP_DATA_WORD_BITS - ch->cachebits, 0); 3296 } 3297 EXPORT_SYMBOL_NS_GPL(cs_dsp_chunk_flush, FW_CS_DSP); 3298 3299 /** 3300 * cs_dsp_chunk_read() - Parse data from a DSP memory chunk 3301 * @ch: Pointer to the chunk structure 3302 * @nbits: Number of bits to read 3303 * 3304 * This function sequentially reads values from a DSP memory formatted buffer, 3305 * it handles both removing of the padding bytes and converting from big endian. 3306 * 3307 * Return: A negative number is returned on error, otherwise the read value. 3308 */ 3309 int cs_dsp_chunk_read(struct cs_dsp_chunk *ch, int nbits) 3310 { 3311 int nread, i; 3312 u32 result; 3313 3314 if (!ch->cachebits) { 3315 if (cs_dsp_chunk_end(ch)) 3316 return -ENOSPC; 3317 3318 ch->cache = 0; 3319 ch->cachebits = CS_DSP_DATA_WORD_BITS; 3320 3321 for (i = 0; i < sizeof(ch->cache); i++, ch->cache <<= BITS_PER_BYTE) 3322 ch->cache |= *ch->data++; 3323 3324 ch->bytes += sizeof(ch->cache); 3325 } 3326 3327 nread = min(ch->cachebits, nbits); 3328 nbits -= nread; 3329 3330 result = ch->cache >> ((sizeof(ch->cache) * BITS_PER_BYTE) - nread); 3331 ch->cache <<= nread; 3332 ch->cachebits -= nread; 3333 3334 if (nbits) 3335 result = (result << nbits) | cs_dsp_chunk_read(ch, nbits); 3336 3337 return result; 3338 } 3339 EXPORT_SYMBOL_NS_GPL(cs_dsp_chunk_read, FW_CS_DSP); 3340 3341 MODULE_DESCRIPTION("Cirrus Logic DSP Support"); 3342 MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>"); 3343 MODULE_LICENSE("GPL v2"); 3344