1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * System Control and Management Interface (SCMI) Performance Protocol 4 * 5 * Copyright (C) 2018 ARM Ltd. 6 */ 7 8 #include <linux/bits.h> 9 #include <linux/of.h> 10 #include <linux/io.h> 11 #include <linux/io-64-nonatomic-hi-lo.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_opp.h> 14 #include <linux/sort.h> 15 16 #include "common.h" 17 18 enum scmi_performance_protocol_cmd { 19 PERF_DOMAIN_ATTRIBUTES = 0x3, 20 PERF_DESCRIBE_LEVELS = 0x4, 21 PERF_LIMITS_SET = 0x5, 22 PERF_LIMITS_GET = 0x6, 23 PERF_LEVEL_SET = 0x7, 24 PERF_LEVEL_GET = 0x8, 25 PERF_NOTIFY_LIMITS = 0x9, 26 PERF_NOTIFY_LEVEL = 0xa, 27 PERF_DESCRIBE_FASTCHANNEL = 0xb, 28 }; 29 30 struct scmi_opp { 31 u32 perf; 32 u32 power; 33 u32 trans_latency_us; 34 }; 35 36 struct scmi_msg_resp_perf_attributes { 37 __le16 num_domains; 38 __le16 flags; 39 #define POWER_SCALE_IN_MILLIWATT(x) ((x) & BIT(0)) 40 __le32 stats_addr_low; 41 __le32 stats_addr_high; 42 __le32 stats_size; 43 }; 44 45 struct scmi_msg_resp_perf_domain_attributes { 46 __le32 flags; 47 #define SUPPORTS_SET_LIMITS(x) ((x) & BIT(31)) 48 #define SUPPORTS_SET_PERF_LVL(x) ((x) & BIT(30)) 49 #define SUPPORTS_PERF_LIMIT_NOTIFY(x) ((x) & BIT(29)) 50 #define SUPPORTS_PERF_LEVEL_NOTIFY(x) ((x) & BIT(28)) 51 #define SUPPORTS_PERF_FASTCHANNELS(x) ((x) & BIT(27)) 52 __le32 rate_limit_us; 53 __le32 sustained_freq_khz; 54 __le32 sustained_perf_level; 55 u8 name[SCMI_MAX_STR_SIZE]; 56 }; 57 58 struct scmi_msg_perf_describe_levels { 59 __le32 domain; 60 __le32 level_index; 61 }; 62 63 struct scmi_perf_set_limits { 64 __le32 domain; 65 __le32 max_level; 66 __le32 min_level; 67 }; 68 69 struct scmi_perf_get_limits { 70 __le32 max_level; 71 __le32 min_level; 72 }; 73 74 struct scmi_perf_set_level { 75 __le32 domain; 76 __le32 level; 77 }; 78 79 struct scmi_perf_notify_level_or_limits { 80 __le32 domain; 81 __le32 notify_enable; 82 }; 83 84 struct scmi_msg_resp_perf_describe_levels { 85 __le16 num_returned; 86 __le16 num_remaining; 87 struct { 88 __le32 perf_val; 89 __le32 power; 90 __le16 transition_latency_us; 91 __le16 reserved; 92 } opp[0]; 93 }; 94 95 struct scmi_perf_get_fc_info { 96 __le32 domain; 97 __le32 message_id; 98 }; 99 100 struct scmi_msg_resp_perf_desc_fc { 101 __le32 attr; 102 #define SUPPORTS_DOORBELL(x) ((x) & BIT(0)) 103 #define DOORBELL_REG_WIDTH(x) FIELD_GET(GENMASK(2, 1), (x)) 104 __le32 rate_limit; 105 __le32 chan_addr_low; 106 __le32 chan_addr_high; 107 __le32 chan_size; 108 __le32 db_addr_low; 109 __le32 db_addr_high; 110 __le32 db_set_lmask; 111 __le32 db_set_hmask; 112 __le32 db_preserve_lmask; 113 __le32 db_preserve_hmask; 114 }; 115 116 struct scmi_fc_db_info { 117 int width; 118 u64 set; 119 u64 mask; 120 void __iomem *addr; 121 }; 122 123 struct scmi_fc_info { 124 void __iomem *level_set_addr; 125 void __iomem *limit_set_addr; 126 void __iomem *level_get_addr; 127 void __iomem *limit_get_addr; 128 struct scmi_fc_db_info *level_set_db; 129 struct scmi_fc_db_info *limit_set_db; 130 }; 131 132 struct perf_dom_info { 133 bool set_limits; 134 bool set_perf; 135 bool perf_limit_notify; 136 bool perf_level_notify; 137 bool perf_fastchannels; 138 u32 opp_count; 139 u32 sustained_freq_khz; 140 u32 sustained_perf_level; 141 u32 mult_factor; 142 char name[SCMI_MAX_STR_SIZE]; 143 struct scmi_opp opp[MAX_OPPS]; 144 struct scmi_fc_info *fc_info; 145 }; 146 147 struct scmi_perf_info { 148 u32 version; 149 int num_domains; 150 bool power_scale_mw; 151 u64 stats_addr; 152 u32 stats_size; 153 struct perf_dom_info *dom_info; 154 }; 155 156 static int scmi_perf_attributes_get(const struct scmi_handle *handle, 157 struct scmi_perf_info *pi) 158 { 159 int ret; 160 struct scmi_xfer *t; 161 struct scmi_msg_resp_perf_attributes *attr; 162 163 ret = scmi_xfer_get_init(handle, PROTOCOL_ATTRIBUTES, 164 SCMI_PROTOCOL_PERF, 0, sizeof(*attr), &t); 165 if (ret) 166 return ret; 167 168 attr = t->rx.buf; 169 170 ret = scmi_do_xfer(handle, t); 171 if (!ret) { 172 u16 flags = le16_to_cpu(attr->flags); 173 174 pi->num_domains = le16_to_cpu(attr->num_domains); 175 pi->power_scale_mw = POWER_SCALE_IN_MILLIWATT(flags); 176 pi->stats_addr = le32_to_cpu(attr->stats_addr_low) | 177 (u64)le32_to_cpu(attr->stats_addr_high) << 32; 178 pi->stats_size = le32_to_cpu(attr->stats_size); 179 } 180 181 scmi_xfer_put(handle, t); 182 return ret; 183 } 184 185 static int 186 scmi_perf_domain_attributes_get(const struct scmi_handle *handle, u32 domain, 187 struct perf_dom_info *dom_info) 188 { 189 int ret; 190 struct scmi_xfer *t; 191 struct scmi_msg_resp_perf_domain_attributes *attr; 192 193 ret = scmi_xfer_get_init(handle, PERF_DOMAIN_ATTRIBUTES, 194 SCMI_PROTOCOL_PERF, sizeof(domain), 195 sizeof(*attr), &t); 196 if (ret) 197 return ret; 198 199 put_unaligned_le32(domain, t->tx.buf); 200 attr = t->rx.buf; 201 202 ret = scmi_do_xfer(handle, t); 203 if (!ret) { 204 u32 flags = le32_to_cpu(attr->flags); 205 206 dom_info->set_limits = SUPPORTS_SET_LIMITS(flags); 207 dom_info->set_perf = SUPPORTS_SET_PERF_LVL(flags); 208 dom_info->perf_limit_notify = SUPPORTS_PERF_LIMIT_NOTIFY(flags); 209 dom_info->perf_level_notify = SUPPORTS_PERF_LEVEL_NOTIFY(flags); 210 dom_info->perf_fastchannels = SUPPORTS_PERF_FASTCHANNELS(flags); 211 dom_info->sustained_freq_khz = 212 le32_to_cpu(attr->sustained_freq_khz); 213 dom_info->sustained_perf_level = 214 le32_to_cpu(attr->sustained_perf_level); 215 if (!dom_info->sustained_freq_khz || 216 !dom_info->sustained_perf_level) 217 /* CPUFreq converts to kHz, hence default 1000 */ 218 dom_info->mult_factor = 1000; 219 else 220 dom_info->mult_factor = 221 (dom_info->sustained_freq_khz * 1000) / 222 dom_info->sustained_perf_level; 223 strlcpy(dom_info->name, attr->name, SCMI_MAX_STR_SIZE); 224 } 225 226 scmi_xfer_put(handle, t); 227 return ret; 228 } 229 230 static int opp_cmp_func(const void *opp1, const void *opp2) 231 { 232 const struct scmi_opp *t1 = opp1, *t2 = opp2; 233 234 return t1->perf - t2->perf; 235 } 236 237 static int 238 scmi_perf_describe_levels_get(const struct scmi_handle *handle, u32 domain, 239 struct perf_dom_info *perf_dom) 240 { 241 int ret, cnt; 242 u32 tot_opp_cnt = 0; 243 u16 num_returned, num_remaining; 244 struct scmi_xfer *t; 245 struct scmi_opp *opp; 246 struct scmi_msg_perf_describe_levels *dom_info; 247 struct scmi_msg_resp_perf_describe_levels *level_info; 248 249 ret = scmi_xfer_get_init(handle, PERF_DESCRIBE_LEVELS, 250 SCMI_PROTOCOL_PERF, sizeof(*dom_info), 0, &t); 251 if (ret) 252 return ret; 253 254 dom_info = t->tx.buf; 255 level_info = t->rx.buf; 256 257 do { 258 dom_info->domain = cpu_to_le32(domain); 259 /* Set the number of OPPs to be skipped/already read */ 260 dom_info->level_index = cpu_to_le32(tot_opp_cnt); 261 262 ret = scmi_do_xfer(handle, t); 263 if (ret) 264 break; 265 266 num_returned = le16_to_cpu(level_info->num_returned); 267 num_remaining = le16_to_cpu(level_info->num_remaining); 268 if (tot_opp_cnt + num_returned > MAX_OPPS) { 269 dev_err(handle->dev, "No. of OPPs exceeded MAX_OPPS"); 270 break; 271 } 272 273 opp = &perf_dom->opp[tot_opp_cnt]; 274 for (cnt = 0; cnt < num_returned; cnt++, opp++) { 275 opp->perf = le32_to_cpu(level_info->opp[cnt].perf_val); 276 opp->power = le32_to_cpu(level_info->opp[cnt].power); 277 opp->trans_latency_us = le16_to_cpu 278 (level_info->opp[cnt].transition_latency_us); 279 280 dev_dbg(handle->dev, "Level %d Power %d Latency %dus\n", 281 opp->perf, opp->power, opp->trans_latency_us); 282 } 283 284 tot_opp_cnt += num_returned; 285 /* 286 * check for both returned and remaining to avoid infinite 287 * loop due to buggy firmware 288 */ 289 } while (num_returned && num_remaining); 290 291 perf_dom->opp_count = tot_opp_cnt; 292 scmi_xfer_put(handle, t); 293 294 sort(perf_dom->opp, tot_opp_cnt, sizeof(*opp), opp_cmp_func, NULL); 295 return ret; 296 } 297 298 #define SCMI_PERF_FC_RING_DB(w) \ 299 do { \ 300 u##w val = 0; \ 301 \ 302 if (db->mask) \ 303 val = ioread##w(db->addr) & db->mask; \ 304 iowrite##w((u##w)db->set | val, db->addr); \ 305 } while (0) 306 307 static void scmi_perf_fc_ring_db(struct scmi_fc_db_info *db) 308 { 309 if (!db || !db->addr) 310 return; 311 312 if (db->width == 1) 313 SCMI_PERF_FC_RING_DB(8); 314 else if (db->width == 2) 315 SCMI_PERF_FC_RING_DB(16); 316 else if (db->width == 4) 317 SCMI_PERF_FC_RING_DB(32); 318 else /* db->width == 8 */ 319 #ifdef CONFIG_64BIT 320 SCMI_PERF_FC_RING_DB(64); 321 #else 322 { 323 u64 val = 0; 324 325 if (db->mask) 326 val = ioread64_hi_lo(db->addr) & db->mask; 327 iowrite64_hi_lo(db->set | val, db->addr); 328 } 329 #endif 330 } 331 332 static int scmi_perf_mb_limits_set(const struct scmi_handle *handle, u32 domain, 333 u32 max_perf, u32 min_perf) 334 { 335 int ret; 336 struct scmi_xfer *t; 337 struct scmi_perf_set_limits *limits; 338 339 ret = scmi_xfer_get_init(handle, PERF_LIMITS_SET, SCMI_PROTOCOL_PERF, 340 sizeof(*limits), 0, &t); 341 if (ret) 342 return ret; 343 344 limits = t->tx.buf; 345 limits->domain = cpu_to_le32(domain); 346 limits->max_level = cpu_to_le32(max_perf); 347 limits->min_level = cpu_to_le32(min_perf); 348 349 ret = scmi_do_xfer(handle, t); 350 351 scmi_xfer_put(handle, t); 352 return ret; 353 } 354 355 static int scmi_perf_limits_set(const struct scmi_handle *handle, u32 domain, 356 u32 max_perf, u32 min_perf) 357 { 358 struct scmi_perf_info *pi = handle->perf_priv; 359 struct perf_dom_info *dom = pi->dom_info + domain; 360 361 if (dom->fc_info && dom->fc_info->limit_set_addr) { 362 iowrite32(max_perf, dom->fc_info->limit_set_addr); 363 iowrite32(min_perf, dom->fc_info->limit_set_addr + 4); 364 scmi_perf_fc_ring_db(dom->fc_info->limit_set_db); 365 return 0; 366 } 367 368 return scmi_perf_mb_limits_set(handle, domain, max_perf, min_perf); 369 } 370 371 static int scmi_perf_mb_limits_get(const struct scmi_handle *handle, u32 domain, 372 u32 *max_perf, u32 *min_perf) 373 { 374 int ret; 375 struct scmi_xfer *t; 376 struct scmi_perf_get_limits *limits; 377 378 ret = scmi_xfer_get_init(handle, PERF_LIMITS_GET, SCMI_PROTOCOL_PERF, 379 sizeof(__le32), 0, &t); 380 if (ret) 381 return ret; 382 383 put_unaligned_le32(domain, t->tx.buf); 384 385 ret = scmi_do_xfer(handle, t); 386 if (!ret) { 387 limits = t->rx.buf; 388 389 *max_perf = le32_to_cpu(limits->max_level); 390 *min_perf = le32_to_cpu(limits->min_level); 391 } 392 393 scmi_xfer_put(handle, t); 394 return ret; 395 } 396 397 static int scmi_perf_limits_get(const struct scmi_handle *handle, u32 domain, 398 u32 *max_perf, u32 *min_perf) 399 { 400 struct scmi_perf_info *pi = handle->perf_priv; 401 struct perf_dom_info *dom = pi->dom_info + domain; 402 403 if (dom->fc_info && dom->fc_info->limit_get_addr) { 404 *max_perf = ioread32(dom->fc_info->limit_get_addr); 405 *min_perf = ioread32(dom->fc_info->limit_get_addr + 4); 406 return 0; 407 } 408 409 return scmi_perf_mb_limits_get(handle, domain, max_perf, min_perf); 410 } 411 412 static int scmi_perf_mb_level_set(const struct scmi_handle *handle, u32 domain, 413 u32 level, bool poll) 414 { 415 int ret; 416 struct scmi_xfer *t; 417 struct scmi_perf_set_level *lvl; 418 419 ret = scmi_xfer_get_init(handle, PERF_LEVEL_SET, SCMI_PROTOCOL_PERF, 420 sizeof(*lvl), 0, &t); 421 if (ret) 422 return ret; 423 424 t->hdr.poll_completion = poll; 425 lvl = t->tx.buf; 426 lvl->domain = cpu_to_le32(domain); 427 lvl->level = cpu_to_le32(level); 428 429 ret = scmi_do_xfer(handle, t); 430 431 scmi_xfer_put(handle, t); 432 return ret; 433 } 434 435 static int scmi_perf_level_set(const struct scmi_handle *handle, u32 domain, 436 u32 level, bool poll) 437 { 438 struct scmi_perf_info *pi = handle->perf_priv; 439 struct perf_dom_info *dom = pi->dom_info + domain; 440 441 if (dom->fc_info && dom->fc_info->level_set_addr) { 442 iowrite32(level, dom->fc_info->level_set_addr); 443 scmi_perf_fc_ring_db(dom->fc_info->level_set_db); 444 return 0; 445 } 446 447 return scmi_perf_mb_level_set(handle, domain, level, poll); 448 } 449 450 static int scmi_perf_mb_level_get(const struct scmi_handle *handle, u32 domain, 451 u32 *level, bool poll) 452 { 453 int ret; 454 struct scmi_xfer *t; 455 456 ret = scmi_xfer_get_init(handle, PERF_LEVEL_GET, SCMI_PROTOCOL_PERF, 457 sizeof(u32), sizeof(u32), &t); 458 if (ret) 459 return ret; 460 461 t->hdr.poll_completion = poll; 462 put_unaligned_le32(domain, t->tx.buf); 463 464 ret = scmi_do_xfer(handle, t); 465 if (!ret) 466 *level = get_unaligned_le32(t->rx.buf); 467 468 scmi_xfer_put(handle, t); 469 return ret; 470 } 471 472 static int scmi_perf_level_get(const struct scmi_handle *handle, u32 domain, 473 u32 *level, bool poll) 474 { 475 struct scmi_perf_info *pi = handle->perf_priv; 476 struct perf_dom_info *dom = pi->dom_info + domain; 477 478 if (dom->fc_info && dom->fc_info->level_get_addr) { 479 *level = ioread32(dom->fc_info->level_get_addr); 480 return 0; 481 } 482 483 return scmi_perf_mb_level_get(handle, domain, level, poll); 484 } 485 486 static bool scmi_perf_fc_size_is_valid(u32 msg, u32 size) 487 { 488 if ((msg == PERF_LEVEL_GET || msg == PERF_LEVEL_SET) && size == 4) 489 return true; 490 if ((msg == PERF_LIMITS_GET || msg == PERF_LIMITS_SET) && size == 8) 491 return true; 492 return false; 493 } 494 495 static void 496 scmi_perf_domain_desc_fc(const struct scmi_handle *handle, u32 domain, 497 u32 message_id, void __iomem **p_addr, 498 struct scmi_fc_db_info **p_db) 499 { 500 int ret; 501 u32 flags; 502 u64 phys_addr; 503 u8 size; 504 void __iomem *addr; 505 struct scmi_xfer *t; 506 struct scmi_fc_db_info *db; 507 struct scmi_perf_get_fc_info *info; 508 struct scmi_msg_resp_perf_desc_fc *resp; 509 510 if (!p_addr) 511 return; 512 513 ret = scmi_xfer_get_init(handle, PERF_DESCRIBE_FASTCHANNEL, 514 SCMI_PROTOCOL_PERF, 515 sizeof(*info), sizeof(*resp), &t); 516 if (ret) 517 return; 518 519 info = t->tx.buf; 520 info->domain = cpu_to_le32(domain); 521 info->message_id = cpu_to_le32(message_id); 522 523 ret = scmi_do_xfer(handle, t); 524 if (ret) 525 goto err_xfer; 526 527 resp = t->rx.buf; 528 flags = le32_to_cpu(resp->attr); 529 size = le32_to_cpu(resp->chan_size); 530 if (!scmi_perf_fc_size_is_valid(message_id, size)) 531 goto err_xfer; 532 533 phys_addr = le32_to_cpu(resp->chan_addr_low); 534 phys_addr |= (u64)le32_to_cpu(resp->chan_addr_high) << 32; 535 addr = devm_ioremap(handle->dev, phys_addr, size); 536 if (!addr) 537 goto err_xfer; 538 *p_addr = addr; 539 540 if (p_db && SUPPORTS_DOORBELL(flags)) { 541 db = devm_kzalloc(handle->dev, sizeof(*db), GFP_KERNEL); 542 if (!db) 543 goto err_xfer; 544 545 size = 1 << DOORBELL_REG_WIDTH(flags); 546 phys_addr = le32_to_cpu(resp->db_addr_low); 547 phys_addr |= (u64)le32_to_cpu(resp->db_addr_high) << 32; 548 addr = devm_ioremap(handle->dev, phys_addr, size); 549 if (!addr) 550 goto err_xfer; 551 552 db->addr = addr; 553 db->width = size; 554 db->set = le32_to_cpu(resp->db_set_lmask); 555 db->set |= (u64)le32_to_cpu(resp->db_set_hmask) << 32; 556 db->mask = le32_to_cpu(resp->db_preserve_lmask); 557 db->mask |= (u64)le32_to_cpu(resp->db_preserve_hmask) << 32; 558 *p_db = db; 559 } 560 err_xfer: 561 scmi_xfer_put(handle, t); 562 } 563 564 static void scmi_perf_domain_init_fc(const struct scmi_handle *handle, 565 u32 domain, struct scmi_fc_info **p_fc) 566 { 567 struct scmi_fc_info *fc; 568 569 fc = devm_kzalloc(handle->dev, sizeof(*fc), GFP_KERNEL); 570 if (!fc) 571 return; 572 573 scmi_perf_domain_desc_fc(handle, domain, PERF_LEVEL_SET, 574 &fc->level_set_addr, &fc->level_set_db); 575 scmi_perf_domain_desc_fc(handle, domain, PERF_LEVEL_GET, 576 &fc->level_get_addr, NULL); 577 scmi_perf_domain_desc_fc(handle, domain, PERF_LIMITS_SET, 578 &fc->limit_set_addr, &fc->limit_set_db); 579 scmi_perf_domain_desc_fc(handle, domain, PERF_LIMITS_GET, 580 &fc->limit_get_addr, NULL); 581 *p_fc = fc; 582 } 583 584 /* Device specific ops */ 585 static int scmi_dev_domain_id(struct device *dev) 586 { 587 struct of_phandle_args clkspec; 588 589 if (of_parse_phandle_with_args(dev->of_node, "clocks", "#clock-cells", 590 0, &clkspec)) 591 return -EINVAL; 592 593 return clkspec.args[0]; 594 } 595 596 static int scmi_dvfs_device_opps_add(const struct scmi_handle *handle, 597 struct device *dev) 598 { 599 int idx, ret, domain; 600 unsigned long freq; 601 struct scmi_opp *opp; 602 struct perf_dom_info *dom; 603 struct scmi_perf_info *pi = handle->perf_priv; 604 605 domain = scmi_dev_domain_id(dev); 606 if (domain < 0) 607 return domain; 608 609 dom = pi->dom_info + domain; 610 611 for (opp = dom->opp, idx = 0; idx < dom->opp_count; idx++, opp++) { 612 freq = opp->perf * dom->mult_factor; 613 614 ret = dev_pm_opp_add(dev, freq, 0); 615 if (ret) { 616 dev_warn(dev, "failed to add opp %luHz\n", freq); 617 618 while (idx-- > 0) { 619 freq = (--opp)->perf * dom->mult_factor; 620 dev_pm_opp_remove(dev, freq); 621 } 622 return ret; 623 } 624 } 625 return 0; 626 } 627 628 static int scmi_dvfs_transition_latency_get(const struct scmi_handle *handle, 629 struct device *dev) 630 { 631 struct perf_dom_info *dom; 632 struct scmi_perf_info *pi = handle->perf_priv; 633 int domain = scmi_dev_domain_id(dev); 634 635 if (domain < 0) 636 return domain; 637 638 dom = pi->dom_info + domain; 639 /* uS to nS */ 640 return dom->opp[dom->opp_count - 1].trans_latency_us * 1000; 641 } 642 643 static int scmi_dvfs_freq_set(const struct scmi_handle *handle, u32 domain, 644 unsigned long freq, bool poll) 645 { 646 struct scmi_perf_info *pi = handle->perf_priv; 647 struct perf_dom_info *dom = pi->dom_info + domain; 648 649 return scmi_perf_level_set(handle, domain, freq / dom->mult_factor, 650 poll); 651 } 652 653 static int scmi_dvfs_freq_get(const struct scmi_handle *handle, u32 domain, 654 unsigned long *freq, bool poll) 655 { 656 int ret; 657 u32 level; 658 struct scmi_perf_info *pi = handle->perf_priv; 659 struct perf_dom_info *dom = pi->dom_info + domain; 660 661 ret = scmi_perf_level_get(handle, domain, &level, poll); 662 if (!ret) 663 *freq = level * dom->mult_factor; 664 665 return ret; 666 } 667 668 static int scmi_dvfs_est_power_get(const struct scmi_handle *handle, u32 domain, 669 unsigned long *freq, unsigned long *power) 670 { 671 struct scmi_perf_info *pi = handle->perf_priv; 672 struct perf_dom_info *dom; 673 unsigned long opp_freq; 674 int idx, ret = -EINVAL; 675 struct scmi_opp *opp; 676 677 dom = pi->dom_info + domain; 678 if (!dom) 679 return -EIO; 680 681 for (opp = dom->opp, idx = 0; idx < dom->opp_count; idx++, opp++) { 682 opp_freq = opp->perf * dom->mult_factor; 683 if (opp_freq < *freq) 684 continue; 685 686 *freq = opp_freq; 687 *power = opp->power; 688 ret = 0; 689 break; 690 } 691 692 return ret; 693 } 694 695 static struct scmi_perf_ops perf_ops = { 696 .limits_set = scmi_perf_limits_set, 697 .limits_get = scmi_perf_limits_get, 698 .level_set = scmi_perf_level_set, 699 .level_get = scmi_perf_level_get, 700 .device_domain_id = scmi_dev_domain_id, 701 .transition_latency_get = scmi_dvfs_transition_latency_get, 702 .device_opps_add = scmi_dvfs_device_opps_add, 703 .freq_set = scmi_dvfs_freq_set, 704 .freq_get = scmi_dvfs_freq_get, 705 .est_power_get = scmi_dvfs_est_power_get, 706 }; 707 708 static int scmi_perf_protocol_init(struct scmi_handle *handle) 709 { 710 int domain; 711 u32 version; 712 struct scmi_perf_info *pinfo; 713 714 scmi_version_get(handle, SCMI_PROTOCOL_PERF, &version); 715 716 dev_dbg(handle->dev, "Performance Version %d.%d\n", 717 PROTOCOL_REV_MAJOR(version), PROTOCOL_REV_MINOR(version)); 718 719 pinfo = devm_kzalloc(handle->dev, sizeof(*pinfo), GFP_KERNEL); 720 if (!pinfo) 721 return -ENOMEM; 722 723 scmi_perf_attributes_get(handle, pinfo); 724 725 pinfo->dom_info = devm_kcalloc(handle->dev, pinfo->num_domains, 726 sizeof(*pinfo->dom_info), GFP_KERNEL); 727 if (!pinfo->dom_info) 728 return -ENOMEM; 729 730 for (domain = 0; domain < pinfo->num_domains; domain++) { 731 struct perf_dom_info *dom = pinfo->dom_info + domain; 732 733 scmi_perf_domain_attributes_get(handle, domain, dom); 734 scmi_perf_describe_levels_get(handle, domain, dom); 735 736 if (dom->perf_fastchannels) 737 scmi_perf_domain_init_fc(handle, domain, &dom->fc_info); 738 } 739 740 pinfo->version = version; 741 handle->perf_ops = &perf_ops; 742 handle->perf_priv = pinfo; 743 744 return 0; 745 } 746 747 static int __init scmi_perf_init(void) 748 { 749 return scmi_protocol_register(SCMI_PROTOCOL_PERF, 750 &scmi_perf_protocol_init); 751 } 752 subsys_initcall(scmi_perf_init); 753