1 /* 2 * Driver for OHCI 1394 controllers 3 * 4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software Foundation, 18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 */ 20 21 #include <linux/bitops.h> 22 #include <linux/bug.h> 23 #include <linux/compiler.h> 24 #include <linux/delay.h> 25 #include <linux/device.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/firewire.h> 28 #include <linux/firewire-constants.h> 29 #include <linux/init.h> 30 #include <linux/interrupt.h> 31 #include <linux/io.h> 32 #include <linux/kernel.h> 33 #include <linux/list.h> 34 #include <linux/mm.h> 35 #include <linux/module.h> 36 #include <linux/moduleparam.h> 37 #include <linux/mutex.h> 38 #include <linux/pci.h> 39 #include <linux/pci_ids.h> 40 #include <linux/slab.h> 41 #include <linux/spinlock.h> 42 #include <linux/string.h> 43 #include <linux/time.h> 44 #include <linux/vmalloc.h> 45 46 #include <asm/byteorder.h> 47 #include <asm/page.h> 48 #include <asm/system.h> 49 50 #ifdef CONFIG_PPC_PMAC 51 #include <asm/pmac_feature.h> 52 #endif 53 54 #include "core.h" 55 #include "ohci.h" 56 57 #define DESCRIPTOR_OUTPUT_MORE 0 58 #define DESCRIPTOR_OUTPUT_LAST (1 << 12) 59 #define DESCRIPTOR_INPUT_MORE (2 << 12) 60 #define DESCRIPTOR_INPUT_LAST (3 << 12) 61 #define DESCRIPTOR_STATUS (1 << 11) 62 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8) 63 #define DESCRIPTOR_PING (1 << 7) 64 #define DESCRIPTOR_YY (1 << 6) 65 #define DESCRIPTOR_NO_IRQ (0 << 4) 66 #define DESCRIPTOR_IRQ_ERROR (1 << 4) 67 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4) 68 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2) 69 #define DESCRIPTOR_WAIT (3 << 0) 70 71 struct descriptor { 72 __le16 req_count; 73 __le16 control; 74 __le32 data_address; 75 __le32 branch_address; 76 __le16 res_count; 77 __le16 transfer_status; 78 } __attribute__((aligned(16))); 79 80 #define CONTROL_SET(regs) (regs) 81 #define CONTROL_CLEAR(regs) ((regs) + 4) 82 #define COMMAND_PTR(regs) ((regs) + 12) 83 #define CONTEXT_MATCH(regs) ((regs) + 16) 84 85 #define AR_BUFFER_SIZE (32*1024) 86 #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE) 87 /* we need at least two pages for proper list management */ 88 #define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2) 89 90 #define MAX_ASYNC_PAYLOAD 4096 91 #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4) 92 #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE) 93 94 struct ar_context { 95 struct fw_ohci *ohci; 96 struct page *pages[AR_BUFFERS]; 97 void *buffer; 98 struct descriptor *descriptors; 99 dma_addr_t descriptors_bus; 100 void *pointer; 101 unsigned int last_buffer_index; 102 u32 regs; 103 struct tasklet_struct tasklet; 104 }; 105 106 struct context; 107 108 typedef int (*descriptor_callback_t)(struct context *ctx, 109 struct descriptor *d, 110 struct descriptor *last); 111 112 /* 113 * A buffer that contains a block of DMA-able coherent memory used for 114 * storing a portion of a DMA descriptor program. 115 */ 116 struct descriptor_buffer { 117 struct list_head list; 118 dma_addr_t buffer_bus; 119 size_t buffer_size; 120 size_t used; 121 struct descriptor buffer[0]; 122 }; 123 124 struct context { 125 struct fw_ohci *ohci; 126 u32 regs; 127 int total_allocation; 128 bool running; 129 bool flushing; 130 131 /* 132 * List of page-sized buffers for storing DMA descriptors. 133 * Head of list contains buffers in use and tail of list contains 134 * free buffers. 135 */ 136 struct list_head buffer_list; 137 138 /* 139 * Pointer to a buffer inside buffer_list that contains the tail 140 * end of the current DMA program. 141 */ 142 struct descriptor_buffer *buffer_tail; 143 144 /* 145 * The descriptor containing the branch address of the first 146 * descriptor that has not yet been filled by the device. 147 */ 148 struct descriptor *last; 149 150 /* 151 * The last descriptor in the DMA program. It contains the branch 152 * address that must be updated upon appending a new descriptor. 153 */ 154 struct descriptor *prev; 155 156 descriptor_callback_t callback; 157 158 struct tasklet_struct tasklet; 159 }; 160 161 #define IT_HEADER_SY(v) ((v) << 0) 162 #define IT_HEADER_TCODE(v) ((v) << 4) 163 #define IT_HEADER_CHANNEL(v) ((v) << 8) 164 #define IT_HEADER_TAG(v) ((v) << 14) 165 #define IT_HEADER_SPEED(v) ((v) << 16) 166 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16) 167 168 struct iso_context { 169 struct fw_iso_context base; 170 struct context context; 171 int excess_bytes; 172 void *header; 173 size_t header_length; 174 175 u8 sync; 176 u8 tags; 177 }; 178 179 #define CONFIG_ROM_SIZE 1024 180 181 struct fw_ohci { 182 struct fw_card card; 183 184 __iomem char *registers; 185 int node_id; 186 int generation; 187 int request_generation; /* for timestamping incoming requests */ 188 unsigned quirks; 189 unsigned int pri_req_max; 190 u32 bus_time; 191 bool is_root; 192 bool csr_state_setclear_abdicate; 193 int n_ir; 194 int n_it; 195 /* 196 * Spinlock for accessing fw_ohci data. Never call out of 197 * this driver with this lock held. 198 */ 199 spinlock_t lock; 200 201 struct mutex phy_reg_mutex; 202 203 void *misc_buffer; 204 dma_addr_t misc_buffer_bus; 205 206 struct ar_context ar_request_ctx; 207 struct ar_context ar_response_ctx; 208 struct context at_request_ctx; 209 struct context at_response_ctx; 210 211 u32 it_context_support; 212 u32 it_context_mask; /* unoccupied IT contexts */ 213 struct iso_context *it_context_list; 214 u64 ir_context_channels; /* unoccupied channels */ 215 u32 ir_context_support; 216 u32 ir_context_mask; /* unoccupied IR contexts */ 217 struct iso_context *ir_context_list; 218 u64 mc_channels; /* channels in use by the multichannel IR context */ 219 bool mc_allocated; 220 221 __be32 *config_rom; 222 dma_addr_t config_rom_bus; 223 __be32 *next_config_rom; 224 dma_addr_t next_config_rom_bus; 225 __be32 next_header; 226 227 __le32 *self_id_cpu; 228 dma_addr_t self_id_bus; 229 struct tasklet_struct bus_reset_tasklet; 230 231 u32 self_id_buffer[512]; 232 }; 233 234 static inline struct fw_ohci *fw_ohci(struct fw_card *card) 235 { 236 return container_of(card, struct fw_ohci, card); 237 } 238 239 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 240 #define IR_CONTEXT_BUFFER_FILL 0x80000000 241 #define IR_CONTEXT_ISOCH_HEADER 0x40000000 242 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 243 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 244 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 245 246 #define CONTEXT_RUN 0x8000 247 #define CONTEXT_WAKE 0x1000 248 #define CONTEXT_DEAD 0x0800 249 #define CONTEXT_ACTIVE 0x0400 250 251 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf 252 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 253 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 254 255 #define OHCI1394_REGISTER_SIZE 0x800 256 #define OHCI1394_PCI_HCI_Control 0x40 257 #define SELF_ID_BUF_SIZE 0x800 258 #define OHCI_TCODE_PHY_PACKET 0x0e 259 #define OHCI_VERSION_1_1 0x010010 260 261 static char ohci_driver_name[] = KBUILD_MODNAME; 262 263 #define PCI_DEVICE_ID_AGERE_FW643 0x5901 264 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380 265 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009 266 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd 267 268 #define QUIRK_CYCLE_TIMER 1 269 #define QUIRK_RESET_PACKET 2 270 #define QUIRK_BE_HEADERS 4 271 #define QUIRK_NO_1394A 8 272 #define QUIRK_NO_MSI 16 273 274 /* In case of multiple matches in ohci_quirks[], only the first one is used. */ 275 static const struct { 276 unsigned short vendor, device, revision, flags; 277 } ohci_quirks[] = { 278 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID, 279 QUIRK_CYCLE_TIMER}, 280 281 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID, 282 QUIRK_BE_HEADERS}, 283 284 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6, 285 QUIRK_NO_MSI}, 286 287 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID, 288 QUIRK_NO_MSI}, 289 290 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID, 291 QUIRK_CYCLE_TIMER}, 292 293 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID, 294 QUIRK_NO_MSI}, 295 296 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID, 297 QUIRK_CYCLE_TIMER}, 298 299 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID, 300 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A}, 301 302 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID, 303 QUIRK_RESET_PACKET}, 304 305 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID, 306 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, 307 }; 308 309 /* This overrides anything that was found in ohci_quirks[]. */ 310 static int param_quirks; 311 module_param_named(quirks, param_quirks, int, 0644); 312 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0" 313 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER) 314 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET) 315 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS) 316 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A) 317 ", disable MSI = " __stringify(QUIRK_NO_MSI) 318 ")"); 319 320 #define OHCI_PARAM_DEBUG_AT_AR 1 321 #define OHCI_PARAM_DEBUG_SELFIDS 2 322 #define OHCI_PARAM_DEBUG_IRQS 4 323 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */ 324 325 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG 326 327 static int param_debug; 328 module_param_named(debug, param_debug, int, 0644); 329 MODULE_PARM_DESC(debug, "Verbose logging (default = 0" 330 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR) 331 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS) 332 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS) 333 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS) 334 ", or a combination, or all = -1)"); 335 336 static void log_irqs(u32 evt) 337 { 338 if (likely(!(param_debug & 339 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS)))) 340 return; 341 342 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) && 343 !(evt & OHCI1394_busReset)) 344 return; 345 346 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt, 347 evt & OHCI1394_selfIDComplete ? " selfID" : "", 348 evt & OHCI1394_RQPkt ? " AR_req" : "", 349 evt & OHCI1394_RSPkt ? " AR_resp" : "", 350 evt & OHCI1394_reqTxComplete ? " AT_req" : "", 351 evt & OHCI1394_respTxComplete ? " AT_resp" : "", 352 evt & OHCI1394_isochRx ? " IR" : "", 353 evt & OHCI1394_isochTx ? " IT" : "", 354 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", 355 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", 356 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "", 357 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "", 358 evt & OHCI1394_regAccessFail ? " regAccessFail" : "", 359 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "", 360 evt & OHCI1394_busReset ? " busReset" : "", 361 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | 362 OHCI1394_RSPkt | OHCI1394_reqTxComplete | 363 OHCI1394_respTxComplete | OHCI1394_isochRx | 364 OHCI1394_isochTx | OHCI1394_postedWriteErr | 365 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds | 366 OHCI1394_cycleInconsistent | 367 OHCI1394_regAccessFail | OHCI1394_busReset) 368 ? " ?" : ""); 369 } 370 371 static const char *speed[] = { 372 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta", 373 }; 374 static const char *power[] = { 375 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W", 376 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W", 377 }; 378 static const char port[] = { '.', '-', 'p', 'c', }; 379 380 static char _p(u32 *s, int shift) 381 { 382 return port[*s >> shift & 3]; 383 } 384 385 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s) 386 { 387 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) 388 return; 389 390 fw_notify("%d selfIDs, generation %d, local node ID %04x\n", 391 self_id_count, generation, node_id); 392 393 for (; self_id_count--; ++s) 394 if ((*s & 1 << 23) == 0) 395 fw_notify("selfID 0: %08x, phy %d [%c%c%c] " 396 "%s gc=%d %s %s%s%s\n", 397 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2), 398 speed[*s >> 14 & 3], *s >> 16 & 63, 399 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", 400 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); 401 else 402 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n", 403 *s, *s >> 24 & 63, 404 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10), 405 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2)); 406 } 407 408 static const char *evts[] = { 409 [0x00] = "evt_no_status", [0x01] = "-reserved-", 410 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack", 411 [0x04] = "evt_underrun", [0x05] = "evt_overrun", 412 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read", 413 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset", 414 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err", 415 [0x0c] = "-reserved-", [0x0d] = "-reserved-", 416 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed", 417 [0x10] = "-reserved-", [0x11] = "ack_complete", 418 [0x12] = "ack_pending ", [0x13] = "-reserved-", 419 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A", 420 [0x16] = "ack_busy_B", [0x17] = "-reserved-", 421 [0x18] = "-reserved-", [0x19] = "-reserved-", 422 [0x1a] = "-reserved-", [0x1b] = "ack_tardy", 423 [0x1c] = "-reserved-", [0x1d] = "ack_data_error", 424 [0x1e] = "ack_type_error", [0x1f] = "-reserved-", 425 [0x20] = "pending/cancelled", 426 }; 427 static const char *tcodes[] = { 428 [0x0] = "QW req", [0x1] = "BW req", 429 [0x2] = "W resp", [0x3] = "-reserved-", 430 [0x4] = "QR req", [0x5] = "BR req", 431 [0x6] = "QR resp", [0x7] = "BR resp", 432 [0x8] = "cycle start", [0x9] = "Lk req", 433 [0xa] = "async stream packet", [0xb] = "Lk resp", 434 [0xc] = "-reserved-", [0xd] = "-reserved-", 435 [0xe] = "link internal", [0xf] = "-reserved-", 436 }; 437 438 static void log_ar_at_event(char dir, int speed, u32 *header, int evt) 439 { 440 int tcode = header[0] >> 4 & 0xf; 441 char specific[12]; 442 443 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR))) 444 return; 445 446 if (unlikely(evt >= ARRAY_SIZE(evts))) 447 evt = 0x1f; 448 449 if (evt == OHCI1394_evt_bus_reset) { 450 fw_notify("A%c evt_bus_reset, generation %d\n", 451 dir, (header[2] >> 16) & 0xff); 452 return; 453 } 454 455 switch (tcode) { 456 case 0x0: case 0x6: case 0x8: 457 snprintf(specific, sizeof(specific), " = %08x", 458 be32_to_cpu((__force __be32)header[3])); 459 break; 460 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb: 461 snprintf(specific, sizeof(specific), " %x,%x", 462 header[3] >> 16, header[3] & 0xffff); 463 break; 464 default: 465 specific[0] = '\0'; 466 } 467 468 switch (tcode) { 469 case 0xa: 470 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]); 471 break; 472 case 0xe: 473 fw_notify("A%c %s, PHY %08x %08x\n", 474 dir, evts[evt], header[1], header[2]); 475 break; 476 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9: 477 fw_notify("A%c spd %x tl %02x, " 478 "%04x -> %04x, %s, " 479 "%s, %04x%08x%s\n", 480 dir, speed, header[0] >> 10 & 0x3f, 481 header[1] >> 16, header[0] >> 16, evts[evt], 482 tcodes[tcode], header[1] & 0xffff, header[2], specific); 483 break; 484 default: 485 fw_notify("A%c spd %x tl %02x, " 486 "%04x -> %04x, %s, " 487 "%s%s\n", 488 dir, speed, header[0] >> 10 & 0x3f, 489 header[1] >> 16, header[0] >> 16, evts[evt], 490 tcodes[tcode], specific); 491 } 492 } 493 494 #else 495 496 #define param_debug 0 497 static inline void log_irqs(u32 evt) {} 498 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {} 499 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {} 500 501 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */ 502 503 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) 504 { 505 writel(data, ohci->registers + offset); 506 } 507 508 static inline u32 reg_read(const struct fw_ohci *ohci, int offset) 509 { 510 return readl(ohci->registers + offset); 511 } 512 513 static inline void flush_writes(const struct fw_ohci *ohci) 514 { 515 /* Do a dummy read to flush writes. */ 516 reg_read(ohci, OHCI1394_Version); 517 } 518 519 /* 520 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and 521 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex. 522 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg() 523 * directly. Exceptions are intrinsically serialized contexts like pci_probe. 524 */ 525 static int read_phy_reg(struct fw_ohci *ohci, int addr) 526 { 527 u32 val; 528 int i; 529 530 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); 531 for (i = 0; i < 3 + 100; i++) { 532 val = reg_read(ohci, OHCI1394_PhyControl); 533 if (!~val) 534 return -ENODEV; /* Card was ejected. */ 535 536 if (val & OHCI1394_PhyControl_ReadDone) 537 return OHCI1394_PhyControl_ReadData(val); 538 539 /* 540 * Try a few times without waiting. Sleeping is necessary 541 * only when the link/PHY interface is busy. 542 */ 543 if (i >= 3) 544 msleep(1); 545 } 546 fw_error("failed to read phy reg\n"); 547 548 return -EBUSY; 549 } 550 551 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val) 552 { 553 int i; 554 555 reg_write(ohci, OHCI1394_PhyControl, 556 OHCI1394_PhyControl_Write(addr, val)); 557 for (i = 0; i < 3 + 100; i++) { 558 val = reg_read(ohci, OHCI1394_PhyControl); 559 if (!~val) 560 return -ENODEV; /* Card was ejected. */ 561 562 if (!(val & OHCI1394_PhyControl_WritePending)) 563 return 0; 564 565 if (i >= 3) 566 msleep(1); 567 } 568 fw_error("failed to write phy reg\n"); 569 570 return -EBUSY; 571 } 572 573 static int update_phy_reg(struct fw_ohci *ohci, int addr, 574 int clear_bits, int set_bits) 575 { 576 int ret = read_phy_reg(ohci, addr); 577 if (ret < 0) 578 return ret; 579 580 /* 581 * The interrupt status bits are cleared by writing a one bit. 582 * Avoid clearing them unless explicitly requested in set_bits. 583 */ 584 if (addr == 5) 585 clear_bits |= PHY_INT_STATUS_BITS; 586 587 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits); 588 } 589 590 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr) 591 { 592 int ret; 593 594 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5); 595 if (ret < 0) 596 return ret; 597 598 return read_phy_reg(ohci, addr); 599 } 600 601 static int ohci_read_phy_reg(struct fw_card *card, int addr) 602 { 603 struct fw_ohci *ohci = fw_ohci(card); 604 int ret; 605 606 mutex_lock(&ohci->phy_reg_mutex); 607 ret = read_phy_reg(ohci, addr); 608 mutex_unlock(&ohci->phy_reg_mutex); 609 610 return ret; 611 } 612 613 static int ohci_update_phy_reg(struct fw_card *card, int addr, 614 int clear_bits, int set_bits) 615 { 616 struct fw_ohci *ohci = fw_ohci(card); 617 int ret; 618 619 mutex_lock(&ohci->phy_reg_mutex); 620 ret = update_phy_reg(ohci, addr, clear_bits, set_bits); 621 mutex_unlock(&ohci->phy_reg_mutex); 622 623 return ret; 624 } 625 626 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i) 627 { 628 return page_private(ctx->pages[i]); 629 } 630 631 static void ar_context_link_page(struct ar_context *ctx, unsigned int index) 632 { 633 struct descriptor *d; 634 635 d = &ctx->descriptors[index]; 636 d->branch_address &= cpu_to_le32(~0xf); 637 d->res_count = cpu_to_le16(PAGE_SIZE); 638 d->transfer_status = 0; 639 640 wmb(); /* finish init of new descriptors before branch_address update */ 641 d = &ctx->descriptors[ctx->last_buffer_index]; 642 d->branch_address |= cpu_to_le32(1); 643 644 ctx->last_buffer_index = index; 645 646 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 647 } 648 649 static void ar_context_release(struct ar_context *ctx) 650 { 651 unsigned int i; 652 653 if (ctx->buffer) 654 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES); 655 656 for (i = 0; i < AR_BUFFERS; i++) 657 if (ctx->pages[i]) { 658 dma_unmap_page(ctx->ohci->card.device, 659 ar_buffer_bus(ctx, i), 660 PAGE_SIZE, DMA_FROM_DEVICE); 661 __free_page(ctx->pages[i]); 662 } 663 } 664 665 static void ar_context_abort(struct ar_context *ctx, const char *error_msg) 666 { 667 if (reg_read(ctx->ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) { 668 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 669 flush_writes(ctx->ohci); 670 671 fw_error("AR error: %s; DMA stopped\n", error_msg); 672 } 673 /* FIXME: restart? */ 674 } 675 676 static inline unsigned int ar_next_buffer_index(unsigned int index) 677 { 678 return (index + 1) % AR_BUFFERS; 679 } 680 681 static inline unsigned int ar_prev_buffer_index(unsigned int index) 682 { 683 return (index - 1 + AR_BUFFERS) % AR_BUFFERS; 684 } 685 686 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx) 687 { 688 return ar_next_buffer_index(ctx->last_buffer_index); 689 } 690 691 /* 692 * We search for the buffer that contains the last AR packet DMA data written 693 * by the controller. 694 */ 695 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx, 696 unsigned int *buffer_offset) 697 { 698 unsigned int i, next_i, last = ctx->last_buffer_index; 699 __le16 res_count, next_res_count; 700 701 i = ar_first_buffer_index(ctx); 702 res_count = ACCESS_ONCE(ctx->descriptors[i].res_count); 703 704 /* A buffer that is not yet completely filled must be the last one. */ 705 while (i != last && res_count == 0) { 706 707 /* Peek at the next descriptor. */ 708 next_i = ar_next_buffer_index(i); 709 rmb(); /* read descriptors in order */ 710 next_res_count = ACCESS_ONCE( 711 ctx->descriptors[next_i].res_count); 712 /* 713 * If the next descriptor is still empty, we must stop at this 714 * descriptor. 715 */ 716 if (next_res_count == cpu_to_le16(PAGE_SIZE)) { 717 /* 718 * The exception is when the DMA data for one packet is 719 * split over three buffers; in this case, the middle 720 * buffer's descriptor might be never updated by the 721 * controller and look still empty, and we have to peek 722 * at the third one. 723 */ 724 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) { 725 next_i = ar_next_buffer_index(next_i); 726 rmb(); 727 next_res_count = ACCESS_ONCE( 728 ctx->descriptors[next_i].res_count); 729 if (next_res_count != cpu_to_le16(PAGE_SIZE)) 730 goto next_buffer_is_active; 731 } 732 733 break; 734 } 735 736 next_buffer_is_active: 737 i = next_i; 738 res_count = next_res_count; 739 } 740 741 rmb(); /* read res_count before the DMA data */ 742 743 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count); 744 if (*buffer_offset > PAGE_SIZE) { 745 *buffer_offset = 0; 746 ar_context_abort(ctx, "corrupted descriptor"); 747 } 748 749 return i; 750 } 751 752 static void ar_sync_buffers_for_cpu(struct ar_context *ctx, 753 unsigned int end_buffer_index, 754 unsigned int end_buffer_offset) 755 { 756 unsigned int i; 757 758 i = ar_first_buffer_index(ctx); 759 while (i != end_buffer_index) { 760 dma_sync_single_for_cpu(ctx->ohci->card.device, 761 ar_buffer_bus(ctx, i), 762 PAGE_SIZE, DMA_FROM_DEVICE); 763 i = ar_next_buffer_index(i); 764 } 765 if (end_buffer_offset > 0) 766 dma_sync_single_for_cpu(ctx->ohci->card.device, 767 ar_buffer_bus(ctx, i), 768 end_buffer_offset, DMA_FROM_DEVICE); 769 } 770 771 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) 772 #define cond_le32_to_cpu(v) \ 773 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v)) 774 #else 775 #define cond_le32_to_cpu(v) le32_to_cpu(v) 776 #endif 777 778 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) 779 { 780 struct fw_ohci *ohci = ctx->ohci; 781 struct fw_packet p; 782 u32 status, length, tcode; 783 int evt; 784 785 p.header[0] = cond_le32_to_cpu(buffer[0]); 786 p.header[1] = cond_le32_to_cpu(buffer[1]); 787 p.header[2] = cond_le32_to_cpu(buffer[2]); 788 789 tcode = (p.header[0] >> 4) & 0x0f; 790 switch (tcode) { 791 case TCODE_WRITE_QUADLET_REQUEST: 792 case TCODE_READ_QUADLET_RESPONSE: 793 p.header[3] = (__force __u32) buffer[3]; 794 p.header_length = 16; 795 p.payload_length = 0; 796 break; 797 798 case TCODE_READ_BLOCK_REQUEST : 799 p.header[3] = cond_le32_to_cpu(buffer[3]); 800 p.header_length = 16; 801 p.payload_length = 0; 802 break; 803 804 case TCODE_WRITE_BLOCK_REQUEST: 805 case TCODE_READ_BLOCK_RESPONSE: 806 case TCODE_LOCK_REQUEST: 807 case TCODE_LOCK_RESPONSE: 808 p.header[3] = cond_le32_to_cpu(buffer[3]); 809 p.header_length = 16; 810 p.payload_length = p.header[3] >> 16; 811 if (p.payload_length > MAX_ASYNC_PAYLOAD) { 812 ar_context_abort(ctx, "invalid packet length"); 813 return NULL; 814 } 815 break; 816 817 case TCODE_WRITE_RESPONSE: 818 case TCODE_READ_QUADLET_REQUEST: 819 case OHCI_TCODE_PHY_PACKET: 820 p.header_length = 12; 821 p.payload_length = 0; 822 break; 823 824 default: 825 ar_context_abort(ctx, "invalid tcode"); 826 return NULL; 827 } 828 829 p.payload = (void *) buffer + p.header_length; 830 831 /* FIXME: What to do about evt_* errors? */ 832 length = (p.header_length + p.payload_length + 3) / 4; 833 status = cond_le32_to_cpu(buffer[length]); 834 evt = (status >> 16) & 0x1f; 835 836 p.ack = evt - 16; 837 p.speed = (status >> 21) & 0x7; 838 p.timestamp = status & 0xffff; 839 p.generation = ohci->request_generation; 840 841 log_ar_at_event('R', p.speed, p.header, evt); 842 843 /* 844 * Several controllers, notably from NEC and VIA, forget to 845 * write ack_complete status at PHY packet reception. 846 */ 847 if (evt == OHCI1394_evt_no_status && 848 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4)) 849 p.ack = ACK_COMPLETE; 850 851 /* 852 * The OHCI bus reset handler synthesizes a PHY packet with 853 * the new generation number when a bus reset happens (see 854 * section 8.4.2.3). This helps us determine when a request 855 * was received and make sure we send the response in the same 856 * generation. We only need this for requests; for responses 857 * we use the unique tlabel for finding the matching 858 * request. 859 * 860 * Alas some chips sometimes emit bus reset packets with a 861 * wrong generation. We set the correct generation for these 862 * at a slightly incorrect time (in bus_reset_tasklet). 863 */ 864 if (evt == OHCI1394_evt_bus_reset) { 865 if (!(ohci->quirks & QUIRK_RESET_PACKET)) 866 ohci->request_generation = (p.header[2] >> 16) & 0xff; 867 } else if (ctx == &ohci->ar_request_ctx) { 868 fw_core_handle_request(&ohci->card, &p); 869 } else { 870 fw_core_handle_response(&ohci->card, &p); 871 } 872 873 return buffer + length + 1; 874 } 875 876 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end) 877 { 878 void *next; 879 880 while (p < end) { 881 next = handle_ar_packet(ctx, p); 882 if (!next) 883 return p; 884 p = next; 885 } 886 887 return p; 888 } 889 890 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer) 891 { 892 unsigned int i; 893 894 i = ar_first_buffer_index(ctx); 895 while (i != end_buffer) { 896 dma_sync_single_for_device(ctx->ohci->card.device, 897 ar_buffer_bus(ctx, i), 898 PAGE_SIZE, DMA_FROM_DEVICE); 899 ar_context_link_page(ctx, i); 900 i = ar_next_buffer_index(i); 901 } 902 } 903 904 static void ar_context_tasklet(unsigned long data) 905 { 906 struct ar_context *ctx = (struct ar_context *)data; 907 unsigned int end_buffer_index, end_buffer_offset; 908 void *p, *end; 909 910 p = ctx->pointer; 911 if (!p) 912 return; 913 914 end_buffer_index = ar_search_last_active_buffer(ctx, 915 &end_buffer_offset); 916 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset); 917 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset; 918 919 if (end_buffer_index < ar_first_buffer_index(ctx)) { 920 /* 921 * The filled part of the overall buffer wraps around; handle 922 * all packets up to the buffer end here. If the last packet 923 * wraps around, its tail will be visible after the buffer end 924 * because the buffer start pages are mapped there again. 925 */ 926 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE; 927 p = handle_ar_packets(ctx, p, buffer_end); 928 if (p < buffer_end) 929 goto error; 930 /* adjust p to point back into the actual buffer */ 931 p -= AR_BUFFERS * PAGE_SIZE; 932 } 933 934 p = handle_ar_packets(ctx, p, end); 935 if (p != end) { 936 if (p > end) 937 ar_context_abort(ctx, "inconsistent descriptor"); 938 goto error; 939 } 940 941 ctx->pointer = p; 942 ar_recycle_buffers(ctx, end_buffer_index); 943 944 return; 945 946 error: 947 ctx->pointer = NULL; 948 } 949 950 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, 951 unsigned int descriptors_offset, u32 regs) 952 { 953 unsigned int i; 954 dma_addr_t dma_addr; 955 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES]; 956 struct descriptor *d; 957 958 ctx->regs = regs; 959 ctx->ohci = ohci; 960 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); 961 962 for (i = 0; i < AR_BUFFERS; i++) { 963 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32); 964 if (!ctx->pages[i]) 965 goto out_of_memory; 966 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i], 967 0, PAGE_SIZE, DMA_FROM_DEVICE); 968 if (dma_mapping_error(ohci->card.device, dma_addr)) { 969 __free_page(ctx->pages[i]); 970 ctx->pages[i] = NULL; 971 goto out_of_memory; 972 } 973 set_page_private(ctx->pages[i], dma_addr); 974 } 975 976 for (i = 0; i < AR_BUFFERS; i++) 977 pages[i] = ctx->pages[i]; 978 for (i = 0; i < AR_WRAPAROUND_PAGES; i++) 979 pages[AR_BUFFERS + i] = ctx->pages[i]; 980 ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES, 981 -1, PAGE_KERNEL); 982 if (!ctx->buffer) 983 goto out_of_memory; 984 985 ctx->descriptors = ohci->misc_buffer + descriptors_offset; 986 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset; 987 988 for (i = 0; i < AR_BUFFERS; i++) { 989 d = &ctx->descriptors[i]; 990 d->req_count = cpu_to_le16(PAGE_SIZE); 991 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 992 DESCRIPTOR_STATUS | 993 DESCRIPTOR_BRANCH_ALWAYS); 994 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i)); 995 d->branch_address = cpu_to_le32(ctx->descriptors_bus + 996 ar_next_buffer_index(i) * sizeof(struct descriptor)); 997 } 998 999 return 0; 1000 1001 out_of_memory: 1002 ar_context_release(ctx); 1003 1004 return -ENOMEM; 1005 } 1006 1007 static void ar_context_run(struct ar_context *ctx) 1008 { 1009 unsigned int i; 1010 1011 for (i = 0; i < AR_BUFFERS; i++) 1012 ar_context_link_page(ctx, i); 1013 1014 ctx->pointer = ctx->buffer; 1015 1016 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1); 1017 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); 1018 } 1019 1020 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z) 1021 { 1022 __le16 branch; 1023 1024 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS); 1025 1026 /* figure out which descriptor the branch address goes in */ 1027 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 1028 return d; 1029 else 1030 return d + z - 1; 1031 } 1032 1033 static void context_tasklet(unsigned long data) 1034 { 1035 struct context *ctx = (struct context *) data; 1036 struct descriptor *d, *last; 1037 u32 address; 1038 int z; 1039 struct descriptor_buffer *desc; 1040 1041 desc = list_entry(ctx->buffer_list.next, 1042 struct descriptor_buffer, list); 1043 last = ctx->last; 1044 while (last->branch_address != 0) { 1045 struct descriptor_buffer *old_desc = desc; 1046 address = le32_to_cpu(last->branch_address); 1047 z = address & 0xf; 1048 address &= ~0xf; 1049 1050 /* If the branch address points to a buffer outside of the 1051 * current buffer, advance to the next buffer. */ 1052 if (address < desc->buffer_bus || 1053 address >= desc->buffer_bus + desc->used) 1054 desc = list_entry(desc->list.next, 1055 struct descriptor_buffer, list); 1056 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d); 1057 last = find_branch_descriptor(d, z); 1058 1059 if (!ctx->callback(ctx, d, last)) 1060 break; 1061 1062 if (old_desc != desc) { 1063 /* If we've advanced to the next buffer, move the 1064 * previous buffer to the free list. */ 1065 unsigned long flags; 1066 old_desc->used = 0; 1067 spin_lock_irqsave(&ctx->ohci->lock, flags); 1068 list_move_tail(&old_desc->list, &ctx->buffer_list); 1069 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1070 } 1071 ctx->last = last; 1072 } 1073 } 1074 1075 /* 1076 * Allocate a new buffer and add it to the list of free buffers for this 1077 * context. Must be called with ohci->lock held. 1078 */ 1079 static int context_add_buffer(struct context *ctx) 1080 { 1081 struct descriptor_buffer *desc; 1082 dma_addr_t uninitialized_var(bus_addr); 1083 int offset; 1084 1085 /* 1086 * 16MB of descriptors should be far more than enough for any DMA 1087 * program. This will catch run-away userspace or DoS attacks. 1088 */ 1089 if (ctx->total_allocation >= 16*1024*1024) 1090 return -ENOMEM; 1091 1092 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE, 1093 &bus_addr, GFP_ATOMIC); 1094 if (!desc) 1095 return -ENOMEM; 1096 1097 offset = (void *)&desc->buffer - (void *)desc; 1098 desc->buffer_size = PAGE_SIZE - offset; 1099 desc->buffer_bus = bus_addr + offset; 1100 desc->used = 0; 1101 1102 list_add_tail(&desc->list, &ctx->buffer_list); 1103 ctx->total_allocation += PAGE_SIZE; 1104 1105 return 0; 1106 } 1107 1108 static int context_init(struct context *ctx, struct fw_ohci *ohci, 1109 u32 regs, descriptor_callback_t callback) 1110 { 1111 ctx->ohci = ohci; 1112 ctx->regs = regs; 1113 ctx->total_allocation = 0; 1114 1115 INIT_LIST_HEAD(&ctx->buffer_list); 1116 if (context_add_buffer(ctx) < 0) 1117 return -ENOMEM; 1118 1119 ctx->buffer_tail = list_entry(ctx->buffer_list.next, 1120 struct descriptor_buffer, list); 1121 1122 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); 1123 ctx->callback = callback; 1124 1125 /* 1126 * We put a dummy descriptor in the buffer that has a NULL 1127 * branch address and looks like it's been sent. That way we 1128 * have a descriptor to append DMA programs to. 1129 */ 1130 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer)); 1131 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST); 1132 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011); 1133 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer); 1134 ctx->last = ctx->buffer_tail->buffer; 1135 ctx->prev = ctx->buffer_tail->buffer; 1136 1137 return 0; 1138 } 1139 1140 static void context_release(struct context *ctx) 1141 { 1142 struct fw_card *card = &ctx->ohci->card; 1143 struct descriptor_buffer *desc, *tmp; 1144 1145 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list) 1146 dma_free_coherent(card->device, PAGE_SIZE, desc, 1147 desc->buffer_bus - 1148 ((void *)&desc->buffer - (void *)desc)); 1149 } 1150 1151 /* Must be called with ohci->lock held */ 1152 static struct descriptor *context_get_descriptors(struct context *ctx, 1153 int z, dma_addr_t *d_bus) 1154 { 1155 struct descriptor *d = NULL; 1156 struct descriptor_buffer *desc = ctx->buffer_tail; 1157 1158 if (z * sizeof(*d) > desc->buffer_size) 1159 return NULL; 1160 1161 if (z * sizeof(*d) > desc->buffer_size - desc->used) { 1162 /* No room for the descriptor in this buffer, so advance to the 1163 * next one. */ 1164 1165 if (desc->list.next == &ctx->buffer_list) { 1166 /* If there is no free buffer next in the list, 1167 * allocate one. */ 1168 if (context_add_buffer(ctx) < 0) 1169 return NULL; 1170 } 1171 desc = list_entry(desc->list.next, 1172 struct descriptor_buffer, list); 1173 ctx->buffer_tail = desc; 1174 } 1175 1176 d = desc->buffer + desc->used / sizeof(*d); 1177 memset(d, 0, z * sizeof(*d)); 1178 *d_bus = desc->buffer_bus + desc->used; 1179 1180 return d; 1181 } 1182 1183 static void context_run(struct context *ctx, u32 extra) 1184 { 1185 struct fw_ohci *ohci = ctx->ohci; 1186 1187 reg_write(ohci, COMMAND_PTR(ctx->regs), 1188 le32_to_cpu(ctx->last->branch_address)); 1189 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); 1190 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); 1191 ctx->running = true; 1192 flush_writes(ohci); 1193 } 1194 1195 static void context_append(struct context *ctx, 1196 struct descriptor *d, int z, int extra) 1197 { 1198 dma_addr_t d_bus; 1199 struct descriptor_buffer *desc = ctx->buffer_tail; 1200 1201 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d); 1202 1203 desc->used += (z + extra) * sizeof(*d); 1204 1205 wmb(); /* finish init of new descriptors before branch_address update */ 1206 ctx->prev->branch_address = cpu_to_le32(d_bus | z); 1207 ctx->prev = find_branch_descriptor(d, z); 1208 } 1209 1210 static void context_stop(struct context *ctx) 1211 { 1212 u32 reg; 1213 int i; 1214 1215 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 1216 ctx->running = false; 1217 1218 for (i = 0; i < 1000; i++) { 1219 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs)); 1220 if ((reg & CONTEXT_ACTIVE) == 0) 1221 return; 1222 1223 if (i) 1224 udelay(10); 1225 } 1226 fw_error("Error: DMA context still active (0x%08x)\n", reg); 1227 } 1228 1229 struct driver_data { 1230 u8 inline_data[8]; 1231 struct fw_packet *packet; 1232 }; 1233 1234 /* 1235 * This function apppends a packet to the DMA queue for transmission. 1236 * Must always be called with the ochi->lock held to ensure proper 1237 * generation handling and locking around packet queue manipulation. 1238 */ 1239 static int at_context_queue_packet(struct context *ctx, 1240 struct fw_packet *packet) 1241 { 1242 struct fw_ohci *ohci = ctx->ohci; 1243 dma_addr_t d_bus, uninitialized_var(payload_bus); 1244 struct driver_data *driver_data; 1245 struct descriptor *d, *last; 1246 __le32 *header; 1247 int z, tcode; 1248 1249 d = context_get_descriptors(ctx, 4, &d_bus); 1250 if (d == NULL) { 1251 packet->ack = RCODE_SEND_ERROR; 1252 return -1; 1253 } 1254 1255 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 1256 d[0].res_count = cpu_to_le16(packet->timestamp); 1257 1258 /* 1259 * The DMA format for asyncronous link packets is different 1260 * from the IEEE1394 layout, so shift the fields around 1261 * accordingly. 1262 */ 1263 1264 tcode = (packet->header[0] >> 4) & 0x0f; 1265 header = (__le32 *) &d[1]; 1266 switch (tcode) { 1267 case TCODE_WRITE_QUADLET_REQUEST: 1268 case TCODE_WRITE_BLOCK_REQUEST: 1269 case TCODE_WRITE_RESPONSE: 1270 case TCODE_READ_QUADLET_REQUEST: 1271 case TCODE_READ_BLOCK_REQUEST: 1272 case TCODE_READ_QUADLET_RESPONSE: 1273 case TCODE_READ_BLOCK_RESPONSE: 1274 case TCODE_LOCK_REQUEST: 1275 case TCODE_LOCK_RESPONSE: 1276 header[0] = cpu_to_le32((packet->header[0] & 0xffff) | 1277 (packet->speed << 16)); 1278 header[1] = cpu_to_le32((packet->header[1] & 0xffff) | 1279 (packet->header[0] & 0xffff0000)); 1280 header[2] = cpu_to_le32(packet->header[2]); 1281 1282 if (TCODE_IS_BLOCK_PACKET(tcode)) 1283 header[3] = cpu_to_le32(packet->header[3]); 1284 else 1285 header[3] = (__force __le32) packet->header[3]; 1286 1287 d[0].req_count = cpu_to_le16(packet->header_length); 1288 break; 1289 1290 case TCODE_LINK_INTERNAL: 1291 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) | 1292 (packet->speed << 16)); 1293 header[1] = cpu_to_le32(packet->header[1]); 1294 header[2] = cpu_to_le32(packet->header[2]); 1295 d[0].req_count = cpu_to_le16(12); 1296 1297 if (is_ping_packet(&packet->header[1])) 1298 d[0].control |= cpu_to_le16(DESCRIPTOR_PING); 1299 break; 1300 1301 case TCODE_STREAM_DATA: 1302 header[0] = cpu_to_le32((packet->header[0] & 0xffff) | 1303 (packet->speed << 16)); 1304 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000); 1305 d[0].req_count = cpu_to_le16(8); 1306 break; 1307 1308 default: 1309 /* BUG(); */ 1310 packet->ack = RCODE_SEND_ERROR; 1311 return -1; 1312 } 1313 1314 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor)); 1315 driver_data = (struct driver_data *) &d[3]; 1316 driver_data->packet = packet; 1317 packet->driver_data = driver_data; 1318 1319 if (packet->payload_length > 0) { 1320 if (packet->payload_length > sizeof(driver_data->inline_data)) { 1321 payload_bus = dma_map_single(ohci->card.device, 1322 packet->payload, 1323 packet->payload_length, 1324 DMA_TO_DEVICE); 1325 if (dma_mapping_error(ohci->card.device, payload_bus)) { 1326 packet->ack = RCODE_SEND_ERROR; 1327 return -1; 1328 } 1329 packet->payload_bus = payload_bus; 1330 packet->payload_mapped = true; 1331 } else { 1332 memcpy(driver_data->inline_data, packet->payload, 1333 packet->payload_length); 1334 payload_bus = d_bus + 3 * sizeof(*d); 1335 } 1336 1337 d[2].req_count = cpu_to_le16(packet->payload_length); 1338 d[2].data_address = cpu_to_le32(payload_bus); 1339 last = &d[2]; 1340 z = 3; 1341 } else { 1342 last = &d[0]; 1343 z = 2; 1344 } 1345 1346 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 1347 DESCRIPTOR_IRQ_ALWAYS | 1348 DESCRIPTOR_BRANCH_ALWAYS); 1349 1350 /* FIXME: Document how the locking works. */ 1351 if (ohci->generation != packet->generation) { 1352 if (packet->payload_mapped) 1353 dma_unmap_single(ohci->card.device, payload_bus, 1354 packet->payload_length, DMA_TO_DEVICE); 1355 packet->ack = RCODE_GENERATION; 1356 return -1; 1357 } 1358 1359 context_append(ctx, d, z, 4 - z); 1360 1361 if (ctx->running) 1362 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 1363 else 1364 context_run(ctx, 0); 1365 1366 return 0; 1367 } 1368 1369 static void at_context_flush(struct context *ctx) 1370 { 1371 tasklet_disable(&ctx->tasklet); 1372 1373 ctx->flushing = true; 1374 context_tasklet((unsigned long)ctx); 1375 ctx->flushing = false; 1376 1377 tasklet_enable(&ctx->tasklet); 1378 } 1379 1380 static int handle_at_packet(struct context *context, 1381 struct descriptor *d, 1382 struct descriptor *last) 1383 { 1384 struct driver_data *driver_data; 1385 struct fw_packet *packet; 1386 struct fw_ohci *ohci = context->ohci; 1387 int evt; 1388 1389 if (last->transfer_status == 0 && !context->flushing) 1390 /* This descriptor isn't done yet, stop iteration. */ 1391 return 0; 1392 1393 driver_data = (struct driver_data *) &d[3]; 1394 packet = driver_data->packet; 1395 if (packet == NULL) 1396 /* This packet was cancelled, just continue. */ 1397 return 1; 1398 1399 if (packet->payload_mapped) 1400 dma_unmap_single(ohci->card.device, packet->payload_bus, 1401 packet->payload_length, DMA_TO_DEVICE); 1402 1403 evt = le16_to_cpu(last->transfer_status) & 0x1f; 1404 packet->timestamp = le16_to_cpu(last->res_count); 1405 1406 log_ar_at_event('T', packet->speed, packet->header, evt); 1407 1408 switch (evt) { 1409 case OHCI1394_evt_timeout: 1410 /* Async response transmit timed out. */ 1411 packet->ack = RCODE_CANCELLED; 1412 break; 1413 1414 case OHCI1394_evt_flushed: 1415 /* 1416 * The packet was flushed should give same error as 1417 * when we try to use a stale generation count. 1418 */ 1419 packet->ack = RCODE_GENERATION; 1420 break; 1421 1422 case OHCI1394_evt_missing_ack: 1423 if (context->flushing) 1424 packet->ack = RCODE_GENERATION; 1425 else { 1426 /* 1427 * Using a valid (current) generation count, but the 1428 * node is not on the bus or not sending acks. 1429 */ 1430 packet->ack = RCODE_NO_ACK; 1431 } 1432 break; 1433 1434 case ACK_COMPLETE + 0x10: 1435 case ACK_PENDING + 0x10: 1436 case ACK_BUSY_X + 0x10: 1437 case ACK_BUSY_A + 0x10: 1438 case ACK_BUSY_B + 0x10: 1439 case ACK_DATA_ERROR + 0x10: 1440 case ACK_TYPE_ERROR + 0x10: 1441 packet->ack = evt - 0x10; 1442 break; 1443 1444 case OHCI1394_evt_no_status: 1445 if (context->flushing) { 1446 packet->ack = RCODE_GENERATION; 1447 break; 1448 } 1449 /* fall through */ 1450 1451 default: 1452 packet->ack = RCODE_SEND_ERROR; 1453 break; 1454 } 1455 1456 packet->callback(packet, &ohci->card, packet->ack); 1457 1458 return 1; 1459 } 1460 1461 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff) 1462 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f) 1463 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff) 1464 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff) 1465 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff) 1466 1467 static void handle_local_rom(struct fw_ohci *ohci, 1468 struct fw_packet *packet, u32 csr) 1469 { 1470 struct fw_packet response; 1471 int tcode, length, i; 1472 1473 tcode = HEADER_GET_TCODE(packet->header[0]); 1474 if (TCODE_IS_BLOCK_PACKET(tcode)) 1475 length = HEADER_GET_DATA_LENGTH(packet->header[3]); 1476 else 1477 length = 4; 1478 1479 i = csr - CSR_CONFIG_ROM; 1480 if (i + length > CONFIG_ROM_SIZE) { 1481 fw_fill_response(&response, packet->header, 1482 RCODE_ADDRESS_ERROR, NULL, 0); 1483 } else if (!TCODE_IS_READ_REQUEST(tcode)) { 1484 fw_fill_response(&response, packet->header, 1485 RCODE_TYPE_ERROR, NULL, 0); 1486 } else { 1487 fw_fill_response(&response, packet->header, RCODE_COMPLETE, 1488 (void *) ohci->config_rom + i, length); 1489 } 1490 1491 fw_core_handle_response(&ohci->card, &response); 1492 } 1493 1494 static void handle_local_lock(struct fw_ohci *ohci, 1495 struct fw_packet *packet, u32 csr) 1496 { 1497 struct fw_packet response; 1498 int tcode, length, ext_tcode, sel, try; 1499 __be32 *payload, lock_old; 1500 u32 lock_arg, lock_data; 1501 1502 tcode = HEADER_GET_TCODE(packet->header[0]); 1503 length = HEADER_GET_DATA_LENGTH(packet->header[3]); 1504 payload = packet->payload; 1505 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]); 1506 1507 if (tcode == TCODE_LOCK_REQUEST && 1508 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { 1509 lock_arg = be32_to_cpu(payload[0]); 1510 lock_data = be32_to_cpu(payload[1]); 1511 } else if (tcode == TCODE_READ_QUADLET_REQUEST) { 1512 lock_arg = 0; 1513 lock_data = 0; 1514 } else { 1515 fw_fill_response(&response, packet->header, 1516 RCODE_TYPE_ERROR, NULL, 0); 1517 goto out; 1518 } 1519 1520 sel = (csr - CSR_BUS_MANAGER_ID) / 4; 1521 reg_write(ohci, OHCI1394_CSRData, lock_data); 1522 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); 1523 reg_write(ohci, OHCI1394_CSRControl, sel); 1524 1525 for (try = 0; try < 20; try++) 1526 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) { 1527 lock_old = cpu_to_be32(reg_read(ohci, 1528 OHCI1394_CSRData)); 1529 fw_fill_response(&response, packet->header, 1530 RCODE_COMPLETE, 1531 &lock_old, sizeof(lock_old)); 1532 goto out; 1533 } 1534 1535 fw_error("swap not done (CSR lock timeout)\n"); 1536 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0); 1537 1538 out: 1539 fw_core_handle_response(&ohci->card, &response); 1540 } 1541 1542 static void handle_local_request(struct context *ctx, struct fw_packet *packet) 1543 { 1544 u64 offset, csr; 1545 1546 if (ctx == &ctx->ohci->at_request_ctx) { 1547 packet->ack = ACK_PENDING; 1548 packet->callback(packet, &ctx->ohci->card, packet->ack); 1549 } 1550 1551 offset = 1552 ((unsigned long long) 1553 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) | 1554 packet->header[2]; 1555 csr = offset - CSR_REGISTER_BASE; 1556 1557 /* Handle config rom reads. */ 1558 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) 1559 handle_local_rom(ctx->ohci, packet, csr); 1560 else switch (csr) { 1561 case CSR_BUS_MANAGER_ID: 1562 case CSR_BANDWIDTH_AVAILABLE: 1563 case CSR_CHANNELS_AVAILABLE_HI: 1564 case CSR_CHANNELS_AVAILABLE_LO: 1565 handle_local_lock(ctx->ohci, packet, csr); 1566 break; 1567 default: 1568 if (ctx == &ctx->ohci->at_request_ctx) 1569 fw_core_handle_request(&ctx->ohci->card, packet); 1570 else 1571 fw_core_handle_response(&ctx->ohci->card, packet); 1572 break; 1573 } 1574 1575 if (ctx == &ctx->ohci->at_response_ctx) { 1576 packet->ack = ACK_COMPLETE; 1577 packet->callback(packet, &ctx->ohci->card, packet->ack); 1578 } 1579 } 1580 1581 static void at_context_transmit(struct context *ctx, struct fw_packet *packet) 1582 { 1583 unsigned long flags; 1584 int ret; 1585 1586 spin_lock_irqsave(&ctx->ohci->lock, flags); 1587 1588 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id && 1589 ctx->ohci->generation == packet->generation) { 1590 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1591 handle_local_request(ctx, packet); 1592 return; 1593 } 1594 1595 ret = at_context_queue_packet(ctx, packet); 1596 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1597 1598 if (ret < 0) 1599 packet->callback(packet, &ctx->ohci->card, packet->ack); 1600 1601 } 1602 1603 static void detect_dead_context(struct fw_ohci *ohci, 1604 const char *name, unsigned int regs) 1605 { 1606 u32 ctl; 1607 1608 ctl = reg_read(ohci, CONTROL_SET(regs)); 1609 if (ctl & CONTEXT_DEAD) { 1610 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG 1611 fw_error("DMA context %s has stopped, error code: %s\n", 1612 name, evts[ctl & 0x1f]); 1613 #else 1614 fw_error("DMA context %s has stopped, error code: %#x\n", 1615 name, ctl & 0x1f); 1616 #endif 1617 } 1618 } 1619 1620 static void handle_dead_contexts(struct fw_ohci *ohci) 1621 { 1622 unsigned int i; 1623 char name[8]; 1624 1625 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase); 1626 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase); 1627 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase); 1628 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase); 1629 for (i = 0; i < 32; ++i) { 1630 if (!(ohci->it_context_support & (1 << i))) 1631 continue; 1632 sprintf(name, "IT%u", i); 1633 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i)); 1634 } 1635 for (i = 0; i < 32; ++i) { 1636 if (!(ohci->ir_context_support & (1 << i))) 1637 continue; 1638 sprintf(name, "IR%u", i); 1639 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i)); 1640 } 1641 /* TODO: maybe try to flush and restart the dead contexts */ 1642 } 1643 1644 static u32 cycle_timer_ticks(u32 cycle_timer) 1645 { 1646 u32 ticks; 1647 1648 ticks = cycle_timer & 0xfff; 1649 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff); 1650 ticks += (3072 * 8000) * (cycle_timer >> 25); 1651 1652 return ticks; 1653 } 1654 1655 /* 1656 * Some controllers exhibit one or more of the following bugs when updating the 1657 * iso cycle timer register: 1658 * - When the lowest six bits are wrapping around to zero, a read that happens 1659 * at the same time will return garbage in the lowest ten bits. 1660 * - When the cycleOffset field wraps around to zero, the cycleCount field is 1661 * not incremented for about 60 ns. 1662 * - Occasionally, the entire register reads zero. 1663 * 1664 * To catch these, we read the register three times and ensure that the 1665 * difference between each two consecutive reads is approximately the same, i.e. 1666 * less than twice the other. Furthermore, any negative difference indicates an 1667 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to 1668 * execute, so we have enough precision to compute the ratio of the differences.) 1669 */ 1670 static u32 get_cycle_time(struct fw_ohci *ohci) 1671 { 1672 u32 c0, c1, c2; 1673 u32 t0, t1, t2; 1674 s32 diff01, diff12; 1675 int i; 1676 1677 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1678 1679 if (ohci->quirks & QUIRK_CYCLE_TIMER) { 1680 i = 0; 1681 c1 = c2; 1682 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1683 do { 1684 c0 = c1; 1685 c1 = c2; 1686 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1687 t0 = cycle_timer_ticks(c0); 1688 t1 = cycle_timer_ticks(c1); 1689 t2 = cycle_timer_ticks(c2); 1690 diff01 = t1 - t0; 1691 diff12 = t2 - t1; 1692 } while ((diff01 <= 0 || diff12 <= 0 || 1693 diff01 / diff12 >= 2 || diff12 / diff01 >= 2) 1694 && i++ < 20); 1695 } 1696 1697 return c2; 1698 } 1699 1700 /* 1701 * This function has to be called at least every 64 seconds. The bus_time 1702 * field stores not only the upper 25 bits of the BUS_TIME register but also 1703 * the most significant bit of the cycle timer in bit 6 so that we can detect 1704 * changes in this bit. 1705 */ 1706 static u32 update_bus_time(struct fw_ohci *ohci) 1707 { 1708 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25; 1709 1710 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40)) 1711 ohci->bus_time += 0x40; 1712 1713 return ohci->bus_time | cycle_time_seconds; 1714 } 1715 1716 static void bus_reset_tasklet(unsigned long data) 1717 { 1718 struct fw_ohci *ohci = (struct fw_ohci *)data; 1719 int self_id_count, i, j, reg; 1720 int generation, new_generation; 1721 unsigned long flags; 1722 void *free_rom = NULL; 1723 dma_addr_t free_rom_bus = 0; 1724 bool is_new_root; 1725 1726 reg = reg_read(ohci, OHCI1394_NodeID); 1727 if (!(reg & OHCI1394_NodeID_idValid)) { 1728 fw_notify("node ID not valid, new bus reset in progress\n"); 1729 return; 1730 } 1731 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { 1732 fw_notify("malconfigured bus\n"); 1733 return; 1734 } 1735 ohci->node_id = reg & (OHCI1394_NodeID_busNumber | 1736 OHCI1394_NodeID_nodeNumber); 1737 1738 is_new_root = (reg & OHCI1394_NodeID_root) != 0; 1739 if (!(ohci->is_root && is_new_root)) 1740 reg_write(ohci, OHCI1394_LinkControlSet, 1741 OHCI1394_LinkControl_cycleMaster); 1742 ohci->is_root = is_new_root; 1743 1744 reg = reg_read(ohci, OHCI1394_SelfIDCount); 1745 if (reg & OHCI1394_SelfIDCount_selfIDError) { 1746 fw_notify("inconsistent self IDs\n"); 1747 return; 1748 } 1749 /* 1750 * The count in the SelfIDCount register is the number of 1751 * bytes in the self ID receive buffer. Since we also receive 1752 * the inverted quadlets and a header quadlet, we shift one 1753 * bit extra to get the actual number of self IDs. 1754 */ 1755 self_id_count = (reg >> 3) & 0xff; 1756 if (self_id_count == 0 || self_id_count > 252) { 1757 fw_notify("inconsistent self IDs\n"); 1758 return; 1759 } 1760 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff; 1761 rmb(); 1762 1763 for (i = 1, j = 0; j < self_id_count; i += 2, j++) { 1764 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) { 1765 fw_notify("inconsistent self IDs\n"); 1766 return; 1767 } 1768 ohci->self_id_buffer[j] = 1769 cond_le32_to_cpu(ohci->self_id_cpu[i]); 1770 } 1771 rmb(); 1772 1773 /* 1774 * Check the consistency of the self IDs we just read. The 1775 * problem we face is that a new bus reset can start while we 1776 * read out the self IDs from the DMA buffer. If this happens, 1777 * the DMA buffer will be overwritten with new self IDs and we 1778 * will read out inconsistent data. The OHCI specification 1779 * (section 11.2) recommends a technique similar to 1780 * linux/seqlock.h, where we remember the generation of the 1781 * self IDs in the buffer before reading them out and compare 1782 * it to the current generation after reading them out. If 1783 * the two generations match we know we have a consistent set 1784 * of self IDs. 1785 */ 1786 1787 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; 1788 if (new_generation != generation) { 1789 fw_notify("recursive bus reset detected, " 1790 "discarding self ids\n"); 1791 return; 1792 } 1793 1794 /* FIXME: Document how the locking works. */ 1795 spin_lock_irqsave(&ohci->lock, flags); 1796 1797 ohci->generation = -1; /* prevent AT packet queueing */ 1798 context_stop(&ohci->at_request_ctx); 1799 context_stop(&ohci->at_response_ctx); 1800 1801 spin_unlock_irqrestore(&ohci->lock, flags); 1802 1803 /* 1804 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent 1805 * packets in the AT queues and software needs to drain them. 1806 * Some OHCI 1.1 controllers (JMicron) apparently require this too. 1807 */ 1808 at_context_flush(&ohci->at_request_ctx); 1809 at_context_flush(&ohci->at_response_ctx); 1810 1811 spin_lock_irqsave(&ohci->lock, flags); 1812 1813 ohci->generation = generation; 1814 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); 1815 1816 if (ohci->quirks & QUIRK_RESET_PACKET) 1817 ohci->request_generation = generation; 1818 1819 /* 1820 * This next bit is unrelated to the AT context stuff but we 1821 * have to do it under the spinlock also. If a new config rom 1822 * was set up before this reset, the old one is now no longer 1823 * in use and we can free it. Update the config rom pointers 1824 * to point to the current config rom and clear the 1825 * next_config_rom pointer so a new update can take place. 1826 */ 1827 1828 if (ohci->next_config_rom != NULL) { 1829 if (ohci->next_config_rom != ohci->config_rom) { 1830 free_rom = ohci->config_rom; 1831 free_rom_bus = ohci->config_rom_bus; 1832 } 1833 ohci->config_rom = ohci->next_config_rom; 1834 ohci->config_rom_bus = ohci->next_config_rom_bus; 1835 ohci->next_config_rom = NULL; 1836 1837 /* 1838 * Restore config_rom image and manually update 1839 * config_rom registers. Writing the header quadlet 1840 * will indicate that the config rom is ready, so we 1841 * do that last. 1842 */ 1843 reg_write(ohci, OHCI1394_BusOptions, 1844 be32_to_cpu(ohci->config_rom[2])); 1845 ohci->config_rom[0] = ohci->next_header; 1846 reg_write(ohci, OHCI1394_ConfigROMhdr, 1847 be32_to_cpu(ohci->next_header)); 1848 } 1849 1850 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA 1851 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0); 1852 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0); 1853 #endif 1854 1855 spin_unlock_irqrestore(&ohci->lock, flags); 1856 1857 if (free_rom) 1858 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 1859 free_rom, free_rom_bus); 1860 1861 log_selfids(ohci->node_id, generation, 1862 self_id_count, ohci->self_id_buffer); 1863 1864 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, 1865 self_id_count, ohci->self_id_buffer, 1866 ohci->csr_state_setclear_abdicate); 1867 ohci->csr_state_setclear_abdicate = false; 1868 } 1869 1870 static irqreturn_t irq_handler(int irq, void *data) 1871 { 1872 struct fw_ohci *ohci = data; 1873 u32 event, iso_event; 1874 int i; 1875 1876 event = reg_read(ohci, OHCI1394_IntEventClear); 1877 1878 if (!event || !~event) 1879 return IRQ_NONE; 1880 1881 /* 1882 * busReset and postedWriteErr must not be cleared yet 1883 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1) 1884 */ 1885 reg_write(ohci, OHCI1394_IntEventClear, 1886 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr)); 1887 log_irqs(event); 1888 1889 if (event & OHCI1394_selfIDComplete) 1890 tasklet_schedule(&ohci->bus_reset_tasklet); 1891 1892 if (event & OHCI1394_RQPkt) 1893 tasklet_schedule(&ohci->ar_request_ctx.tasklet); 1894 1895 if (event & OHCI1394_RSPkt) 1896 tasklet_schedule(&ohci->ar_response_ctx.tasklet); 1897 1898 if (event & OHCI1394_reqTxComplete) 1899 tasklet_schedule(&ohci->at_request_ctx.tasklet); 1900 1901 if (event & OHCI1394_respTxComplete) 1902 tasklet_schedule(&ohci->at_response_ctx.tasklet); 1903 1904 if (event & OHCI1394_isochRx) { 1905 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); 1906 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); 1907 1908 while (iso_event) { 1909 i = ffs(iso_event) - 1; 1910 tasklet_schedule( 1911 &ohci->ir_context_list[i].context.tasklet); 1912 iso_event &= ~(1 << i); 1913 } 1914 } 1915 1916 if (event & OHCI1394_isochTx) { 1917 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); 1918 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); 1919 1920 while (iso_event) { 1921 i = ffs(iso_event) - 1; 1922 tasklet_schedule( 1923 &ohci->it_context_list[i].context.tasklet); 1924 iso_event &= ~(1 << i); 1925 } 1926 } 1927 1928 if (unlikely(event & OHCI1394_regAccessFail)) 1929 fw_error("Register access failure - " 1930 "please notify linux1394-devel@lists.sf.net\n"); 1931 1932 if (unlikely(event & OHCI1394_postedWriteErr)) { 1933 reg_read(ohci, OHCI1394_PostedWriteAddressHi); 1934 reg_read(ohci, OHCI1394_PostedWriteAddressLo); 1935 reg_write(ohci, OHCI1394_IntEventClear, 1936 OHCI1394_postedWriteErr); 1937 fw_error("PCI posted write error\n"); 1938 } 1939 1940 if (unlikely(event & OHCI1394_cycleTooLong)) { 1941 if (printk_ratelimit()) 1942 fw_notify("isochronous cycle too long\n"); 1943 reg_write(ohci, OHCI1394_LinkControlSet, 1944 OHCI1394_LinkControl_cycleMaster); 1945 } 1946 1947 if (unlikely(event & OHCI1394_cycleInconsistent)) { 1948 /* 1949 * We need to clear this event bit in order to make 1950 * cycleMatch isochronous I/O work. In theory we should 1951 * stop active cycleMatch iso contexts now and restart 1952 * them at least two cycles later. (FIXME?) 1953 */ 1954 if (printk_ratelimit()) 1955 fw_notify("isochronous cycle inconsistent\n"); 1956 } 1957 1958 if (unlikely(event & OHCI1394_unrecoverableError)) 1959 handle_dead_contexts(ohci); 1960 1961 if (event & OHCI1394_cycle64Seconds) { 1962 spin_lock(&ohci->lock); 1963 update_bus_time(ohci); 1964 spin_unlock(&ohci->lock); 1965 } else 1966 flush_writes(ohci); 1967 1968 return IRQ_HANDLED; 1969 } 1970 1971 static int software_reset(struct fw_ohci *ohci) 1972 { 1973 u32 val; 1974 int i; 1975 1976 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); 1977 for (i = 0; i < 500; i++) { 1978 val = reg_read(ohci, OHCI1394_HCControlSet); 1979 if (!~val) 1980 return -ENODEV; /* Card was ejected. */ 1981 1982 if (!(val & OHCI1394_HCControl_softReset)) 1983 return 0; 1984 1985 msleep(1); 1986 } 1987 1988 return -EBUSY; 1989 } 1990 1991 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length) 1992 { 1993 size_t size = length * 4; 1994 1995 memcpy(dest, src, size); 1996 if (size < CONFIG_ROM_SIZE) 1997 memset(&dest[length], 0, CONFIG_ROM_SIZE - size); 1998 } 1999 2000 static int configure_1394a_enhancements(struct fw_ohci *ohci) 2001 { 2002 bool enable_1394a; 2003 int ret, clear, set, offset; 2004 2005 /* Check if the driver should configure link and PHY. */ 2006 if (!(reg_read(ohci, OHCI1394_HCControlSet) & 2007 OHCI1394_HCControl_programPhyEnable)) 2008 return 0; 2009 2010 /* Paranoia: check whether the PHY supports 1394a, too. */ 2011 enable_1394a = false; 2012 ret = read_phy_reg(ohci, 2); 2013 if (ret < 0) 2014 return ret; 2015 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) { 2016 ret = read_paged_phy_reg(ohci, 1, 8); 2017 if (ret < 0) 2018 return ret; 2019 if (ret >= 1) 2020 enable_1394a = true; 2021 } 2022 2023 if (ohci->quirks & QUIRK_NO_1394A) 2024 enable_1394a = false; 2025 2026 /* Configure PHY and link consistently. */ 2027 if (enable_1394a) { 2028 clear = 0; 2029 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2030 } else { 2031 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2032 set = 0; 2033 } 2034 ret = update_phy_reg(ohci, 5, clear, set); 2035 if (ret < 0) 2036 return ret; 2037 2038 if (enable_1394a) 2039 offset = OHCI1394_HCControlSet; 2040 else 2041 offset = OHCI1394_HCControlClear; 2042 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable); 2043 2044 /* Clean up: configuration has been taken care of. */ 2045 reg_write(ohci, OHCI1394_HCControlClear, 2046 OHCI1394_HCControl_programPhyEnable); 2047 2048 return 0; 2049 } 2050 2051 static int ohci_enable(struct fw_card *card, 2052 const __be32 *config_rom, size_t length) 2053 { 2054 struct fw_ohci *ohci = fw_ohci(card); 2055 struct pci_dev *dev = to_pci_dev(card->device); 2056 u32 lps, seconds, version, irqs; 2057 int i, ret; 2058 2059 if (software_reset(ohci)) { 2060 fw_error("Failed to reset ohci card.\n"); 2061 return -EBUSY; 2062 } 2063 2064 /* 2065 * Now enable LPS, which we need in order to start accessing 2066 * most of the registers. In fact, on some cards (ALI M5251), 2067 * accessing registers in the SClk domain without LPS enabled 2068 * will lock up the machine. Wait 50msec to make sure we have 2069 * full link enabled. However, with some cards (well, at least 2070 * a JMicron PCIe card), we have to try again sometimes. 2071 */ 2072 reg_write(ohci, OHCI1394_HCControlSet, 2073 OHCI1394_HCControl_LPS | 2074 OHCI1394_HCControl_postedWriteEnable); 2075 flush_writes(ohci); 2076 2077 for (lps = 0, i = 0; !lps && i < 3; i++) { 2078 msleep(50); 2079 lps = reg_read(ohci, OHCI1394_HCControlSet) & 2080 OHCI1394_HCControl_LPS; 2081 } 2082 2083 if (!lps) { 2084 fw_error("Failed to set Link Power Status\n"); 2085 return -EIO; 2086 } 2087 2088 reg_write(ohci, OHCI1394_HCControlClear, 2089 OHCI1394_HCControl_noByteSwapData); 2090 2091 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); 2092 reg_write(ohci, OHCI1394_LinkControlSet, 2093 OHCI1394_LinkControl_cycleTimerEnable | 2094 OHCI1394_LinkControl_cycleMaster); 2095 2096 reg_write(ohci, OHCI1394_ATRetries, 2097 OHCI1394_MAX_AT_REQ_RETRIES | 2098 (OHCI1394_MAX_AT_RESP_RETRIES << 4) | 2099 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) | 2100 (200 << 16)); 2101 2102 seconds = lower_32_bits(get_seconds()); 2103 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25); 2104 ohci->bus_time = seconds & ~0x3f; 2105 2106 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 2107 if (version >= OHCI_VERSION_1_1) { 2108 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi, 2109 0xfffffffe); 2110 card->broadcast_channel_auto_allocated = true; 2111 } 2112 2113 /* Get implemented bits of the priority arbitration request counter. */ 2114 reg_write(ohci, OHCI1394_FairnessControl, 0x3f); 2115 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f; 2116 reg_write(ohci, OHCI1394_FairnessControl, 0); 2117 card->priority_budget_implemented = ohci->pri_req_max != 0; 2118 2119 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000); 2120 reg_write(ohci, OHCI1394_IntEventClear, ~0); 2121 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 2122 2123 ret = configure_1394a_enhancements(ohci); 2124 if (ret < 0) 2125 return ret; 2126 2127 /* Activate link_on bit and contender bit in our self ID packets.*/ 2128 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER); 2129 if (ret < 0) 2130 return ret; 2131 2132 /* 2133 * When the link is not yet enabled, the atomic config rom 2134 * update mechanism described below in ohci_set_config_rom() 2135 * is not active. We have to update ConfigRomHeader and 2136 * BusOptions manually, and the write to ConfigROMmap takes 2137 * effect immediately. We tie this to the enabling of the 2138 * link, so we have a valid config rom before enabling - the 2139 * OHCI requires that ConfigROMhdr and BusOptions have valid 2140 * values before enabling. 2141 * 2142 * However, when the ConfigROMmap is written, some controllers 2143 * always read back quadlets 0 and 2 from the config rom to 2144 * the ConfigRomHeader and BusOptions registers on bus reset. 2145 * They shouldn't do that in this initial case where the link 2146 * isn't enabled. This means we have to use the same 2147 * workaround here, setting the bus header to 0 and then write 2148 * the right values in the bus reset tasklet. 2149 */ 2150 2151 if (config_rom) { 2152 ohci->next_config_rom = 2153 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2154 &ohci->next_config_rom_bus, 2155 GFP_KERNEL); 2156 if (ohci->next_config_rom == NULL) 2157 return -ENOMEM; 2158 2159 copy_config_rom(ohci->next_config_rom, config_rom, length); 2160 } else { 2161 /* 2162 * In the suspend case, config_rom is NULL, which 2163 * means that we just reuse the old config rom. 2164 */ 2165 ohci->next_config_rom = ohci->config_rom; 2166 ohci->next_config_rom_bus = ohci->config_rom_bus; 2167 } 2168 2169 ohci->next_header = ohci->next_config_rom[0]; 2170 ohci->next_config_rom[0] = 0; 2171 reg_write(ohci, OHCI1394_ConfigROMhdr, 0); 2172 reg_write(ohci, OHCI1394_BusOptions, 2173 be32_to_cpu(ohci->next_config_rom[2])); 2174 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2175 2176 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); 2177 2178 if (!(ohci->quirks & QUIRK_NO_MSI)) 2179 pci_enable_msi(dev); 2180 if (request_irq(dev->irq, irq_handler, 2181 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED, 2182 ohci_driver_name, ohci)) { 2183 fw_error("Failed to allocate interrupt %d.\n", dev->irq); 2184 pci_disable_msi(dev); 2185 2186 if (config_rom) { 2187 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2188 ohci->next_config_rom, 2189 ohci->next_config_rom_bus); 2190 ohci->next_config_rom = NULL; 2191 } 2192 return -EIO; 2193 } 2194 2195 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete | 2196 OHCI1394_RQPkt | OHCI1394_RSPkt | 2197 OHCI1394_isochTx | OHCI1394_isochRx | 2198 OHCI1394_postedWriteErr | 2199 OHCI1394_selfIDComplete | 2200 OHCI1394_regAccessFail | 2201 OHCI1394_cycle64Seconds | 2202 OHCI1394_cycleInconsistent | 2203 OHCI1394_unrecoverableError | 2204 OHCI1394_cycleTooLong | 2205 OHCI1394_masterIntEnable; 2206 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS) 2207 irqs |= OHCI1394_busReset; 2208 reg_write(ohci, OHCI1394_IntMaskSet, irqs); 2209 2210 reg_write(ohci, OHCI1394_HCControlSet, 2211 OHCI1394_HCControl_linkEnable | 2212 OHCI1394_HCControl_BIBimageValid); 2213 2214 reg_write(ohci, OHCI1394_LinkControlSet, 2215 OHCI1394_LinkControl_rcvSelfID | 2216 OHCI1394_LinkControl_rcvPhyPkt); 2217 2218 ar_context_run(&ohci->ar_request_ctx); 2219 ar_context_run(&ohci->ar_response_ctx); 2220 2221 flush_writes(ohci); 2222 2223 /* We are ready to go, reset bus to finish initialization. */ 2224 fw_schedule_bus_reset(&ohci->card, false, true); 2225 2226 return 0; 2227 } 2228 2229 static int ohci_set_config_rom(struct fw_card *card, 2230 const __be32 *config_rom, size_t length) 2231 { 2232 struct fw_ohci *ohci; 2233 unsigned long flags; 2234 __be32 *next_config_rom; 2235 dma_addr_t uninitialized_var(next_config_rom_bus); 2236 2237 ohci = fw_ohci(card); 2238 2239 /* 2240 * When the OHCI controller is enabled, the config rom update 2241 * mechanism is a bit tricky, but easy enough to use. See 2242 * section 5.5.6 in the OHCI specification. 2243 * 2244 * The OHCI controller caches the new config rom address in a 2245 * shadow register (ConfigROMmapNext) and needs a bus reset 2246 * for the changes to take place. When the bus reset is 2247 * detected, the controller loads the new values for the 2248 * ConfigRomHeader and BusOptions registers from the specified 2249 * config rom and loads ConfigROMmap from the ConfigROMmapNext 2250 * shadow register. All automatically and atomically. 2251 * 2252 * Now, there's a twist to this story. The automatic load of 2253 * ConfigRomHeader and BusOptions doesn't honor the 2254 * noByteSwapData bit, so with a be32 config rom, the 2255 * controller will load be32 values in to these registers 2256 * during the atomic update, even on litte endian 2257 * architectures. The workaround we use is to put a 0 in the 2258 * header quadlet; 0 is endian agnostic and means that the 2259 * config rom isn't ready yet. In the bus reset tasklet we 2260 * then set up the real values for the two registers. 2261 * 2262 * We use ohci->lock to avoid racing with the code that sets 2263 * ohci->next_config_rom to NULL (see bus_reset_tasklet). 2264 */ 2265 2266 next_config_rom = 2267 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2268 &next_config_rom_bus, GFP_KERNEL); 2269 if (next_config_rom == NULL) 2270 return -ENOMEM; 2271 2272 spin_lock_irqsave(&ohci->lock, flags); 2273 2274 /* 2275 * If there is not an already pending config_rom update, 2276 * push our new allocation into the ohci->next_config_rom 2277 * and then mark the local variable as null so that we 2278 * won't deallocate the new buffer. 2279 * 2280 * OTOH, if there is a pending config_rom update, just 2281 * use that buffer with the new config_rom data, and 2282 * let this routine free the unused DMA allocation. 2283 */ 2284 2285 if (ohci->next_config_rom == NULL) { 2286 ohci->next_config_rom = next_config_rom; 2287 ohci->next_config_rom_bus = next_config_rom_bus; 2288 next_config_rom = NULL; 2289 } 2290 2291 copy_config_rom(ohci->next_config_rom, config_rom, length); 2292 2293 ohci->next_header = config_rom[0]; 2294 ohci->next_config_rom[0] = 0; 2295 2296 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2297 2298 spin_unlock_irqrestore(&ohci->lock, flags); 2299 2300 /* If we didn't use the DMA allocation, delete it. */ 2301 if (next_config_rom != NULL) 2302 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2303 next_config_rom, next_config_rom_bus); 2304 2305 /* 2306 * Now initiate a bus reset to have the changes take 2307 * effect. We clean up the old config rom memory and DMA 2308 * mappings in the bus reset tasklet, since the OHCI 2309 * controller could need to access it before the bus reset 2310 * takes effect. 2311 */ 2312 2313 fw_schedule_bus_reset(&ohci->card, true, true); 2314 2315 return 0; 2316 } 2317 2318 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) 2319 { 2320 struct fw_ohci *ohci = fw_ohci(card); 2321 2322 at_context_transmit(&ohci->at_request_ctx, packet); 2323 } 2324 2325 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) 2326 { 2327 struct fw_ohci *ohci = fw_ohci(card); 2328 2329 at_context_transmit(&ohci->at_response_ctx, packet); 2330 } 2331 2332 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) 2333 { 2334 struct fw_ohci *ohci = fw_ohci(card); 2335 struct context *ctx = &ohci->at_request_ctx; 2336 struct driver_data *driver_data = packet->driver_data; 2337 int ret = -ENOENT; 2338 2339 tasklet_disable(&ctx->tasklet); 2340 2341 if (packet->ack != 0) 2342 goto out; 2343 2344 if (packet->payload_mapped) 2345 dma_unmap_single(ohci->card.device, packet->payload_bus, 2346 packet->payload_length, DMA_TO_DEVICE); 2347 2348 log_ar_at_event('T', packet->speed, packet->header, 0x20); 2349 driver_data->packet = NULL; 2350 packet->ack = RCODE_CANCELLED; 2351 packet->callback(packet, &ohci->card, packet->ack); 2352 ret = 0; 2353 out: 2354 tasklet_enable(&ctx->tasklet); 2355 2356 return ret; 2357 } 2358 2359 static int ohci_enable_phys_dma(struct fw_card *card, 2360 int node_id, int generation) 2361 { 2362 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA 2363 return 0; 2364 #else 2365 struct fw_ohci *ohci = fw_ohci(card); 2366 unsigned long flags; 2367 int n, ret = 0; 2368 2369 /* 2370 * FIXME: Make sure this bitmask is cleared when we clear the busReset 2371 * interrupt bit. Clear physReqResourceAllBuses on bus reset. 2372 */ 2373 2374 spin_lock_irqsave(&ohci->lock, flags); 2375 2376 if (ohci->generation != generation) { 2377 ret = -ESTALE; 2378 goto out; 2379 } 2380 2381 /* 2382 * Note, if the node ID contains a non-local bus ID, physical DMA is 2383 * enabled for _all_ nodes on remote buses. 2384 */ 2385 2386 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; 2387 if (n < 32) 2388 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); 2389 else 2390 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); 2391 2392 flush_writes(ohci); 2393 out: 2394 spin_unlock_irqrestore(&ohci->lock, flags); 2395 2396 return ret; 2397 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */ 2398 } 2399 2400 static u32 ohci_read_csr(struct fw_card *card, int csr_offset) 2401 { 2402 struct fw_ohci *ohci = fw_ohci(card); 2403 unsigned long flags; 2404 u32 value; 2405 2406 switch (csr_offset) { 2407 case CSR_STATE_CLEAR: 2408 case CSR_STATE_SET: 2409 if (ohci->is_root && 2410 (reg_read(ohci, OHCI1394_LinkControlSet) & 2411 OHCI1394_LinkControl_cycleMaster)) 2412 value = CSR_STATE_BIT_CMSTR; 2413 else 2414 value = 0; 2415 if (ohci->csr_state_setclear_abdicate) 2416 value |= CSR_STATE_BIT_ABDICATE; 2417 2418 return value; 2419 2420 case CSR_NODE_IDS: 2421 return reg_read(ohci, OHCI1394_NodeID) << 16; 2422 2423 case CSR_CYCLE_TIME: 2424 return get_cycle_time(ohci); 2425 2426 case CSR_BUS_TIME: 2427 /* 2428 * We might be called just after the cycle timer has wrapped 2429 * around but just before the cycle64Seconds handler, so we 2430 * better check here, too, if the bus time needs to be updated. 2431 */ 2432 spin_lock_irqsave(&ohci->lock, flags); 2433 value = update_bus_time(ohci); 2434 spin_unlock_irqrestore(&ohci->lock, flags); 2435 return value; 2436 2437 case CSR_BUSY_TIMEOUT: 2438 value = reg_read(ohci, OHCI1394_ATRetries); 2439 return (value >> 4) & 0x0ffff00f; 2440 2441 case CSR_PRIORITY_BUDGET: 2442 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) | 2443 (ohci->pri_req_max << 8); 2444 2445 default: 2446 WARN_ON(1); 2447 return 0; 2448 } 2449 } 2450 2451 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value) 2452 { 2453 struct fw_ohci *ohci = fw_ohci(card); 2454 unsigned long flags; 2455 2456 switch (csr_offset) { 2457 case CSR_STATE_CLEAR: 2458 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2459 reg_write(ohci, OHCI1394_LinkControlClear, 2460 OHCI1394_LinkControl_cycleMaster); 2461 flush_writes(ohci); 2462 } 2463 if (value & CSR_STATE_BIT_ABDICATE) 2464 ohci->csr_state_setclear_abdicate = false; 2465 break; 2466 2467 case CSR_STATE_SET: 2468 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2469 reg_write(ohci, OHCI1394_LinkControlSet, 2470 OHCI1394_LinkControl_cycleMaster); 2471 flush_writes(ohci); 2472 } 2473 if (value & CSR_STATE_BIT_ABDICATE) 2474 ohci->csr_state_setclear_abdicate = true; 2475 break; 2476 2477 case CSR_NODE_IDS: 2478 reg_write(ohci, OHCI1394_NodeID, value >> 16); 2479 flush_writes(ohci); 2480 break; 2481 2482 case CSR_CYCLE_TIME: 2483 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value); 2484 reg_write(ohci, OHCI1394_IntEventSet, 2485 OHCI1394_cycleInconsistent); 2486 flush_writes(ohci); 2487 break; 2488 2489 case CSR_BUS_TIME: 2490 spin_lock_irqsave(&ohci->lock, flags); 2491 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f); 2492 spin_unlock_irqrestore(&ohci->lock, flags); 2493 break; 2494 2495 case CSR_BUSY_TIMEOUT: 2496 value = (value & 0xf) | ((value & 0xf) << 4) | 2497 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4); 2498 reg_write(ohci, OHCI1394_ATRetries, value); 2499 flush_writes(ohci); 2500 break; 2501 2502 case CSR_PRIORITY_BUDGET: 2503 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f); 2504 flush_writes(ohci); 2505 break; 2506 2507 default: 2508 WARN_ON(1); 2509 break; 2510 } 2511 } 2512 2513 static void copy_iso_headers(struct iso_context *ctx, void *p) 2514 { 2515 int i = ctx->header_length; 2516 2517 if (i + ctx->base.header_size > PAGE_SIZE) 2518 return; 2519 2520 /* 2521 * The iso header is byteswapped to little endian by 2522 * the controller, but the remaining header quadlets 2523 * are big endian. We want to present all the headers 2524 * as big endian, so we have to swap the first quadlet. 2525 */ 2526 if (ctx->base.header_size > 0) 2527 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4)); 2528 if (ctx->base.header_size > 4) 2529 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p); 2530 if (ctx->base.header_size > 8) 2531 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8); 2532 ctx->header_length += ctx->base.header_size; 2533 } 2534 2535 static int handle_ir_packet_per_buffer(struct context *context, 2536 struct descriptor *d, 2537 struct descriptor *last) 2538 { 2539 struct iso_context *ctx = 2540 container_of(context, struct iso_context, context); 2541 struct descriptor *pd; 2542 __le32 *ir_header; 2543 void *p; 2544 2545 for (pd = d; pd <= last; pd++) 2546 if (pd->transfer_status) 2547 break; 2548 if (pd > last) 2549 /* Descriptor(s) not done yet, stop iteration */ 2550 return 0; 2551 2552 p = last + 1; 2553 copy_iso_headers(ctx, p); 2554 2555 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) { 2556 ir_header = (__le32 *) p; 2557 ctx->base.callback.sc(&ctx->base, 2558 le32_to_cpu(ir_header[0]) & 0xffff, 2559 ctx->header_length, ctx->header, 2560 ctx->base.callback_data); 2561 ctx->header_length = 0; 2562 } 2563 2564 return 1; 2565 } 2566 2567 /* d == last because each descriptor block is only a single descriptor. */ 2568 static int handle_ir_buffer_fill(struct context *context, 2569 struct descriptor *d, 2570 struct descriptor *last) 2571 { 2572 struct iso_context *ctx = 2573 container_of(context, struct iso_context, context); 2574 2575 if (!last->transfer_status) 2576 /* Descriptor(s) not done yet, stop iteration */ 2577 return 0; 2578 2579 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) 2580 ctx->base.callback.mc(&ctx->base, 2581 le32_to_cpu(last->data_address) + 2582 le16_to_cpu(last->req_count) - 2583 le16_to_cpu(last->res_count), 2584 ctx->base.callback_data); 2585 2586 return 1; 2587 } 2588 2589 static int handle_it_packet(struct context *context, 2590 struct descriptor *d, 2591 struct descriptor *last) 2592 { 2593 struct iso_context *ctx = 2594 container_of(context, struct iso_context, context); 2595 int i; 2596 struct descriptor *pd; 2597 2598 for (pd = d; pd <= last; pd++) 2599 if (pd->transfer_status) 2600 break; 2601 if (pd > last) 2602 /* Descriptor(s) not done yet, stop iteration */ 2603 return 0; 2604 2605 i = ctx->header_length; 2606 if (i + 4 < PAGE_SIZE) { 2607 /* Present this value as big-endian to match the receive code */ 2608 *(__be32 *)(ctx->header + i) = cpu_to_be32( 2609 ((u32)le16_to_cpu(pd->transfer_status) << 16) | 2610 le16_to_cpu(pd->res_count)); 2611 ctx->header_length += 4; 2612 } 2613 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) { 2614 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count), 2615 ctx->header_length, ctx->header, 2616 ctx->base.callback_data); 2617 ctx->header_length = 0; 2618 } 2619 return 1; 2620 } 2621 2622 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels) 2623 { 2624 u32 hi = channels >> 32, lo = channels; 2625 2626 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi); 2627 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo); 2628 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi); 2629 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo); 2630 mmiowb(); 2631 ohci->mc_channels = channels; 2632 } 2633 2634 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card, 2635 int type, int channel, size_t header_size) 2636 { 2637 struct fw_ohci *ohci = fw_ohci(card); 2638 struct iso_context *uninitialized_var(ctx); 2639 descriptor_callback_t uninitialized_var(callback); 2640 u64 *uninitialized_var(channels); 2641 u32 *uninitialized_var(mask), uninitialized_var(regs); 2642 unsigned long flags; 2643 int index, ret = -EBUSY; 2644 2645 spin_lock_irqsave(&ohci->lock, flags); 2646 2647 switch (type) { 2648 case FW_ISO_CONTEXT_TRANSMIT: 2649 mask = &ohci->it_context_mask; 2650 callback = handle_it_packet; 2651 index = ffs(*mask) - 1; 2652 if (index >= 0) { 2653 *mask &= ~(1 << index); 2654 regs = OHCI1394_IsoXmitContextBase(index); 2655 ctx = &ohci->it_context_list[index]; 2656 } 2657 break; 2658 2659 case FW_ISO_CONTEXT_RECEIVE: 2660 channels = &ohci->ir_context_channels; 2661 mask = &ohci->ir_context_mask; 2662 callback = handle_ir_packet_per_buffer; 2663 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1; 2664 if (index >= 0) { 2665 *channels &= ~(1ULL << channel); 2666 *mask &= ~(1 << index); 2667 regs = OHCI1394_IsoRcvContextBase(index); 2668 ctx = &ohci->ir_context_list[index]; 2669 } 2670 break; 2671 2672 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2673 mask = &ohci->ir_context_mask; 2674 callback = handle_ir_buffer_fill; 2675 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1; 2676 if (index >= 0) { 2677 ohci->mc_allocated = true; 2678 *mask &= ~(1 << index); 2679 regs = OHCI1394_IsoRcvContextBase(index); 2680 ctx = &ohci->ir_context_list[index]; 2681 } 2682 break; 2683 2684 default: 2685 index = -1; 2686 ret = -ENOSYS; 2687 } 2688 2689 spin_unlock_irqrestore(&ohci->lock, flags); 2690 2691 if (index < 0) 2692 return ERR_PTR(ret); 2693 2694 memset(ctx, 0, sizeof(*ctx)); 2695 ctx->header_length = 0; 2696 ctx->header = (void *) __get_free_page(GFP_KERNEL); 2697 if (ctx->header == NULL) { 2698 ret = -ENOMEM; 2699 goto out; 2700 } 2701 ret = context_init(&ctx->context, ohci, regs, callback); 2702 if (ret < 0) 2703 goto out_with_header; 2704 2705 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) 2706 set_multichannel_mask(ohci, 0); 2707 2708 return &ctx->base; 2709 2710 out_with_header: 2711 free_page((unsigned long)ctx->header); 2712 out: 2713 spin_lock_irqsave(&ohci->lock, flags); 2714 2715 switch (type) { 2716 case FW_ISO_CONTEXT_RECEIVE: 2717 *channels |= 1ULL << channel; 2718 break; 2719 2720 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2721 ohci->mc_allocated = false; 2722 break; 2723 } 2724 *mask |= 1 << index; 2725 2726 spin_unlock_irqrestore(&ohci->lock, flags); 2727 2728 return ERR_PTR(ret); 2729 } 2730 2731 static int ohci_start_iso(struct fw_iso_context *base, 2732 s32 cycle, u32 sync, u32 tags) 2733 { 2734 struct iso_context *ctx = container_of(base, struct iso_context, base); 2735 struct fw_ohci *ohci = ctx->context.ohci; 2736 u32 control = IR_CONTEXT_ISOCH_HEADER, match; 2737 int index; 2738 2739 /* the controller cannot start without any queued packets */ 2740 if (ctx->context.last->branch_address == 0) 2741 return -ENODATA; 2742 2743 switch (ctx->base.type) { 2744 case FW_ISO_CONTEXT_TRANSMIT: 2745 index = ctx - ohci->it_context_list; 2746 match = 0; 2747 if (cycle >= 0) 2748 match = IT_CONTEXT_CYCLE_MATCH_ENABLE | 2749 (cycle & 0x7fff) << 16; 2750 2751 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); 2752 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); 2753 context_run(&ctx->context, match); 2754 break; 2755 2756 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2757 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE; 2758 /* fall through */ 2759 case FW_ISO_CONTEXT_RECEIVE: 2760 index = ctx - ohci->ir_context_list; 2761 match = (tags << 28) | (sync << 8) | ctx->base.channel; 2762 if (cycle >= 0) { 2763 match |= (cycle & 0x07fff) << 12; 2764 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE; 2765 } 2766 2767 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); 2768 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); 2769 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match); 2770 context_run(&ctx->context, control); 2771 2772 ctx->sync = sync; 2773 ctx->tags = tags; 2774 2775 break; 2776 } 2777 2778 return 0; 2779 } 2780 2781 static int ohci_stop_iso(struct fw_iso_context *base) 2782 { 2783 struct fw_ohci *ohci = fw_ohci(base->card); 2784 struct iso_context *ctx = container_of(base, struct iso_context, base); 2785 int index; 2786 2787 switch (ctx->base.type) { 2788 case FW_ISO_CONTEXT_TRANSMIT: 2789 index = ctx - ohci->it_context_list; 2790 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); 2791 break; 2792 2793 case FW_ISO_CONTEXT_RECEIVE: 2794 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2795 index = ctx - ohci->ir_context_list; 2796 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); 2797 break; 2798 } 2799 flush_writes(ohci); 2800 context_stop(&ctx->context); 2801 tasklet_kill(&ctx->context.tasklet); 2802 2803 return 0; 2804 } 2805 2806 static void ohci_free_iso_context(struct fw_iso_context *base) 2807 { 2808 struct fw_ohci *ohci = fw_ohci(base->card); 2809 struct iso_context *ctx = container_of(base, struct iso_context, base); 2810 unsigned long flags; 2811 int index; 2812 2813 ohci_stop_iso(base); 2814 context_release(&ctx->context); 2815 free_page((unsigned long)ctx->header); 2816 2817 spin_lock_irqsave(&ohci->lock, flags); 2818 2819 switch (base->type) { 2820 case FW_ISO_CONTEXT_TRANSMIT: 2821 index = ctx - ohci->it_context_list; 2822 ohci->it_context_mask |= 1 << index; 2823 break; 2824 2825 case FW_ISO_CONTEXT_RECEIVE: 2826 index = ctx - ohci->ir_context_list; 2827 ohci->ir_context_mask |= 1 << index; 2828 ohci->ir_context_channels |= 1ULL << base->channel; 2829 break; 2830 2831 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2832 index = ctx - ohci->ir_context_list; 2833 ohci->ir_context_mask |= 1 << index; 2834 ohci->ir_context_channels |= ohci->mc_channels; 2835 ohci->mc_channels = 0; 2836 ohci->mc_allocated = false; 2837 break; 2838 } 2839 2840 spin_unlock_irqrestore(&ohci->lock, flags); 2841 } 2842 2843 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels) 2844 { 2845 struct fw_ohci *ohci = fw_ohci(base->card); 2846 unsigned long flags; 2847 int ret; 2848 2849 switch (base->type) { 2850 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2851 2852 spin_lock_irqsave(&ohci->lock, flags); 2853 2854 /* Don't allow multichannel to grab other contexts' channels. */ 2855 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) { 2856 *channels = ohci->ir_context_channels; 2857 ret = -EBUSY; 2858 } else { 2859 set_multichannel_mask(ohci, *channels); 2860 ret = 0; 2861 } 2862 2863 spin_unlock_irqrestore(&ohci->lock, flags); 2864 2865 break; 2866 default: 2867 ret = -EINVAL; 2868 } 2869 2870 return ret; 2871 } 2872 2873 #ifdef CONFIG_PM 2874 static void ohci_resume_iso_dma(struct fw_ohci *ohci) 2875 { 2876 int i; 2877 struct iso_context *ctx; 2878 2879 for (i = 0 ; i < ohci->n_ir ; i++) { 2880 ctx = &ohci->ir_context_list[i]; 2881 if (ctx->context.running) 2882 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 2883 } 2884 2885 for (i = 0 ; i < ohci->n_it ; i++) { 2886 ctx = &ohci->it_context_list[i]; 2887 if (ctx->context.running) 2888 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 2889 } 2890 } 2891 #endif 2892 2893 static int queue_iso_transmit(struct iso_context *ctx, 2894 struct fw_iso_packet *packet, 2895 struct fw_iso_buffer *buffer, 2896 unsigned long payload) 2897 { 2898 struct descriptor *d, *last, *pd; 2899 struct fw_iso_packet *p; 2900 __le32 *header; 2901 dma_addr_t d_bus, page_bus; 2902 u32 z, header_z, payload_z, irq; 2903 u32 payload_index, payload_end_index, next_page_index; 2904 int page, end_page, i, length, offset; 2905 2906 p = packet; 2907 payload_index = payload; 2908 2909 if (p->skip) 2910 z = 1; 2911 else 2912 z = 2; 2913 if (p->header_length > 0) 2914 z++; 2915 2916 /* Determine the first page the payload isn't contained in. */ 2917 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; 2918 if (p->payload_length > 0) 2919 payload_z = end_page - (payload_index >> PAGE_SHIFT); 2920 else 2921 payload_z = 0; 2922 2923 z += payload_z; 2924 2925 /* Get header size in number of descriptors. */ 2926 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d)); 2927 2928 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); 2929 if (d == NULL) 2930 return -ENOMEM; 2931 2932 if (!p->skip) { 2933 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 2934 d[0].req_count = cpu_to_le16(8); 2935 /* 2936 * Link the skip address to this descriptor itself. This causes 2937 * a context to skip a cycle whenever lost cycles or FIFO 2938 * overruns occur, without dropping the data. The application 2939 * should then decide whether this is an error condition or not. 2940 * FIXME: Make the context's cycle-lost behaviour configurable? 2941 */ 2942 d[0].branch_address = cpu_to_le32(d_bus | z); 2943 2944 header = (__le32 *) &d[1]; 2945 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) | 2946 IT_HEADER_TAG(p->tag) | 2947 IT_HEADER_TCODE(TCODE_STREAM_DATA) | 2948 IT_HEADER_CHANNEL(ctx->base.channel) | 2949 IT_HEADER_SPEED(ctx->base.speed)); 2950 header[1] = 2951 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length + 2952 p->payload_length)); 2953 } 2954 2955 if (p->header_length > 0) { 2956 d[2].req_count = cpu_to_le16(p->header_length); 2957 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d)); 2958 memcpy(&d[z], p->header, p->header_length); 2959 } 2960 2961 pd = d + z - payload_z; 2962 payload_end_index = payload_index + p->payload_length; 2963 for (i = 0; i < payload_z; i++) { 2964 page = payload_index >> PAGE_SHIFT; 2965 offset = payload_index & ~PAGE_MASK; 2966 next_page_index = (page + 1) << PAGE_SHIFT; 2967 length = 2968 min(next_page_index, payload_end_index) - payload_index; 2969 pd[i].req_count = cpu_to_le16(length); 2970 2971 page_bus = page_private(buffer->pages[page]); 2972 pd[i].data_address = cpu_to_le32(page_bus + offset); 2973 2974 payload_index += length; 2975 } 2976 2977 if (p->interrupt) 2978 irq = DESCRIPTOR_IRQ_ALWAYS; 2979 else 2980 irq = DESCRIPTOR_NO_IRQ; 2981 2982 last = z == 2 ? d : d + z - 1; 2983 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 2984 DESCRIPTOR_STATUS | 2985 DESCRIPTOR_BRANCH_ALWAYS | 2986 irq); 2987 2988 context_append(&ctx->context, d, z, header_z); 2989 2990 return 0; 2991 } 2992 2993 static int queue_iso_packet_per_buffer(struct iso_context *ctx, 2994 struct fw_iso_packet *packet, 2995 struct fw_iso_buffer *buffer, 2996 unsigned long payload) 2997 { 2998 struct descriptor *d, *pd; 2999 dma_addr_t d_bus, page_bus; 3000 u32 z, header_z, rest; 3001 int i, j, length; 3002 int page, offset, packet_count, header_size, payload_per_buffer; 3003 3004 /* 3005 * The OHCI controller puts the isochronous header and trailer in the 3006 * buffer, so we need at least 8 bytes. 3007 */ 3008 packet_count = packet->header_length / ctx->base.header_size; 3009 header_size = max(ctx->base.header_size, (size_t)8); 3010 3011 /* Get header size in number of descriptors. */ 3012 header_z = DIV_ROUND_UP(header_size, sizeof(*d)); 3013 page = payload >> PAGE_SHIFT; 3014 offset = payload & ~PAGE_MASK; 3015 payload_per_buffer = packet->payload_length / packet_count; 3016 3017 for (i = 0; i < packet_count; i++) { 3018 /* d points to the header descriptor */ 3019 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1; 3020 d = context_get_descriptors(&ctx->context, 3021 z + header_z, &d_bus); 3022 if (d == NULL) 3023 return -ENOMEM; 3024 3025 d->control = cpu_to_le16(DESCRIPTOR_STATUS | 3026 DESCRIPTOR_INPUT_MORE); 3027 if (packet->skip && i == 0) 3028 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3029 d->req_count = cpu_to_le16(header_size); 3030 d->res_count = d->req_count; 3031 d->transfer_status = 0; 3032 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d))); 3033 3034 rest = payload_per_buffer; 3035 pd = d; 3036 for (j = 1; j < z; j++) { 3037 pd++; 3038 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3039 DESCRIPTOR_INPUT_MORE); 3040 3041 if (offset + rest < PAGE_SIZE) 3042 length = rest; 3043 else 3044 length = PAGE_SIZE - offset; 3045 pd->req_count = cpu_to_le16(length); 3046 pd->res_count = pd->req_count; 3047 pd->transfer_status = 0; 3048 3049 page_bus = page_private(buffer->pages[page]); 3050 pd->data_address = cpu_to_le32(page_bus + offset); 3051 3052 offset = (offset + length) & ~PAGE_MASK; 3053 rest -= length; 3054 if (offset == 0) 3055 page++; 3056 } 3057 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3058 DESCRIPTOR_INPUT_LAST | 3059 DESCRIPTOR_BRANCH_ALWAYS); 3060 if (packet->interrupt && i == packet_count - 1) 3061 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3062 3063 context_append(&ctx->context, d, z, header_z); 3064 } 3065 3066 return 0; 3067 } 3068 3069 static int queue_iso_buffer_fill(struct iso_context *ctx, 3070 struct fw_iso_packet *packet, 3071 struct fw_iso_buffer *buffer, 3072 unsigned long payload) 3073 { 3074 struct descriptor *d; 3075 dma_addr_t d_bus, page_bus; 3076 int page, offset, rest, z, i, length; 3077 3078 page = payload >> PAGE_SHIFT; 3079 offset = payload & ~PAGE_MASK; 3080 rest = packet->payload_length; 3081 3082 /* We need one descriptor for each page in the buffer. */ 3083 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE); 3084 3085 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count)) 3086 return -EFAULT; 3087 3088 for (i = 0; i < z; i++) { 3089 d = context_get_descriptors(&ctx->context, 1, &d_bus); 3090 if (d == NULL) 3091 return -ENOMEM; 3092 3093 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 3094 DESCRIPTOR_BRANCH_ALWAYS); 3095 if (packet->skip && i == 0) 3096 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3097 if (packet->interrupt && i == z - 1) 3098 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3099 3100 if (offset + rest < PAGE_SIZE) 3101 length = rest; 3102 else 3103 length = PAGE_SIZE - offset; 3104 d->req_count = cpu_to_le16(length); 3105 d->res_count = d->req_count; 3106 d->transfer_status = 0; 3107 3108 page_bus = page_private(buffer->pages[page]); 3109 d->data_address = cpu_to_le32(page_bus + offset); 3110 3111 rest -= length; 3112 offset = 0; 3113 page++; 3114 3115 context_append(&ctx->context, d, 1, 0); 3116 } 3117 3118 return 0; 3119 } 3120 3121 static int ohci_queue_iso(struct fw_iso_context *base, 3122 struct fw_iso_packet *packet, 3123 struct fw_iso_buffer *buffer, 3124 unsigned long payload) 3125 { 3126 struct iso_context *ctx = container_of(base, struct iso_context, base); 3127 unsigned long flags; 3128 int ret = -ENOSYS; 3129 3130 spin_lock_irqsave(&ctx->context.ohci->lock, flags); 3131 switch (base->type) { 3132 case FW_ISO_CONTEXT_TRANSMIT: 3133 ret = queue_iso_transmit(ctx, packet, buffer, payload); 3134 break; 3135 case FW_ISO_CONTEXT_RECEIVE: 3136 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload); 3137 break; 3138 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3139 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload); 3140 break; 3141 } 3142 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags); 3143 3144 return ret; 3145 } 3146 3147 static void ohci_flush_queue_iso(struct fw_iso_context *base) 3148 { 3149 struct context *ctx = 3150 &container_of(base, struct iso_context, base)->context; 3151 3152 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 3153 } 3154 3155 static const struct fw_card_driver ohci_driver = { 3156 .enable = ohci_enable, 3157 .read_phy_reg = ohci_read_phy_reg, 3158 .update_phy_reg = ohci_update_phy_reg, 3159 .set_config_rom = ohci_set_config_rom, 3160 .send_request = ohci_send_request, 3161 .send_response = ohci_send_response, 3162 .cancel_packet = ohci_cancel_packet, 3163 .enable_phys_dma = ohci_enable_phys_dma, 3164 .read_csr = ohci_read_csr, 3165 .write_csr = ohci_write_csr, 3166 3167 .allocate_iso_context = ohci_allocate_iso_context, 3168 .free_iso_context = ohci_free_iso_context, 3169 .set_iso_channels = ohci_set_iso_channels, 3170 .queue_iso = ohci_queue_iso, 3171 .flush_queue_iso = ohci_flush_queue_iso, 3172 .start_iso = ohci_start_iso, 3173 .stop_iso = ohci_stop_iso, 3174 }; 3175 3176 #ifdef CONFIG_PPC_PMAC 3177 static void pmac_ohci_on(struct pci_dev *dev) 3178 { 3179 if (machine_is(powermac)) { 3180 struct device_node *ofn = pci_device_to_OF_node(dev); 3181 3182 if (ofn) { 3183 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1); 3184 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1); 3185 } 3186 } 3187 } 3188 3189 static void pmac_ohci_off(struct pci_dev *dev) 3190 { 3191 if (machine_is(powermac)) { 3192 struct device_node *ofn = pci_device_to_OF_node(dev); 3193 3194 if (ofn) { 3195 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0); 3196 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0); 3197 } 3198 } 3199 } 3200 #else 3201 static inline void pmac_ohci_on(struct pci_dev *dev) {} 3202 static inline void pmac_ohci_off(struct pci_dev *dev) {} 3203 #endif /* CONFIG_PPC_PMAC */ 3204 3205 static int __devinit pci_probe(struct pci_dev *dev, 3206 const struct pci_device_id *ent) 3207 { 3208 struct fw_ohci *ohci; 3209 u32 bus_options, max_receive, link_speed, version; 3210 u64 guid; 3211 int i, err; 3212 size_t size; 3213 3214 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) { 3215 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n"); 3216 return -ENOSYS; 3217 } 3218 3219 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL); 3220 if (ohci == NULL) { 3221 err = -ENOMEM; 3222 goto fail; 3223 } 3224 3225 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); 3226 3227 pmac_ohci_on(dev); 3228 3229 err = pci_enable_device(dev); 3230 if (err) { 3231 fw_error("Failed to enable OHCI hardware\n"); 3232 goto fail_free; 3233 } 3234 3235 pci_set_master(dev); 3236 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); 3237 pci_set_drvdata(dev, ohci); 3238 3239 spin_lock_init(&ohci->lock); 3240 mutex_init(&ohci->phy_reg_mutex); 3241 3242 tasklet_init(&ohci->bus_reset_tasklet, 3243 bus_reset_tasklet, (unsigned long)ohci); 3244 3245 err = pci_request_region(dev, 0, ohci_driver_name); 3246 if (err) { 3247 fw_error("MMIO resource unavailable\n"); 3248 goto fail_disable; 3249 } 3250 3251 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE); 3252 if (ohci->registers == NULL) { 3253 fw_error("Failed to remap registers\n"); 3254 err = -ENXIO; 3255 goto fail_iomem; 3256 } 3257 3258 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++) 3259 if ((ohci_quirks[i].vendor == dev->vendor) && 3260 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID || 3261 ohci_quirks[i].device == dev->device) && 3262 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID || 3263 ohci_quirks[i].revision >= dev->revision)) { 3264 ohci->quirks = ohci_quirks[i].flags; 3265 break; 3266 } 3267 if (param_quirks) 3268 ohci->quirks = param_quirks; 3269 3270 /* 3271 * Because dma_alloc_coherent() allocates at least one page, 3272 * we save space by using a common buffer for the AR request/ 3273 * response descriptors and the self IDs buffer. 3274 */ 3275 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4); 3276 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2); 3277 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device, 3278 PAGE_SIZE, 3279 &ohci->misc_buffer_bus, 3280 GFP_KERNEL); 3281 if (!ohci->misc_buffer) { 3282 err = -ENOMEM; 3283 goto fail_iounmap; 3284 } 3285 3286 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0, 3287 OHCI1394_AsReqRcvContextControlSet); 3288 if (err < 0) 3289 goto fail_misc_buf; 3290 3291 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4, 3292 OHCI1394_AsRspRcvContextControlSet); 3293 if (err < 0) 3294 goto fail_arreq_ctx; 3295 3296 err = context_init(&ohci->at_request_ctx, ohci, 3297 OHCI1394_AsReqTrContextControlSet, handle_at_packet); 3298 if (err < 0) 3299 goto fail_arrsp_ctx; 3300 3301 err = context_init(&ohci->at_response_ctx, ohci, 3302 OHCI1394_AsRspTrContextControlSet, handle_at_packet); 3303 if (err < 0) 3304 goto fail_atreq_ctx; 3305 3306 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); 3307 ohci->ir_context_channels = ~0ULL; 3308 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); 3309 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); 3310 ohci->ir_context_mask = ohci->ir_context_support; 3311 ohci->n_ir = hweight32(ohci->ir_context_mask); 3312 size = sizeof(struct iso_context) * ohci->n_ir; 3313 ohci->ir_context_list = kzalloc(size, GFP_KERNEL); 3314 3315 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); 3316 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); 3317 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); 3318 ohci->it_context_mask = ohci->it_context_support; 3319 ohci->n_it = hweight32(ohci->it_context_mask); 3320 size = sizeof(struct iso_context) * ohci->n_it; 3321 ohci->it_context_list = kzalloc(size, GFP_KERNEL); 3322 3323 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) { 3324 err = -ENOMEM; 3325 goto fail_contexts; 3326 } 3327 3328 ohci->self_id_cpu = ohci->misc_buffer + PAGE_SIZE/2; 3329 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2; 3330 3331 bus_options = reg_read(ohci, OHCI1394_BusOptions); 3332 max_receive = (bus_options >> 12) & 0xf; 3333 link_speed = bus_options & 0x7; 3334 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | 3335 reg_read(ohci, OHCI1394_GUIDLo); 3336 3337 err = fw_card_add(&ohci->card, max_receive, link_speed, guid); 3338 if (err) 3339 goto fail_contexts; 3340 3341 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 3342 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, " 3343 "%d IR + %d IT contexts, quirks 0x%x\n", 3344 dev_name(&dev->dev), version >> 16, version & 0xff, 3345 ohci->n_ir, ohci->n_it, ohci->quirks); 3346 3347 return 0; 3348 3349 fail_contexts: 3350 kfree(ohci->ir_context_list); 3351 kfree(ohci->it_context_list); 3352 context_release(&ohci->at_response_ctx); 3353 fail_atreq_ctx: 3354 context_release(&ohci->at_request_ctx); 3355 fail_arrsp_ctx: 3356 ar_context_release(&ohci->ar_response_ctx); 3357 fail_arreq_ctx: 3358 ar_context_release(&ohci->ar_request_ctx); 3359 fail_misc_buf: 3360 dma_free_coherent(ohci->card.device, PAGE_SIZE, 3361 ohci->misc_buffer, ohci->misc_buffer_bus); 3362 fail_iounmap: 3363 pci_iounmap(dev, ohci->registers); 3364 fail_iomem: 3365 pci_release_region(dev, 0); 3366 fail_disable: 3367 pci_disable_device(dev); 3368 fail_free: 3369 kfree(ohci); 3370 pmac_ohci_off(dev); 3371 fail: 3372 if (err == -ENOMEM) 3373 fw_error("Out of memory\n"); 3374 3375 return err; 3376 } 3377 3378 static void pci_remove(struct pci_dev *dev) 3379 { 3380 struct fw_ohci *ohci; 3381 3382 ohci = pci_get_drvdata(dev); 3383 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 3384 flush_writes(ohci); 3385 fw_core_remove_card(&ohci->card); 3386 3387 /* 3388 * FIXME: Fail all pending packets here, now that the upper 3389 * layers can't queue any more. 3390 */ 3391 3392 software_reset(ohci); 3393 free_irq(dev->irq, ohci); 3394 3395 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom) 3396 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 3397 ohci->next_config_rom, ohci->next_config_rom_bus); 3398 if (ohci->config_rom) 3399 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 3400 ohci->config_rom, ohci->config_rom_bus); 3401 ar_context_release(&ohci->ar_request_ctx); 3402 ar_context_release(&ohci->ar_response_ctx); 3403 dma_free_coherent(ohci->card.device, PAGE_SIZE, 3404 ohci->misc_buffer, ohci->misc_buffer_bus); 3405 context_release(&ohci->at_request_ctx); 3406 context_release(&ohci->at_response_ctx); 3407 kfree(ohci->it_context_list); 3408 kfree(ohci->ir_context_list); 3409 pci_disable_msi(dev); 3410 pci_iounmap(dev, ohci->registers); 3411 pci_release_region(dev, 0); 3412 pci_disable_device(dev); 3413 kfree(ohci); 3414 pmac_ohci_off(dev); 3415 3416 fw_notify("Removed fw-ohci device.\n"); 3417 } 3418 3419 #ifdef CONFIG_PM 3420 static int pci_suspend(struct pci_dev *dev, pm_message_t state) 3421 { 3422 struct fw_ohci *ohci = pci_get_drvdata(dev); 3423 int err; 3424 3425 software_reset(ohci); 3426 free_irq(dev->irq, ohci); 3427 pci_disable_msi(dev); 3428 err = pci_save_state(dev); 3429 if (err) { 3430 fw_error("pci_save_state failed\n"); 3431 return err; 3432 } 3433 err = pci_set_power_state(dev, pci_choose_state(dev, state)); 3434 if (err) 3435 fw_error("pci_set_power_state failed with %d\n", err); 3436 pmac_ohci_off(dev); 3437 3438 return 0; 3439 } 3440 3441 static int pci_resume(struct pci_dev *dev) 3442 { 3443 struct fw_ohci *ohci = pci_get_drvdata(dev); 3444 int err; 3445 3446 pmac_ohci_on(dev); 3447 pci_set_power_state(dev, PCI_D0); 3448 pci_restore_state(dev); 3449 err = pci_enable_device(dev); 3450 if (err) { 3451 fw_error("pci_enable_device failed\n"); 3452 return err; 3453 } 3454 3455 /* Some systems don't setup GUID register on resume from ram */ 3456 if (!reg_read(ohci, OHCI1394_GUIDLo) && 3457 !reg_read(ohci, OHCI1394_GUIDHi)) { 3458 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid); 3459 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32)); 3460 } 3461 3462 err = ohci_enable(&ohci->card, NULL, 0); 3463 if (err) 3464 return err; 3465 3466 ohci_resume_iso_dma(ohci); 3467 3468 return 0; 3469 } 3470 #endif 3471 3472 static const struct pci_device_id pci_table[] = { 3473 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, 3474 { } 3475 }; 3476 3477 MODULE_DEVICE_TABLE(pci, pci_table); 3478 3479 static struct pci_driver fw_ohci_pci_driver = { 3480 .name = ohci_driver_name, 3481 .id_table = pci_table, 3482 .probe = pci_probe, 3483 .remove = pci_remove, 3484 #ifdef CONFIG_PM 3485 .resume = pci_resume, 3486 .suspend = pci_suspend, 3487 #endif 3488 }; 3489 3490 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); 3491 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); 3492 MODULE_LICENSE("GPL"); 3493 3494 /* Provide a module alias so root-on-sbp2 initrds don't break. */ 3495 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE 3496 MODULE_ALIAS("ohci1394"); 3497 #endif 3498 3499 static int __init fw_ohci_init(void) 3500 { 3501 return pci_register_driver(&fw_ohci_pci_driver); 3502 } 3503 3504 static void __exit fw_ohci_cleanup(void) 3505 { 3506 pci_unregister_driver(&fw_ohci_pci_driver); 3507 } 3508 3509 module_init(fw_ohci_init); 3510 module_exit(fw_ohci_cleanup); 3511