1 /* 2 * Driver for OHCI 1394 controllers 3 * 4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software Foundation, 18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 */ 20 21 #include <linux/bitops.h> 22 #include <linux/bug.h> 23 #include <linux/compiler.h> 24 #include <linux/delay.h> 25 #include <linux/device.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/firewire.h> 28 #include <linux/firewire-constants.h> 29 #include <linux/init.h> 30 #include <linux/interrupt.h> 31 #include <linux/io.h> 32 #include <linux/kernel.h> 33 #include <linux/list.h> 34 #include <linux/mm.h> 35 #include <linux/module.h> 36 #include <linux/moduleparam.h> 37 #include <linux/mutex.h> 38 #include <linux/pci.h> 39 #include <linux/pci_ids.h> 40 #include <linux/slab.h> 41 #include <linux/spinlock.h> 42 #include <linux/string.h> 43 #include <linux/time.h> 44 #include <linux/vmalloc.h> 45 46 #include <asm/byteorder.h> 47 #include <asm/page.h> 48 #include <asm/system.h> 49 50 #ifdef CONFIG_PPC_PMAC 51 #include <asm/pmac_feature.h> 52 #endif 53 54 #include "core.h" 55 #include "ohci.h" 56 57 #define DESCRIPTOR_OUTPUT_MORE 0 58 #define DESCRIPTOR_OUTPUT_LAST (1 << 12) 59 #define DESCRIPTOR_INPUT_MORE (2 << 12) 60 #define DESCRIPTOR_INPUT_LAST (3 << 12) 61 #define DESCRIPTOR_STATUS (1 << 11) 62 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8) 63 #define DESCRIPTOR_PING (1 << 7) 64 #define DESCRIPTOR_YY (1 << 6) 65 #define DESCRIPTOR_NO_IRQ (0 << 4) 66 #define DESCRIPTOR_IRQ_ERROR (1 << 4) 67 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4) 68 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2) 69 #define DESCRIPTOR_WAIT (3 << 0) 70 71 struct descriptor { 72 __le16 req_count; 73 __le16 control; 74 __le32 data_address; 75 __le32 branch_address; 76 __le16 res_count; 77 __le16 transfer_status; 78 } __attribute__((aligned(16))); 79 80 #define CONTROL_SET(regs) (regs) 81 #define CONTROL_CLEAR(regs) ((regs) + 4) 82 #define COMMAND_PTR(regs) ((regs) + 12) 83 #define CONTEXT_MATCH(regs) ((regs) + 16) 84 85 #define AR_BUFFER_SIZE (32*1024) 86 #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE) 87 /* we need at least two pages for proper list management */ 88 #define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2) 89 90 #define MAX_ASYNC_PAYLOAD 4096 91 #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4) 92 #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE) 93 94 struct ar_context { 95 struct fw_ohci *ohci; 96 struct page *pages[AR_BUFFERS]; 97 void *buffer; 98 struct descriptor *descriptors; 99 dma_addr_t descriptors_bus; 100 void *pointer; 101 unsigned int last_buffer_index; 102 u32 regs; 103 struct tasklet_struct tasklet; 104 }; 105 106 struct context; 107 108 typedef int (*descriptor_callback_t)(struct context *ctx, 109 struct descriptor *d, 110 struct descriptor *last); 111 112 /* 113 * A buffer that contains a block of DMA-able coherent memory used for 114 * storing a portion of a DMA descriptor program. 115 */ 116 struct descriptor_buffer { 117 struct list_head list; 118 dma_addr_t buffer_bus; 119 size_t buffer_size; 120 size_t used; 121 struct descriptor buffer[0]; 122 }; 123 124 struct context { 125 struct fw_ohci *ohci; 126 u32 regs; 127 int total_allocation; 128 bool running; 129 bool flushing; 130 131 /* 132 * List of page-sized buffers for storing DMA descriptors. 133 * Head of list contains buffers in use and tail of list contains 134 * free buffers. 135 */ 136 struct list_head buffer_list; 137 138 /* 139 * Pointer to a buffer inside buffer_list that contains the tail 140 * end of the current DMA program. 141 */ 142 struct descriptor_buffer *buffer_tail; 143 144 /* 145 * The descriptor containing the branch address of the first 146 * descriptor that has not yet been filled by the device. 147 */ 148 struct descriptor *last; 149 150 /* 151 * The last descriptor in the DMA program. It contains the branch 152 * address that must be updated upon appending a new descriptor. 153 */ 154 struct descriptor *prev; 155 156 descriptor_callback_t callback; 157 158 struct tasklet_struct tasklet; 159 }; 160 161 #define IT_HEADER_SY(v) ((v) << 0) 162 #define IT_HEADER_TCODE(v) ((v) << 4) 163 #define IT_HEADER_CHANNEL(v) ((v) << 8) 164 #define IT_HEADER_TAG(v) ((v) << 14) 165 #define IT_HEADER_SPEED(v) ((v) << 16) 166 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16) 167 168 struct iso_context { 169 struct fw_iso_context base; 170 struct context context; 171 int excess_bytes; 172 void *header; 173 size_t header_length; 174 175 u8 sync; 176 u8 tags; 177 }; 178 179 #define CONFIG_ROM_SIZE 1024 180 181 struct fw_ohci { 182 struct fw_card card; 183 184 __iomem char *registers; 185 int node_id; 186 int generation; 187 int request_generation; /* for timestamping incoming requests */ 188 unsigned quirks; 189 unsigned int pri_req_max; 190 u32 bus_time; 191 bool is_root; 192 bool csr_state_setclear_abdicate; 193 int n_ir; 194 int n_it; 195 /* 196 * Spinlock for accessing fw_ohci data. Never call out of 197 * this driver with this lock held. 198 */ 199 spinlock_t lock; 200 201 struct mutex phy_reg_mutex; 202 203 void *misc_buffer; 204 dma_addr_t misc_buffer_bus; 205 206 struct ar_context ar_request_ctx; 207 struct ar_context ar_response_ctx; 208 struct context at_request_ctx; 209 struct context at_response_ctx; 210 211 u32 it_context_support; 212 u32 it_context_mask; /* unoccupied IT contexts */ 213 struct iso_context *it_context_list; 214 u64 ir_context_channels; /* unoccupied channels */ 215 u32 ir_context_support; 216 u32 ir_context_mask; /* unoccupied IR contexts */ 217 struct iso_context *ir_context_list; 218 u64 mc_channels; /* channels in use by the multichannel IR context */ 219 bool mc_allocated; 220 221 __be32 *config_rom; 222 dma_addr_t config_rom_bus; 223 __be32 *next_config_rom; 224 dma_addr_t next_config_rom_bus; 225 __be32 next_header; 226 227 __le32 *self_id_cpu; 228 dma_addr_t self_id_bus; 229 struct tasklet_struct bus_reset_tasklet; 230 231 u32 self_id_buffer[512]; 232 }; 233 234 static inline struct fw_ohci *fw_ohci(struct fw_card *card) 235 { 236 return container_of(card, struct fw_ohci, card); 237 } 238 239 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 240 #define IR_CONTEXT_BUFFER_FILL 0x80000000 241 #define IR_CONTEXT_ISOCH_HEADER 0x40000000 242 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 243 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 244 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 245 246 #define CONTEXT_RUN 0x8000 247 #define CONTEXT_WAKE 0x1000 248 #define CONTEXT_DEAD 0x0800 249 #define CONTEXT_ACTIVE 0x0400 250 251 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf 252 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 253 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 254 255 #define OHCI1394_REGISTER_SIZE 0x800 256 #define OHCI1394_PCI_HCI_Control 0x40 257 #define SELF_ID_BUF_SIZE 0x800 258 #define OHCI_TCODE_PHY_PACKET 0x0e 259 #define OHCI_VERSION_1_1 0x010010 260 261 static char ohci_driver_name[] = KBUILD_MODNAME; 262 263 #define PCI_DEVICE_ID_AGERE_FW643 0x5901 264 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380 265 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009 266 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd 267 268 #define QUIRK_CYCLE_TIMER 1 269 #define QUIRK_RESET_PACKET 2 270 #define QUIRK_BE_HEADERS 4 271 #define QUIRK_NO_1394A 8 272 #define QUIRK_NO_MSI 16 273 274 /* In case of multiple matches in ohci_quirks[], only the first one is used. */ 275 static const struct { 276 unsigned short vendor, device, revision, flags; 277 } ohci_quirks[] = { 278 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID, 279 QUIRK_CYCLE_TIMER}, 280 281 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID, 282 QUIRK_BE_HEADERS}, 283 284 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6, 285 QUIRK_NO_MSI}, 286 287 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID, 288 QUIRK_NO_MSI}, 289 290 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID, 291 QUIRK_CYCLE_TIMER}, 292 293 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID, 294 QUIRK_CYCLE_TIMER}, 295 296 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID, 297 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A}, 298 299 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID, 300 QUIRK_RESET_PACKET}, 301 302 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID, 303 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, 304 }; 305 306 /* This overrides anything that was found in ohci_quirks[]. */ 307 static int param_quirks; 308 module_param_named(quirks, param_quirks, int, 0644); 309 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0" 310 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER) 311 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET) 312 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS) 313 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A) 314 ", disable MSI = " __stringify(QUIRK_NO_MSI) 315 ")"); 316 317 #define OHCI_PARAM_DEBUG_AT_AR 1 318 #define OHCI_PARAM_DEBUG_SELFIDS 2 319 #define OHCI_PARAM_DEBUG_IRQS 4 320 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */ 321 322 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG 323 324 static int param_debug; 325 module_param_named(debug, param_debug, int, 0644); 326 MODULE_PARM_DESC(debug, "Verbose logging (default = 0" 327 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR) 328 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS) 329 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS) 330 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS) 331 ", or a combination, or all = -1)"); 332 333 static void log_irqs(u32 evt) 334 { 335 if (likely(!(param_debug & 336 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS)))) 337 return; 338 339 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) && 340 !(evt & OHCI1394_busReset)) 341 return; 342 343 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt, 344 evt & OHCI1394_selfIDComplete ? " selfID" : "", 345 evt & OHCI1394_RQPkt ? " AR_req" : "", 346 evt & OHCI1394_RSPkt ? " AR_resp" : "", 347 evt & OHCI1394_reqTxComplete ? " AT_req" : "", 348 evt & OHCI1394_respTxComplete ? " AT_resp" : "", 349 evt & OHCI1394_isochRx ? " IR" : "", 350 evt & OHCI1394_isochTx ? " IT" : "", 351 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", 352 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", 353 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "", 354 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "", 355 evt & OHCI1394_regAccessFail ? " regAccessFail" : "", 356 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "", 357 evt & OHCI1394_busReset ? " busReset" : "", 358 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | 359 OHCI1394_RSPkt | OHCI1394_reqTxComplete | 360 OHCI1394_respTxComplete | OHCI1394_isochRx | 361 OHCI1394_isochTx | OHCI1394_postedWriteErr | 362 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds | 363 OHCI1394_cycleInconsistent | 364 OHCI1394_regAccessFail | OHCI1394_busReset) 365 ? " ?" : ""); 366 } 367 368 static const char *speed[] = { 369 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta", 370 }; 371 static const char *power[] = { 372 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W", 373 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W", 374 }; 375 static const char port[] = { '.', '-', 'p', 'c', }; 376 377 static char _p(u32 *s, int shift) 378 { 379 return port[*s >> shift & 3]; 380 } 381 382 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s) 383 { 384 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) 385 return; 386 387 fw_notify("%d selfIDs, generation %d, local node ID %04x\n", 388 self_id_count, generation, node_id); 389 390 for (; self_id_count--; ++s) 391 if ((*s & 1 << 23) == 0) 392 fw_notify("selfID 0: %08x, phy %d [%c%c%c] " 393 "%s gc=%d %s %s%s%s\n", 394 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2), 395 speed[*s >> 14 & 3], *s >> 16 & 63, 396 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", 397 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); 398 else 399 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n", 400 *s, *s >> 24 & 63, 401 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10), 402 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2)); 403 } 404 405 static const char *evts[] = { 406 [0x00] = "evt_no_status", [0x01] = "-reserved-", 407 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack", 408 [0x04] = "evt_underrun", [0x05] = "evt_overrun", 409 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read", 410 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset", 411 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err", 412 [0x0c] = "-reserved-", [0x0d] = "-reserved-", 413 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed", 414 [0x10] = "-reserved-", [0x11] = "ack_complete", 415 [0x12] = "ack_pending ", [0x13] = "-reserved-", 416 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A", 417 [0x16] = "ack_busy_B", [0x17] = "-reserved-", 418 [0x18] = "-reserved-", [0x19] = "-reserved-", 419 [0x1a] = "-reserved-", [0x1b] = "ack_tardy", 420 [0x1c] = "-reserved-", [0x1d] = "ack_data_error", 421 [0x1e] = "ack_type_error", [0x1f] = "-reserved-", 422 [0x20] = "pending/cancelled", 423 }; 424 static const char *tcodes[] = { 425 [0x0] = "QW req", [0x1] = "BW req", 426 [0x2] = "W resp", [0x3] = "-reserved-", 427 [0x4] = "QR req", [0x5] = "BR req", 428 [0x6] = "QR resp", [0x7] = "BR resp", 429 [0x8] = "cycle start", [0x9] = "Lk req", 430 [0xa] = "async stream packet", [0xb] = "Lk resp", 431 [0xc] = "-reserved-", [0xd] = "-reserved-", 432 [0xe] = "link internal", [0xf] = "-reserved-", 433 }; 434 435 static void log_ar_at_event(char dir, int speed, u32 *header, int evt) 436 { 437 int tcode = header[0] >> 4 & 0xf; 438 char specific[12]; 439 440 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR))) 441 return; 442 443 if (unlikely(evt >= ARRAY_SIZE(evts))) 444 evt = 0x1f; 445 446 if (evt == OHCI1394_evt_bus_reset) { 447 fw_notify("A%c evt_bus_reset, generation %d\n", 448 dir, (header[2] >> 16) & 0xff); 449 return; 450 } 451 452 switch (tcode) { 453 case 0x0: case 0x6: case 0x8: 454 snprintf(specific, sizeof(specific), " = %08x", 455 be32_to_cpu((__force __be32)header[3])); 456 break; 457 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb: 458 snprintf(specific, sizeof(specific), " %x,%x", 459 header[3] >> 16, header[3] & 0xffff); 460 break; 461 default: 462 specific[0] = '\0'; 463 } 464 465 switch (tcode) { 466 case 0xa: 467 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]); 468 break; 469 case 0xe: 470 fw_notify("A%c %s, PHY %08x %08x\n", 471 dir, evts[evt], header[1], header[2]); 472 break; 473 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9: 474 fw_notify("A%c spd %x tl %02x, " 475 "%04x -> %04x, %s, " 476 "%s, %04x%08x%s\n", 477 dir, speed, header[0] >> 10 & 0x3f, 478 header[1] >> 16, header[0] >> 16, evts[evt], 479 tcodes[tcode], header[1] & 0xffff, header[2], specific); 480 break; 481 default: 482 fw_notify("A%c spd %x tl %02x, " 483 "%04x -> %04x, %s, " 484 "%s%s\n", 485 dir, speed, header[0] >> 10 & 0x3f, 486 header[1] >> 16, header[0] >> 16, evts[evt], 487 tcodes[tcode], specific); 488 } 489 } 490 491 #else 492 493 #define param_debug 0 494 static inline void log_irqs(u32 evt) {} 495 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {} 496 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {} 497 498 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */ 499 500 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) 501 { 502 writel(data, ohci->registers + offset); 503 } 504 505 static inline u32 reg_read(const struct fw_ohci *ohci, int offset) 506 { 507 return readl(ohci->registers + offset); 508 } 509 510 static inline void flush_writes(const struct fw_ohci *ohci) 511 { 512 /* Do a dummy read to flush writes. */ 513 reg_read(ohci, OHCI1394_Version); 514 } 515 516 /* 517 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and 518 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex. 519 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg() 520 * directly. Exceptions are intrinsically serialized contexts like pci_probe. 521 */ 522 static int read_phy_reg(struct fw_ohci *ohci, int addr) 523 { 524 u32 val; 525 int i; 526 527 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); 528 for (i = 0; i < 3 + 100; i++) { 529 val = reg_read(ohci, OHCI1394_PhyControl); 530 if (!~val) 531 return -ENODEV; /* Card was ejected. */ 532 533 if (val & OHCI1394_PhyControl_ReadDone) 534 return OHCI1394_PhyControl_ReadData(val); 535 536 /* 537 * Try a few times without waiting. Sleeping is necessary 538 * only when the link/PHY interface is busy. 539 */ 540 if (i >= 3) 541 msleep(1); 542 } 543 fw_error("failed to read phy reg\n"); 544 545 return -EBUSY; 546 } 547 548 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val) 549 { 550 int i; 551 552 reg_write(ohci, OHCI1394_PhyControl, 553 OHCI1394_PhyControl_Write(addr, val)); 554 for (i = 0; i < 3 + 100; i++) { 555 val = reg_read(ohci, OHCI1394_PhyControl); 556 if (!~val) 557 return -ENODEV; /* Card was ejected. */ 558 559 if (!(val & OHCI1394_PhyControl_WritePending)) 560 return 0; 561 562 if (i >= 3) 563 msleep(1); 564 } 565 fw_error("failed to write phy reg\n"); 566 567 return -EBUSY; 568 } 569 570 static int update_phy_reg(struct fw_ohci *ohci, int addr, 571 int clear_bits, int set_bits) 572 { 573 int ret = read_phy_reg(ohci, addr); 574 if (ret < 0) 575 return ret; 576 577 /* 578 * The interrupt status bits are cleared by writing a one bit. 579 * Avoid clearing them unless explicitly requested in set_bits. 580 */ 581 if (addr == 5) 582 clear_bits |= PHY_INT_STATUS_BITS; 583 584 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits); 585 } 586 587 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr) 588 { 589 int ret; 590 591 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5); 592 if (ret < 0) 593 return ret; 594 595 return read_phy_reg(ohci, addr); 596 } 597 598 static int ohci_read_phy_reg(struct fw_card *card, int addr) 599 { 600 struct fw_ohci *ohci = fw_ohci(card); 601 int ret; 602 603 mutex_lock(&ohci->phy_reg_mutex); 604 ret = read_phy_reg(ohci, addr); 605 mutex_unlock(&ohci->phy_reg_mutex); 606 607 return ret; 608 } 609 610 static int ohci_update_phy_reg(struct fw_card *card, int addr, 611 int clear_bits, int set_bits) 612 { 613 struct fw_ohci *ohci = fw_ohci(card); 614 int ret; 615 616 mutex_lock(&ohci->phy_reg_mutex); 617 ret = update_phy_reg(ohci, addr, clear_bits, set_bits); 618 mutex_unlock(&ohci->phy_reg_mutex); 619 620 return ret; 621 } 622 623 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i) 624 { 625 return page_private(ctx->pages[i]); 626 } 627 628 static void ar_context_link_page(struct ar_context *ctx, unsigned int index) 629 { 630 struct descriptor *d; 631 632 d = &ctx->descriptors[index]; 633 d->branch_address &= cpu_to_le32(~0xf); 634 d->res_count = cpu_to_le16(PAGE_SIZE); 635 d->transfer_status = 0; 636 637 wmb(); /* finish init of new descriptors before branch_address update */ 638 d = &ctx->descriptors[ctx->last_buffer_index]; 639 d->branch_address |= cpu_to_le32(1); 640 641 ctx->last_buffer_index = index; 642 643 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 644 } 645 646 static void ar_context_release(struct ar_context *ctx) 647 { 648 unsigned int i; 649 650 if (ctx->buffer) 651 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES); 652 653 for (i = 0; i < AR_BUFFERS; i++) 654 if (ctx->pages[i]) { 655 dma_unmap_page(ctx->ohci->card.device, 656 ar_buffer_bus(ctx, i), 657 PAGE_SIZE, DMA_FROM_DEVICE); 658 __free_page(ctx->pages[i]); 659 } 660 } 661 662 static void ar_context_abort(struct ar_context *ctx, const char *error_msg) 663 { 664 if (reg_read(ctx->ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) { 665 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 666 flush_writes(ctx->ohci); 667 668 fw_error("AR error: %s; DMA stopped\n", error_msg); 669 } 670 /* FIXME: restart? */ 671 } 672 673 static inline unsigned int ar_next_buffer_index(unsigned int index) 674 { 675 return (index + 1) % AR_BUFFERS; 676 } 677 678 static inline unsigned int ar_prev_buffer_index(unsigned int index) 679 { 680 return (index - 1 + AR_BUFFERS) % AR_BUFFERS; 681 } 682 683 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx) 684 { 685 return ar_next_buffer_index(ctx->last_buffer_index); 686 } 687 688 /* 689 * We search for the buffer that contains the last AR packet DMA data written 690 * by the controller. 691 */ 692 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx, 693 unsigned int *buffer_offset) 694 { 695 unsigned int i, next_i, last = ctx->last_buffer_index; 696 __le16 res_count, next_res_count; 697 698 i = ar_first_buffer_index(ctx); 699 res_count = ACCESS_ONCE(ctx->descriptors[i].res_count); 700 701 /* A buffer that is not yet completely filled must be the last one. */ 702 while (i != last && res_count == 0) { 703 704 /* Peek at the next descriptor. */ 705 next_i = ar_next_buffer_index(i); 706 rmb(); /* read descriptors in order */ 707 next_res_count = ACCESS_ONCE( 708 ctx->descriptors[next_i].res_count); 709 /* 710 * If the next descriptor is still empty, we must stop at this 711 * descriptor. 712 */ 713 if (next_res_count == cpu_to_le16(PAGE_SIZE)) { 714 /* 715 * The exception is when the DMA data for one packet is 716 * split over three buffers; in this case, the middle 717 * buffer's descriptor might be never updated by the 718 * controller and look still empty, and we have to peek 719 * at the third one. 720 */ 721 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) { 722 next_i = ar_next_buffer_index(next_i); 723 rmb(); 724 next_res_count = ACCESS_ONCE( 725 ctx->descriptors[next_i].res_count); 726 if (next_res_count != cpu_to_le16(PAGE_SIZE)) 727 goto next_buffer_is_active; 728 } 729 730 break; 731 } 732 733 next_buffer_is_active: 734 i = next_i; 735 res_count = next_res_count; 736 } 737 738 rmb(); /* read res_count before the DMA data */ 739 740 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count); 741 if (*buffer_offset > PAGE_SIZE) { 742 *buffer_offset = 0; 743 ar_context_abort(ctx, "corrupted descriptor"); 744 } 745 746 return i; 747 } 748 749 static void ar_sync_buffers_for_cpu(struct ar_context *ctx, 750 unsigned int end_buffer_index, 751 unsigned int end_buffer_offset) 752 { 753 unsigned int i; 754 755 i = ar_first_buffer_index(ctx); 756 while (i != end_buffer_index) { 757 dma_sync_single_for_cpu(ctx->ohci->card.device, 758 ar_buffer_bus(ctx, i), 759 PAGE_SIZE, DMA_FROM_DEVICE); 760 i = ar_next_buffer_index(i); 761 } 762 if (end_buffer_offset > 0) 763 dma_sync_single_for_cpu(ctx->ohci->card.device, 764 ar_buffer_bus(ctx, i), 765 end_buffer_offset, DMA_FROM_DEVICE); 766 } 767 768 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) 769 #define cond_le32_to_cpu(v) \ 770 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v)) 771 #else 772 #define cond_le32_to_cpu(v) le32_to_cpu(v) 773 #endif 774 775 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) 776 { 777 struct fw_ohci *ohci = ctx->ohci; 778 struct fw_packet p; 779 u32 status, length, tcode; 780 int evt; 781 782 p.header[0] = cond_le32_to_cpu(buffer[0]); 783 p.header[1] = cond_le32_to_cpu(buffer[1]); 784 p.header[2] = cond_le32_to_cpu(buffer[2]); 785 786 tcode = (p.header[0] >> 4) & 0x0f; 787 switch (tcode) { 788 case TCODE_WRITE_QUADLET_REQUEST: 789 case TCODE_READ_QUADLET_RESPONSE: 790 p.header[3] = (__force __u32) buffer[3]; 791 p.header_length = 16; 792 p.payload_length = 0; 793 break; 794 795 case TCODE_READ_BLOCK_REQUEST : 796 p.header[3] = cond_le32_to_cpu(buffer[3]); 797 p.header_length = 16; 798 p.payload_length = 0; 799 break; 800 801 case TCODE_WRITE_BLOCK_REQUEST: 802 case TCODE_READ_BLOCK_RESPONSE: 803 case TCODE_LOCK_REQUEST: 804 case TCODE_LOCK_RESPONSE: 805 p.header[3] = cond_le32_to_cpu(buffer[3]); 806 p.header_length = 16; 807 p.payload_length = p.header[3] >> 16; 808 if (p.payload_length > MAX_ASYNC_PAYLOAD) { 809 ar_context_abort(ctx, "invalid packet length"); 810 return NULL; 811 } 812 break; 813 814 case TCODE_WRITE_RESPONSE: 815 case TCODE_READ_QUADLET_REQUEST: 816 case OHCI_TCODE_PHY_PACKET: 817 p.header_length = 12; 818 p.payload_length = 0; 819 break; 820 821 default: 822 ar_context_abort(ctx, "invalid tcode"); 823 return NULL; 824 } 825 826 p.payload = (void *) buffer + p.header_length; 827 828 /* FIXME: What to do about evt_* errors? */ 829 length = (p.header_length + p.payload_length + 3) / 4; 830 status = cond_le32_to_cpu(buffer[length]); 831 evt = (status >> 16) & 0x1f; 832 833 p.ack = evt - 16; 834 p.speed = (status >> 21) & 0x7; 835 p.timestamp = status & 0xffff; 836 p.generation = ohci->request_generation; 837 838 log_ar_at_event('R', p.speed, p.header, evt); 839 840 /* 841 * Several controllers, notably from NEC and VIA, forget to 842 * write ack_complete status at PHY packet reception. 843 */ 844 if (evt == OHCI1394_evt_no_status && 845 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4)) 846 p.ack = ACK_COMPLETE; 847 848 /* 849 * The OHCI bus reset handler synthesizes a PHY packet with 850 * the new generation number when a bus reset happens (see 851 * section 8.4.2.3). This helps us determine when a request 852 * was received and make sure we send the response in the same 853 * generation. We only need this for requests; for responses 854 * we use the unique tlabel for finding the matching 855 * request. 856 * 857 * Alas some chips sometimes emit bus reset packets with a 858 * wrong generation. We set the correct generation for these 859 * at a slightly incorrect time (in bus_reset_tasklet). 860 */ 861 if (evt == OHCI1394_evt_bus_reset) { 862 if (!(ohci->quirks & QUIRK_RESET_PACKET)) 863 ohci->request_generation = (p.header[2] >> 16) & 0xff; 864 } else if (ctx == &ohci->ar_request_ctx) { 865 fw_core_handle_request(&ohci->card, &p); 866 } else { 867 fw_core_handle_response(&ohci->card, &p); 868 } 869 870 return buffer + length + 1; 871 } 872 873 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end) 874 { 875 void *next; 876 877 while (p < end) { 878 next = handle_ar_packet(ctx, p); 879 if (!next) 880 return p; 881 p = next; 882 } 883 884 return p; 885 } 886 887 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer) 888 { 889 unsigned int i; 890 891 i = ar_first_buffer_index(ctx); 892 while (i != end_buffer) { 893 dma_sync_single_for_device(ctx->ohci->card.device, 894 ar_buffer_bus(ctx, i), 895 PAGE_SIZE, DMA_FROM_DEVICE); 896 ar_context_link_page(ctx, i); 897 i = ar_next_buffer_index(i); 898 } 899 } 900 901 static void ar_context_tasklet(unsigned long data) 902 { 903 struct ar_context *ctx = (struct ar_context *)data; 904 unsigned int end_buffer_index, end_buffer_offset; 905 void *p, *end; 906 907 p = ctx->pointer; 908 if (!p) 909 return; 910 911 end_buffer_index = ar_search_last_active_buffer(ctx, 912 &end_buffer_offset); 913 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset); 914 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset; 915 916 if (end_buffer_index < ar_first_buffer_index(ctx)) { 917 /* 918 * The filled part of the overall buffer wraps around; handle 919 * all packets up to the buffer end here. If the last packet 920 * wraps around, its tail will be visible after the buffer end 921 * because the buffer start pages are mapped there again. 922 */ 923 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE; 924 p = handle_ar_packets(ctx, p, buffer_end); 925 if (p < buffer_end) 926 goto error; 927 /* adjust p to point back into the actual buffer */ 928 p -= AR_BUFFERS * PAGE_SIZE; 929 } 930 931 p = handle_ar_packets(ctx, p, end); 932 if (p != end) { 933 if (p > end) 934 ar_context_abort(ctx, "inconsistent descriptor"); 935 goto error; 936 } 937 938 ctx->pointer = p; 939 ar_recycle_buffers(ctx, end_buffer_index); 940 941 return; 942 943 error: 944 ctx->pointer = NULL; 945 } 946 947 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, 948 unsigned int descriptors_offset, u32 regs) 949 { 950 unsigned int i; 951 dma_addr_t dma_addr; 952 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES]; 953 struct descriptor *d; 954 955 ctx->regs = regs; 956 ctx->ohci = ohci; 957 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); 958 959 for (i = 0; i < AR_BUFFERS; i++) { 960 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32); 961 if (!ctx->pages[i]) 962 goto out_of_memory; 963 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i], 964 0, PAGE_SIZE, DMA_FROM_DEVICE); 965 if (dma_mapping_error(ohci->card.device, dma_addr)) { 966 __free_page(ctx->pages[i]); 967 ctx->pages[i] = NULL; 968 goto out_of_memory; 969 } 970 set_page_private(ctx->pages[i], dma_addr); 971 } 972 973 for (i = 0; i < AR_BUFFERS; i++) 974 pages[i] = ctx->pages[i]; 975 for (i = 0; i < AR_WRAPAROUND_PAGES; i++) 976 pages[AR_BUFFERS + i] = ctx->pages[i]; 977 ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES, 978 -1, PAGE_KERNEL); 979 if (!ctx->buffer) 980 goto out_of_memory; 981 982 ctx->descriptors = ohci->misc_buffer + descriptors_offset; 983 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset; 984 985 for (i = 0; i < AR_BUFFERS; i++) { 986 d = &ctx->descriptors[i]; 987 d->req_count = cpu_to_le16(PAGE_SIZE); 988 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 989 DESCRIPTOR_STATUS | 990 DESCRIPTOR_BRANCH_ALWAYS); 991 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i)); 992 d->branch_address = cpu_to_le32(ctx->descriptors_bus + 993 ar_next_buffer_index(i) * sizeof(struct descriptor)); 994 } 995 996 return 0; 997 998 out_of_memory: 999 ar_context_release(ctx); 1000 1001 return -ENOMEM; 1002 } 1003 1004 static void ar_context_run(struct ar_context *ctx) 1005 { 1006 unsigned int i; 1007 1008 for (i = 0; i < AR_BUFFERS; i++) 1009 ar_context_link_page(ctx, i); 1010 1011 ctx->pointer = ctx->buffer; 1012 1013 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1); 1014 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); 1015 } 1016 1017 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z) 1018 { 1019 __le16 branch; 1020 1021 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS); 1022 1023 /* figure out which descriptor the branch address goes in */ 1024 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 1025 return d; 1026 else 1027 return d + z - 1; 1028 } 1029 1030 static void context_tasklet(unsigned long data) 1031 { 1032 struct context *ctx = (struct context *) data; 1033 struct descriptor *d, *last; 1034 u32 address; 1035 int z; 1036 struct descriptor_buffer *desc; 1037 1038 desc = list_entry(ctx->buffer_list.next, 1039 struct descriptor_buffer, list); 1040 last = ctx->last; 1041 while (last->branch_address != 0) { 1042 struct descriptor_buffer *old_desc = desc; 1043 address = le32_to_cpu(last->branch_address); 1044 z = address & 0xf; 1045 address &= ~0xf; 1046 1047 /* If the branch address points to a buffer outside of the 1048 * current buffer, advance to the next buffer. */ 1049 if (address < desc->buffer_bus || 1050 address >= desc->buffer_bus + desc->used) 1051 desc = list_entry(desc->list.next, 1052 struct descriptor_buffer, list); 1053 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d); 1054 last = find_branch_descriptor(d, z); 1055 1056 if (!ctx->callback(ctx, d, last)) 1057 break; 1058 1059 if (old_desc != desc) { 1060 /* If we've advanced to the next buffer, move the 1061 * previous buffer to the free list. */ 1062 unsigned long flags; 1063 old_desc->used = 0; 1064 spin_lock_irqsave(&ctx->ohci->lock, flags); 1065 list_move_tail(&old_desc->list, &ctx->buffer_list); 1066 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1067 } 1068 ctx->last = last; 1069 } 1070 } 1071 1072 /* 1073 * Allocate a new buffer and add it to the list of free buffers for this 1074 * context. Must be called with ohci->lock held. 1075 */ 1076 static int context_add_buffer(struct context *ctx) 1077 { 1078 struct descriptor_buffer *desc; 1079 dma_addr_t uninitialized_var(bus_addr); 1080 int offset; 1081 1082 /* 1083 * 16MB of descriptors should be far more than enough for any DMA 1084 * program. This will catch run-away userspace or DoS attacks. 1085 */ 1086 if (ctx->total_allocation >= 16*1024*1024) 1087 return -ENOMEM; 1088 1089 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE, 1090 &bus_addr, GFP_ATOMIC); 1091 if (!desc) 1092 return -ENOMEM; 1093 1094 offset = (void *)&desc->buffer - (void *)desc; 1095 desc->buffer_size = PAGE_SIZE - offset; 1096 desc->buffer_bus = bus_addr + offset; 1097 desc->used = 0; 1098 1099 list_add_tail(&desc->list, &ctx->buffer_list); 1100 ctx->total_allocation += PAGE_SIZE; 1101 1102 return 0; 1103 } 1104 1105 static int context_init(struct context *ctx, struct fw_ohci *ohci, 1106 u32 regs, descriptor_callback_t callback) 1107 { 1108 ctx->ohci = ohci; 1109 ctx->regs = regs; 1110 ctx->total_allocation = 0; 1111 1112 INIT_LIST_HEAD(&ctx->buffer_list); 1113 if (context_add_buffer(ctx) < 0) 1114 return -ENOMEM; 1115 1116 ctx->buffer_tail = list_entry(ctx->buffer_list.next, 1117 struct descriptor_buffer, list); 1118 1119 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); 1120 ctx->callback = callback; 1121 1122 /* 1123 * We put a dummy descriptor in the buffer that has a NULL 1124 * branch address and looks like it's been sent. That way we 1125 * have a descriptor to append DMA programs to. 1126 */ 1127 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer)); 1128 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST); 1129 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011); 1130 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer); 1131 ctx->last = ctx->buffer_tail->buffer; 1132 ctx->prev = ctx->buffer_tail->buffer; 1133 1134 return 0; 1135 } 1136 1137 static void context_release(struct context *ctx) 1138 { 1139 struct fw_card *card = &ctx->ohci->card; 1140 struct descriptor_buffer *desc, *tmp; 1141 1142 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list) 1143 dma_free_coherent(card->device, PAGE_SIZE, desc, 1144 desc->buffer_bus - 1145 ((void *)&desc->buffer - (void *)desc)); 1146 } 1147 1148 /* Must be called with ohci->lock held */ 1149 static struct descriptor *context_get_descriptors(struct context *ctx, 1150 int z, dma_addr_t *d_bus) 1151 { 1152 struct descriptor *d = NULL; 1153 struct descriptor_buffer *desc = ctx->buffer_tail; 1154 1155 if (z * sizeof(*d) > desc->buffer_size) 1156 return NULL; 1157 1158 if (z * sizeof(*d) > desc->buffer_size - desc->used) { 1159 /* No room for the descriptor in this buffer, so advance to the 1160 * next one. */ 1161 1162 if (desc->list.next == &ctx->buffer_list) { 1163 /* If there is no free buffer next in the list, 1164 * allocate one. */ 1165 if (context_add_buffer(ctx) < 0) 1166 return NULL; 1167 } 1168 desc = list_entry(desc->list.next, 1169 struct descriptor_buffer, list); 1170 ctx->buffer_tail = desc; 1171 } 1172 1173 d = desc->buffer + desc->used / sizeof(*d); 1174 memset(d, 0, z * sizeof(*d)); 1175 *d_bus = desc->buffer_bus + desc->used; 1176 1177 return d; 1178 } 1179 1180 static void context_run(struct context *ctx, u32 extra) 1181 { 1182 struct fw_ohci *ohci = ctx->ohci; 1183 1184 reg_write(ohci, COMMAND_PTR(ctx->regs), 1185 le32_to_cpu(ctx->last->branch_address)); 1186 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); 1187 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); 1188 ctx->running = true; 1189 flush_writes(ohci); 1190 } 1191 1192 static void context_append(struct context *ctx, 1193 struct descriptor *d, int z, int extra) 1194 { 1195 dma_addr_t d_bus; 1196 struct descriptor_buffer *desc = ctx->buffer_tail; 1197 1198 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d); 1199 1200 desc->used += (z + extra) * sizeof(*d); 1201 1202 wmb(); /* finish init of new descriptors before branch_address update */ 1203 ctx->prev->branch_address = cpu_to_le32(d_bus | z); 1204 ctx->prev = find_branch_descriptor(d, z); 1205 } 1206 1207 static void context_stop(struct context *ctx) 1208 { 1209 u32 reg; 1210 int i; 1211 1212 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 1213 ctx->running = false; 1214 1215 for (i = 0; i < 1000; i++) { 1216 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs)); 1217 if ((reg & CONTEXT_ACTIVE) == 0) 1218 return; 1219 1220 if (i) 1221 udelay(10); 1222 } 1223 fw_error("Error: DMA context still active (0x%08x)\n", reg); 1224 } 1225 1226 struct driver_data { 1227 u8 inline_data[8]; 1228 struct fw_packet *packet; 1229 }; 1230 1231 /* 1232 * This function apppends a packet to the DMA queue for transmission. 1233 * Must always be called with the ochi->lock held to ensure proper 1234 * generation handling and locking around packet queue manipulation. 1235 */ 1236 static int at_context_queue_packet(struct context *ctx, 1237 struct fw_packet *packet) 1238 { 1239 struct fw_ohci *ohci = ctx->ohci; 1240 dma_addr_t d_bus, uninitialized_var(payload_bus); 1241 struct driver_data *driver_data; 1242 struct descriptor *d, *last; 1243 __le32 *header; 1244 int z, tcode; 1245 1246 d = context_get_descriptors(ctx, 4, &d_bus); 1247 if (d == NULL) { 1248 packet->ack = RCODE_SEND_ERROR; 1249 return -1; 1250 } 1251 1252 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 1253 d[0].res_count = cpu_to_le16(packet->timestamp); 1254 1255 /* 1256 * The DMA format for asyncronous link packets is different 1257 * from the IEEE1394 layout, so shift the fields around 1258 * accordingly. 1259 */ 1260 1261 tcode = (packet->header[0] >> 4) & 0x0f; 1262 header = (__le32 *) &d[1]; 1263 switch (tcode) { 1264 case TCODE_WRITE_QUADLET_REQUEST: 1265 case TCODE_WRITE_BLOCK_REQUEST: 1266 case TCODE_WRITE_RESPONSE: 1267 case TCODE_READ_QUADLET_REQUEST: 1268 case TCODE_READ_BLOCK_REQUEST: 1269 case TCODE_READ_QUADLET_RESPONSE: 1270 case TCODE_READ_BLOCK_RESPONSE: 1271 case TCODE_LOCK_REQUEST: 1272 case TCODE_LOCK_RESPONSE: 1273 header[0] = cpu_to_le32((packet->header[0] & 0xffff) | 1274 (packet->speed << 16)); 1275 header[1] = cpu_to_le32((packet->header[1] & 0xffff) | 1276 (packet->header[0] & 0xffff0000)); 1277 header[2] = cpu_to_le32(packet->header[2]); 1278 1279 if (TCODE_IS_BLOCK_PACKET(tcode)) 1280 header[3] = cpu_to_le32(packet->header[3]); 1281 else 1282 header[3] = (__force __le32) packet->header[3]; 1283 1284 d[0].req_count = cpu_to_le16(packet->header_length); 1285 break; 1286 1287 case TCODE_LINK_INTERNAL: 1288 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) | 1289 (packet->speed << 16)); 1290 header[1] = cpu_to_le32(packet->header[1]); 1291 header[2] = cpu_to_le32(packet->header[2]); 1292 d[0].req_count = cpu_to_le16(12); 1293 1294 if (is_ping_packet(&packet->header[1])) 1295 d[0].control |= cpu_to_le16(DESCRIPTOR_PING); 1296 break; 1297 1298 case TCODE_STREAM_DATA: 1299 header[0] = cpu_to_le32((packet->header[0] & 0xffff) | 1300 (packet->speed << 16)); 1301 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000); 1302 d[0].req_count = cpu_to_le16(8); 1303 break; 1304 1305 default: 1306 /* BUG(); */ 1307 packet->ack = RCODE_SEND_ERROR; 1308 return -1; 1309 } 1310 1311 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor)); 1312 driver_data = (struct driver_data *) &d[3]; 1313 driver_data->packet = packet; 1314 packet->driver_data = driver_data; 1315 1316 if (packet->payload_length > 0) { 1317 if (packet->payload_length > sizeof(driver_data->inline_data)) { 1318 payload_bus = dma_map_single(ohci->card.device, 1319 packet->payload, 1320 packet->payload_length, 1321 DMA_TO_DEVICE); 1322 if (dma_mapping_error(ohci->card.device, payload_bus)) { 1323 packet->ack = RCODE_SEND_ERROR; 1324 return -1; 1325 } 1326 packet->payload_bus = payload_bus; 1327 packet->payload_mapped = true; 1328 } else { 1329 memcpy(driver_data->inline_data, packet->payload, 1330 packet->payload_length); 1331 payload_bus = d_bus + 3 * sizeof(*d); 1332 } 1333 1334 d[2].req_count = cpu_to_le16(packet->payload_length); 1335 d[2].data_address = cpu_to_le32(payload_bus); 1336 last = &d[2]; 1337 z = 3; 1338 } else { 1339 last = &d[0]; 1340 z = 2; 1341 } 1342 1343 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 1344 DESCRIPTOR_IRQ_ALWAYS | 1345 DESCRIPTOR_BRANCH_ALWAYS); 1346 1347 /* FIXME: Document how the locking works. */ 1348 if (ohci->generation != packet->generation) { 1349 if (packet->payload_mapped) 1350 dma_unmap_single(ohci->card.device, payload_bus, 1351 packet->payload_length, DMA_TO_DEVICE); 1352 packet->ack = RCODE_GENERATION; 1353 return -1; 1354 } 1355 1356 context_append(ctx, d, z, 4 - z); 1357 1358 if (ctx->running) 1359 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 1360 else 1361 context_run(ctx, 0); 1362 1363 return 0; 1364 } 1365 1366 static void at_context_flush(struct context *ctx) 1367 { 1368 tasklet_disable(&ctx->tasklet); 1369 1370 ctx->flushing = true; 1371 context_tasklet((unsigned long)ctx); 1372 ctx->flushing = false; 1373 1374 tasklet_enable(&ctx->tasklet); 1375 } 1376 1377 static int handle_at_packet(struct context *context, 1378 struct descriptor *d, 1379 struct descriptor *last) 1380 { 1381 struct driver_data *driver_data; 1382 struct fw_packet *packet; 1383 struct fw_ohci *ohci = context->ohci; 1384 int evt; 1385 1386 if (last->transfer_status == 0 && !context->flushing) 1387 /* This descriptor isn't done yet, stop iteration. */ 1388 return 0; 1389 1390 driver_data = (struct driver_data *) &d[3]; 1391 packet = driver_data->packet; 1392 if (packet == NULL) 1393 /* This packet was cancelled, just continue. */ 1394 return 1; 1395 1396 if (packet->payload_mapped) 1397 dma_unmap_single(ohci->card.device, packet->payload_bus, 1398 packet->payload_length, DMA_TO_DEVICE); 1399 1400 evt = le16_to_cpu(last->transfer_status) & 0x1f; 1401 packet->timestamp = le16_to_cpu(last->res_count); 1402 1403 log_ar_at_event('T', packet->speed, packet->header, evt); 1404 1405 switch (evt) { 1406 case OHCI1394_evt_timeout: 1407 /* Async response transmit timed out. */ 1408 packet->ack = RCODE_CANCELLED; 1409 break; 1410 1411 case OHCI1394_evt_flushed: 1412 /* 1413 * The packet was flushed should give same error as 1414 * when we try to use a stale generation count. 1415 */ 1416 packet->ack = RCODE_GENERATION; 1417 break; 1418 1419 case OHCI1394_evt_missing_ack: 1420 if (context->flushing) 1421 packet->ack = RCODE_GENERATION; 1422 else { 1423 /* 1424 * Using a valid (current) generation count, but the 1425 * node is not on the bus or not sending acks. 1426 */ 1427 packet->ack = RCODE_NO_ACK; 1428 } 1429 break; 1430 1431 case ACK_COMPLETE + 0x10: 1432 case ACK_PENDING + 0x10: 1433 case ACK_BUSY_X + 0x10: 1434 case ACK_BUSY_A + 0x10: 1435 case ACK_BUSY_B + 0x10: 1436 case ACK_DATA_ERROR + 0x10: 1437 case ACK_TYPE_ERROR + 0x10: 1438 packet->ack = evt - 0x10; 1439 break; 1440 1441 case OHCI1394_evt_no_status: 1442 if (context->flushing) { 1443 packet->ack = RCODE_GENERATION; 1444 break; 1445 } 1446 /* fall through */ 1447 1448 default: 1449 packet->ack = RCODE_SEND_ERROR; 1450 break; 1451 } 1452 1453 packet->callback(packet, &ohci->card, packet->ack); 1454 1455 return 1; 1456 } 1457 1458 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff) 1459 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f) 1460 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff) 1461 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff) 1462 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff) 1463 1464 static void handle_local_rom(struct fw_ohci *ohci, 1465 struct fw_packet *packet, u32 csr) 1466 { 1467 struct fw_packet response; 1468 int tcode, length, i; 1469 1470 tcode = HEADER_GET_TCODE(packet->header[0]); 1471 if (TCODE_IS_BLOCK_PACKET(tcode)) 1472 length = HEADER_GET_DATA_LENGTH(packet->header[3]); 1473 else 1474 length = 4; 1475 1476 i = csr - CSR_CONFIG_ROM; 1477 if (i + length > CONFIG_ROM_SIZE) { 1478 fw_fill_response(&response, packet->header, 1479 RCODE_ADDRESS_ERROR, NULL, 0); 1480 } else if (!TCODE_IS_READ_REQUEST(tcode)) { 1481 fw_fill_response(&response, packet->header, 1482 RCODE_TYPE_ERROR, NULL, 0); 1483 } else { 1484 fw_fill_response(&response, packet->header, RCODE_COMPLETE, 1485 (void *) ohci->config_rom + i, length); 1486 } 1487 1488 fw_core_handle_response(&ohci->card, &response); 1489 } 1490 1491 static void handle_local_lock(struct fw_ohci *ohci, 1492 struct fw_packet *packet, u32 csr) 1493 { 1494 struct fw_packet response; 1495 int tcode, length, ext_tcode, sel, try; 1496 __be32 *payload, lock_old; 1497 u32 lock_arg, lock_data; 1498 1499 tcode = HEADER_GET_TCODE(packet->header[0]); 1500 length = HEADER_GET_DATA_LENGTH(packet->header[3]); 1501 payload = packet->payload; 1502 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]); 1503 1504 if (tcode == TCODE_LOCK_REQUEST && 1505 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { 1506 lock_arg = be32_to_cpu(payload[0]); 1507 lock_data = be32_to_cpu(payload[1]); 1508 } else if (tcode == TCODE_READ_QUADLET_REQUEST) { 1509 lock_arg = 0; 1510 lock_data = 0; 1511 } else { 1512 fw_fill_response(&response, packet->header, 1513 RCODE_TYPE_ERROR, NULL, 0); 1514 goto out; 1515 } 1516 1517 sel = (csr - CSR_BUS_MANAGER_ID) / 4; 1518 reg_write(ohci, OHCI1394_CSRData, lock_data); 1519 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); 1520 reg_write(ohci, OHCI1394_CSRControl, sel); 1521 1522 for (try = 0; try < 20; try++) 1523 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) { 1524 lock_old = cpu_to_be32(reg_read(ohci, 1525 OHCI1394_CSRData)); 1526 fw_fill_response(&response, packet->header, 1527 RCODE_COMPLETE, 1528 &lock_old, sizeof(lock_old)); 1529 goto out; 1530 } 1531 1532 fw_error("swap not done (CSR lock timeout)\n"); 1533 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0); 1534 1535 out: 1536 fw_core_handle_response(&ohci->card, &response); 1537 } 1538 1539 static void handle_local_request(struct context *ctx, struct fw_packet *packet) 1540 { 1541 u64 offset, csr; 1542 1543 if (ctx == &ctx->ohci->at_request_ctx) { 1544 packet->ack = ACK_PENDING; 1545 packet->callback(packet, &ctx->ohci->card, packet->ack); 1546 } 1547 1548 offset = 1549 ((unsigned long long) 1550 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) | 1551 packet->header[2]; 1552 csr = offset - CSR_REGISTER_BASE; 1553 1554 /* Handle config rom reads. */ 1555 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) 1556 handle_local_rom(ctx->ohci, packet, csr); 1557 else switch (csr) { 1558 case CSR_BUS_MANAGER_ID: 1559 case CSR_BANDWIDTH_AVAILABLE: 1560 case CSR_CHANNELS_AVAILABLE_HI: 1561 case CSR_CHANNELS_AVAILABLE_LO: 1562 handle_local_lock(ctx->ohci, packet, csr); 1563 break; 1564 default: 1565 if (ctx == &ctx->ohci->at_request_ctx) 1566 fw_core_handle_request(&ctx->ohci->card, packet); 1567 else 1568 fw_core_handle_response(&ctx->ohci->card, packet); 1569 break; 1570 } 1571 1572 if (ctx == &ctx->ohci->at_response_ctx) { 1573 packet->ack = ACK_COMPLETE; 1574 packet->callback(packet, &ctx->ohci->card, packet->ack); 1575 } 1576 } 1577 1578 static void at_context_transmit(struct context *ctx, struct fw_packet *packet) 1579 { 1580 unsigned long flags; 1581 int ret; 1582 1583 spin_lock_irqsave(&ctx->ohci->lock, flags); 1584 1585 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id && 1586 ctx->ohci->generation == packet->generation) { 1587 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1588 handle_local_request(ctx, packet); 1589 return; 1590 } 1591 1592 ret = at_context_queue_packet(ctx, packet); 1593 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1594 1595 if (ret < 0) 1596 packet->callback(packet, &ctx->ohci->card, packet->ack); 1597 1598 } 1599 1600 static void detect_dead_context(struct fw_ohci *ohci, 1601 const char *name, unsigned int regs) 1602 { 1603 u32 ctl; 1604 1605 ctl = reg_read(ohci, CONTROL_SET(regs)); 1606 if (ctl & CONTEXT_DEAD) { 1607 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG 1608 fw_error("DMA context %s has stopped, error code: %s\n", 1609 name, evts[ctl & 0x1f]); 1610 #else 1611 fw_error("DMA context %s has stopped, error code: %#x\n", 1612 name, ctl & 0x1f); 1613 #endif 1614 } 1615 } 1616 1617 static void handle_dead_contexts(struct fw_ohci *ohci) 1618 { 1619 unsigned int i; 1620 char name[8]; 1621 1622 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase); 1623 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase); 1624 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase); 1625 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase); 1626 for (i = 0; i < 32; ++i) { 1627 if (!(ohci->it_context_support & (1 << i))) 1628 continue; 1629 sprintf(name, "IT%u", i); 1630 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i)); 1631 } 1632 for (i = 0; i < 32; ++i) { 1633 if (!(ohci->ir_context_support & (1 << i))) 1634 continue; 1635 sprintf(name, "IR%u", i); 1636 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i)); 1637 } 1638 /* TODO: maybe try to flush and restart the dead contexts */ 1639 } 1640 1641 static u32 cycle_timer_ticks(u32 cycle_timer) 1642 { 1643 u32 ticks; 1644 1645 ticks = cycle_timer & 0xfff; 1646 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff); 1647 ticks += (3072 * 8000) * (cycle_timer >> 25); 1648 1649 return ticks; 1650 } 1651 1652 /* 1653 * Some controllers exhibit one or more of the following bugs when updating the 1654 * iso cycle timer register: 1655 * - When the lowest six bits are wrapping around to zero, a read that happens 1656 * at the same time will return garbage in the lowest ten bits. 1657 * - When the cycleOffset field wraps around to zero, the cycleCount field is 1658 * not incremented for about 60 ns. 1659 * - Occasionally, the entire register reads zero. 1660 * 1661 * To catch these, we read the register three times and ensure that the 1662 * difference between each two consecutive reads is approximately the same, i.e. 1663 * less than twice the other. Furthermore, any negative difference indicates an 1664 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to 1665 * execute, so we have enough precision to compute the ratio of the differences.) 1666 */ 1667 static u32 get_cycle_time(struct fw_ohci *ohci) 1668 { 1669 u32 c0, c1, c2; 1670 u32 t0, t1, t2; 1671 s32 diff01, diff12; 1672 int i; 1673 1674 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1675 1676 if (ohci->quirks & QUIRK_CYCLE_TIMER) { 1677 i = 0; 1678 c1 = c2; 1679 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1680 do { 1681 c0 = c1; 1682 c1 = c2; 1683 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1684 t0 = cycle_timer_ticks(c0); 1685 t1 = cycle_timer_ticks(c1); 1686 t2 = cycle_timer_ticks(c2); 1687 diff01 = t1 - t0; 1688 diff12 = t2 - t1; 1689 } while ((diff01 <= 0 || diff12 <= 0 || 1690 diff01 / diff12 >= 2 || diff12 / diff01 >= 2) 1691 && i++ < 20); 1692 } 1693 1694 return c2; 1695 } 1696 1697 /* 1698 * This function has to be called at least every 64 seconds. The bus_time 1699 * field stores not only the upper 25 bits of the BUS_TIME register but also 1700 * the most significant bit of the cycle timer in bit 6 so that we can detect 1701 * changes in this bit. 1702 */ 1703 static u32 update_bus_time(struct fw_ohci *ohci) 1704 { 1705 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25; 1706 1707 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40)) 1708 ohci->bus_time += 0x40; 1709 1710 return ohci->bus_time | cycle_time_seconds; 1711 } 1712 1713 static void bus_reset_tasklet(unsigned long data) 1714 { 1715 struct fw_ohci *ohci = (struct fw_ohci *)data; 1716 int self_id_count, i, j, reg; 1717 int generation, new_generation; 1718 unsigned long flags; 1719 void *free_rom = NULL; 1720 dma_addr_t free_rom_bus = 0; 1721 bool is_new_root; 1722 1723 reg = reg_read(ohci, OHCI1394_NodeID); 1724 if (!(reg & OHCI1394_NodeID_idValid)) { 1725 fw_notify("node ID not valid, new bus reset in progress\n"); 1726 return; 1727 } 1728 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { 1729 fw_notify("malconfigured bus\n"); 1730 return; 1731 } 1732 ohci->node_id = reg & (OHCI1394_NodeID_busNumber | 1733 OHCI1394_NodeID_nodeNumber); 1734 1735 is_new_root = (reg & OHCI1394_NodeID_root) != 0; 1736 if (!(ohci->is_root && is_new_root)) 1737 reg_write(ohci, OHCI1394_LinkControlSet, 1738 OHCI1394_LinkControl_cycleMaster); 1739 ohci->is_root = is_new_root; 1740 1741 reg = reg_read(ohci, OHCI1394_SelfIDCount); 1742 if (reg & OHCI1394_SelfIDCount_selfIDError) { 1743 fw_notify("inconsistent self IDs\n"); 1744 return; 1745 } 1746 /* 1747 * The count in the SelfIDCount register is the number of 1748 * bytes in the self ID receive buffer. Since we also receive 1749 * the inverted quadlets and a header quadlet, we shift one 1750 * bit extra to get the actual number of self IDs. 1751 */ 1752 self_id_count = (reg >> 3) & 0xff; 1753 if (self_id_count == 0 || self_id_count > 252) { 1754 fw_notify("inconsistent self IDs\n"); 1755 return; 1756 } 1757 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff; 1758 rmb(); 1759 1760 for (i = 1, j = 0; j < self_id_count; i += 2, j++) { 1761 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) { 1762 fw_notify("inconsistent self IDs\n"); 1763 return; 1764 } 1765 ohci->self_id_buffer[j] = 1766 cond_le32_to_cpu(ohci->self_id_cpu[i]); 1767 } 1768 rmb(); 1769 1770 /* 1771 * Check the consistency of the self IDs we just read. The 1772 * problem we face is that a new bus reset can start while we 1773 * read out the self IDs from the DMA buffer. If this happens, 1774 * the DMA buffer will be overwritten with new self IDs and we 1775 * will read out inconsistent data. The OHCI specification 1776 * (section 11.2) recommends a technique similar to 1777 * linux/seqlock.h, where we remember the generation of the 1778 * self IDs in the buffer before reading them out and compare 1779 * it to the current generation after reading them out. If 1780 * the two generations match we know we have a consistent set 1781 * of self IDs. 1782 */ 1783 1784 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; 1785 if (new_generation != generation) { 1786 fw_notify("recursive bus reset detected, " 1787 "discarding self ids\n"); 1788 return; 1789 } 1790 1791 /* FIXME: Document how the locking works. */ 1792 spin_lock_irqsave(&ohci->lock, flags); 1793 1794 ohci->generation = -1; /* prevent AT packet queueing */ 1795 context_stop(&ohci->at_request_ctx); 1796 context_stop(&ohci->at_response_ctx); 1797 1798 spin_unlock_irqrestore(&ohci->lock, flags); 1799 1800 /* 1801 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent 1802 * packets in the AT queues and software needs to drain them. 1803 * Some OHCI 1.1 controllers (JMicron) apparently require this too. 1804 */ 1805 at_context_flush(&ohci->at_request_ctx); 1806 at_context_flush(&ohci->at_response_ctx); 1807 1808 spin_lock_irqsave(&ohci->lock, flags); 1809 1810 ohci->generation = generation; 1811 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); 1812 1813 if (ohci->quirks & QUIRK_RESET_PACKET) 1814 ohci->request_generation = generation; 1815 1816 /* 1817 * This next bit is unrelated to the AT context stuff but we 1818 * have to do it under the spinlock also. If a new config rom 1819 * was set up before this reset, the old one is now no longer 1820 * in use and we can free it. Update the config rom pointers 1821 * to point to the current config rom and clear the 1822 * next_config_rom pointer so a new update can take place. 1823 */ 1824 1825 if (ohci->next_config_rom != NULL) { 1826 if (ohci->next_config_rom != ohci->config_rom) { 1827 free_rom = ohci->config_rom; 1828 free_rom_bus = ohci->config_rom_bus; 1829 } 1830 ohci->config_rom = ohci->next_config_rom; 1831 ohci->config_rom_bus = ohci->next_config_rom_bus; 1832 ohci->next_config_rom = NULL; 1833 1834 /* 1835 * Restore config_rom image and manually update 1836 * config_rom registers. Writing the header quadlet 1837 * will indicate that the config rom is ready, so we 1838 * do that last. 1839 */ 1840 reg_write(ohci, OHCI1394_BusOptions, 1841 be32_to_cpu(ohci->config_rom[2])); 1842 ohci->config_rom[0] = ohci->next_header; 1843 reg_write(ohci, OHCI1394_ConfigROMhdr, 1844 be32_to_cpu(ohci->next_header)); 1845 } 1846 1847 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA 1848 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0); 1849 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0); 1850 #endif 1851 1852 spin_unlock_irqrestore(&ohci->lock, flags); 1853 1854 if (free_rom) 1855 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 1856 free_rom, free_rom_bus); 1857 1858 log_selfids(ohci->node_id, generation, 1859 self_id_count, ohci->self_id_buffer); 1860 1861 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, 1862 self_id_count, ohci->self_id_buffer, 1863 ohci->csr_state_setclear_abdicate); 1864 ohci->csr_state_setclear_abdicate = false; 1865 } 1866 1867 static irqreturn_t irq_handler(int irq, void *data) 1868 { 1869 struct fw_ohci *ohci = data; 1870 u32 event, iso_event; 1871 int i; 1872 1873 event = reg_read(ohci, OHCI1394_IntEventClear); 1874 1875 if (!event || !~event) 1876 return IRQ_NONE; 1877 1878 /* 1879 * busReset and postedWriteErr must not be cleared yet 1880 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1) 1881 */ 1882 reg_write(ohci, OHCI1394_IntEventClear, 1883 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr)); 1884 log_irqs(event); 1885 1886 if (event & OHCI1394_selfIDComplete) 1887 tasklet_schedule(&ohci->bus_reset_tasklet); 1888 1889 if (event & OHCI1394_RQPkt) 1890 tasklet_schedule(&ohci->ar_request_ctx.tasklet); 1891 1892 if (event & OHCI1394_RSPkt) 1893 tasklet_schedule(&ohci->ar_response_ctx.tasklet); 1894 1895 if (event & OHCI1394_reqTxComplete) 1896 tasklet_schedule(&ohci->at_request_ctx.tasklet); 1897 1898 if (event & OHCI1394_respTxComplete) 1899 tasklet_schedule(&ohci->at_response_ctx.tasklet); 1900 1901 if (event & OHCI1394_isochRx) { 1902 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); 1903 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); 1904 1905 while (iso_event) { 1906 i = ffs(iso_event) - 1; 1907 tasklet_schedule( 1908 &ohci->ir_context_list[i].context.tasklet); 1909 iso_event &= ~(1 << i); 1910 } 1911 } 1912 1913 if (event & OHCI1394_isochTx) { 1914 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); 1915 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); 1916 1917 while (iso_event) { 1918 i = ffs(iso_event) - 1; 1919 tasklet_schedule( 1920 &ohci->it_context_list[i].context.tasklet); 1921 iso_event &= ~(1 << i); 1922 } 1923 } 1924 1925 if (unlikely(event & OHCI1394_regAccessFail)) 1926 fw_error("Register access failure - " 1927 "please notify linux1394-devel@lists.sf.net\n"); 1928 1929 if (unlikely(event & OHCI1394_postedWriteErr)) { 1930 reg_read(ohci, OHCI1394_PostedWriteAddressHi); 1931 reg_read(ohci, OHCI1394_PostedWriteAddressLo); 1932 reg_write(ohci, OHCI1394_IntEventClear, 1933 OHCI1394_postedWriteErr); 1934 fw_error("PCI posted write error\n"); 1935 } 1936 1937 if (unlikely(event & OHCI1394_cycleTooLong)) { 1938 if (printk_ratelimit()) 1939 fw_notify("isochronous cycle too long\n"); 1940 reg_write(ohci, OHCI1394_LinkControlSet, 1941 OHCI1394_LinkControl_cycleMaster); 1942 } 1943 1944 if (unlikely(event & OHCI1394_cycleInconsistent)) { 1945 /* 1946 * We need to clear this event bit in order to make 1947 * cycleMatch isochronous I/O work. In theory we should 1948 * stop active cycleMatch iso contexts now and restart 1949 * them at least two cycles later. (FIXME?) 1950 */ 1951 if (printk_ratelimit()) 1952 fw_notify("isochronous cycle inconsistent\n"); 1953 } 1954 1955 if (unlikely(event & OHCI1394_unrecoverableError)) 1956 handle_dead_contexts(ohci); 1957 1958 if (event & OHCI1394_cycle64Seconds) { 1959 spin_lock(&ohci->lock); 1960 update_bus_time(ohci); 1961 spin_unlock(&ohci->lock); 1962 } else 1963 flush_writes(ohci); 1964 1965 return IRQ_HANDLED; 1966 } 1967 1968 static int software_reset(struct fw_ohci *ohci) 1969 { 1970 u32 val; 1971 int i; 1972 1973 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); 1974 for (i = 0; i < 500; i++) { 1975 val = reg_read(ohci, OHCI1394_HCControlSet); 1976 if (!~val) 1977 return -ENODEV; /* Card was ejected. */ 1978 1979 if (!(val & OHCI1394_HCControl_softReset)) 1980 return 0; 1981 1982 msleep(1); 1983 } 1984 1985 return -EBUSY; 1986 } 1987 1988 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length) 1989 { 1990 size_t size = length * 4; 1991 1992 memcpy(dest, src, size); 1993 if (size < CONFIG_ROM_SIZE) 1994 memset(&dest[length], 0, CONFIG_ROM_SIZE - size); 1995 } 1996 1997 static int configure_1394a_enhancements(struct fw_ohci *ohci) 1998 { 1999 bool enable_1394a; 2000 int ret, clear, set, offset; 2001 2002 /* Check if the driver should configure link and PHY. */ 2003 if (!(reg_read(ohci, OHCI1394_HCControlSet) & 2004 OHCI1394_HCControl_programPhyEnable)) 2005 return 0; 2006 2007 /* Paranoia: check whether the PHY supports 1394a, too. */ 2008 enable_1394a = false; 2009 ret = read_phy_reg(ohci, 2); 2010 if (ret < 0) 2011 return ret; 2012 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) { 2013 ret = read_paged_phy_reg(ohci, 1, 8); 2014 if (ret < 0) 2015 return ret; 2016 if (ret >= 1) 2017 enable_1394a = true; 2018 } 2019 2020 if (ohci->quirks & QUIRK_NO_1394A) 2021 enable_1394a = false; 2022 2023 /* Configure PHY and link consistently. */ 2024 if (enable_1394a) { 2025 clear = 0; 2026 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2027 } else { 2028 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2029 set = 0; 2030 } 2031 ret = update_phy_reg(ohci, 5, clear, set); 2032 if (ret < 0) 2033 return ret; 2034 2035 if (enable_1394a) 2036 offset = OHCI1394_HCControlSet; 2037 else 2038 offset = OHCI1394_HCControlClear; 2039 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable); 2040 2041 /* Clean up: configuration has been taken care of. */ 2042 reg_write(ohci, OHCI1394_HCControlClear, 2043 OHCI1394_HCControl_programPhyEnable); 2044 2045 return 0; 2046 } 2047 2048 static int ohci_enable(struct fw_card *card, 2049 const __be32 *config_rom, size_t length) 2050 { 2051 struct fw_ohci *ohci = fw_ohci(card); 2052 struct pci_dev *dev = to_pci_dev(card->device); 2053 u32 lps, seconds, version, irqs; 2054 int i, ret; 2055 2056 if (software_reset(ohci)) { 2057 fw_error("Failed to reset ohci card.\n"); 2058 return -EBUSY; 2059 } 2060 2061 /* 2062 * Now enable LPS, which we need in order to start accessing 2063 * most of the registers. In fact, on some cards (ALI M5251), 2064 * accessing registers in the SClk domain without LPS enabled 2065 * will lock up the machine. Wait 50msec to make sure we have 2066 * full link enabled. However, with some cards (well, at least 2067 * a JMicron PCIe card), we have to try again sometimes. 2068 */ 2069 reg_write(ohci, OHCI1394_HCControlSet, 2070 OHCI1394_HCControl_LPS | 2071 OHCI1394_HCControl_postedWriteEnable); 2072 flush_writes(ohci); 2073 2074 for (lps = 0, i = 0; !lps && i < 3; i++) { 2075 msleep(50); 2076 lps = reg_read(ohci, OHCI1394_HCControlSet) & 2077 OHCI1394_HCControl_LPS; 2078 } 2079 2080 if (!lps) { 2081 fw_error("Failed to set Link Power Status\n"); 2082 return -EIO; 2083 } 2084 2085 reg_write(ohci, OHCI1394_HCControlClear, 2086 OHCI1394_HCControl_noByteSwapData); 2087 2088 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); 2089 reg_write(ohci, OHCI1394_LinkControlSet, 2090 OHCI1394_LinkControl_cycleTimerEnable | 2091 OHCI1394_LinkControl_cycleMaster); 2092 2093 reg_write(ohci, OHCI1394_ATRetries, 2094 OHCI1394_MAX_AT_REQ_RETRIES | 2095 (OHCI1394_MAX_AT_RESP_RETRIES << 4) | 2096 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) | 2097 (200 << 16)); 2098 2099 seconds = lower_32_bits(get_seconds()); 2100 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25); 2101 ohci->bus_time = seconds & ~0x3f; 2102 2103 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 2104 if (version >= OHCI_VERSION_1_1) { 2105 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi, 2106 0xfffffffe); 2107 card->broadcast_channel_auto_allocated = true; 2108 } 2109 2110 /* Get implemented bits of the priority arbitration request counter. */ 2111 reg_write(ohci, OHCI1394_FairnessControl, 0x3f); 2112 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f; 2113 reg_write(ohci, OHCI1394_FairnessControl, 0); 2114 card->priority_budget_implemented = ohci->pri_req_max != 0; 2115 2116 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000); 2117 reg_write(ohci, OHCI1394_IntEventClear, ~0); 2118 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 2119 2120 ret = configure_1394a_enhancements(ohci); 2121 if (ret < 0) 2122 return ret; 2123 2124 /* Activate link_on bit and contender bit in our self ID packets.*/ 2125 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER); 2126 if (ret < 0) 2127 return ret; 2128 2129 /* 2130 * When the link is not yet enabled, the atomic config rom 2131 * update mechanism described below in ohci_set_config_rom() 2132 * is not active. We have to update ConfigRomHeader and 2133 * BusOptions manually, and the write to ConfigROMmap takes 2134 * effect immediately. We tie this to the enabling of the 2135 * link, so we have a valid config rom before enabling - the 2136 * OHCI requires that ConfigROMhdr and BusOptions have valid 2137 * values before enabling. 2138 * 2139 * However, when the ConfigROMmap is written, some controllers 2140 * always read back quadlets 0 and 2 from the config rom to 2141 * the ConfigRomHeader and BusOptions registers on bus reset. 2142 * They shouldn't do that in this initial case where the link 2143 * isn't enabled. This means we have to use the same 2144 * workaround here, setting the bus header to 0 and then write 2145 * the right values in the bus reset tasklet. 2146 */ 2147 2148 if (config_rom) { 2149 ohci->next_config_rom = 2150 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2151 &ohci->next_config_rom_bus, 2152 GFP_KERNEL); 2153 if (ohci->next_config_rom == NULL) 2154 return -ENOMEM; 2155 2156 copy_config_rom(ohci->next_config_rom, config_rom, length); 2157 } else { 2158 /* 2159 * In the suspend case, config_rom is NULL, which 2160 * means that we just reuse the old config rom. 2161 */ 2162 ohci->next_config_rom = ohci->config_rom; 2163 ohci->next_config_rom_bus = ohci->config_rom_bus; 2164 } 2165 2166 ohci->next_header = ohci->next_config_rom[0]; 2167 ohci->next_config_rom[0] = 0; 2168 reg_write(ohci, OHCI1394_ConfigROMhdr, 0); 2169 reg_write(ohci, OHCI1394_BusOptions, 2170 be32_to_cpu(ohci->next_config_rom[2])); 2171 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2172 2173 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); 2174 2175 if (!(ohci->quirks & QUIRK_NO_MSI)) 2176 pci_enable_msi(dev); 2177 if (request_irq(dev->irq, irq_handler, 2178 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED, 2179 ohci_driver_name, ohci)) { 2180 fw_error("Failed to allocate interrupt %d.\n", dev->irq); 2181 pci_disable_msi(dev); 2182 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2183 ohci->config_rom, ohci->config_rom_bus); 2184 return -EIO; 2185 } 2186 2187 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete | 2188 OHCI1394_RQPkt | OHCI1394_RSPkt | 2189 OHCI1394_isochTx | OHCI1394_isochRx | 2190 OHCI1394_postedWriteErr | 2191 OHCI1394_selfIDComplete | 2192 OHCI1394_regAccessFail | 2193 OHCI1394_cycle64Seconds | 2194 OHCI1394_cycleInconsistent | 2195 OHCI1394_unrecoverableError | 2196 OHCI1394_cycleTooLong | 2197 OHCI1394_masterIntEnable; 2198 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS) 2199 irqs |= OHCI1394_busReset; 2200 reg_write(ohci, OHCI1394_IntMaskSet, irqs); 2201 2202 reg_write(ohci, OHCI1394_HCControlSet, 2203 OHCI1394_HCControl_linkEnable | 2204 OHCI1394_HCControl_BIBimageValid); 2205 2206 reg_write(ohci, OHCI1394_LinkControlSet, 2207 OHCI1394_LinkControl_rcvSelfID | 2208 OHCI1394_LinkControl_rcvPhyPkt); 2209 2210 ar_context_run(&ohci->ar_request_ctx); 2211 ar_context_run(&ohci->ar_response_ctx); 2212 2213 flush_writes(ohci); 2214 2215 /* We are ready to go, reset bus to finish initialization. */ 2216 fw_schedule_bus_reset(&ohci->card, false, true); 2217 2218 return 0; 2219 } 2220 2221 static int ohci_set_config_rom(struct fw_card *card, 2222 const __be32 *config_rom, size_t length) 2223 { 2224 struct fw_ohci *ohci; 2225 unsigned long flags; 2226 __be32 *next_config_rom; 2227 dma_addr_t uninitialized_var(next_config_rom_bus); 2228 2229 ohci = fw_ohci(card); 2230 2231 /* 2232 * When the OHCI controller is enabled, the config rom update 2233 * mechanism is a bit tricky, but easy enough to use. See 2234 * section 5.5.6 in the OHCI specification. 2235 * 2236 * The OHCI controller caches the new config rom address in a 2237 * shadow register (ConfigROMmapNext) and needs a bus reset 2238 * for the changes to take place. When the bus reset is 2239 * detected, the controller loads the new values for the 2240 * ConfigRomHeader and BusOptions registers from the specified 2241 * config rom and loads ConfigROMmap from the ConfigROMmapNext 2242 * shadow register. All automatically and atomically. 2243 * 2244 * Now, there's a twist to this story. The automatic load of 2245 * ConfigRomHeader and BusOptions doesn't honor the 2246 * noByteSwapData bit, so with a be32 config rom, the 2247 * controller will load be32 values in to these registers 2248 * during the atomic update, even on litte endian 2249 * architectures. The workaround we use is to put a 0 in the 2250 * header quadlet; 0 is endian agnostic and means that the 2251 * config rom isn't ready yet. In the bus reset tasklet we 2252 * then set up the real values for the two registers. 2253 * 2254 * We use ohci->lock to avoid racing with the code that sets 2255 * ohci->next_config_rom to NULL (see bus_reset_tasklet). 2256 */ 2257 2258 next_config_rom = 2259 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2260 &next_config_rom_bus, GFP_KERNEL); 2261 if (next_config_rom == NULL) 2262 return -ENOMEM; 2263 2264 spin_lock_irqsave(&ohci->lock, flags); 2265 2266 /* 2267 * If there is not an already pending config_rom update, 2268 * push our new allocation into the ohci->next_config_rom 2269 * and then mark the local variable as null so that we 2270 * won't deallocate the new buffer. 2271 * 2272 * OTOH, if there is a pending config_rom update, just 2273 * use that buffer with the new config_rom data, and 2274 * let this routine free the unused DMA allocation. 2275 */ 2276 2277 if (ohci->next_config_rom == NULL) { 2278 ohci->next_config_rom = next_config_rom; 2279 ohci->next_config_rom_bus = next_config_rom_bus; 2280 next_config_rom = NULL; 2281 } 2282 2283 copy_config_rom(ohci->next_config_rom, config_rom, length); 2284 2285 ohci->next_header = config_rom[0]; 2286 ohci->next_config_rom[0] = 0; 2287 2288 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2289 2290 spin_unlock_irqrestore(&ohci->lock, flags); 2291 2292 /* If we didn't use the DMA allocation, delete it. */ 2293 if (next_config_rom != NULL) 2294 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2295 next_config_rom, next_config_rom_bus); 2296 2297 /* 2298 * Now initiate a bus reset to have the changes take 2299 * effect. We clean up the old config rom memory and DMA 2300 * mappings in the bus reset tasklet, since the OHCI 2301 * controller could need to access it before the bus reset 2302 * takes effect. 2303 */ 2304 2305 fw_schedule_bus_reset(&ohci->card, true, true); 2306 2307 return 0; 2308 } 2309 2310 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) 2311 { 2312 struct fw_ohci *ohci = fw_ohci(card); 2313 2314 at_context_transmit(&ohci->at_request_ctx, packet); 2315 } 2316 2317 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) 2318 { 2319 struct fw_ohci *ohci = fw_ohci(card); 2320 2321 at_context_transmit(&ohci->at_response_ctx, packet); 2322 } 2323 2324 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) 2325 { 2326 struct fw_ohci *ohci = fw_ohci(card); 2327 struct context *ctx = &ohci->at_request_ctx; 2328 struct driver_data *driver_data = packet->driver_data; 2329 int ret = -ENOENT; 2330 2331 tasklet_disable(&ctx->tasklet); 2332 2333 if (packet->ack != 0) 2334 goto out; 2335 2336 if (packet->payload_mapped) 2337 dma_unmap_single(ohci->card.device, packet->payload_bus, 2338 packet->payload_length, DMA_TO_DEVICE); 2339 2340 log_ar_at_event('T', packet->speed, packet->header, 0x20); 2341 driver_data->packet = NULL; 2342 packet->ack = RCODE_CANCELLED; 2343 packet->callback(packet, &ohci->card, packet->ack); 2344 ret = 0; 2345 out: 2346 tasklet_enable(&ctx->tasklet); 2347 2348 return ret; 2349 } 2350 2351 static int ohci_enable_phys_dma(struct fw_card *card, 2352 int node_id, int generation) 2353 { 2354 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA 2355 return 0; 2356 #else 2357 struct fw_ohci *ohci = fw_ohci(card); 2358 unsigned long flags; 2359 int n, ret = 0; 2360 2361 /* 2362 * FIXME: Make sure this bitmask is cleared when we clear the busReset 2363 * interrupt bit. Clear physReqResourceAllBuses on bus reset. 2364 */ 2365 2366 spin_lock_irqsave(&ohci->lock, flags); 2367 2368 if (ohci->generation != generation) { 2369 ret = -ESTALE; 2370 goto out; 2371 } 2372 2373 /* 2374 * Note, if the node ID contains a non-local bus ID, physical DMA is 2375 * enabled for _all_ nodes on remote buses. 2376 */ 2377 2378 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; 2379 if (n < 32) 2380 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); 2381 else 2382 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); 2383 2384 flush_writes(ohci); 2385 out: 2386 spin_unlock_irqrestore(&ohci->lock, flags); 2387 2388 return ret; 2389 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */ 2390 } 2391 2392 static u32 ohci_read_csr(struct fw_card *card, int csr_offset) 2393 { 2394 struct fw_ohci *ohci = fw_ohci(card); 2395 unsigned long flags; 2396 u32 value; 2397 2398 switch (csr_offset) { 2399 case CSR_STATE_CLEAR: 2400 case CSR_STATE_SET: 2401 if (ohci->is_root && 2402 (reg_read(ohci, OHCI1394_LinkControlSet) & 2403 OHCI1394_LinkControl_cycleMaster)) 2404 value = CSR_STATE_BIT_CMSTR; 2405 else 2406 value = 0; 2407 if (ohci->csr_state_setclear_abdicate) 2408 value |= CSR_STATE_BIT_ABDICATE; 2409 2410 return value; 2411 2412 case CSR_NODE_IDS: 2413 return reg_read(ohci, OHCI1394_NodeID) << 16; 2414 2415 case CSR_CYCLE_TIME: 2416 return get_cycle_time(ohci); 2417 2418 case CSR_BUS_TIME: 2419 /* 2420 * We might be called just after the cycle timer has wrapped 2421 * around but just before the cycle64Seconds handler, so we 2422 * better check here, too, if the bus time needs to be updated. 2423 */ 2424 spin_lock_irqsave(&ohci->lock, flags); 2425 value = update_bus_time(ohci); 2426 spin_unlock_irqrestore(&ohci->lock, flags); 2427 return value; 2428 2429 case CSR_BUSY_TIMEOUT: 2430 value = reg_read(ohci, OHCI1394_ATRetries); 2431 return (value >> 4) & 0x0ffff00f; 2432 2433 case CSR_PRIORITY_BUDGET: 2434 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) | 2435 (ohci->pri_req_max << 8); 2436 2437 default: 2438 WARN_ON(1); 2439 return 0; 2440 } 2441 } 2442 2443 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value) 2444 { 2445 struct fw_ohci *ohci = fw_ohci(card); 2446 unsigned long flags; 2447 2448 switch (csr_offset) { 2449 case CSR_STATE_CLEAR: 2450 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2451 reg_write(ohci, OHCI1394_LinkControlClear, 2452 OHCI1394_LinkControl_cycleMaster); 2453 flush_writes(ohci); 2454 } 2455 if (value & CSR_STATE_BIT_ABDICATE) 2456 ohci->csr_state_setclear_abdicate = false; 2457 break; 2458 2459 case CSR_STATE_SET: 2460 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2461 reg_write(ohci, OHCI1394_LinkControlSet, 2462 OHCI1394_LinkControl_cycleMaster); 2463 flush_writes(ohci); 2464 } 2465 if (value & CSR_STATE_BIT_ABDICATE) 2466 ohci->csr_state_setclear_abdicate = true; 2467 break; 2468 2469 case CSR_NODE_IDS: 2470 reg_write(ohci, OHCI1394_NodeID, value >> 16); 2471 flush_writes(ohci); 2472 break; 2473 2474 case CSR_CYCLE_TIME: 2475 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value); 2476 reg_write(ohci, OHCI1394_IntEventSet, 2477 OHCI1394_cycleInconsistent); 2478 flush_writes(ohci); 2479 break; 2480 2481 case CSR_BUS_TIME: 2482 spin_lock_irqsave(&ohci->lock, flags); 2483 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f); 2484 spin_unlock_irqrestore(&ohci->lock, flags); 2485 break; 2486 2487 case CSR_BUSY_TIMEOUT: 2488 value = (value & 0xf) | ((value & 0xf) << 4) | 2489 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4); 2490 reg_write(ohci, OHCI1394_ATRetries, value); 2491 flush_writes(ohci); 2492 break; 2493 2494 case CSR_PRIORITY_BUDGET: 2495 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f); 2496 flush_writes(ohci); 2497 break; 2498 2499 default: 2500 WARN_ON(1); 2501 break; 2502 } 2503 } 2504 2505 static void copy_iso_headers(struct iso_context *ctx, void *p) 2506 { 2507 int i = ctx->header_length; 2508 2509 if (i + ctx->base.header_size > PAGE_SIZE) 2510 return; 2511 2512 /* 2513 * The iso header is byteswapped to little endian by 2514 * the controller, but the remaining header quadlets 2515 * are big endian. We want to present all the headers 2516 * as big endian, so we have to swap the first quadlet. 2517 */ 2518 if (ctx->base.header_size > 0) 2519 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4)); 2520 if (ctx->base.header_size > 4) 2521 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p); 2522 if (ctx->base.header_size > 8) 2523 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8); 2524 ctx->header_length += ctx->base.header_size; 2525 } 2526 2527 static int handle_ir_packet_per_buffer(struct context *context, 2528 struct descriptor *d, 2529 struct descriptor *last) 2530 { 2531 struct iso_context *ctx = 2532 container_of(context, struct iso_context, context); 2533 struct descriptor *pd; 2534 __le32 *ir_header; 2535 void *p; 2536 2537 for (pd = d; pd <= last; pd++) 2538 if (pd->transfer_status) 2539 break; 2540 if (pd > last) 2541 /* Descriptor(s) not done yet, stop iteration */ 2542 return 0; 2543 2544 p = last + 1; 2545 copy_iso_headers(ctx, p); 2546 2547 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) { 2548 ir_header = (__le32 *) p; 2549 ctx->base.callback.sc(&ctx->base, 2550 le32_to_cpu(ir_header[0]) & 0xffff, 2551 ctx->header_length, ctx->header, 2552 ctx->base.callback_data); 2553 ctx->header_length = 0; 2554 } 2555 2556 return 1; 2557 } 2558 2559 /* d == last because each descriptor block is only a single descriptor. */ 2560 static int handle_ir_buffer_fill(struct context *context, 2561 struct descriptor *d, 2562 struct descriptor *last) 2563 { 2564 struct iso_context *ctx = 2565 container_of(context, struct iso_context, context); 2566 2567 if (!last->transfer_status) 2568 /* Descriptor(s) not done yet, stop iteration */ 2569 return 0; 2570 2571 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) 2572 ctx->base.callback.mc(&ctx->base, 2573 le32_to_cpu(last->data_address) + 2574 le16_to_cpu(last->req_count) - 2575 le16_to_cpu(last->res_count), 2576 ctx->base.callback_data); 2577 2578 return 1; 2579 } 2580 2581 static int handle_it_packet(struct context *context, 2582 struct descriptor *d, 2583 struct descriptor *last) 2584 { 2585 struct iso_context *ctx = 2586 container_of(context, struct iso_context, context); 2587 int i; 2588 struct descriptor *pd; 2589 2590 for (pd = d; pd <= last; pd++) 2591 if (pd->transfer_status) 2592 break; 2593 if (pd > last) 2594 /* Descriptor(s) not done yet, stop iteration */ 2595 return 0; 2596 2597 i = ctx->header_length; 2598 if (i + 4 < PAGE_SIZE) { 2599 /* Present this value as big-endian to match the receive code */ 2600 *(__be32 *)(ctx->header + i) = cpu_to_be32( 2601 ((u32)le16_to_cpu(pd->transfer_status) << 16) | 2602 le16_to_cpu(pd->res_count)); 2603 ctx->header_length += 4; 2604 } 2605 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) { 2606 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count), 2607 ctx->header_length, ctx->header, 2608 ctx->base.callback_data); 2609 ctx->header_length = 0; 2610 } 2611 return 1; 2612 } 2613 2614 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels) 2615 { 2616 u32 hi = channels >> 32, lo = channels; 2617 2618 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi); 2619 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo); 2620 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi); 2621 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo); 2622 mmiowb(); 2623 ohci->mc_channels = channels; 2624 } 2625 2626 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card, 2627 int type, int channel, size_t header_size) 2628 { 2629 struct fw_ohci *ohci = fw_ohci(card); 2630 struct iso_context *uninitialized_var(ctx); 2631 descriptor_callback_t uninitialized_var(callback); 2632 u64 *uninitialized_var(channels); 2633 u32 *uninitialized_var(mask), uninitialized_var(regs); 2634 unsigned long flags; 2635 int index, ret = -EBUSY; 2636 2637 spin_lock_irqsave(&ohci->lock, flags); 2638 2639 switch (type) { 2640 case FW_ISO_CONTEXT_TRANSMIT: 2641 mask = &ohci->it_context_mask; 2642 callback = handle_it_packet; 2643 index = ffs(*mask) - 1; 2644 if (index >= 0) { 2645 *mask &= ~(1 << index); 2646 regs = OHCI1394_IsoXmitContextBase(index); 2647 ctx = &ohci->it_context_list[index]; 2648 } 2649 break; 2650 2651 case FW_ISO_CONTEXT_RECEIVE: 2652 channels = &ohci->ir_context_channels; 2653 mask = &ohci->ir_context_mask; 2654 callback = handle_ir_packet_per_buffer; 2655 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1; 2656 if (index >= 0) { 2657 *channels &= ~(1ULL << channel); 2658 *mask &= ~(1 << index); 2659 regs = OHCI1394_IsoRcvContextBase(index); 2660 ctx = &ohci->ir_context_list[index]; 2661 } 2662 break; 2663 2664 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2665 mask = &ohci->ir_context_mask; 2666 callback = handle_ir_buffer_fill; 2667 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1; 2668 if (index >= 0) { 2669 ohci->mc_allocated = true; 2670 *mask &= ~(1 << index); 2671 regs = OHCI1394_IsoRcvContextBase(index); 2672 ctx = &ohci->ir_context_list[index]; 2673 } 2674 break; 2675 2676 default: 2677 index = -1; 2678 ret = -ENOSYS; 2679 } 2680 2681 spin_unlock_irqrestore(&ohci->lock, flags); 2682 2683 if (index < 0) 2684 return ERR_PTR(ret); 2685 2686 memset(ctx, 0, sizeof(*ctx)); 2687 ctx->header_length = 0; 2688 ctx->header = (void *) __get_free_page(GFP_KERNEL); 2689 if (ctx->header == NULL) { 2690 ret = -ENOMEM; 2691 goto out; 2692 } 2693 ret = context_init(&ctx->context, ohci, regs, callback); 2694 if (ret < 0) 2695 goto out_with_header; 2696 2697 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) 2698 set_multichannel_mask(ohci, 0); 2699 2700 return &ctx->base; 2701 2702 out_with_header: 2703 free_page((unsigned long)ctx->header); 2704 out: 2705 spin_lock_irqsave(&ohci->lock, flags); 2706 2707 switch (type) { 2708 case FW_ISO_CONTEXT_RECEIVE: 2709 *channels |= 1ULL << channel; 2710 break; 2711 2712 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2713 ohci->mc_allocated = false; 2714 break; 2715 } 2716 *mask |= 1 << index; 2717 2718 spin_unlock_irqrestore(&ohci->lock, flags); 2719 2720 return ERR_PTR(ret); 2721 } 2722 2723 static int ohci_start_iso(struct fw_iso_context *base, 2724 s32 cycle, u32 sync, u32 tags) 2725 { 2726 struct iso_context *ctx = container_of(base, struct iso_context, base); 2727 struct fw_ohci *ohci = ctx->context.ohci; 2728 u32 control = IR_CONTEXT_ISOCH_HEADER, match; 2729 int index; 2730 2731 /* the controller cannot start without any queued packets */ 2732 if (ctx->context.last->branch_address == 0) 2733 return -ENODATA; 2734 2735 switch (ctx->base.type) { 2736 case FW_ISO_CONTEXT_TRANSMIT: 2737 index = ctx - ohci->it_context_list; 2738 match = 0; 2739 if (cycle >= 0) 2740 match = IT_CONTEXT_CYCLE_MATCH_ENABLE | 2741 (cycle & 0x7fff) << 16; 2742 2743 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); 2744 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); 2745 context_run(&ctx->context, match); 2746 break; 2747 2748 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2749 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE; 2750 /* fall through */ 2751 case FW_ISO_CONTEXT_RECEIVE: 2752 index = ctx - ohci->ir_context_list; 2753 match = (tags << 28) | (sync << 8) | ctx->base.channel; 2754 if (cycle >= 0) { 2755 match |= (cycle & 0x07fff) << 12; 2756 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE; 2757 } 2758 2759 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); 2760 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); 2761 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match); 2762 context_run(&ctx->context, control); 2763 2764 ctx->sync = sync; 2765 ctx->tags = tags; 2766 2767 break; 2768 } 2769 2770 return 0; 2771 } 2772 2773 static int ohci_stop_iso(struct fw_iso_context *base) 2774 { 2775 struct fw_ohci *ohci = fw_ohci(base->card); 2776 struct iso_context *ctx = container_of(base, struct iso_context, base); 2777 int index; 2778 2779 switch (ctx->base.type) { 2780 case FW_ISO_CONTEXT_TRANSMIT: 2781 index = ctx - ohci->it_context_list; 2782 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); 2783 break; 2784 2785 case FW_ISO_CONTEXT_RECEIVE: 2786 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2787 index = ctx - ohci->ir_context_list; 2788 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); 2789 break; 2790 } 2791 flush_writes(ohci); 2792 context_stop(&ctx->context); 2793 tasklet_kill(&ctx->context.tasklet); 2794 2795 return 0; 2796 } 2797 2798 static void ohci_free_iso_context(struct fw_iso_context *base) 2799 { 2800 struct fw_ohci *ohci = fw_ohci(base->card); 2801 struct iso_context *ctx = container_of(base, struct iso_context, base); 2802 unsigned long flags; 2803 int index; 2804 2805 ohci_stop_iso(base); 2806 context_release(&ctx->context); 2807 free_page((unsigned long)ctx->header); 2808 2809 spin_lock_irqsave(&ohci->lock, flags); 2810 2811 switch (base->type) { 2812 case FW_ISO_CONTEXT_TRANSMIT: 2813 index = ctx - ohci->it_context_list; 2814 ohci->it_context_mask |= 1 << index; 2815 break; 2816 2817 case FW_ISO_CONTEXT_RECEIVE: 2818 index = ctx - ohci->ir_context_list; 2819 ohci->ir_context_mask |= 1 << index; 2820 ohci->ir_context_channels |= 1ULL << base->channel; 2821 break; 2822 2823 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2824 index = ctx - ohci->ir_context_list; 2825 ohci->ir_context_mask |= 1 << index; 2826 ohci->ir_context_channels |= ohci->mc_channels; 2827 ohci->mc_channels = 0; 2828 ohci->mc_allocated = false; 2829 break; 2830 } 2831 2832 spin_unlock_irqrestore(&ohci->lock, flags); 2833 } 2834 2835 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels) 2836 { 2837 struct fw_ohci *ohci = fw_ohci(base->card); 2838 unsigned long flags; 2839 int ret; 2840 2841 switch (base->type) { 2842 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2843 2844 spin_lock_irqsave(&ohci->lock, flags); 2845 2846 /* Don't allow multichannel to grab other contexts' channels. */ 2847 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) { 2848 *channels = ohci->ir_context_channels; 2849 ret = -EBUSY; 2850 } else { 2851 set_multichannel_mask(ohci, *channels); 2852 ret = 0; 2853 } 2854 2855 spin_unlock_irqrestore(&ohci->lock, flags); 2856 2857 break; 2858 default: 2859 ret = -EINVAL; 2860 } 2861 2862 return ret; 2863 } 2864 2865 #ifdef CONFIG_PM 2866 static void ohci_resume_iso_dma(struct fw_ohci *ohci) 2867 { 2868 int i; 2869 struct iso_context *ctx; 2870 2871 for (i = 0 ; i < ohci->n_ir ; i++) { 2872 ctx = &ohci->ir_context_list[i]; 2873 if (ctx->context.running) 2874 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 2875 } 2876 2877 for (i = 0 ; i < ohci->n_it ; i++) { 2878 ctx = &ohci->it_context_list[i]; 2879 if (ctx->context.running) 2880 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 2881 } 2882 } 2883 #endif 2884 2885 static int queue_iso_transmit(struct iso_context *ctx, 2886 struct fw_iso_packet *packet, 2887 struct fw_iso_buffer *buffer, 2888 unsigned long payload) 2889 { 2890 struct descriptor *d, *last, *pd; 2891 struct fw_iso_packet *p; 2892 __le32 *header; 2893 dma_addr_t d_bus, page_bus; 2894 u32 z, header_z, payload_z, irq; 2895 u32 payload_index, payload_end_index, next_page_index; 2896 int page, end_page, i, length, offset; 2897 2898 p = packet; 2899 payload_index = payload; 2900 2901 if (p->skip) 2902 z = 1; 2903 else 2904 z = 2; 2905 if (p->header_length > 0) 2906 z++; 2907 2908 /* Determine the first page the payload isn't contained in. */ 2909 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; 2910 if (p->payload_length > 0) 2911 payload_z = end_page - (payload_index >> PAGE_SHIFT); 2912 else 2913 payload_z = 0; 2914 2915 z += payload_z; 2916 2917 /* Get header size in number of descriptors. */ 2918 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d)); 2919 2920 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); 2921 if (d == NULL) 2922 return -ENOMEM; 2923 2924 if (!p->skip) { 2925 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 2926 d[0].req_count = cpu_to_le16(8); 2927 /* 2928 * Link the skip address to this descriptor itself. This causes 2929 * a context to skip a cycle whenever lost cycles or FIFO 2930 * overruns occur, without dropping the data. The application 2931 * should then decide whether this is an error condition or not. 2932 * FIXME: Make the context's cycle-lost behaviour configurable? 2933 */ 2934 d[0].branch_address = cpu_to_le32(d_bus | z); 2935 2936 header = (__le32 *) &d[1]; 2937 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) | 2938 IT_HEADER_TAG(p->tag) | 2939 IT_HEADER_TCODE(TCODE_STREAM_DATA) | 2940 IT_HEADER_CHANNEL(ctx->base.channel) | 2941 IT_HEADER_SPEED(ctx->base.speed)); 2942 header[1] = 2943 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length + 2944 p->payload_length)); 2945 } 2946 2947 if (p->header_length > 0) { 2948 d[2].req_count = cpu_to_le16(p->header_length); 2949 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d)); 2950 memcpy(&d[z], p->header, p->header_length); 2951 } 2952 2953 pd = d + z - payload_z; 2954 payload_end_index = payload_index + p->payload_length; 2955 for (i = 0; i < payload_z; i++) { 2956 page = payload_index >> PAGE_SHIFT; 2957 offset = payload_index & ~PAGE_MASK; 2958 next_page_index = (page + 1) << PAGE_SHIFT; 2959 length = 2960 min(next_page_index, payload_end_index) - payload_index; 2961 pd[i].req_count = cpu_to_le16(length); 2962 2963 page_bus = page_private(buffer->pages[page]); 2964 pd[i].data_address = cpu_to_le32(page_bus + offset); 2965 2966 payload_index += length; 2967 } 2968 2969 if (p->interrupt) 2970 irq = DESCRIPTOR_IRQ_ALWAYS; 2971 else 2972 irq = DESCRIPTOR_NO_IRQ; 2973 2974 last = z == 2 ? d : d + z - 1; 2975 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 2976 DESCRIPTOR_STATUS | 2977 DESCRIPTOR_BRANCH_ALWAYS | 2978 irq); 2979 2980 context_append(&ctx->context, d, z, header_z); 2981 2982 return 0; 2983 } 2984 2985 static int queue_iso_packet_per_buffer(struct iso_context *ctx, 2986 struct fw_iso_packet *packet, 2987 struct fw_iso_buffer *buffer, 2988 unsigned long payload) 2989 { 2990 struct descriptor *d, *pd; 2991 dma_addr_t d_bus, page_bus; 2992 u32 z, header_z, rest; 2993 int i, j, length; 2994 int page, offset, packet_count, header_size, payload_per_buffer; 2995 2996 /* 2997 * The OHCI controller puts the isochronous header and trailer in the 2998 * buffer, so we need at least 8 bytes. 2999 */ 3000 packet_count = packet->header_length / ctx->base.header_size; 3001 header_size = max(ctx->base.header_size, (size_t)8); 3002 3003 /* Get header size in number of descriptors. */ 3004 header_z = DIV_ROUND_UP(header_size, sizeof(*d)); 3005 page = payload >> PAGE_SHIFT; 3006 offset = payload & ~PAGE_MASK; 3007 payload_per_buffer = packet->payload_length / packet_count; 3008 3009 for (i = 0; i < packet_count; i++) { 3010 /* d points to the header descriptor */ 3011 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1; 3012 d = context_get_descriptors(&ctx->context, 3013 z + header_z, &d_bus); 3014 if (d == NULL) 3015 return -ENOMEM; 3016 3017 d->control = cpu_to_le16(DESCRIPTOR_STATUS | 3018 DESCRIPTOR_INPUT_MORE); 3019 if (packet->skip && i == 0) 3020 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3021 d->req_count = cpu_to_le16(header_size); 3022 d->res_count = d->req_count; 3023 d->transfer_status = 0; 3024 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d))); 3025 3026 rest = payload_per_buffer; 3027 pd = d; 3028 for (j = 1; j < z; j++) { 3029 pd++; 3030 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3031 DESCRIPTOR_INPUT_MORE); 3032 3033 if (offset + rest < PAGE_SIZE) 3034 length = rest; 3035 else 3036 length = PAGE_SIZE - offset; 3037 pd->req_count = cpu_to_le16(length); 3038 pd->res_count = pd->req_count; 3039 pd->transfer_status = 0; 3040 3041 page_bus = page_private(buffer->pages[page]); 3042 pd->data_address = cpu_to_le32(page_bus + offset); 3043 3044 offset = (offset + length) & ~PAGE_MASK; 3045 rest -= length; 3046 if (offset == 0) 3047 page++; 3048 } 3049 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3050 DESCRIPTOR_INPUT_LAST | 3051 DESCRIPTOR_BRANCH_ALWAYS); 3052 if (packet->interrupt && i == packet_count - 1) 3053 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3054 3055 context_append(&ctx->context, d, z, header_z); 3056 } 3057 3058 return 0; 3059 } 3060 3061 static int queue_iso_buffer_fill(struct iso_context *ctx, 3062 struct fw_iso_packet *packet, 3063 struct fw_iso_buffer *buffer, 3064 unsigned long payload) 3065 { 3066 struct descriptor *d; 3067 dma_addr_t d_bus, page_bus; 3068 int page, offset, rest, z, i, length; 3069 3070 page = payload >> PAGE_SHIFT; 3071 offset = payload & ~PAGE_MASK; 3072 rest = packet->payload_length; 3073 3074 /* We need one descriptor for each page in the buffer. */ 3075 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE); 3076 3077 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count)) 3078 return -EFAULT; 3079 3080 for (i = 0; i < z; i++) { 3081 d = context_get_descriptors(&ctx->context, 1, &d_bus); 3082 if (d == NULL) 3083 return -ENOMEM; 3084 3085 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 3086 DESCRIPTOR_BRANCH_ALWAYS); 3087 if (packet->skip && i == 0) 3088 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3089 if (packet->interrupt && i == z - 1) 3090 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3091 3092 if (offset + rest < PAGE_SIZE) 3093 length = rest; 3094 else 3095 length = PAGE_SIZE - offset; 3096 d->req_count = cpu_to_le16(length); 3097 d->res_count = d->req_count; 3098 d->transfer_status = 0; 3099 3100 page_bus = page_private(buffer->pages[page]); 3101 d->data_address = cpu_to_le32(page_bus + offset); 3102 3103 rest -= length; 3104 offset = 0; 3105 page++; 3106 3107 context_append(&ctx->context, d, 1, 0); 3108 } 3109 3110 return 0; 3111 } 3112 3113 static int ohci_queue_iso(struct fw_iso_context *base, 3114 struct fw_iso_packet *packet, 3115 struct fw_iso_buffer *buffer, 3116 unsigned long payload) 3117 { 3118 struct iso_context *ctx = container_of(base, struct iso_context, base); 3119 unsigned long flags; 3120 int ret = -ENOSYS; 3121 3122 spin_lock_irqsave(&ctx->context.ohci->lock, flags); 3123 switch (base->type) { 3124 case FW_ISO_CONTEXT_TRANSMIT: 3125 ret = queue_iso_transmit(ctx, packet, buffer, payload); 3126 break; 3127 case FW_ISO_CONTEXT_RECEIVE: 3128 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload); 3129 break; 3130 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3131 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload); 3132 break; 3133 } 3134 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags); 3135 3136 return ret; 3137 } 3138 3139 static void ohci_flush_queue_iso(struct fw_iso_context *base) 3140 { 3141 struct context *ctx = 3142 &container_of(base, struct iso_context, base)->context; 3143 3144 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 3145 } 3146 3147 static const struct fw_card_driver ohci_driver = { 3148 .enable = ohci_enable, 3149 .read_phy_reg = ohci_read_phy_reg, 3150 .update_phy_reg = ohci_update_phy_reg, 3151 .set_config_rom = ohci_set_config_rom, 3152 .send_request = ohci_send_request, 3153 .send_response = ohci_send_response, 3154 .cancel_packet = ohci_cancel_packet, 3155 .enable_phys_dma = ohci_enable_phys_dma, 3156 .read_csr = ohci_read_csr, 3157 .write_csr = ohci_write_csr, 3158 3159 .allocate_iso_context = ohci_allocate_iso_context, 3160 .free_iso_context = ohci_free_iso_context, 3161 .set_iso_channels = ohci_set_iso_channels, 3162 .queue_iso = ohci_queue_iso, 3163 .flush_queue_iso = ohci_flush_queue_iso, 3164 .start_iso = ohci_start_iso, 3165 .stop_iso = ohci_stop_iso, 3166 }; 3167 3168 #ifdef CONFIG_PPC_PMAC 3169 static void pmac_ohci_on(struct pci_dev *dev) 3170 { 3171 if (machine_is(powermac)) { 3172 struct device_node *ofn = pci_device_to_OF_node(dev); 3173 3174 if (ofn) { 3175 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1); 3176 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1); 3177 } 3178 } 3179 } 3180 3181 static void pmac_ohci_off(struct pci_dev *dev) 3182 { 3183 if (machine_is(powermac)) { 3184 struct device_node *ofn = pci_device_to_OF_node(dev); 3185 3186 if (ofn) { 3187 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0); 3188 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0); 3189 } 3190 } 3191 } 3192 #else 3193 static inline void pmac_ohci_on(struct pci_dev *dev) {} 3194 static inline void pmac_ohci_off(struct pci_dev *dev) {} 3195 #endif /* CONFIG_PPC_PMAC */ 3196 3197 static int __devinit pci_probe(struct pci_dev *dev, 3198 const struct pci_device_id *ent) 3199 { 3200 struct fw_ohci *ohci; 3201 u32 bus_options, max_receive, link_speed, version; 3202 u64 guid; 3203 int i, err; 3204 size_t size; 3205 3206 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) { 3207 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n"); 3208 return -ENOSYS; 3209 } 3210 3211 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL); 3212 if (ohci == NULL) { 3213 err = -ENOMEM; 3214 goto fail; 3215 } 3216 3217 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); 3218 3219 pmac_ohci_on(dev); 3220 3221 err = pci_enable_device(dev); 3222 if (err) { 3223 fw_error("Failed to enable OHCI hardware\n"); 3224 goto fail_free; 3225 } 3226 3227 pci_set_master(dev); 3228 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); 3229 pci_set_drvdata(dev, ohci); 3230 3231 spin_lock_init(&ohci->lock); 3232 mutex_init(&ohci->phy_reg_mutex); 3233 3234 tasklet_init(&ohci->bus_reset_tasklet, 3235 bus_reset_tasklet, (unsigned long)ohci); 3236 3237 err = pci_request_region(dev, 0, ohci_driver_name); 3238 if (err) { 3239 fw_error("MMIO resource unavailable\n"); 3240 goto fail_disable; 3241 } 3242 3243 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE); 3244 if (ohci->registers == NULL) { 3245 fw_error("Failed to remap registers\n"); 3246 err = -ENXIO; 3247 goto fail_iomem; 3248 } 3249 3250 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++) 3251 if ((ohci_quirks[i].vendor == dev->vendor) && 3252 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID || 3253 ohci_quirks[i].device == dev->device) && 3254 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID || 3255 ohci_quirks[i].revision >= dev->revision)) { 3256 ohci->quirks = ohci_quirks[i].flags; 3257 break; 3258 } 3259 if (param_quirks) 3260 ohci->quirks = param_quirks; 3261 3262 /* 3263 * Because dma_alloc_coherent() allocates at least one page, 3264 * we save space by using a common buffer for the AR request/ 3265 * response descriptors and the self IDs buffer. 3266 */ 3267 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4); 3268 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2); 3269 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device, 3270 PAGE_SIZE, 3271 &ohci->misc_buffer_bus, 3272 GFP_KERNEL); 3273 if (!ohci->misc_buffer) { 3274 err = -ENOMEM; 3275 goto fail_iounmap; 3276 } 3277 3278 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0, 3279 OHCI1394_AsReqRcvContextControlSet); 3280 if (err < 0) 3281 goto fail_misc_buf; 3282 3283 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4, 3284 OHCI1394_AsRspRcvContextControlSet); 3285 if (err < 0) 3286 goto fail_arreq_ctx; 3287 3288 err = context_init(&ohci->at_request_ctx, ohci, 3289 OHCI1394_AsReqTrContextControlSet, handle_at_packet); 3290 if (err < 0) 3291 goto fail_arrsp_ctx; 3292 3293 err = context_init(&ohci->at_response_ctx, ohci, 3294 OHCI1394_AsRspTrContextControlSet, handle_at_packet); 3295 if (err < 0) 3296 goto fail_atreq_ctx; 3297 3298 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); 3299 ohci->ir_context_channels = ~0ULL; 3300 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); 3301 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); 3302 ohci->ir_context_mask = ohci->ir_context_support; 3303 ohci->n_ir = hweight32(ohci->ir_context_mask); 3304 size = sizeof(struct iso_context) * ohci->n_ir; 3305 ohci->ir_context_list = kzalloc(size, GFP_KERNEL); 3306 3307 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); 3308 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); 3309 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); 3310 ohci->it_context_mask = ohci->it_context_support; 3311 ohci->n_it = hweight32(ohci->it_context_mask); 3312 size = sizeof(struct iso_context) * ohci->n_it; 3313 ohci->it_context_list = kzalloc(size, GFP_KERNEL); 3314 3315 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) { 3316 err = -ENOMEM; 3317 goto fail_contexts; 3318 } 3319 3320 ohci->self_id_cpu = ohci->misc_buffer + PAGE_SIZE/2; 3321 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2; 3322 3323 bus_options = reg_read(ohci, OHCI1394_BusOptions); 3324 max_receive = (bus_options >> 12) & 0xf; 3325 link_speed = bus_options & 0x7; 3326 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | 3327 reg_read(ohci, OHCI1394_GUIDLo); 3328 3329 err = fw_card_add(&ohci->card, max_receive, link_speed, guid); 3330 if (err) 3331 goto fail_contexts; 3332 3333 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 3334 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, " 3335 "%d IR + %d IT contexts, quirks 0x%x\n", 3336 dev_name(&dev->dev), version >> 16, version & 0xff, 3337 ohci->n_ir, ohci->n_it, ohci->quirks); 3338 3339 return 0; 3340 3341 fail_contexts: 3342 kfree(ohci->ir_context_list); 3343 kfree(ohci->it_context_list); 3344 context_release(&ohci->at_response_ctx); 3345 fail_atreq_ctx: 3346 context_release(&ohci->at_request_ctx); 3347 fail_arrsp_ctx: 3348 ar_context_release(&ohci->ar_response_ctx); 3349 fail_arreq_ctx: 3350 ar_context_release(&ohci->ar_request_ctx); 3351 fail_misc_buf: 3352 dma_free_coherent(ohci->card.device, PAGE_SIZE, 3353 ohci->misc_buffer, ohci->misc_buffer_bus); 3354 fail_iounmap: 3355 pci_iounmap(dev, ohci->registers); 3356 fail_iomem: 3357 pci_release_region(dev, 0); 3358 fail_disable: 3359 pci_disable_device(dev); 3360 fail_free: 3361 kfree(ohci); 3362 pmac_ohci_off(dev); 3363 fail: 3364 if (err == -ENOMEM) 3365 fw_error("Out of memory\n"); 3366 3367 return err; 3368 } 3369 3370 static void pci_remove(struct pci_dev *dev) 3371 { 3372 struct fw_ohci *ohci; 3373 3374 ohci = pci_get_drvdata(dev); 3375 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 3376 flush_writes(ohci); 3377 fw_core_remove_card(&ohci->card); 3378 3379 /* 3380 * FIXME: Fail all pending packets here, now that the upper 3381 * layers can't queue any more. 3382 */ 3383 3384 software_reset(ohci); 3385 free_irq(dev->irq, ohci); 3386 3387 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom) 3388 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 3389 ohci->next_config_rom, ohci->next_config_rom_bus); 3390 if (ohci->config_rom) 3391 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 3392 ohci->config_rom, ohci->config_rom_bus); 3393 ar_context_release(&ohci->ar_request_ctx); 3394 ar_context_release(&ohci->ar_response_ctx); 3395 dma_free_coherent(ohci->card.device, PAGE_SIZE, 3396 ohci->misc_buffer, ohci->misc_buffer_bus); 3397 context_release(&ohci->at_request_ctx); 3398 context_release(&ohci->at_response_ctx); 3399 kfree(ohci->it_context_list); 3400 kfree(ohci->ir_context_list); 3401 pci_disable_msi(dev); 3402 pci_iounmap(dev, ohci->registers); 3403 pci_release_region(dev, 0); 3404 pci_disable_device(dev); 3405 kfree(ohci); 3406 pmac_ohci_off(dev); 3407 3408 fw_notify("Removed fw-ohci device.\n"); 3409 } 3410 3411 #ifdef CONFIG_PM 3412 static int pci_suspend(struct pci_dev *dev, pm_message_t state) 3413 { 3414 struct fw_ohci *ohci = pci_get_drvdata(dev); 3415 int err; 3416 3417 software_reset(ohci); 3418 free_irq(dev->irq, ohci); 3419 pci_disable_msi(dev); 3420 err = pci_save_state(dev); 3421 if (err) { 3422 fw_error("pci_save_state failed\n"); 3423 return err; 3424 } 3425 err = pci_set_power_state(dev, pci_choose_state(dev, state)); 3426 if (err) 3427 fw_error("pci_set_power_state failed with %d\n", err); 3428 pmac_ohci_off(dev); 3429 3430 return 0; 3431 } 3432 3433 static int pci_resume(struct pci_dev *dev) 3434 { 3435 struct fw_ohci *ohci = pci_get_drvdata(dev); 3436 int err; 3437 3438 pmac_ohci_on(dev); 3439 pci_set_power_state(dev, PCI_D0); 3440 pci_restore_state(dev); 3441 err = pci_enable_device(dev); 3442 if (err) { 3443 fw_error("pci_enable_device failed\n"); 3444 return err; 3445 } 3446 3447 /* Some systems don't setup GUID register on resume from ram */ 3448 if (!reg_read(ohci, OHCI1394_GUIDLo) && 3449 !reg_read(ohci, OHCI1394_GUIDHi)) { 3450 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid); 3451 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32)); 3452 } 3453 3454 err = ohci_enable(&ohci->card, NULL, 0); 3455 if (err) 3456 return err; 3457 3458 ohci_resume_iso_dma(ohci); 3459 3460 return 0; 3461 } 3462 #endif 3463 3464 static const struct pci_device_id pci_table[] = { 3465 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, 3466 { } 3467 }; 3468 3469 MODULE_DEVICE_TABLE(pci, pci_table); 3470 3471 static struct pci_driver fw_ohci_pci_driver = { 3472 .name = ohci_driver_name, 3473 .id_table = pci_table, 3474 .probe = pci_probe, 3475 .remove = pci_remove, 3476 #ifdef CONFIG_PM 3477 .resume = pci_resume, 3478 .suspend = pci_suspend, 3479 #endif 3480 }; 3481 3482 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); 3483 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); 3484 MODULE_LICENSE("GPL"); 3485 3486 /* Provide a module alias so root-on-sbp2 initrds don't break. */ 3487 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE 3488 MODULE_ALIAS("ohci1394"); 3489 #endif 3490 3491 static int __init fw_ohci_init(void) 3492 { 3493 return pci_register_driver(&fw_ohci_pci_driver); 3494 } 3495 3496 static void __exit fw_ohci_cleanup(void) 3497 { 3498 pci_unregister_driver(&fw_ohci_pci_driver); 3499 } 3500 3501 module_init(fw_ohci_init); 3502 module_exit(fw_ohci_cleanup); 3503