1 /* 2 * Driver for OHCI 1394 controllers 3 * 4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software Foundation, 18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 */ 20 21 #include <linux/bitops.h> 22 #include <linux/bug.h> 23 #include <linux/compiler.h> 24 #include <linux/delay.h> 25 #include <linux/device.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/firewire.h> 28 #include <linux/firewire-constants.h> 29 #include <linux/init.h> 30 #include <linux/interrupt.h> 31 #include <linux/io.h> 32 #include <linux/kernel.h> 33 #include <linux/list.h> 34 #include <linux/mm.h> 35 #include <linux/module.h> 36 #include <linux/moduleparam.h> 37 #include <linux/mutex.h> 38 #include <linux/pci.h> 39 #include <linux/pci_ids.h> 40 #include <linux/slab.h> 41 #include <linux/spinlock.h> 42 #include <linux/string.h> 43 #include <linux/time.h> 44 #include <linux/vmalloc.h> 45 46 #include <asm/byteorder.h> 47 #include <asm/page.h> 48 #include <asm/system.h> 49 50 #ifdef CONFIG_PPC_PMAC 51 #include <asm/pmac_feature.h> 52 #endif 53 54 #include "core.h" 55 #include "ohci.h" 56 57 #define DESCRIPTOR_OUTPUT_MORE 0 58 #define DESCRIPTOR_OUTPUT_LAST (1 << 12) 59 #define DESCRIPTOR_INPUT_MORE (2 << 12) 60 #define DESCRIPTOR_INPUT_LAST (3 << 12) 61 #define DESCRIPTOR_STATUS (1 << 11) 62 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8) 63 #define DESCRIPTOR_PING (1 << 7) 64 #define DESCRIPTOR_YY (1 << 6) 65 #define DESCRIPTOR_NO_IRQ (0 << 4) 66 #define DESCRIPTOR_IRQ_ERROR (1 << 4) 67 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4) 68 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2) 69 #define DESCRIPTOR_WAIT (3 << 0) 70 71 struct descriptor { 72 __le16 req_count; 73 __le16 control; 74 __le32 data_address; 75 __le32 branch_address; 76 __le16 res_count; 77 __le16 transfer_status; 78 } __attribute__((aligned(16))); 79 80 #define CONTROL_SET(regs) (regs) 81 #define CONTROL_CLEAR(regs) ((regs) + 4) 82 #define COMMAND_PTR(regs) ((regs) + 12) 83 #define CONTEXT_MATCH(regs) ((regs) + 16) 84 85 #define AR_BUFFER_SIZE (32*1024) 86 #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE) 87 /* we need at least two pages for proper list management */ 88 #define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2) 89 90 #define MAX_ASYNC_PAYLOAD 4096 91 #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4) 92 #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE) 93 94 struct ar_context { 95 struct fw_ohci *ohci; 96 struct page *pages[AR_BUFFERS]; 97 void *buffer; 98 struct descriptor *descriptors; 99 dma_addr_t descriptors_bus; 100 void *pointer; 101 unsigned int last_buffer_index; 102 u32 regs; 103 struct tasklet_struct tasklet; 104 }; 105 106 struct context; 107 108 typedef int (*descriptor_callback_t)(struct context *ctx, 109 struct descriptor *d, 110 struct descriptor *last); 111 112 /* 113 * A buffer that contains a block of DMA-able coherent memory used for 114 * storing a portion of a DMA descriptor program. 115 */ 116 struct descriptor_buffer { 117 struct list_head list; 118 dma_addr_t buffer_bus; 119 size_t buffer_size; 120 size_t used; 121 struct descriptor buffer[0]; 122 }; 123 124 struct context { 125 struct fw_ohci *ohci; 126 u32 regs; 127 int total_allocation; 128 bool running; 129 bool flushing; 130 131 /* 132 * List of page-sized buffers for storing DMA descriptors. 133 * Head of list contains buffers in use and tail of list contains 134 * free buffers. 135 */ 136 struct list_head buffer_list; 137 138 /* 139 * Pointer to a buffer inside buffer_list that contains the tail 140 * end of the current DMA program. 141 */ 142 struct descriptor_buffer *buffer_tail; 143 144 /* 145 * The descriptor containing the branch address of the first 146 * descriptor that has not yet been filled by the device. 147 */ 148 struct descriptor *last; 149 150 /* 151 * The last descriptor in the DMA program. It contains the branch 152 * address that must be updated upon appending a new descriptor. 153 */ 154 struct descriptor *prev; 155 156 descriptor_callback_t callback; 157 158 struct tasklet_struct tasklet; 159 }; 160 161 #define IT_HEADER_SY(v) ((v) << 0) 162 #define IT_HEADER_TCODE(v) ((v) << 4) 163 #define IT_HEADER_CHANNEL(v) ((v) << 8) 164 #define IT_HEADER_TAG(v) ((v) << 14) 165 #define IT_HEADER_SPEED(v) ((v) << 16) 166 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16) 167 168 struct iso_context { 169 struct fw_iso_context base; 170 struct context context; 171 int excess_bytes; 172 void *header; 173 size_t header_length; 174 175 u8 sync; 176 u8 tags; 177 }; 178 179 #define CONFIG_ROM_SIZE 1024 180 181 struct fw_ohci { 182 struct fw_card card; 183 184 __iomem char *registers; 185 int node_id; 186 int generation; 187 int request_generation; /* for timestamping incoming requests */ 188 unsigned quirks; 189 unsigned int pri_req_max; 190 u32 bus_time; 191 bool is_root; 192 bool csr_state_setclear_abdicate; 193 int n_ir; 194 int n_it; 195 /* 196 * Spinlock for accessing fw_ohci data. Never call out of 197 * this driver with this lock held. 198 */ 199 spinlock_t lock; 200 201 struct mutex phy_reg_mutex; 202 203 void *misc_buffer; 204 dma_addr_t misc_buffer_bus; 205 206 struct ar_context ar_request_ctx; 207 struct ar_context ar_response_ctx; 208 struct context at_request_ctx; 209 struct context at_response_ctx; 210 211 u32 it_context_mask; /* unoccupied IT contexts */ 212 struct iso_context *it_context_list; 213 u64 ir_context_channels; /* unoccupied channels */ 214 u32 ir_context_mask; /* unoccupied IR contexts */ 215 struct iso_context *ir_context_list; 216 u64 mc_channels; /* channels in use by the multichannel IR context */ 217 bool mc_allocated; 218 219 __be32 *config_rom; 220 dma_addr_t config_rom_bus; 221 __be32 *next_config_rom; 222 dma_addr_t next_config_rom_bus; 223 __be32 next_header; 224 225 __le32 *self_id_cpu; 226 dma_addr_t self_id_bus; 227 struct tasklet_struct bus_reset_tasklet; 228 229 u32 self_id_buffer[512]; 230 }; 231 232 static inline struct fw_ohci *fw_ohci(struct fw_card *card) 233 { 234 return container_of(card, struct fw_ohci, card); 235 } 236 237 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 238 #define IR_CONTEXT_BUFFER_FILL 0x80000000 239 #define IR_CONTEXT_ISOCH_HEADER 0x40000000 240 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 241 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 242 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 243 244 #define CONTEXT_RUN 0x8000 245 #define CONTEXT_WAKE 0x1000 246 #define CONTEXT_DEAD 0x0800 247 #define CONTEXT_ACTIVE 0x0400 248 249 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf 250 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 251 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 252 253 #define OHCI1394_REGISTER_SIZE 0x800 254 #define OHCI_LOOP_COUNT 500 255 #define OHCI1394_PCI_HCI_Control 0x40 256 #define SELF_ID_BUF_SIZE 0x800 257 #define OHCI_TCODE_PHY_PACKET 0x0e 258 #define OHCI_VERSION_1_1 0x010010 259 260 static char ohci_driver_name[] = KBUILD_MODNAME; 261 262 #define PCI_DEVICE_ID_AGERE_FW643 0x5901 263 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380 264 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009 265 266 #define QUIRK_CYCLE_TIMER 1 267 #define QUIRK_RESET_PACKET 2 268 #define QUIRK_BE_HEADERS 4 269 #define QUIRK_NO_1394A 8 270 #define QUIRK_NO_MSI 16 271 272 /* In case of multiple matches in ohci_quirks[], only the first one is used. */ 273 static const struct { 274 unsigned short vendor, device, revision, flags; 275 } ohci_quirks[] = { 276 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID, 277 QUIRK_CYCLE_TIMER}, 278 279 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID, 280 QUIRK_BE_HEADERS}, 281 282 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6, 283 QUIRK_NO_MSI}, 284 285 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID, 286 QUIRK_NO_MSI}, 287 288 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID, 289 QUIRK_CYCLE_TIMER}, 290 291 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID, 292 QUIRK_CYCLE_TIMER}, 293 294 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID, 295 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A}, 296 297 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID, 298 QUIRK_RESET_PACKET}, 299 300 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID, 301 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, 302 }; 303 304 /* This overrides anything that was found in ohci_quirks[]. */ 305 static int param_quirks; 306 module_param_named(quirks, param_quirks, int, 0644); 307 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0" 308 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER) 309 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET) 310 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS) 311 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A) 312 ", disable MSI = " __stringify(QUIRK_NO_MSI) 313 ")"); 314 315 #define OHCI_PARAM_DEBUG_AT_AR 1 316 #define OHCI_PARAM_DEBUG_SELFIDS 2 317 #define OHCI_PARAM_DEBUG_IRQS 4 318 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */ 319 320 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG 321 322 static int param_debug; 323 module_param_named(debug, param_debug, int, 0644); 324 MODULE_PARM_DESC(debug, "Verbose logging (default = 0" 325 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR) 326 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS) 327 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS) 328 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS) 329 ", or a combination, or all = -1)"); 330 331 static void log_irqs(u32 evt) 332 { 333 if (likely(!(param_debug & 334 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS)))) 335 return; 336 337 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) && 338 !(evt & OHCI1394_busReset)) 339 return; 340 341 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt, 342 evt & OHCI1394_selfIDComplete ? " selfID" : "", 343 evt & OHCI1394_RQPkt ? " AR_req" : "", 344 evt & OHCI1394_RSPkt ? " AR_resp" : "", 345 evt & OHCI1394_reqTxComplete ? " AT_req" : "", 346 evt & OHCI1394_respTxComplete ? " AT_resp" : "", 347 evt & OHCI1394_isochRx ? " IR" : "", 348 evt & OHCI1394_isochTx ? " IT" : "", 349 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", 350 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", 351 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "", 352 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "", 353 evt & OHCI1394_regAccessFail ? " regAccessFail" : "", 354 evt & OHCI1394_busReset ? " busReset" : "", 355 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | 356 OHCI1394_RSPkt | OHCI1394_reqTxComplete | 357 OHCI1394_respTxComplete | OHCI1394_isochRx | 358 OHCI1394_isochTx | OHCI1394_postedWriteErr | 359 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds | 360 OHCI1394_cycleInconsistent | 361 OHCI1394_regAccessFail | OHCI1394_busReset) 362 ? " ?" : ""); 363 } 364 365 static const char *speed[] = { 366 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta", 367 }; 368 static const char *power[] = { 369 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W", 370 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W", 371 }; 372 static const char port[] = { '.', '-', 'p', 'c', }; 373 374 static char _p(u32 *s, int shift) 375 { 376 return port[*s >> shift & 3]; 377 } 378 379 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s) 380 { 381 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) 382 return; 383 384 fw_notify("%d selfIDs, generation %d, local node ID %04x\n", 385 self_id_count, generation, node_id); 386 387 for (; self_id_count--; ++s) 388 if ((*s & 1 << 23) == 0) 389 fw_notify("selfID 0: %08x, phy %d [%c%c%c] " 390 "%s gc=%d %s %s%s%s\n", 391 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2), 392 speed[*s >> 14 & 3], *s >> 16 & 63, 393 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", 394 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); 395 else 396 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n", 397 *s, *s >> 24 & 63, 398 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10), 399 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2)); 400 } 401 402 static const char *evts[] = { 403 [0x00] = "evt_no_status", [0x01] = "-reserved-", 404 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack", 405 [0x04] = "evt_underrun", [0x05] = "evt_overrun", 406 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read", 407 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset", 408 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err", 409 [0x0c] = "-reserved-", [0x0d] = "-reserved-", 410 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed", 411 [0x10] = "-reserved-", [0x11] = "ack_complete", 412 [0x12] = "ack_pending ", [0x13] = "-reserved-", 413 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A", 414 [0x16] = "ack_busy_B", [0x17] = "-reserved-", 415 [0x18] = "-reserved-", [0x19] = "-reserved-", 416 [0x1a] = "-reserved-", [0x1b] = "ack_tardy", 417 [0x1c] = "-reserved-", [0x1d] = "ack_data_error", 418 [0x1e] = "ack_type_error", [0x1f] = "-reserved-", 419 [0x20] = "pending/cancelled", 420 }; 421 static const char *tcodes[] = { 422 [0x0] = "QW req", [0x1] = "BW req", 423 [0x2] = "W resp", [0x3] = "-reserved-", 424 [0x4] = "QR req", [0x5] = "BR req", 425 [0x6] = "QR resp", [0x7] = "BR resp", 426 [0x8] = "cycle start", [0x9] = "Lk req", 427 [0xa] = "async stream packet", [0xb] = "Lk resp", 428 [0xc] = "-reserved-", [0xd] = "-reserved-", 429 [0xe] = "link internal", [0xf] = "-reserved-", 430 }; 431 432 static void log_ar_at_event(char dir, int speed, u32 *header, int evt) 433 { 434 int tcode = header[0] >> 4 & 0xf; 435 char specific[12]; 436 437 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR))) 438 return; 439 440 if (unlikely(evt >= ARRAY_SIZE(evts))) 441 evt = 0x1f; 442 443 if (evt == OHCI1394_evt_bus_reset) { 444 fw_notify("A%c evt_bus_reset, generation %d\n", 445 dir, (header[2] >> 16) & 0xff); 446 return; 447 } 448 449 switch (tcode) { 450 case 0x0: case 0x6: case 0x8: 451 snprintf(specific, sizeof(specific), " = %08x", 452 be32_to_cpu((__force __be32)header[3])); 453 break; 454 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb: 455 snprintf(specific, sizeof(specific), " %x,%x", 456 header[3] >> 16, header[3] & 0xffff); 457 break; 458 default: 459 specific[0] = '\0'; 460 } 461 462 switch (tcode) { 463 case 0xa: 464 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]); 465 break; 466 case 0xe: 467 fw_notify("A%c %s, PHY %08x %08x\n", 468 dir, evts[evt], header[1], header[2]); 469 break; 470 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9: 471 fw_notify("A%c spd %x tl %02x, " 472 "%04x -> %04x, %s, " 473 "%s, %04x%08x%s\n", 474 dir, speed, header[0] >> 10 & 0x3f, 475 header[1] >> 16, header[0] >> 16, evts[evt], 476 tcodes[tcode], header[1] & 0xffff, header[2], specific); 477 break; 478 default: 479 fw_notify("A%c spd %x tl %02x, " 480 "%04x -> %04x, %s, " 481 "%s%s\n", 482 dir, speed, header[0] >> 10 & 0x3f, 483 header[1] >> 16, header[0] >> 16, evts[evt], 484 tcodes[tcode], specific); 485 } 486 } 487 488 #else 489 490 #define param_debug 0 491 static inline void log_irqs(u32 evt) {} 492 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {} 493 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {} 494 495 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */ 496 497 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) 498 { 499 writel(data, ohci->registers + offset); 500 } 501 502 static inline u32 reg_read(const struct fw_ohci *ohci, int offset) 503 { 504 return readl(ohci->registers + offset); 505 } 506 507 static inline void flush_writes(const struct fw_ohci *ohci) 508 { 509 /* Do a dummy read to flush writes. */ 510 reg_read(ohci, OHCI1394_Version); 511 } 512 513 static int read_phy_reg(struct fw_ohci *ohci, int addr) 514 { 515 u32 val; 516 int i; 517 518 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); 519 for (i = 0; i < 3 + 100; i++) { 520 val = reg_read(ohci, OHCI1394_PhyControl); 521 if (val & OHCI1394_PhyControl_ReadDone) 522 return OHCI1394_PhyControl_ReadData(val); 523 524 /* 525 * Try a few times without waiting. Sleeping is necessary 526 * only when the link/PHY interface is busy. 527 */ 528 if (i >= 3) 529 msleep(1); 530 } 531 fw_error("failed to read phy reg\n"); 532 533 return -EBUSY; 534 } 535 536 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val) 537 { 538 int i; 539 540 reg_write(ohci, OHCI1394_PhyControl, 541 OHCI1394_PhyControl_Write(addr, val)); 542 for (i = 0; i < 3 + 100; i++) { 543 val = reg_read(ohci, OHCI1394_PhyControl); 544 if (!(val & OHCI1394_PhyControl_WritePending)) 545 return 0; 546 547 if (i >= 3) 548 msleep(1); 549 } 550 fw_error("failed to write phy reg\n"); 551 552 return -EBUSY; 553 } 554 555 static int update_phy_reg(struct fw_ohci *ohci, int addr, 556 int clear_bits, int set_bits) 557 { 558 int ret = read_phy_reg(ohci, addr); 559 if (ret < 0) 560 return ret; 561 562 /* 563 * The interrupt status bits are cleared by writing a one bit. 564 * Avoid clearing them unless explicitly requested in set_bits. 565 */ 566 if (addr == 5) 567 clear_bits |= PHY_INT_STATUS_BITS; 568 569 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits); 570 } 571 572 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr) 573 { 574 int ret; 575 576 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5); 577 if (ret < 0) 578 return ret; 579 580 return read_phy_reg(ohci, addr); 581 } 582 583 static int ohci_read_phy_reg(struct fw_card *card, int addr) 584 { 585 struct fw_ohci *ohci = fw_ohci(card); 586 int ret; 587 588 mutex_lock(&ohci->phy_reg_mutex); 589 ret = read_phy_reg(ohci, addr); 590 mutex_unlock(&ohci->phy_reg_mutex); 591 592 return ret; 593 } 594 595 static int ohci_update_phy_reg(struct fw_card *card, int addr, 596 int clear_bits, int set_bits) 597 { 598 struct fw_ohci *ohci = fw_ohci(card); 599 int ret; 600 601 mutex_lock(&ohci->phy_reg_mutex); 602 ret = update_phy_reg(ohci, addr, clear_bits, set_bits); 603 mutex_unlock(&ohci->phy_reg_mutex); 604 605 return ret; 606 } 607 608 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i) 609 { 610 return page_private(ctx->pages[i]); 611 } 612 613 static void ar_context_link_page(struct ar_context *ctx, unsigned int index) 614 { 615 struct descriptor *d; 616 617 d = &ctx->descriptors[index]; 618 d->branch_address &= cpu_to_le32(~0xf); 619 d->res_count = cpu_to_le16(PAGE_SIZE); 620 d->transfer_status = 0; 621 622 wmb(); /* finish init of new descriptors before branch_address update */ 623 d = &ctx->descriptors[ctx->last_buffer_index]; 624 d->branch_address |= cpu_to_le32(1); 625 626 ctx->last_buffer_index = index; 627 628 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 629 flush_writes(ctx->ohci); 630 } 631 632 static void ar_context_release(struct ar_context *ctx) 633 { 634 unsigned int i; 635 636 if (ctx->buffer) 637 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES); 638 639 for (i = 0; i < AR_BUFFERS; i++) 640 if (ctx->pages[i]) { 641 dma_unmap_page(ctx->ohci->card.device, 642 ar_buffer_bus(ctx, i), 643 PAGE_SIZE, DMA_FROM_DEVICE); 644 __free_page(ctx->pages[i]); 645 } 646 } 647 648 static void ar_context_abort(struct ar_context *ctx, const char *error_msg) 649 { 650 if (reg_read(ctx->ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) { 651 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 652 flush_writes(ctx->ohci); 653 654 fw_error("AR error: %s; DMA stopped\n", error_msg); 655 } 656 /* FIXME: restart? */ 657 } 658 659 static inline unsigned int ar_next_buffer_index(unsigned int index) 660 { 661 return (index + 1) % AR_BUFFERS; 662 } 663 664 static inline unsigned int ar_prev_buffer_index(unsigned int index) 665 { 666 return (index - 1 + AR_BUFFERS) % AR_BUFFERS; 667 } 668 669 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx) 670 { 671 return ar_next_buffer_index(ctx->last_buffer_index); 672 } 673 674 /* 675 * We search for the buffer that contains the last AR packet DMA data written 676 * by the controller. 677 */ 678 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx, 679 unsigned int *buffer_offset) 680 { 681 unsigned int i, next_i, last = ctx->last_buffer_index; 682 __le16 res_count, next_res_count; 683 684 i = ar_first_buffer_index(ctx); 685 res_count = ACCESS_ONCE(ctx->descriptors[i].res_count); 686 687 /* A buffer that is not yet completely filled must be the last one. */ 688 while (i != last && res_count == 0) { 689 690 /* Peek at the next descriptor. */ 691 next_i = ar_next_buffer_index(i); 692 rmb(); /* read descriptors in order */ 693 next_res_count = ACCESS_ONCE( 694 ctx->descriptors[next_i].res_count); 695 /* 696 * If the next descriptor is still empty, we must stop at this 697 * descriptor. 698 */ 699 if (next_res_count == cpu_to_le16(PAGE_SIZE)) { 700 /* 701 * The exception is when the DMA data for one packet is 702 * split over three buffers; in this case, the middle 703 * buffer's descriptor might be never updated by the 704 * controller and look still empty, and we have to peek 705 * at the third one. 706 */ 707 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) { 708 next_i = ar_next_buffer_index(next_i); 709 rmb(); 710 next_res_count = ACCESS_ONCE( 711 ctx->descriptors[next_i].res_count); 712 if (next_res_count != cpu_to_le16(PAGE_SIZE)) 713 goto next_buffer_is_active; 714 } 715 716 break; 717 } 718 719 next_buffer_is_active: 720 i = next_i; 721 res_count = next_res_count; 722 } 723 724 rmb(); /* read res_count before the DMA data */ 725 726 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count); 727 if (*buffer_offset > PAGE_SIZE) { 728 *buffer_offset = 0; 729 ar_context_abort(ctx, "corrupted descriptor"); 730 } 731 732 return i; 733 } 734 735 static void ar_sync_buffers_for_cpu(struct ar_context *ctx, 736 unsigned int end_buffer_index, 737 unsigned int end_buffer_offset) 738 { 739 unsigned int i; 740 741 i = ar_first_buffer_index(ctx); 742 while (i != end_buffer_index) { 743 dma_sync_single_for_cpu(ctx->ohci->card.device, 744 ar_buffer_bus(ctx, i), 745 PAGE_SIZE, DMA_FROM_DEVICE); 746 i = ar_next_buffer_index(i); 747 } 748 if (end_buffer_offset > 0) 749 dma_sync_single_for_cpu(ctx->ohci->card.device, 750 ar_buffer_bus(ctx, i), 751 end_buffer_offset, DMA_FROM_DEVICE); 752 } 753 754 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) 755 #define cond_le32_to_cpu(v) \ 756 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v)) 757 #else 758 #define cond_le32_to_cpu(v) le32_to_cpu(v) 759 #endif 760 761 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) 762 { 763 struct fw_ohci *ohci = ctx->ohci; 764 struct fw_packet p; 765 u32 status, length, tcode; 766 int evt; 767 768 p.header[0] = cond_le32_to_cpu(buffer[0]); 769 p.header[1] = cond_le32_to_cpu(buffer[1]); 770 p.header[2] = cond_le32_to_cpu(buffer[2]); 771 772 tcode = (p.header[0] >> 4) & 0x0f; 773 switch (tcode) { 774 case TCODE_WRITE_QUADLET_REQUEST: 775 case TCODE_READ_QUADLET_RESPONSE: 776 p.header[3] = (__force __u32) buffer[3]; 777 p.header_length = 16; 778 p.payload_length = 0; 779 break; 780 781 case TCODE_READ_BLOCK_REQUEST : 782 p.header[3] = cond_le32_to_cpu(buffer[3]); 783 p.header_length = 16; 784 p.payload_length = 0; 785 break; 786 787 case TCODE_WRITE_BLOCK_REQUEST: 788 case TCODE_READ_BLOCK_RESPONSE: 789 case TCODE_LOCK_REQUEST: 790 case TCODE_LOCK_RESPONSE: 791 p.header[3] = cond_le32_to_cpu(buffer[3]); 792 p.header_length = 16; 793 p.payload_length = p.header[3] >> 16; 794 if (p.payload_length > MAX_ASYNC_PAYLOAD) { 795 ar_context_abort(ctx, "invalid packet length"); 796 return NULL; 797 } 798 break; 799 800 case TCODE_WRITE_RESPONSE: 801 case TCODE_READ_QUADLET_REQUEST: 802 case OHCI_TCODE_PHY_PACKET: 803 p.header_length = 12; 804 p.payload_length = 0; 805 break; 806 807 default: 808 ar_context_abort(ctx, "invalid tcode"); 809 return NULL; 810 } 811 812 p.payload = (void *) buffer + p.header_length; 813 814 /* FIXME: What to do about evt_* errors? */ 815 length = (p.header_length + p.payload_length + 3) / 4; 816 status = cond_le32_to_cpu(buffer[length]); 817 evt = (status >> 16) & 0x1f; 818 819 p.ack = evt - 16; 820 p.speed = (status >> 21) & 0x7; 821 p.timestamp = status & 0xffff; 822 p.generation = ohci->request_generation; 823 824 log_ar_at_event('R', p.speed, p.header, evt); 825 826 /* 827 * Several controllers, notably from NEC and VIA, forget to 828 * write ack_complete status at PHY packet reception. 829 */ 830 if (evt == OHCI1394_evt_no_status && 831 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4)) 832 p.ack = ACK_COMPLETE; 833 834 /* 835 * The OHCI bus reset handler synthesizes a PHY packet with 836 * the new generation number when a bus reset happens (see 837 * section 8.4.2.3). This helps us determine when a request 838 * was received and make sure we send the response in the same 839 * generation. We only need this for requests; for responses 840 * we use the unique tlabel for finding the matching 841 * request. 842 * 843 * Alas some chips sometimes emit bus reset packets with a 844 * wrong generation. We set the correct generation for these 845 * at a slightly incorrect time (in bus_reset_tasklet). 846 */ 847 if (evt == OHCI1394_evt_bus_reset) { 848 if (!(ohci->quirks & QUIRK_RESET_PACKET)) 849 ohci->request_generation = (p.header[2] >> 16) & 0xff; 850 } else if (ctx == &ohci->ar_request_ctx) { 851 fw_core_handle_request(&ohci->card, &p); 852 } else { 853 fw_core_handle_response(&ohci->card, &p); 854 } 855 856 return buffer + length + 1; 857 } 858 859 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end) 860 { 861 void *next; 862 863 while (p < end) { 864 next = handle_ar_packet(ctx, p); 865 if (!next) 866 return p; 867 p = next; 868 } 869 870 return p; 871 } 872 873 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer) 874 { 875 unsigned int i; 876 877 i = ar_first_buffer_index(ctx); 878 while (i != end_buffer) { 879 dma_sync_single_for_device(ctx->ohci->card.device, 880 ar_buffer_bus(ctx, i), 881 PAGE_SIZE, DMA_FROM_DEVICE); 882 ar_context_link_page(ctx, i); 883 i = ar_next_buffer_index(i); 884 } 885 } 886 887 static void ar_context_tasklet(unsigned long data) 888 { 889 struct ar_context *ctx = (struct ar_context *)data; 890 unsigned int end_buffer_index, end_buffer_offset; 891 void *p, *end; 892 893 p = ctx->pointer; 894 if (!p) 895 return; 896 897 end_buffer_index = ar_search_last_active_buffer(ctx, 898 &end_buffer_offset); 899 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset); 900 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset; 901 902 if (end_buffer_index < ar_first_buffer_index(ctx)) { 903 /* 904 * The filled part of the overall buffer wraps around; handle 905 * all packets up to the buffer end here. If the last packet 906 * wraps around, its tail will be visible after the buffer end 907 * because the buffer start pages are mapped there again. 908 */ 909 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE; 910 p = handle_ar_packets(ctx, p, buffer_end); 911 if (p < buffer_end) 912 goto error; 913 /* adjust p to point back into the actual buffer */ 914 p -= AR_BUFFERS * PAGE_SIZE; 915 } 916 917 p = handle_ar_packets(ctx, p, end); 918 if (p != end) { 919 if (p > end) 920 ar_context_abort(ctx, "inconsistent descriptor"); 921 goto error; 922 } 923 924 ctx->pointer = p; 925 ar_recycle_buffers(ctx, end_buffer_index); 926 927 return; 928 929 error: 930 ctx->pointer = NULL; 931 } 932 933 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, 934 unsigned int descriptors_offset, u32 regs) 935 { 936 unsigned int i; 937 dma_addr_t dma_addr; 938 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES]; 939 struct descriptor *d; 940 941 ctx->regs = regs; 942 ctx->ohci = ohci; 943 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); 944 945 for (i = 0; i < AR_BUFFERS; i++) { 946 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32); 947 if (!ctx->pages[i]) 948 goto out_of_memory; 949 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i], 950 0, PAGE_SIZE, DMA_FROM_DEVICE); 951 if (dma_mapping_error(ohci->card.device, dma_addr)) { 952 __free_page(ctx->pages[i]); 953 ctx->pages[i] = NULL; 954 goto out_of_memory; 955 } 956 set_page_private(ctx->pages[i], dma_addr); 957 } 958 959 for (i = 0; i < AR_BUFFERS; i++) 960 pages[i] = ctx->pages[i]; 961 for (i = 0; i < AR_WRAPAROUND_PAGES; i++) 962 pages[AR_BUFFERS + i] = ctx->pages[i]; 963 ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES, 964 -1, PAGE_KERNEL); 965 if (!ctx->buffer) 966 goto out_of_memory; 967 968 ctx->descriptors = ohci->misc_buffer + descriptors_offset; 969 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset; 970 971 for (i = 0; i < AR_BUFFERS; i++) { 972 d = &ctx->descriptors[i]; 973 d->req_count = cpu_to_le16(PAGE_SIZE); 974 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 975 DESCRIPTOR_STATUS | 976 DESCRIPTOR_BRANCH_ALWAYS); 977 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i)); 978 d->branch_address = cpu_to_le32(ctx->descriptors_bus + 979 ar_next_buffer_index(i) * sizeof(struct descriptor)); 980 } 981 982 return 0; 983 984 out_of_memory: 985 ar_context_release(ctx); 986 987 return -ENOMEM; 988 } 989 990 static void ar_context_run(struct ar_context *ctx) 991 { 992 unsigned int i; 993 994 for (i = 0; i < AR_BUFFERS; i++) 995 ar_context_link_page(ctx, i); 996 997 ctx->pointer = ctx->buffer; 998 999 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1); 1000 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); 1001 flush_writes(ctx->ohci); 1002 } 1003 1004 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z) 1005 { 1006 int b, key; 1007 1008 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2; 1009 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8; 1010 1011 /* figure out which descriptor the branch address goes in */ 1012 if (z == 2 && (b == 3 || key == 2)) 1013 return d; 1014 else 1015 return d + z - 1; 1016 } 1017 1018 static void context_tasklet(unsigned long data) 1019 { 1020 struct context *ctx = (struct context *) data; 1021 struct descriptor *d, *last; 1022 u32 address; 1023 int z; 1024 struct descriptor_buffer *desc; 1025 1026 desc = list_entry(ctx->buffer_list.next, 1027 struct descriptor_buffer, list); 1028 last = ctx->last; 1029 while (last->branch_address != 0) { 1030 struct descriptor_buffer *old_desc = desc; 1031 address = le32_to_cpu(last->branch_address); 1032 z = address & 0xf; 1033 address &= ~0xf; 1034 1035 /* If the branch address points to a buffer outside of the 1036 * current buffer, advance to the next buffer. */ 1037 if (address < desc->buffer_bus || 1038 address >= desc->buffer_bus + desc->used) 1039 desc = list_entry(desc->list.next, 1040 struct descriptor_buffer, list); 1041 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d); 1042 last = find_branch_descriptor(d, z); 1043 1044 if (!ctx->callback(ctx, d, last)) 1045 break; 1046 1047 if (old_desc != desc) { 1048 /* If we've advanced to the next buffer, move the 1049 * previous buffer to the free list. */ 1050 unsigned long flags; 1051 old_desc->used = 0; 1052 spin_lock_irqsave(&ctx->ohci->lock, flags); 1053 list_move_tail(&old_desc->list, &ctx->buffer_list); 1054 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1055 } 1056 ctx->last = last; 1057 } 1058 } 1059 1060 /* 1061 * Allocate a new buffer and add it to the list of free buffers for this 1062 * context. Must be called with ohci->lock held. 1063 */ 1064 static int context_add_buffer(struct context *ctx) 1065 { 1066 struct descriptor_buffer *desc; 1067 dma_addr_t uninitialized_var(bus_addr); 1068 int offset; 1069 1070 /* 1071 * 16MB of descriptors should be far more than enough for any DMA 1072 * program. This will catch run-away userspace or DoS attacks. 1073 */ 1074 if (ctx->total_allocation >= 16*1024*1024) 1075 return -ENOMEM; 1076 1077 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE, 1078 &bus_addr, GFP_ATOMIC); 1079 if (!desc) 1080 return -ENOMEM; 1081 1082 offset = (void *)&desc->buffer - (void *)desc; 1083 desc->buffer_size = PAGE_SIZE - offset; 1084 desc->buffer_bus = bus_addr + offset; 1085 desc->used = 0; 1086 1087 list_add_tail(&desc->list, &ctx->buffer_list); 1088 ctx->total_allocation += PAGE_SIZE; 1089 1090 return 0; 1091 } 1092 1093 static int context_init(struct context *ctx, struct fw_ohci *ohci, 1094 u32 regs, descriptor_callback_t callback) 1095 { 1096 ctx->ohci = ohci; 1097 ctx->regs = regs; 1098 ctx->total_allocation = 0; 1099 1100 INIT_LIST_HEAD(&ctx->buffer_list); 1101 if (context_add_buffer(ctx) < 0) 1102 return -ENOMEM; 1103 1104 ctx->buffer_tail = list_entry(ctx->buffer_list.next, 1105 struct descriptor_buffer, list); 1106 1107 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); 1108 ctx->callback = callback; 1109 1110 /* 1111 * We put a dummy descriptor in the buffer that has a NULL 1112 * branch address and looks like it's been sent. That way we 1113 * have a descriptor to append DMA programs to. 1114 */ 1115 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer)); 1116 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST); 1117 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011); 1118 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer); 1119 ctx->last = ctx->buffer_tail->buffer; 1120 ctx->prev = ctx->buffer_tail->buffer; 1121 1122 return 0; 1123 } 1124 1125 static void context_release(struct context *ctx) 1126 { 1127 struct fw_card *card = &ctx->ohci->card; 1128 struct descriptor_buffer *desc, *tmp; 1129 1130 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list) 1131 dma_free_coherent(card->device, PAGE_SIZE, desc, 1132 desc->buffer_bus - 1133 ((void *)&desc->buffer - (void *)desc)); 1134 } 1135 1136 /* Must be called with ohci->lock held */ 1137 static struct descriptor *context_get_descriptors(struct context *ctx, 1138 int z, dma_addr_t *d_bus) 1139 { 1140 struct descriptor *d = NULL; 1141 struct descriptor_buffer *desc = ctx->buffer_tail; 1142 1143 if (z * sizeof(*d) > desc->buffer_size) 1144 return NULL; 1145 1146 if (z * sizeof(*d) > desc->buffer_size - desc->used) { 1147 /* No room for the descriptor in this buffer, so advance to the 1148 * next one. */ 1149 1150 if (desc->list.next == &ctx->buffer_list) { 1151 /* If there is no free buffer next in the list, 1152 * allocate one. */ 1153 if (context_add_buffer(ctx) < 0) 1154 return NULL; 1155 } 1156 desc = list_entry(desc->list.next, 1157 struct descriptor_buffer, list); 1158 ctx->buffer_tail = desc; 1159 } 1160 1161 d = desc->buffer + desc->used / sizeof(*d); 1162 memset(d, 0, z * sizeof(*d)); 1163 *d_bus = desc->buffer_bus + desc->used; 1164 1165 return d; 1166 } 1167 1168 static void context_run(struct context *ctx, u32 extra) 1169 { 1170 struct fw_ohci *ohci = ctx->ohci; 1171 1172 reg_write(ohci, COMMAND_PTR(ctx->regs), 1173 le32_to_cpu(ctx->last->branch_address)); 1174 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); 1175 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); 1176 ctx->running = true; 1177 flush_writes(ohci); 1178 } 1179 1180 static void context_append(struct context *ctx, 1181 struct descriptor *d, int z, int extra) 1182 { 1183 dma_addr_t d_bus; 1184 struct descriptor_buffer *desc = ctx->buffer_tail; 1185 1186 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d); 1187 1188 desc->used += (z + extra) * sizeof(*d); 1189 1190 wmb(); /* finish init of new descriptors before branch_address update */ 1191 ctx->prev->branch_address = cpu_to_le32(d_bus | z); 1192 ctx->prev = find_branch_descriptor(d, z); 1193 1194 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 1195 flush_writes(ctx->ohci); 1196 } 1197 1198 static void context_stop(struct context *ctx) 1199 { 1200 u32 reg; 1201 int i; 1202 1203 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 1204 ctx->running = false; 1205 flush_writes(ctx->ohci); 1206 1207 for (i = 0; i < 10; i++) { 1208 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs)); 1209 if ((reg & CONTEXT_ACTIVE) == 0) 1210 return; 1211 1212 mdelay(1); 1213 } 1214 fw_error("Error: DMA context still active (0x%08x)\n", reg); 1215 } 1216 1217 struct driver_data { 1218 struct fw_packet *packet; 1219 }; 1220 1221 /* 1222 * This function apppends a packet to the DMA queue for transmission. 1223 * Must always be called with the ochi->lock held to ensure proper 1224 * generation handling and locking around packet queue manipulation. 1225 */ 1226 static int at_context_queue_packet(struct context *ctx, 1227 struct fw_packet *packet) 1228 { 1229 struct fw_ohci *ohci = ctx->ohci; 1230 dma_addr_t d_bus, uninitialized_var(payload_bus); 1231 struct driver_data *driver_data; 1232 struct descriptor *d, *last; 1233 __le32 *header; 1234 int z, tcode; 1235 1236 d = context_get_descriptors(ctx, 4, &d_bus); 1237 if (d == NULL) { 1238 packet->ack = RCODE_SEND_ERROR; 1239 return -1; 1240 } 1241 1242 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 1243 d[0].res_count = cpu_to_le16(packet->timestamp); 1244 1245 /* 1246 * The DMA format for asyncronous link packets is different 1247 * from the IEEE1394 layout, so shift the fields around 1248 * accordingly. 1249 */ 1250 1251 tcode = (packet->header[0] >> 4) & 0x0f; 1252 header = (__le32 *) &d[1]; 1253 switch (tcode) { 1254 case TCODE_WRITE_QUADLET_REQUEST: 1255 case TCODE_WRITE_BLOCK_REQUEST: 1256 case TCODE_WRITE_RESPONSE: 1257 case TCODE_READ_QUADLET_REQUEST: 1258 case TCODE_READ_BLOCK_REQUEST: 1259 case TCODE_READ_QUADLET_RESPONSE: 1260 case TCODE_READ_BLOCK_RESPONSE: 1261 case TCODE_LOCK_REQUEST: 1262 case TCODE_LOCK_RESPONSE: 1263 header[0] = cpu_to_le32((packet->header[0] & 0xffff) | 1264 (packet->speed << 16)); 1265 header[1] = cpu_to_le32((packet->header[1] & 0xffff) | 1266 (packet->header[0] & 0xffff0000)); 1267 header[2] = cpu_to_le32(packet->header[2]); 1268 1269 if (TCODE_IS_BLOCK_PACKET(tcode)) 1270 header[3] = cpu_to_le32(packet->header[3]); 1271 else 1272 header[3] = (__force __le32) packet->header[3]; 1273 1274 d[0].req_count = cpu_to_le16(packet->header_length); 1275 break; 1276 1277 case TCODE_LINK_INTERNAL: 1278 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) | 1279 (packet->speed << 16)); 1280 header[1] = cpu_to_le32(packet->header[1]); 1281 header[2] = cpu_to_le32(packet->header[2]); 1282 d[0].req_count = cpu_to_le16(12); 1283 1284 if (is_ping_packet(&packet->header[1])) 1285 d[0].control |= cpu_to_le16(DESCRIPTOR_PING); 1286 break; 1287 1288 case TCODE_STREAM_DATA: 1289 header[0] = cpu_to_le32((packet->header[0] & 0xffff) | 1290 (packet->speed << 16)); 1291 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000); 1292 d[0].req_count = cpu_to_le16(8); 1293 break; 1294 1295 default: 1296 /* BUG(); */ 1297 packet->ack = RCODE_SEND_ERROR; 1298 return -1; 1299 } 1300 1301 driver_data = (struct driver_data *) &d[3]; 1302 driver_data->packet = packet; 1303 packet->driver_data = driver_data; 1304 1305 if (packet->payload_length > 0) { 1306 payload_bus = 1307 dma_map_single(ohci->card.device, packet->payload, 1308 packet->payload_length, DMA_TO_DEVICE); 1309 if (dma_mapping_error(ohci->card.device, payload_bus)) { 1310 packet->ack = RCODE_SEND_ERROR; 1311 return -1; 1312 } 1313 packet->payload_bus = payload_bus; 1314 packet->payload_mapped = true; 1315 1316 d[2].req_count = cpu_to_le16(packet->payload_length); 1317 d[2].data_address = cpu_to_le32(payload_bus); 1318 last = &d[2]; 1319 z = 3; 1320 } else { 1321 last = &d[0]; 1322 z = 2; 1323 } 1324 1325 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 1326 DESCRIPTOR_IRQ_ALWAYS | 1327 DESCRIPTOR_BRANCH_ALWAYS); 1328 1329 /* 1330 * If the controller and packet generations don't match, we need to 1331 * bail out and try again. If IntEvent.busReset is set, the AT context 1332 * is halted, so appending to the context and trying to run it is 1333 * futile. Most controllers do the right thing and just flush the AT 1334 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but 1335 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind 1336 * up stalling out. So we just bail out in software and try again 1337 * later, and everyone is happy. 1338 * FIXME: Test of IntEvent.busReset may no longer be necessary since we 1339 * flush AT queues in bus_reset_tasklet. 1340 * FIXME: Document how the locking works. 1341 */ 1342 if (ohci->generation != packet->generation || 1343 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) { 1344 if (packet->payload_mapped) 1345 dma_unmap_single(ohci->card.device, payload_bus, 1346 packet->payload_length, DMA_TO_DEVICE); 1347 packet->ack = RCODE_GENERATION; 1348 return -1; 1349 } 1350 1351 context_append(ctx, d, z, 4 - z); 1352 1353 if (!ctx->running) 1354 context_run(ctx, 0); 1355 1356 return 0; 1357 } 1358 1359 static void at_context_flush(struct context *ctx) 1360 { 1361 tasklet_disable(&ctx->tasklet); 1362 1363 ctx->flushing = true; 1364 context_tasklet((unsigned long)ctx); 1365 ctx->flushing = false; 1366 1367 tasklet_enable(&ctx->tasklet); 1368 } 1369 1370 static int handle_at_packet(struct context *context, 1371 struct descriptor *d, 1372 struct descriptor *last) 1373 { 1374 struct driver_data *driver_data; 1375 struct fw_packet *packet; 1376 struct fw_ohci *ohci = context->ohci; 1377 int evt; 1378 1379 if (last->transfer_status == 0 && !context->flushing) 1380 /* This descriptor isn't done yet, stop iteration. */ 1381 return 0; 1382 1383 driver_data = (struct driver_data *) &d[3]; 1384 packet = driver_data->packet; 1385 if (packet == NULL) 1386 /* This packet was cancelled, just continue. */ 1387 return 1; 1388 1389 if (packet->payload_mapped) 1390 dma_unmap_single(ohci->card.device, packet->payload_bus, 1391 packet->payload_length, DMA_TO_DEVICE); 1392 1393 evt = le16_to_cpu(last->transfer_status) & 0x1f; 1394 packet->timestamp = le16_to_cpu(last->res_count); 1395 1396 log_ar_at_event('T', packet->speed, packet->header, evt); 1397 1398 switch (evt) { 1399 case OHCI1394_evt_timeout: 1400 /* Async response transmit timed out. */ 1401 packet->ack = RCODE_CANCELLED; 1402 break; 1403 1404 case OHCI1394_evt_flushed: 1405 /* 1406 * The packet was flushed should give same error as 1407 * when we try to use a stale generation count. 1408 */ 1409 packet->ack = RCODE_GENERATION; 1410 break; 1411 1412 case OHCI1394_evt_missing_ack: 1413 if (context->flushing) 1414 packet->ack = RCODE_GENERATION; 1415 else { 1416 /* 1417 * Using a valid (current) generation count, but the 1418 * node is not on the bus or not sending acks. 1419 */ 1420 packet->ack = RCODE_NO_ACK; 1421 } 1422 break; 1423 1424 case ACK_COMPLETE + 0x10: 1425 case ACK_PENDING + 0x10: 1426 case ACK_BUSY_X + 0x10: 1427 case ACK_BUSY_A + 0x10: 1428 case ACK_BUSY_B + 0x10: 1429 case ACK_DATA_ERROR + 0x10: 1430 case ACK_TYPE_ERROR + 0x10: 1431 packet->ack = evt - 0x10; 1432 break; 1433 1434 case OHCI1394_evt_no_status: 1435 if (context->flushing) { 1436 packet->ack = RCODE_GENERATION; 1437 break; 1438 } 1439 /* fall through */ 1440 1441 default: 1442 packet->ack = RCODE_SEND_ERROR; 1443 break; 1444 } 1445 1446 packet->callback(packet, &ohci->card, packet->ack); 1447 1448 return 1; 1449 } 1450 1451 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff) 1452 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f) 1453 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff) 1454 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff) 1455 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff) 1456 1457 static void handle_local_rom(struct fw_ohci *ohci, 1458 struct fw_packet *packet, u32 csr) 1459 { 1460 struct fw_packet response; 1461 int tcode, length, i; 1462 1463 tcode = HEADER_GET_TCODE(packet->header[0]); 1464 if (TCODE_IS_BLOCK_PACKET(tcode)) 1465 length = HEADER_GET_DATA_LENGTH(packet->header[3]); 1466 else 1467 length = 4; 1468 1469 i = csr - CSR_CONFIG_ROM; 1470 if (i + length > CONFIG_ROM_SIZE) { 1471 fw_fill_response(&response, packet->header, 1472 RCODE_ADDRESS_ERROR, NULL, 0); 1473 } else if (!TCODE_IS_READ_REQUEST(tcode)) { 1474 fw_fill_response(&response, packet->header, 1475 RCODE_TYPE_ERROR, NULL, 0); 1476 } else { 1477 fw_fill_response(&response, packet->header, RCODE_COMPLETE, 1478 (void *) ohci->config_rom + i, length); 1479 } 1480 1481 fw_core_handle_response(&ohci->card, &response); 1482 } 1483 1484 static void handle_local_lock(struct fw_ohci *ohci, 1485 struct fw_packet *packet, u32 csr) 1486 { 1487 struct fw_packet response; 1488 int tcode, length, ext_tcode, sel, try; 1489 __be32 *payload, lock_old; 1490 u32 lock_arg, lock_data; 1491 1492 tcode = HEADER_GET_TCODE(packet->header[0]); 1493 length = HEADER_GET_DATA_LENGTH(packet->header[3]); 1494 payload = packet->payload; 1495 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]); 1496 1497 if (tcode == TCODE_LOCK_REQUEST && 1498 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { 1499 lock_arg = be32_to_cpu(payload[0]); 1500 lock_data = be32_to_cpu(payload[1]); 1501 } else if (tcode == TCODE_READ_QUADLET_REQUEST) { 1502 lock_arg = 0; 1503 lock_data = 0; 1504 } else { 1505 fw_fill_response(&response, packet->header, 1506 RCODE_TYPE_ERROR, NULL, 0); 1507 goto out; 1508 } 1509 1510 sel = (csr - CSR_BUS_MANAGER_ID) / 4; 1511 reg_write(ohci, OHCI1394_CSRData, lock_data); 1512 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); 1513 reg_write(ohci, OHCI1394_CSRControl, sel); 1514 1515 for (try = 0; try < 20; try++) 1516 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) { 1517 lock_old = cpu_to_be32(reg_read(ohci, 1518 OHCI1394_CSRData)); 1519 fw_fill_response(&response, packet->header, 1520 RCODE_COMPLETE, 1521 &lock_old, sizeof(lock_old)); 1522 goto out; 1523 } 1524 1525 fw_error("swap not done (CSR lock timeout)\n"); 1526 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0); 1527 1528 out: 1529 fw_core_handle_response(&ohci->card, &response); 1530 } 1531 1532 static void handle_local_request(struct context *ctx, struct fw_packet *packet) 1533 { 1534 u64 offset, csr; 1535 1536 if (ctx == &ctx->ohci->at_request_ctx) { 1537 packet->ack = ACK_PENDING; 1538 packet->callback(packet, &ctx->ohci->card, packet->ack); 1539 } 1540 1541 offset = 1542 ((unsigned long long) 1543 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) | 1544 packet->header[2]; 1545 csr = offset - CSR_REGISTER_BASE; 1546 1547 /* Handle config rom reads. */ 1548 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) 1549 handle_local_rom(ctx->ohci, packet, csr); 1550 else switch (csr) { 1551 case CSR_BUS_MANAGER_ID: 1552 case CSR_BANDWIDTH_AVAILABLE: 1553 case CSR_CHANNELS_AVAILABLE_HI: 1554 case CSR_CHANNELS_AVAILABLE_LO: 1555 handle_local_lock(ctx->ohci, packet, csr); 1556 break; 1557 default: 1558 if (ctx == &ctx->ohci->at_request_ctx) 1559 fw_core_handle_request(&ctx->ohci->card, packet); 1560 else 1561 fw_core_handle_response(&ctx->ohci->card, packet); 1562 break; 1563 } 1564 1565 if (ctx == &ctx->ohci->at_response_ctx) { 1566 packet->ack = ACK_COMPLETE; 1567 packet->callback(packet, &ctx->ohci->card, packet->ack); 1568 } 1569 } 1570 1571 static void at_context_transmit(struct context *ctx, struct fw_packet *packet) 1572 { 1573 unsigned long flags; 1574 int ret; 1575 1576 spin_lock_irqsave(&ctx->ohci->lock, flags); 1577 1578 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id && 1579 ctx->ohci->generation == packet->generation) { 1580 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1581 handle_local_request(ctx, packet); 1582 return; 1583 } 1584 1585 ret = at_context_queue_packet(ctx, packet); 1586 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1587 1588 if (ret < 0) 1589 packet->callback(packet, &ctx->ohci->card, packet->ack); 1590 1591 } 1592 1593 static u32 cycle_timer_ticks(u32 cycle_timer) 1594 { 1595 u32 ticks; 1596 1597 ticks = cycle_timer & 0xfff; 1598 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff); 1599 ticks += (3072 * 8000) * (cycle_timer >> 25); 1600 1601 return ticks; 1602 } 1603 1604 /* 1605 * Some controllers exhibit one or more of the following bugs when updating the 1606 * iso cycle timer register: 1607 * - When the lowest six bits are wrapping around to zero, a read that happens 1608 * at the same time will return garbage in the lowest ten bits. 1609 * - When the cycleOffset field wraps around to zero, the cycleCount field is 1610 * not incremented for about 60 ns. 1611 * - Occasionally, the entire register reads zero. 1612 * 1613 * To catch these, we read the register three times and ensure that the 1614 * difference between each two consecutive reads is approximately the same, i.e. 1615 * less than twice the other. Furthermore, any negative difference indicates an 1616 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to 1617 * execute, so we have enough precision to compute the ratio of the differences.) 1618 */ 1619 static u32 get_cycle_time(struct fw_ohci *ohci) 1620 { 1621 u32 c0, c1, c2; 1622 u32 t0, t1, t2; 1623 s32 diff01, diff12; 1624 int i; 1625 1626 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1627 1628 if (ohci->quirks & QUIRK_CYCLE_TIMER) { 1629 i = 0; 1630 c1 = c2; 1631 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1632 do { 1633 c0 = c1; 1634 c1 = c2; 1635 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1636 t0 = cycle_timer_ticks(c0); 1637 t1 = cycle_timer_ticks(c1); 1638 t2 = cycle_timer_ticks(c2); 1639 diff01 = t1 - t0; 1640 diff12 = t2 - t1; 1641 } while ((diff01 <= 0 || diff12 <= 0 || 1642 diff01 / diff12 >= 2 || diff12 / diff01 >= 2) 1643 && i++ < 20); 1644 } 1645 1646 return c2; 1647 } 1648 1649 /* 1650 * This function has to be called at least every 64 seconds. The bus_time 1651 * field stores not only the upper 25 bits of the BUS_TIME register but also 1652 * the most significant bit of the cycle timer in bit 6 so that we can detect 1653 * changes in this bit. 1654 */ 1655 static u32 update_bus_time(struct fw_ohci *ohci) 1656 { 1657 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25; 1658 1659 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40)) 1660 ohci->bus_time += 0x40; 1661 1662 return ohci->bus_time | cycle_time_seconds; 1663 } 1664 1665 static void bus_reset_tasklet(unsigned long data) 1666 { 1667 struct fw_ohci *ohci = (struct fw_ohci *)data; 1668 int self_id_count, i, j, reg; 1669 int generation, new_generation; 1670 unsigned long flags; 1671 void *free_rom = NULL; 1672 dma_addr_t free_rom_bus = 0; 1673 bool is_new_root; 1674 1675 reg = reg_read(ohci, OHCI1394_NodeID); 1676 if (!(reg & OHCI1394_NodeID_idValid)) { 1677 fw_notify("node ID not valid, new bus reset in progress\n"); 1678 return; 1679 } 1680 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { 1681 fw_notify("malconfigured bus\n"); 1682 return; 1683 } 1684 ohci->node_id = reg & (OHCI1394_NodeID_busNumber | 1685 OHCI1394_NodeID_nodeNumber); 1686 1687 is_new_root = (reg & OHCI1394_NodeID_root) != 0; 1688 if (!(ohci->is_root && is_new_root)) 1689 reg_write(ohci, OHCI1394_LinkControlSet, 1690 OHCI1394_LinkControl_cycleMaster); 1691 ohci->is_root = is_new_root; 1692 1693 reg = reg_read(ohci, OHCI1394_SelfIDCount); 1694 if (reg & OHCI1394_SelfIDCount_selfIDError) { 1695 fw_notify("inconsistent self IDs\n"); 1696 return; 1697 } 1698 /* 1699 * The count in the SelfIDCount register is the number of 1700 * bytes in the self ID receive buffer. Since we also receive 1701 * the inverted quadlets and a header quadlet, we shift one 1702 * bit extra to get the actual number of self IDs. 1703 */ 1704 self_id_count = (reg >> 3) & 0xff; 1705 if (self_id_count == 0 || self_id_count > 252) { 1706 fw_notify("inconsistent self IDs\n"); 1707 return; 1708 } 1709 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff; 1710 rmb(); 1711 1712 for (i = 1, j = 0; j < self_id_count; i += 2, j++) { 1713 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) { 1714 fw_notify("inconsistent self IDs\n"); 1715 return; 1716 } 1717 ohci->self_id_buffer[j] = 1718 cond_le32_to_cpu(ohci->self_id_cpu[i]); 1719 } 1720 rmb(); 1721 1722 /* 1723 * Check the consistency of the self IDs we just read. The 1724 * problem we face is that a new bus reset can start while we 1725 * read out the self IDs from the DMA buffer. If this happens, 1726 * the DMA buffer will be overwritten with new self IDs and we 1727 * will read out inconsistent data. The OHCI specification 1728 * (section 11.2) recommends a technique similar to 1729 * linux/seqlock.h, where we remember the generation of the 1730 * self IDs in the buffer before reading them out and compare 1731 * it to the current generation after reading them out. If 1732 * the two generations match we know we have a consistent set 1733 * of self IDs. 1734 */ 1735 1736 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; 1737 if (new_generation != generation) { 1738 fw_notify("recursive bus reset detected, " 1739 "discarding self ids\n"); 1740 return; 1741 } 1742 1743 /* FIXME: Document how the locking works. */ 1744 spin_lock_irqsave(&ohci->lock, flags); 1745 1746 ohci->generation = -1; /* prevent AT packet queueing */ 1747 context_stop(&ohci->at_request_ctx); 1748 context_stop(&ohci->at_response_ctx); 1749 1750 spin_unlock_irqrestore(&ohci->lock, flags); 1751 1752 /* 1753 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent 1754 * packets in the AT queues and software needs to drain them. 1755 * Some OHCI 1.1 controllers (JMicron) apparently require this too. 1756 */ 1757 at_context_flush(&ohci->at_request_ctx); 1758 at_context_flush(&ohci->at_response_ctx); 1759 1760 spin_lock_irqsave(&ohci->lock, flags); 1761 1762 ohci->generation = generation; 1763 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); 1764 1765 if (ohci->quirks & QUIRK_RESET_PACKET) 1766 ohci->request_generation = generation; 1767 1768 /* 1769 * This next bit is unrelated to the AT context stuff but we 1770 * have to do it under the spinlock also. If a new config rom 1771 * was set up before this reset, the old one is now no longer 1772 * in use and we can free it. Update the config rom pointers 1773 * to point to the current config rom and clear the 1774 * next_config_rom pointer so a new update can take place. 1775 */ 1776 1777 if (ohci->next_config_rom != NULL) { 1778 if (ohci->next_config_rom != ohci->config_rom) { 1779 free_rom = ohci->config_rom; 1780 free_rom_bus = ohci->config_rom_bus; 1781 } 1782 ohci->config_rom = ohci->next_config_rom; 1783 ohci->config_rom_bus = ohci->next_config_rom_bus; 1784 ohci->next_config_rom = NULL; 1785 1786 /* 1787 * Restore config_rom image and manually update 1788 * config_rom registers. Writing the header quadlet 1789 * will indicate that the config rom is ready, so we 1790 * do that last. 1791 */ 1792 reg_write(ohci, OHCI1394_BusOptions, 1793 be32_to_cpu(ohci->config_rom[2])); 1794 ohci->config_rom[0] = ohci->next_header; 1795 reg_write(ohci, OHCI1394_ConfigROMhdr, 1796 be32_to_cpu(ohci->next_header)); 1797 } 1798 1799 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA 1800 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0); 1801 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0); 1802 #endif 1803 1804 spin_unlock_irqrestore(&ohci->lock, flags); 1805 1806 if (free_rom) 1807 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 1808 free_rom, free_rom_bus); 1809 1810 log_selfids(ohci->node_id, generation, 1811 self_id_count, ohci->self_id_buffer); 1812 1813 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, 1814 self_id_count, ohci->self_id_buffer, 1815 ohci->csr_state_setclear_abdicate); 1816 ohci->csr_state_setclear_abdicate = false; 1817 } 1818 1819 static irqreturn_t irq_handler(int irq, void *data) 1820 { 1821 struct fw_ohci *ohci = data; 1822 u32 event, iso_event; 1823 int i; 1824 1825 event = reg_read(ohci, OHCI1394_IntEventClear); 1826 1827 if (!event || !~event) 1828 return IRQ_NONE; 1829 1830 /* 1831 * busReset and postedWriteErr must not be cleared yet 1832 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1) 1833 */ 1834 reg_write(ohci, OHCI1394_IntEventClear, 1835 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr)); 1836 log_irqs(event); 1837 1838 if (event & OHCI1394_selfIDComplete) 1839 tasklet_schedule(&ohci->bus_reset_tasklet); 1840 1841 if (event & OHCI1394_RQPkt) 1842 tasklet_schedule(&ohci->ar_request_ctx.tasklet); 1843 1844 if (event & OHCI1394_RSPkt) 1845 tasklet_schedule(&ohci->ar_response_ctx.tasklet); 1846 1847 if (event & OHCI1394_reqTxComplete) 1848 tasklet_schedule(&ohci->at_request_ctx.tasklet); 1849 1850 if (event & OHCI1394_respTxComplete) 1851 tasklet_schedule(&ohci->at_response_ctx.tasklet); 1852 1853 if (event & OHCI1394_isochRx) { 1854 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); 1855 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); 1856 1857 while (iso_event) { 1858 i = ffs(iso_event) - 1; 1859 tasklet_schedule( 1860 &ohci->ir_context_list[i].context.tasklet); 1861 iso_event &= ~(1 << i); 1862 } 1863 } 1864 1865 if (event & OHCI1394_isochTx) { 1866 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); 1867 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); 1868 1869 while (iso_event) { 1870 i = ffs(iso_event) - 1; 1871 tasklet_schedule( 1872 &ohci->it_context_list[i].context.tasklet); 1873 iso_event &= ~(1 << i); 1874 } 1875 } 1876 1877 if (unlikely(event & OHCI1394_regAccessFail)) 1878 fw_error("Register access failure - " 1879 "please notify linux1394-devel@lists.sf.net\n"); 1880 1881 if (unlikely(event & OHCI1394_postedWriteErr)) { 1882 reg_read(ohci, OHCI1394_PostedWriteAddressHi); 1883 reg_read(ohci, OHCI1394_PostedWriteAddressLo); 1884 reg_write(ohci, OHCI1394_IntEventClear, 1885 OHCI1394_postedWriteErr); 1886 fw_error("PCI posted write error\n"); 1887 } 1888 1889 if (unlikely(event & OHCI1394_cycleTooLong)) { 1890 if (printk_ratelimit()) 1891 fw_notify("isochronous cycle too long\n"); 1892 reg_write(ohci, OHCI1394_LinkControlSet, 1893 OHCI1394_LinkControl_cycleMaster); 1894 } 1895 1896 if (unlikely(event & OHCI1394_cycleInconsistent)) { 1897 /* 1898 * We need to clear this event bit in order to make 1899 * cycleMatch isochronous I/O work. In theory we should 1900 * stop active cycleMatch iso contexts now and restart 1901 * them at least two cycles later. (FIXME?) 1902 */ 1903 if (printk_ratelimit()) 1904 fw_notify("isochronous cycle inconsistent\n"); 1905 } 1906 1907 if (event & OHCI1394_cycle64Seconds) { 1908 spin_lock(&ohci->lock); 1909 update_bus_time(ohci); 1910 spin_unlock(&ohci->lock); 1911 } else 1912 flush_writes(ohci); 1913 1914 return IRQ_HANDLED; 1915 } 1916 1917 static int software_reset(struct fw_ohci *ohci) 1918 { 1919 int i; 1920 1921 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); 1922 1923 for (i = 0; i < OHCI_LOOP_COUNT; i++) { 1924 if ((reg_read(ohci, OHCI1394_HCControlSet) & 1925 OHCI1394_HCControl_softReset) == 0) 1926 return 0; 1927 msleep(1); 1928 } 1929 1930 return -EBUSY; 1931 } 1932 1933 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length) 1934 { 1935 size_t size = length * 4; 1936 1937 memcpy(dest, src, size); 1938 if (size < CONFIG_ROM_SIZE) 1939 memset(&dest[length], 0, CONFIG_ROM_SIZE - size); 1940 } 1941 1942 static int configure_1394a_enhancements(struct fw_ohci *ohci) 1943 { 1944 bool enable_1394a; 1945 int ret, clear, set, offset; 1946 1947 /* Check if the driver should configure link and PHY. */ 1948 if (!(reg_read(ohci, OHCI1394_HCControlSet) & 1949 OHCI1394_HCControl_programPhyEnable)) 1950 return 0; 1951 1952 /* Paranoia: check whether the PHY supports 1394a, too. */ 1953 enable_1394a = false; 1954 ret = read_phy_reg(ohci, 2); 1955 if (ret < 0) 1956 return ret; 1957 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) { 1958 ret = read_paged_phy_reg(ohci, 1, 8); 1959 if (ret < 0) 1960 return ret; 1961 if (ret >= 1) 1962 enable_1394a = true; 1963 } 1964 1965 if (ohci->quirks & QUIRK_NO_1394A) 1966 enable_1394a = false; 1967 1968 /* Configure PHY and link consistently. */ 1969 if (enable_1394a) { 1970 clear = 0; 1971 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 1972 } else { 1973 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 1974 set = 0; 1975 } 1976 ret = update_phy_reg(ohci, 5, clear, set); 1977 if (ret < 0) 1978 return ret; 1979 1980 if (enable_1394a) 1981 offset = OHCI1394_HCControlSet; 1982 else 1983 offset = OHCI1394_HCControlClear; 1984 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable); 1985 1986 /* Clean up: configuration has been taken care of. */ 1987 reg_write(ohci, OHCI1394_HCControlClear, 1988 OHCI1394_HCControl_programPhyEnable); 1989 1990 return 0; 1991 } 1992 1993 static int ohci_enable(struct fw_card *card, 1994 const __be32 *config_rom, size_t length) 1995 { 1996 struct fw_ohci *ohci = fw_ohci(card); 1997 struct pci_dev *dev = to_pci_dev(card->device); 1998 u32 lps, seconds, version, irqs; 1999 int i, ret; 2000 2001 if (software_reset(ohci)) { 2002 fw_error("Failed to reset ohci card.\n"); 2003 return -EBUSY; 2004 } 2005 2006 /* 2007 * Now enable LPS, which we need in order to start accessing 2008 * most of the registers. In fact, on some cards (ALI M5251), 2009 * accessing registers in the SClk domain without LPS enabled 2010 * will lock up the machine. Wait 50msec to make sure we have 2011 * full link enabled. However, with some cards (well, at least 2012 * a JMicron PCIe card), we have to try again sometimes. 2013 */ 2014 reg_write(ohci, OHCI1394_HCControlSet, 2015 OHCI1394_HCControl_LPS | 2016 OHCI1394_HCControl_postedWriteEnable); 2017 flush_writes(ohci); 2018 2019 for (lps = 0, i = 0; !lps && i < 3; i++) { 2020 msleep(50); 2021 lps = reg_read(ohci, OHCI1394_HCControlSet) & 2022 OHCI1394_HCControl_LPS; 2023 } 2024 2025 if (!lps) { 2026 fw_error("Failed to set Link Power Status\n"); 2027 return -EIO; 2028 } 2029 2030 reg_write(ohci, OHCI1394_HCControlClear, 2031 OHCI1394_HCControl_noByteSwapData); 2032 2033 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); 2034 reg_write(ohci, OHCI1394_LinkControlSet, 2035 OHCI1394_LinkControl_rcvSelfID | 2036 OHCI1394_LinkControl_rcvPhyPkt | 2037 OHCI1394_LinkControl_cycleTimerEnable | 2038 OHCI1394_LinkControl_cycleMaster); 2039 2040 reg_write(ohci, OHCI1394_ATRetries, 2041 OHCI1394_MAX_AT_REQ_RETRIES | 2042 (OHCI1394_MAX_AT_RESP_RETRIES << 4) | 2043 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) | 2044 (200 << 16)); 2045 2046 seconds = lower_32_bits(get_seconds()); 2047 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25); 2048 ohci->bus_time = seconds & ~0x3f; 2049 2050 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 2051 if (version >= OHCI_VERSION_1_1) { 2052 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi, 2053 0xfffffffe); 2054 card->broadcast_channel_auto_allocated = true; 2055 } 2056 2057 /* Get implemented bits of the priority arbitration request counter. */ 2058 reg_write(ohci, OHCI1394_FairnessControl, 0x3f); 2059 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f; 2060 reg_write(ohci, OHCI1394_FairnessControl, 0); 2061 card->priority_budget_implemented = ohci->pri_req_max != 0; 2062 2063 ar_context_run(&ohci->ar_request_ctx); 2064 ar_context_run(&ohci->ar_response_ctx); 2065 2066 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000); 2067 reg_write(ohci, OHCI1394_IntEventClear, ~0); 2068 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 2069 2070 ret = configure_1394a_enhancements(ohci); 2071 if (ret < 0) 2072 return ret; 2073 2074 /* Activate link_on bit and contender bit in our self ID packets.*/ 2075 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER); 2076 if (ret < 0) 2077 return ret; 2078 2079 /* 2080 * When the link is not yet enabled, the atomic config rom 2081 * update mechanism described below in ohci_set_config_rom() 2082 * is not active. We have to update ConfigRomHeader and 2083 * BusOptions manually, and the write to ConfigROMmap takes 2084 * effect immediately. We tie this to the enabling of the 2085 * link, so we have a valid config rom before enabling - the 2086 * OHCI requires that ConfigROMhdr and BusOptions have valid 2087 * values before enabling. 2088 * 2089 * However, when the ConfigROMmap is written, some controllers 2090 * always read back quadlets 0 and 2 from the config rom to 2091 * the ConfigRomHeader and BusOptions registers on bus reset. 2092 * They shouldn't do that in this initial case where the link 2093 * isn't enabled. This means we have to use the same 2094 * workaround here, setting the bus header to 0 and then write 2095 * the right values in the bus reset tasklet. 2096 */ 2097 2098 if (config_rom) { 2099 ohci->next_config_rom = 2100 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2101 &ohci->next_config_rom_bus, 2102 GFP_KERNEL); 2103 if (ohci->next_config_rom == NULL) 2104 return -ENOMEM; 2105 2106 copy_config_rom(ohci->next_config_rom, config_rom, length); 2107 } else { 2108 /* 2109 * In the suspend case, config_rom is NULL, which 2110 * means that we just reuse the old config rom. 2111 */ 2112 ohci->next_config_rom = ohci->config_rom; 2113 ohci->next_config_rom_bus = ohci->config_rom_bus; 2114 } 2115 2116 ohci->next_header = ohci->next_config_rom[0]; 2117 ohci->next_config_rom[0] = 0; 2118 reg_write(ohci, OHCI1394_ConfigROMhdr, 0); 2119 reg_write(ohci, OHCI1394_BusOptions, 2120 be32_to_cpu(ohci->next_config_rom[2])); 2121 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2122 2123 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); 2124 2125 if (!(ohci->quirks & QUIRK_NO_MSI)) 2126 pci_enable_msi(dev); 2127 if (request_irq(dev->irq, irq_handler, 2128 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED, 2129 ohci_driver_name, ohci)) { 2130 fw_error("Failed to allocate interrupt %d.\n", dev->irq); 2131 pci_disable_msi(dev); 2132 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2133 ohci->config_rom, ohci->config_rom_bus); 2134 return -EIO; 2135 } 2136 2137 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete | 2138 OHCI1394_RQPkt | OHCI1394_RSPkt | 2139 OHCI1394_isochTx | OHCI1394_isochRx | 2140 OHCI1394_postedWriteErr | 2141 OHCI1394_selfIDComplete | 2142 OHCI1394_regAccessFail | 2143 OHCI1394_cycle64Seconds | 2144 OHCI1394_cycleInconsistent | OHCI1394_cycleTooLong | 2145 OHCI1394_masterIntEnable; 2146 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS) 2147 irqs |= OHCI1394_busReset; 2148 reg_write(ohci, OHCI1394_IntMaskSet, irqs); 2149 2150 reg_write(ohci, OHCI1394_HCControlSet, 2151 OHCI1394_HCControl_linkEnable | 2152 OHCI1394_HCControl_BIBimageValid); 2153 flush_writes(ohci); 2154 2155 /* We are ready to go, reset bus to finish initialization. */ 2156 fw_schedule_bus_reset(&ohci->card, false, true); 2157 2158 return 0; 2159 } 2160 2161 static int ohci_set_config_rom(struct fw_card *card, 2162 const __be32 *config_rom, size_t length) 2163 { 2164 struct fw_ohci *ohci; 2165 unsigned long flags; 2166 int ret = -EBUSY; 2167 __be32 *next_config_rom; 2168 dma_addr_t uninitialized_var(next_config_rom_bus); 2169 2170 ohci = fw_ohci(card); 2171 2172 /* 2173 * When the OHCI controller is enabled, the config rom update 2174 * mechanism is a bit tricky, but easy enough to use. See 2175 * section 5.5.6 in the OHCI specification. 2176 * 2177 * The OHCI controller caches the new config rom address in a 2178 * shadow register (ConfigROMmapNext) and needs a bus reset 2179 * for the changes to take place. When the bus reset is 2180 * detected, the controller loads the new values for the 2181 * ConfigRomHeader and BusOptions registers from the specified 2182 * config rom and loads ConfigROMmap from the ConfigROMmapNext 2183 * shadow register. All automatically and atomically. 2184 * 2185 * Now, there's a twist to this story. The automatic load of 2186 * ConfigRomHeader and BusOptions doesn't honor the 2187 * noByteSwapData bit, so with a be32 config rom, the 2188 * controller will load be32 values in to these registers 2189 * during the atomic update, even on litte endian 2190 * architectures. The workaround we use is to put a 0 in the 2191 * header quadlet; 0 is endian agnostic and means that the 2192 * config rom isn't ready yet. In the bus reset tasklet we 2193 * then set up the real values for the two registers. 2194 * 2195 * We use ohci->lock to avoid racing with the code that sets 2196 * ohci->next_config_rom to NULL (see bus_reset_tasklet). 2197 */ 2198 2199 next_config_rom = 2200 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2201 &next_config_rom_bus, GFP_KERNEL); 2202 if (next_config_rom == NULL) 2203 return -ENOMEM; 2204 2205 spin_lock_irqsave(&ohci->lock, flags); 2206 2207 if (ohci->next_config_rom == NULL) { 2208 ohci->next_config_rom = next_config_rom; 2209 ohci->next_config_rom_bus = next_config_rom_bus; 2210 2211 copy_config_rom(ohci->next_config_rom, config_rom, length); 2212 2213 ohci->next_header = config_rom[0]; 2214 ohci->next_config_rom[0] = 0; 2215 2216 reg_write(ohci, OHCI1394_ConfigROMmap, 2217 ohci->next_config_rom_bus); 2218 ret = 0; 2219 } 2220 2221 spin_unlock_irqrestore(&ohci->lock, flags); 2222 2223 /* 2224 * Now initiate a bus reset to have the changes take 2225 * effect. We clean up the old config rom memory and DMA 2226 * mappings in the bus reset tasklet, since the OHCI 2227 * controller could need to access it before the bus reset 2228 * takes effect. 2229 */ 2230 if (ret == 0) 2231 fw_schedule_bus_reset(&ohci->card, true, true); 2232 else 2233 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2234 next_config_rom, next_config_rom_bus); 2235 2236 return ret; 2237 } 2238 2239 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) 2240 { 2241 struct fw_ohci *ohci = fw_ohci(card); 2242 2243 at_context_transmit(&ohci->at_request_ctx, packet); 2244 } 2245 2246 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) 2247 { 2248 struct fw_ohci *ohci = fw_ohci(card); 2249 2250 at_context_transmit(&ohci->at_response_ctx, packet); 2251 } 2252 2253 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) 2254 { 2255 struct fw_ohci *ohci = fw_ohci(card); 2256 struct context *ctx = &ohci->at_request_ctx; 2257 struct driver_data *driver_data = packet->driver_data; 2258 int ret = -ENOENT; 2259 2260 tasklet_disable(&ctx->tasklet); 2261 2262 if (packet->ack != 0) 2263 goto out; 2264 2265 if (packet->payload_mapped) 2266 dma_unmap_single(ohci->card.device, packet->payload_bus, 2267 packet->payload_length, DMA_TO_DEVICE); 2268 2269 log_ar_at_event('T', packet->speed, packet->header, 0x20); 2270 driver_data->packet = NULL; 2271 packet->ack = RCODE_CANCELLED; 2272 packet->callback(packet, &ohci->card, packet->ack); 2273 ret = 0; 2274 out: 2275 tasklet_enable(&ctx->tasklet); 2276 2277 return ret; 2278 } 2279 2280 static int ohci_enable_phys_dma(struct fw_card *card, 2281 int node_id, int generation) 2282 { 2283 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA 2284 return 0; 2285 #else 2286 struct fw_ohci *ohci = fw_ohci(card); 2287 unsigned long flags; 2288 int n, ret = 0; 2289 2290 /* 2291 * FIXME: Make sure this bitmask is cleared when we clear the busReset 2292 * interrupt bit. Clear physReqResourceAllBuses on bus reset. 2293 */ 2294 2295 spin_lock_irqsave(&ohci->lock, flags); 2296 2297 if (ohci->generation != generation) { 2298 ret = -ESTALE; 2299 goto out; 2300 } 2301 2302 /* 2303 * Note, if the node ID contains a non-local bus ID, physical DMA is 2304 * enabled for _all_ nodes on remote buses. 2305 */ 2306 2307 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; 2308 if (n < 32) 2309 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); 2310 else 2311 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); 2312 2313 flush_writes(ohci); 2314 out: 2315 spin_unlock_irqrestore(&ohci->lock, flags); 2316 2317 return ret; 2318 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */ 2319 } 2320 2321 static u32 ohci_read_csr(struct fw_card *card, int csr_offset) 2322 { 2323 struct fw_ohci *ohci = fw_ohci(card); 2324 unsigned long flags; 2325 u32 value; 2326 2327 switch (csr_offset) { 2328 case CSR_STATE_CLEAR: 2329 case CSR_STATE_SET: 2330 if (ohci->is_root && 2331 (reg_read(ohci, OHCI1394_LinkControlSet) & 2332 OHCI1394_LinkControl_cycleMaster)) 2333 value = CSR_STATE_BIT_CMSTR; 2334 else 2335 value = 0; 2336 if (ohci->csr_state_setclear_abdicate) 2337 value |= CSR_STATE_BIT_ABDICATE; 2338 2339 return value; 2340 2341 case CSR_NODE_IDS: 2342 return reg_read(ohci, OHCI1394_NodeID) << 16; 2343 2344 case CSR_CYCLE_TIME: 2345 return get_cycle_time(ohci); 2346 2347 case CSR_BUS_TIME: 2348 /* 2349 * We might be called just after the cycle timer has wrapped 2350 * around but just before the cycle64Seconds handler, so we 2351 * better check here, too, if the bus time needs to be updated. 2352 */ 2353 spin_lock_irqsave(&ohci->lock, flags); 2354 value = update_bus_time(ohci); 2355 spin_unlock_irqrestore(&ohci->lock, flags); 2356 return value; 2357 2358 case CSR_BUSY_TIMEOUT: 2359 value = reg_read(ohci, OHCI1394_ATRetries); 2360 return (value >> 4) & 0x0ffff00f; 2361 2362 case CSR_PRIORITY_BUDGET: 2363 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) | 2364 (ohci->pri_req_max << 8); 2365 2366 default: 2367 WARN_ON(1); 2368 return 0; 2369 } 2370 } 2371 2372 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value) 2373 { 2374 struct fw_ohci *ohci = fw_ohci(card); 2375 unsigned long flags; 2376 2377 switch (csr_offset) { 2378 case CSR_STATE_CLEAR: 2379 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2380 reg_write(ohci, OHCI1394_LinkControlClear, 2381 OHCI1394_LinkControl_cycleMaster); 2382 flush_writes(ohci); 2383 } 2384 if (value & CSR_STATE_BIT_ABDICATE) 2385 ohci->csr_state_setclear_abdicate = false; 2386 break; 2387 2388 case CSR_STATE_SET: 2389 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2390 reg_write(ohci, OHCI1394_LinkControlSet, 2391 OHCI1394_LinkControl_cycleMaster); 2392 flush_writes(ohci); 2393 } 2394 if (value & CSR_STATE_BIT_ABDICATE) 2395 ohci->csr_state_setclear_abdicate = true; 2396 break; 2397 2398 case CSR_NODE_IDS: 2399 reg_write(ohci, OHCI1394_NodeID, value >> 16); 2400 flush_writes(ohci); 2401 break; 2402 2403 case CSR_CYCLE_TIME: 2404 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value); 2405 reg_write(ohci, OHCI1394_IntEventSet, 2406 OHCI1394_cycleInconsistent); 2407 flush_writes(ohci); 2408 break; 2409 2410 case CSR_BUS_TIME: 2411 spin_lock_irqsave(&ohci->lock, flags); 2412 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f); 2413 spin_unlock_irqrestore(&ohci->lock, flags); 2414 break; 2415 2416 case CSR_BUSY_TIMEOUT: 2417 value = (value & 0xf) | ((value & 0xf) << 4) | 2418 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4); 2419 reg_write(ohci, OHCI1394_ATRetries, value); 2420 flush_writes(ohci); 2421 break; 2422 2423 case CSR_PRIORITY_BUDGET: 2424 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f); 2425 flush_writes(ohci); 2426 break; 2427 2428 default: 2429 WARN_ON(1); 2430 break; 2431 } 2432 } 2433 2434 static void copy_iso_headers(struct iso_context *ctx, void *p) 2435 { 2436 int i = ctx->header_length; 2437 2438 if (i + ctx->base.header_size > PAGE_SIZE) 2439 return; 2440 2441 /* 2442 * The iso header is byteswapped to little endian by 2443 * the controller, but the remaining header quadlets 2444 * are big endian. We want to present all the headers 2445 * as big endian, so we have to swap the first quadlet. 2446 */ 2447 if (ctx->base.header_size > 0) 2448 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4)); 2449 if (ctx->base.header_size > 4) 2450 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p); 2451 if (ctx->base.header_size > 8) 2452 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8); 2453 ctx->header_length += ctx->base.header_size; 2454 } 2455 2456 static int handle_ir_packet_per_buffer(struct context *context, 2457 struct descriptor *d, 2458 struct descriptor *last) 2459 { 2460 struct iso_context *ctx = 2461 container_of(context, struct iso_context, context); 2462 struct descriptor *pd; 2463 __le32 *ir_header; 2464 void *p; 2465 2466 for (pd = d; pd <= last; pd++) 2467 if (pd->transfer_status) 2468 break; 2469 if (pd > last) 2470 /* Descriptor(s) not done yet, stop iteration */ 2471 return 0; 2472 2473 p = last + 1; 2474 copy_iso_headers(ctx, p); 2475 2476 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) { 2477 ir_header = (__le32 *) p; 2478 ctx->base.callback.sc(&ctx->base, 2479 le32_to_cpu(ir_header[0]) & 0xffff, 2480 ctx->header_length, ctx->header, 2481 ctx->base.callback_data); 2482 ctx->header_length = 0; 2483 } 2484 2485 return 1; 2486 } 2487 2488 /* d == last because each descriptor block is only a single descriptor. */ 2489 static int handle_ir_buffer_fill(struct context *context, 2490 struct descriptor *d, 2491 struct descriptor *last) 2492 { 2493 struct iso_context *ctx = 2494 container_of(context, struct iso_context, context); 2495 2496 if (!last->transfer_status) 2497 /* Descriptor(s) not done yet, stop iteration */ 2498 return 0; 2499 2500 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) 2501 ctx->base.callback.mc(&ctx->base, 2502 le32_to_cpu(last->data_address) + 2503 le16_to_cpu(last->req_count) - 2504 le16_to_cpu(last->res_count), 2505 ctx->base.callback_data); 2506 2507 return 1; 2508 } 2509 2510 static int handle_it_packet(struct context *context, 2511 struct descriptor *d, 2512 struct descriptor *last) 2513 { 2514 struct iso_context *ctx = 2515 container_of(context, struct iso_context, context); 2516 int i; 2517 struct descriptor *pd; 2518 2519 for (pd = d; pd <= last; pd++) 2520 if (pd->transfer_status) 2521 break; 2522 if (pd > last) 2523 /* Descriptor(s) not done yet, stop iteration */ 2524 return 0; 2525 2526 i = ctx->header_length; 2527 if (i + 4 < PAGE_SIZE) { 2528 /* Present this value as big-endian to match the receive code */ 2529 *(__be32 *)(ctx->header + i) = cpu_to_be32( 2530 ((u32)le16_to_cpu(pd->transfer_status) << 16) | 2531 le16_to_cpu(pd->res_count)); 2532 ctx->header_length += 4; 2533 } 2534 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) { 2535 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count), 2536 ctx->header_length, ctx->header, 2537 ctx->base.callback_data); 2538 ctx->header_length = 0; 2539 } 2540 return 1; 2541 } 2542 2543 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels) 2544 { 2545 u32 hi = channels >> 32, lo = channels; 2546 2547 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi); 2548 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo); 2549 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi); 2550 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo); 2551 mmiowb(); 2552 ohci->mc_channels = channels; 2553 } 2554 2555 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card, 2556 int type, int channel, size_t header_size) 2557 { 2558 struct fw_ohci *ohci = fw_ohci(card); 2559 struct iso_context *uninitialized_var(ctx); 2560 descriptor_callback_t uninitialized_var(callback); 2561 u64 *uninitialized_var(channels); 2562 u32 *uninitialized_var(mask), uninitialized_var(regs); 2563 unsigned long flags; 2564 int index, ret = -EBUSY; 2565 2566 spin_lock_irqsave(&ohci->lock, flags); 2567 2568 switch (type) { 2569 case FW_ISO_CONTEXT_TRANSMIT: 2570 mask = &ohci->it_context_mask; 2571 callback = handle_it_packet; 2572 index = ffs(*mask) - 1; 2573 if (index >= 0) { 2574 *mask &= ~(1 << index); 2575 regs = OHCI1394_IsoXmitContextBase(index); 2576 ctx = &ohci->it_context_list[index]; 2577 } 2578 break; 2579 2580 case FW_ISO_CONTEXT_RECEIVE: 2581 channels = &ohci->ir_context_channels; 2582 mask = &ohci->ir_context_mask; 2583 callback = handle_ir_packet_per_buffer; 2584 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1; 2585 if (index >= 0) { 2586 *channels &= ~(1ULL << channel); 2587 *mask &= ~(1 << index); 2588 regs = OHCI1394_IsoRcvContextBase(index); 2589 ctx = &ohci->ir_context_list[index]; 2590 } 2591 break; 2592 2593 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2594 mask = &ohci->ir_context_mask; 2595 callback = handle_ir_buffer_fill; 2596 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1; 2597 if (index >= 0) { 2598 ohci->mc_allocated = true; 2599 *mask &= ~(1 << index); 2600 regs = OHCI1394_IsoRcvContextBase(index); 2601 ctx = &ohci->ir_context_list[index]; 2602 } 2603 break; 2604 2605 default: 2606 index = -1; 2607 ret = -ENOSYS; 2608 } 2609 2610 spin_unlock_irqrestore(&ohci->lock, flags); 2611 2612 if (index < 0) 2613 return ERR_PTR(ret); 2614 2615 memset(ctx, 0, sizeof(*ctx)); 2616 ctx->header_length = 0; 2617 ctx->header = (void *) __get_free_page(GFP_KERNEL); 2618 if (ctx->header == NULL) { 2619 ret = -ENOMEM; 2620 goto out; 2621 } 2622 ret = context_init(&ctx->context, ohci, regs, callback); 2623 if (ret < 0) 2624 goto out_with_header; 2625 2626 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) 2627 set_multichannel_mask(ohci, 0); 2628 2629 return &ctx->base; 2630 2631 out_with_header: 2632 free_page((unsigned long)ctx->header); 2633 out: 2634 spin_lock_irqsave(&ohci->lock, flags); 2635 2636 switch (type) { 2637 case FW_ISO_CONTEXT_RECEIVE: 2638 *channels |= 1ULL << channel; 2639 break; 2640 2641 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2642 ohci->mc_allocated = false; 2643 break; 2644 } 2645 *mask |= 1 << index; 2646 2647 spin_unlock_irqrestore(&ohci->lock, flags); 2648 2649 return ERR_PTR(ret); 2650 } 2651 2652 static int ohci_start_iso(struct fw_iso_context *base, 2653 s32 cycle, u32 sync, u32 tags) 2654 { 2655 struct iso_context *ctx = container_of(base, struct iso_context, base); 2656 struct fw_ohci *ohci = ctx->context.ohci; 2657 u32 control = IR_CONTEXT_ISOCH_HEADER, match; 2658 int index; 2659 2660 switch (ctx->base.type) { 2661 case FW_ISO_CONTEXT_TRANSMIT: 2662 index = ctx - ohci->it_context_list; 2663 match = 0; 2664 if (cycle >= 0) 2665 match = IT_CONTEXT_CYCLE_MATCH_ENABLE | 2666 (cycle & 0x7fff) << 16; 2667 2668 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); 2669 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); 2670 context_run(&ctx->context, match); 2671 break; 2672 2673 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2674 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE; 2675 /* fall through */ 2676 case FW_ISO_CONTEXT_RECEIVE: 2677 index = ctx - ohci->ir_context_list; 2678 match = (tags << 28) | (sync << 8) | ctx->base.channel; 2679 if (cycle >= 0) { 2680 match |= (cycle & 0x07fff) << 12; 2681 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE; 2682 } 2683 2684 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); 2685 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); 2686 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match); 2687 context_run(&ctx->context, control); 2688 2689 ctx->sync = sync; 2690 ctx->tags = tags; 2691 2692 break; 2693 } 2694 2695 return 0; 2696 } 2697 2698 static int ohci_stop_iso(struct fw_iso_context *base) 2699 { 2700 struct fw_ohci *ohci = fw_ohci(base->card); 2701 struct iso_context *ctx = container_of(base, struct iso_context, base); 2702 int index; 2703 2704 switch (ctx->base.type) { 2705 case FW_ISO_CONTEXT_TRANSMIT: 2706 index = ctx - ohci->it_context_list; 2707 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); 2708 break; 2709 2710 case FW_ISO_CONTEXT_RECEIVE: 2711 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2712 index = ctx - ohci->ir_context_list; 2713 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); 2714 break; 2715 } 2716 flush_writes(ohci); 2717 context_stop(&ctx->context); 2718 2719 return 0; 2720 } 2721 2722 static void ohci_free_iso_context(struct fw_iso_context *base) 2723 { 2724 struct fw_ohci *ohci = fw_ohci(base->card); 2725 struct iso_context *ctx = container_of(base, struct iso_context, base); 2726 unsigned long flags; 2727 int index; 2728 2729 ohci_stop_iso(base); 2730 context_release(&ctx->context); 2731 free_page((unsigned long)ctx->header); 2732 2733 spin_lock_irqsave(&ohci->lock, flags); 2734 2735 switch (base->type) { 2736 case FW_ISO_CONTEXT_TRANSMIT: 2737 index = ctx - ohci->it_context_list; 2738 ohci->it_context_mask |= 1 << index; 2739 break; 2740 2741 case FW_ISO_CONTEXT_RECEIVE: 2742 index = ctx - ohci->ir_context_list; 2743 ohci->ir_context_mask |= 1 << index; 2744 ohci->ir_context_channels |= 1ULL << base->channel; 2745 break; 2746 2747 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2748 index = ctx - ohci->ir_context_list; 2749 ohci->ir_context_mask |= 1 << index; 2750 ohci->ir_context_channels |= ohci->mc_channels; 2751 ohci->mc_channels = 0; 2752 ohci->mc_allocated = false; 2753 break; 2754 } 2755 2756 spin_unlock_irqrestore(&ohci->lock, flags); 2757 } 2758 2759 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels) 2760 { 2761 struct fw_ohci *ohci = fw_ohci(base->card); 2762 unsigned long flags; 2763 int ret; 2764 2765 switch (base->type) { 2766 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2767 2768 spin_lock_irqsave(&ohci->lock, flags); 2769 2770 /* Don't allow multichannel to grab other contexts' channels. */ 2771 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) { 2772 *channels = ohci->ir_context_channels; 2773 ret = -EBUSY; 2774 } else { 2775 set_multichannel_mask(ohci, *channels); 2776 ret = 0; 2777 } 2778 2779 spin_unlock_irqrestore(&ohci->lock, flags); 2780 2781 break; 2782 default: 2783 ret = -EINVAL; 2784 } 2785 2786 return ret; 2787 } 2788 2789 #ifdef CONFIG_PM 2790 static void ohci_resume_iso_dma(struct fw_ohci *ohci) 2791 { 2792 int i; 2793 struct iso_context *ctx; 2794 2795 for (i = 0 ; i < ohci->n_ir ; i++) { 2796 ctx = &ohci->ir_context_list[i]; 2797 if (ctx->context.running) 2798 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 2799 } 2800 2801 for (i = 0 ; i < ohci->n_it ; i++) { 2802 ctx = &ohci->it_context_list[i]; 2803 if (ctx->context.running) 2804 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 2805 } 2806 } 2807 #endif 2808 2809 static int queue_iso_transmit(struct iso_context *ctx, 2810 struct fw_iso_packet *packet, 2811 struct fw_iso_buffer *buffer, 2812 unsigned long payload) 2813 { 2814 struct descriptor *d, *last, *pd; 2815 struct fw_iso_packet *p; 2816 __le32 *header; 2817 dma_addr_t d_bus, page_bus; 2818 u32 z, header_z, payload_z, irq; 2819 u32 payload_index, payload_end_index, next_page_index; 2820 int page, end_page, i, length, offset; 2821 2822 p = packet; 2823 payload_index = payload; 2824 2825 if (p->skip) 2826 z = 1; 2827 else 2828 z = 2; 2829 if (p->header_length > 0) 2830 z++; 2831 2832 /* Determine the first page the payload isn't contained in. */ 2833 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; 2834 if (p->payload_length > 0) 2835 payload_z = end_page - (payload_index >> PAGE_SHIFT); 2836 else 2837 payload_z = 0; 2838 2839 z += payload_z; 2840 2841 /* Get header size in number of descriptors. */ 2842 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d)); 2843 2844 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); 2845 if (d == NULL) 2846 return -ENOMEM; 2847 2848 if (!p->skip) { 2849 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 2850 d[0].req_count = cpu_to_le16(8); 2851 /* 2852 * Link the skip address to this descriptor itself. This causes 2853 * a context to skip a cycle whenever lost cycles or FIFO 2854 * overruns occur, without dropping the data. The application 2855 * should then decide whether this is an error condition or not. 2856 * FIXME: Make the context's cycle-lost behaviour configurable? 2857 */ 2858 d[0].branch_address = cpu_to_le32(d_bus | z); 2859 2860 header = (__le32 *) &d[1]; 2861 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) | 2862 IT_HEADER_TAG(p->tag) | 2863 IT_HEADER_TCODE(TCODE_STREAM_DATA) | 2864 IT_HEADER_CHANNEL(ctx->base.channel) | 2865 IT_HEADER_SPEED(ctx->base.speed)); 2866 header[1] = 2867 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length + 2868 p->payload_length)); 2869 } 2870 2871 if (p->header_length > 0) { 2872 d[2].req_count = cpu_to_le16(p->header_length); 2873 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d)); 2874 memcpy(&d[z], p->header, p->header_length); 2875 } 2876 2877 pd = d + z - payload_z; 2878 payload_end_index = payload_index + p->payload_length; 2879 for (i = 0; i < payload_z; i++) { 2880 page = payload_index >> PAGE_SHIFT; 2881 offset = payload_index & ~PAGE_MASK; 2882 next_page_index = (page + 1) << PAGE_SHIFT; 2883 length = 2884 min(next_page_index, payload_end_index) - payload_index; 2885 pd[i].req_count = cpu_to_le16(length); 2886 2887 page_bus = page_private(buffer->pages[page]); 2888 pd[i].data_address = cpu_to_le32(page_bus + offset); 2889 2890 payload_index += length; 2891 } 2892 2893 if (p->interrupt) 2894 irq = DESCRIPTOR_IRQ_ALWAYS; 2895 else 2896 irq = DESCRIPTOR_NO_IRQ; 2897 2898 last = z == 2 ? d : d + z - 1; 2899 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 2900 DESCRIPTOR_STATUS | 2901 DESCRIPTOR_BRANCH_ALWAYS | 2902 irq); 2903 2904 context_append(&ctx->context, d, z, header_z); 2905 2906 return 0; 2907 } 2908 2909 static int queue_iso_packet_per_buffer(struct iso_context *ctx, 2910 struct fw_iso_packet *packet, 2911 struct fw_iso_buffer *buffer, 2912 unsigned long payload) 2913 { 2914 struct descriptor *d, *pd; 2915 dma_addr_t d_bus, page_bus; 2916 u32 z, header_z, rest; 2917 int i, j, length; 2918 int page, offset, packet_count, header_size, payload_per_buffer; 2919 2920 /* 2921 * The OHCI controller puts the isochronous header and trailer in the 2922 * buffer, so we need at least 8 bytes. 2923 */ 2924 packet_count = packet->header_length / ctx->base.header_size; 2925 header_size = max(ctx->base.header_size, (size_t)8); 2926 2927 /* Get header size in number of descriptors. */ 2928 header_z = DIV_ROUND_UP(header_size, sizeof(*d)); 2929 page = payload >> PAGE_SHIFT; 2930 offset = payload & ~PAGE_MASK; 2931 payload_per_buffer = packet->payload_length / packet_count; 2932 2933 for (i = 0; i < packet_count; i++) { 2934 /* d points to the header descriptor */ 2935 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1; 2936 d = context_get_descriptors(&ctx->context, 2937 z + header_z, &d_bus); 2938 if (d == NULL) 2939 return -ENOMEM; 2940 2941 d->control = cpu_to_le16(DESCRIPTOR_STATUS | 2942 DESCRIPTOR_INPUT_MORE); 2943 if (packet->skip && i == 0) 2944 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 2945 d->req_count = cpu_to_le16(header_size); 2946 d->res_count = d->req_count; 2947 d->transfer_status = 0; 2948 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d))); 2949 2950 rest = payload_per_buffer; 2951 pd = d; 2952 for (j = 1; j < z; j++) { 2953 pd++; 2954 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 2955 DESCRIPTOR_INPUT_MORE); 2956 2957 if (offset + rest < PAGE_SIZE) 2958 length = rest; 2959 else 2960 length = PAGE_SIZE - offset; 2961 pd->req_count = cpu_to_le16(length); 2962 pd->res_count = pd->req_count; 2963 pd->transfer_status = 0; 2964 2965 page_bus = page_private(buffer->pages[page]); 2966 pd->data_address = cpu_to_le32(page_bus + offset); 2967 2968 offset = (offset + length) & ~PAGE_MASK; 2969 rest -= length; 2970 if (offset == 0) 2971 page++; 2972 } 2973 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 2974 DESCRIPTOR_INPUT_LAST | 2975 DESCRIPTOR_BRANCH_ALWAYS); 2976 if (packet->interrupt && i == packet_count - 1) 2977 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 2978 2979 context_append(&ctx->context, d, z, header_z); 2980 } 2981 2982 return 0; 2983 } 2984 2985 static int queue_iso_buffer_fill(struct iso_context *ctx, 2986 struct fw_iso_packet *packet, 2987 struct fw_iso_buffer *buffer, 2988 unsigned long payload) 2989 { 2990 struct descriptor *d; 2991 dma_addr_t d_bus, page_bus; 2992 int page, offset, rest, z, i, length; 2993 2994 page = payload >> PAGE_SHIFT; 2995 offset = payload & ~PAGE_MASK; 2996 rest = packet->payload_length; 2997 2998 /* We need one descriptor for each page in the buffer. */ 2999 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE); 3000 3001 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count)) 3002 return -EFAULT; 3003 3004 for (i = 0; i < z; i++) { 3005 d = context_get_descriptors(&ctx->context, 1, &d_bus); 3006 if (d == NULL) 3007 return -ENOMEM; 3008 3009 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 3010 DESCRIPTOR_BRANCH_ALWAYS); 3011 if (packet->skip && i == 0) 3012 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3013 if (packet->interrupt && i == z - 1) 3014 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3015 3016 if (offset + rest < PAGE_SIZE) 3017 length = rest; 3018 else 3019 length = PAGE_SIZE - offset; 3020 d->req_count = cpu_to_le16(length); 3021 d->res_count = d->req_count; 3022 d->transfer_status = 0; 3023 3024 page_bus = page_private(buffer->pages[page]); 3025 d->data_address = cpu_to_le32(page_bus + offset); 3026 3027 rest -= length; 3028 offset = 0; 3029 page++; 3030 3031 context_append(&ctx->context, d, 1, 0); 3032 } 3033 3034 return 0; 3035 } 3036 3037 static int ohci_queue_iso(struct fw_iso_context *base, 3038 struct fw_iso_packet *packet, 3039 struct fw_iso_buffer *buffer, 3040 unsigned long payload) 3041 { 3042 struct iso_context *ctx = container_of(base, struct iso_context, base); 3043 unsigned long flags; 3044 int ret = -ENOSYS; 3045 3046 spin_lock_irqsave(&ctx->context.ohci->lock, flags); 3047 switch (base->type) { 3048 case FW_ISO_CONTEXT_TRANSMIT: 3049 ret = queue_iso_transmit(ctx, packet, buffer, payload); 3050 break; 3051 case FW_ISO_CONTEXT_RECEIVE: 3052 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload); 3053 break; 3054 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3055 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload); 3056 break; 3057 } 3058 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags); 3059 3060 return ret; 3061 } 3062 3063 static const struct fw_card_driver ohci_driver = { 3064 .enable = ohci_enable, 3065 .read_phy_reg = ohci_read_phy_reg, 3066 .update_phy_reg = ohci_update_phy_reg, 3067 .set_config_rom = ohci_set_config_rom, 3068 .send_request = ohci_send_request, 3069 .send_response = ohci_send_response, 3070 .cancel_packet = ohci_cancel_packet, 3071 .enable_phys_dma = ohci_enable_phys_dma, 3072 .read_csr = ohci_read_csr, 3073 .write_csr = ohci_write_csr, 3074 3075 .allocate_iso_context = ohci_allocate_iso_context, 3076 .free_iso_context = ohci_free_iso_context, 3077 .set_iso_channels = ohci_set_iso_channels, 3078 .queue_iso = ohci_queue_iso, 3079 .start_iso = ohci_start_iso, 3080 .stop_iso = ohci_stop_iso, 3081 }; 3082 3083 #ifdef CONFIG_PPC_PMAC 3084 static void pmac_ohci_on(struct pci_dev *dev) 3085 { 3086 if (machine_is(powermac)) { 3087 struct device_node *ofn = pci_device_to_OF_node(dev); 3088 3089 if (ofn) { 3090 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1); 3091 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1); 3092 } 3093 } 3094 } 3095 3096 static void pmac_ohci_off(struct pci_dev *dev) 3097 { 3098 if (machine_is(powermac)) { 3099 struct device_node *ofn = pci_device_to_OF_node(dev); 3100 3101 if (ofn) { 3102 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0); 3103 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0); 3104 } 3105 } 3106 } 3107 #else 3108 static inline void pmac_ohci_on(struct pci_dev *dev) {} 3109 static inline void pmac_ohci_off(struct pci_dev *dev) {} 3110 #endif /* CONFIG_PPC_PMAC */ 3111 3112 static int __devinit pci_probe(struct pci_dev *dev, 3113 const struct pci_device_id *ent) 3114 { 3115 struct fw_ohci *ohci; 3116 u32 bus_options, max_receive, link_speed, version; 3117 u64 guid; 3118 int i, err; 3119 size_t size; 3120 3121 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL); 3122 if (ohci == NULL) { 3123 err = -ENOMEM; 3124 goto fail; 3125 } 3126 3127 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); 3128 3129 pmac_ohci_on(dev); 3130 3131 err = pci_enable_device(dev); 3132 if (err) { 3133 fw_error("Failed to enable OHCI hardware\n"); 3134 goto fail_free; 3135 } 3136 3137 pci_set_master(dev); 3138 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); 3139 pci_set_drvdata(dev, ohci); 3140 3141 spin_lock_init(&ohci->lock); 3142 mutex_init(&ohci->phy_reg_mutex); 3143 3144 tasklet_init(&ohci->bus_reset_tasklet, 3145 bus_reset_tasklet, (unsigned long)ohci); 3146 3147 err = pci_request_region(dev, 0, ohci_driver_name); 3148 if (err) { 3149 fw_error("MMIO resource unavailable\n"); 3150 goto fail_disable; 3151 } 3152 3153 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE); 3154 if (ohci->registers == NULL) { 3155 fw_error("Failed to remap registers\n"); 3156 err = -ENXIO; 3157 goto fail_iomem; 3158 } 3159 3160 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++) 3161 if ((ohci_quirks[i].vendor == dev->vendor) && 3162 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID || 3163 ohci_quirks[i].device == dev->device) && 3164 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID || 3165 ohci_quirks[i].revision >= dev->revision)) { 3166 ohci->quirks = ohci_quirks[i].flags; 3167 break; 3168 } 3169 if (param_quirks) 3170 ohci->quirks = param_quirks; 3171 3172 /* 3173 * Because dma_alloc_coherent() allocates at least one page, 3174 * we save space by using a common buffer for the AR request/ 3175 * response descriptors and the self IDs buffer. 3176 */ 3177 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4); 3178 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2); 3179 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device, 3180 PAGE_SIZE, 3181 &ohci->misc_buffer_bus, 3182 GFP_KERNEL); 3183 if (!ohci->misc_buffer) { 3184 err = -ENOMEM; 3185 goto fail_iounmap; 3186 } 3187 3188 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0, 3189 OHCI1394_AsReqRcvContextControlSet); 3190 if (err < 0) 3191 goto fail_misc_buf; 3192 3193 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4, 3194 OHCI1394_AsRspRcvContextControlSet); 3195 if (err < 0) 3196 goto fail_arreq_ctx; 3197 3198 err = context_init(&ohci->at_request_ctx, ohci, 3199 OHCI1394_AsReqTrContextControlSet, handle_at_packet); 3200 if (err < 0) 3201 goto fail_arrsp_ctx; 3202 3203 err = context_init(&ohci->at_response_ctx, ohci, 3204 OHCI1394_AsRspTrContextControlSet, handle_at_packet); 3205 if (err < 0) 3206 goto fail_atreq_ctx; 3207 3208 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); 3209 ohci->ir_context_channels = ~0ULL; 3210 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); 3211 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); 3212 ohci->n_ir = hweight32(ohci->ir_context_mask); 3213 size = sizeof(struct iso_context) * ohci->n_ir; 3214 ohci->ir_context_list = kzalloc(size, GFP_KERNEL); 3215 3216 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); 3217 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); 3218 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); 3219 ohci->n_it = hweight32(ohci->it_context_mask); 3220 size = sizeof(struct iso_context) * ohci->n_it; 3221 ohci->it_context_list = kzalloc(size, GFP_KERNEL); 3222 3223 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) { 3224 err = -ENOMEM; 3225 goto fail_contexts; 3226 } 3227 3228 ohci->self_id_cpu = ohci->misc_buffer + PAGE_SIZE/2; 3229 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2; 3230 3231 bus_options = reg_read(ohci, OHCI1394_BusOptions); 3232 max_receive = (bus_options >> 12) & 0xf; 3233 link_speed = bus_options & 0x7; 3234 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | 3235 reg_read(ohci, OHCI1394_GUIDLo); 3236 3237 err = fw_card_add(&ohci->card, max_receive, link_speed, guid); 3238 if (err) 3239 goto fail_contexts; 3240 3241 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 3242 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, " 3243 "%d IR + %d IT contexts, quirks 0x%x\n", 3244 dev_name(&dev->dev), version >> 16, version & 0xff, 3245 ohci->n_ir, ohci->n_it, ohci->quirks); 3246 3247 return 0; 3248 3249 fail_contexts: 3250 kfree(ohci->ir_context_list); 3251 kfree(ohci->it_context_list); 3252 context_release(&ohci->at_response_ctx); 3253 fail_atreq_ctx: 3254 context_release(&ohci->at_request_ctx); 3255 fail_arrsp_ctx: 3256 ar_context_release(&ohci->ar_response_ctx); 3257 fail_arreq_ctx: 3258 ar_context_release(&ohci->ar_request_ctx); 3259 fail_misc_buf: 3260 dma_free_coherent(ohci->card.device, PAGE_SIZE, 3261 ohci->misc_buffer, ohci->misc_buffer_bus); 3262 fail_iounmap: 3263 pci_iounmap(dev, ohci->registers); 3264 fail_iomem: 3265 pci_release_region(dev, 0); 3266 fail_disable: 3267 pci_disable_device(dev); 3268 fail_free: 3269 kfree(&ohci->card); 3270 pmac_ohci_off(dev); 3271 fail: 3272 if (err == -ENOMEM) 3273 fw_error("Out of memory\n"); 3274 3275 return err; 3276 } 3277 3278 static void pci_remove(struct pci_dev *dev) 3279 { 3280 struct fw_ohci *ohci; 3281 3282 ohci = pci_get_drvdata(dev); 3283 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 3284 flush_writes(ohci); 3285 fw_core_remove_card(&ohci->card); 3286 3287 /* 3288 * FIXME: Fail all pending packets here, now that the upper 3289 * layers can't queue any more. 3290 */ 3291 3292 software_reset(ohci); 3293 free_irq(dev->irq, ohci); 3294 3295 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom) 3296 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 3297 ohci->next_config_rom, ohci->next_config_rom_bus); 3298 if (ohci->config_rom) 3299 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 3300 ohci->config_rom, ohci->config_rom_bus); 3301 ar_context_release(&ohci->ar_request_ctx); 3302 ar_context_release(&ohci->ar_response_ctx); 3303 dma_free_coherent(ohci->card.device, PAGE_SIZE, 3304 ohci->misc_buffer, ohci->misc_buffer_bus); 3305 context_release(&ohci->at_request_ctx); 3306 context_release(&ohci->at_response_ctx); 3307 kfree(ohci->it_context_list); 3308 kfree(ohci->ir_context_list); 3309 pci_disable_msi(dev); 3310 pci_iounmap(dev, ohci->registers); 3311 pci_release_region(dev, 0); 3312 pci_disable_device(dev); 3313 kfree(&ohci->card); 3314 pmac_ohci_off(dev); 3315 3316 fw_notify("Removed fw-ohci device.\n"); 3317 } 3318 3319 #ifdef CONFIG_PM 3320 static int pci_suspend(struct pci_dev *dev, pm_message_t state) 3321 { 3322 struct fw_ohci *ohci = pci_get_drvdata(dev); 3323 int err; 3324 3325 software_reset(ohci); 3326 free_irq(dev->irq, ohci); 3327 pci_disable_msi(dev); 3328 err = pci_save_state(dev); 3329 if (err) { 3330 fw_error("pci_save_state failed\n"); 3331 return err; 3332 } 3333 err = pci_set_power_state(dev, pci_choose_state(dev, state)); 3334 if (err) 3335 fw_error("pci_set_power_state failed with %d\n", err); 3336 pmac_ohci_off(dev); 3337 3338 return 0; 3339 } 3340 3341 static int pci_resume(struct pci_dev *dev) 3342 { 3343 struct fw_ohci *ohci = pci_get_drvdata(dev); 3344 int err; 3345 3346 pmac_ohci_on(dev); 3347 pci_set_power_state(dev, PCI_D0); 3348 pci_restore_state(dev); 3349 err = pci_enable_device(dev); 3350 if (err) { 3351 fw_error("pci_enable_device failed\n"); 3352 return err; 3353 } 3354 3355 /* Some systems don't setup GUID register on resume from ram */ 3356 if (!reg_read(ohci, OHCI1394_GUIDLo) && 3357 !reg_read(ohci, OHCI1394_GUIDHi)) { 3358 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid); 3359 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32)); 3360 } 3361 3362 err = ohci_enable(&ohci->card, NULL, 0); 3363 if (err) 3364 return err; 3365 3366 ohci_resume_iso_dma(ohci); 3367 3368 return 0; 3369 } 3370 #endif 3371 3372 static const struct pci_device_id pci_table[] = { 3373 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, 3374 { } 3375 }; 3376 3377 MODULE_DEVICE_TABLE(pci, pci_table); 3378 3379 static struct pci_driver fw_ohci_pci_driver = { 3380 .name = ohci_driver_name, 3381 .id_table = pci_table, 3382 .probe = pci_probe, 3383 .remove = pci_remove, 3384 #ifdef CONFIG_PM 3385 .resume = pci_resume, 3386 .suspend = pci_suspend, 3387 #endif 3388 }; 3389 3390 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); 3391 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); 3392 MODULE_LICENSE("GPL"); 3393 3394 /* Provide a module alias so root-on-sbp2 initrds don't break. */ 3395 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE 3396 MODULE_ALIAS("ohci1394"); 3397 #endif 3398 3399 static int __init fw_ohci_init(void) 3400 { 3401 return pci_register_driver(&fw_ohci_pci_driver); 3402 } 3403 3404 static void __exit fw_ohci_cleanup(void) 3405 { 3406 pci_unregister_driver(&fw_ohci_pci_driver); 3407 } 3408 3409 module_init(fw_ohci_init); 3410 module_exit(fw_ohci_cleanup); 3411