1 /* 2 * Driver for OHCI 1394 controllers 3 * 4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software Foundation, 18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 */ 20 21 #include <linux/bitops.h> 22 #include <linux/bug.h> 23 #include <linux/compiler.h> 24 #include <linux/delay.h> 25 #include <linux/device.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/firewire.h> 28 #include <linux/firewire-constants.h> 29 #include <linux/init.h> 30 #include <linux/interrupt.h> 31 #include <linux/io.h> 32 #include <linux/kernel.h> 33 #include <linux/list.h> 34 #include <linux/mm.h> 35 #include <linux/module.h> 36 #include <linux/moduleparam.h> 37 #include <linux/mutex.h> 38 #include <linux/pci.h> 39 #include <linux/pci_ids.h> 40 #include <linux/slab.h> 41 #include <linux/spinlock.h> 42 #include <linux/string.h> 43 #include <linux/time.h> 44 #include <linux/vmalloc.h> 45 #include <linux/workqueue.h> 46 47 #include <asm/byteorder.h> 48 #include <asm/page.h> 49 50 #ifdef CONFIG_PPC_PMAC 51 #include <asm/pmac_feature.h> 52 #endif 53 54 #include "core.h" 55 #include "ohci.h" 56 57 #define ohci_info(ohci, f, args...) dev_info(ohci->card.device, f, ##args) 58 #define ohci_notice(ohci, f, args...) dev_notice(ohci->card.device, f, ##args) 59 #define ohci_err(ohci, f, args...) dev_err(ohci->card.device, f, ##args) 60 61 #define DESCRIPTOR_OUTPUT_MORE 0 62 #define DESCRIPTOR_OUTPUT_LAST (1 << 12) 63 #define DESCRIPTOR_INPUT_MORE (2 << 12) 64 #define DESCRIPTOR_INPUT_LAST (3 << 12) 65 #define DESCRIPTOR_STATUS (1 << 11) 66 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8) 67 #define DESCRIPTOR_PING (1 << 7) 68 #define DESCRIPTOR_YY (1 << 6) 69 #define DESCRIPTOR_NO_IRQ (0 << 4) 70 #define DESCRIPTOR_IRQ_ERROR (1 << 4) 71 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4) 72 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2) 73 #define DESCRIPTOR_WAIT (3 << 0) 74 75 #define DESCRIPTOR_CMD (0xf << 12) 76 77 struct descriptor { 78 __le16 req_count; 79 __le16 control; 80 __le32 data_address; 81 __le32 branch_address; 82 __le16 res_count; 83 __le16 transfer_status; 84 } __attribute__((aligned(16))); 85 86 #define CONTROL_SET(regs) (regs) 87 #define CONTROL_CLEAR(regs) ((regs) + 4) 88 #define COMMAND_PTR(regs) ((regs) + 12) 89 #define CONTEXT_MATCH(regs) ((regs) + 16) 90 91 #define AR_BUFFER_SIZE (32*1024) 92 #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE) 93 /* we need at least two pages for proper list management */ 94 #define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2) 95 96 #define MAX_ASYNC_PAYLOAD 4096 97 #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4) 98 #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE) 99 100 struct ar_context { 101 struct fw_ohci *ohci; 102 struct page *pages[AR_BUFFERS]; 103 void *buffer; 104 struct descriptor *descriptors; 105 dma_addr_t descriptors_bus; 106 void *pointer; 107 unsigned int last_buffer_index; 108 u32 regs; 109 struct tasklet_struct tasklet; 110 }; 111 112 struct context; 113 114 typedef int (*descriptor_callback_t)(struct context *ctx, 115 struct descriptor *d, 116 struct descriptor *last); 117 118 /* 119 * A buffer that contains a block of DMA-able coherent memory used for 120 * storing a portion of a DMA descriptor program. 121 */ 122 struct descriptor_buffer { 123 struct list_head list; 124 dma_addr_t buffer_bus; 125 size_t buffer_size; 126 size_t used; 127 struct descriptor buffer[0]; 128 }; 129 130 struct context { 131 struct fw_ohci *ohci; 132 u32 regs; 133 int total_allocation; 134 u32 current_bus; 135 bool running; 136 bool flushing; 137 138 /* 139 * List of page-sized buffers for storing DMA descriptors. 140 * Head of list contains buffers in use and tail of list contains 141 * free buffers. 142 */ 143 struct list_head buffer_list; 144 145 /* 146 * Pointer to a buffer inside buffer_list that contains the tail 147 * end of the current DMA program. 148 */ 149 struct descriptor_buffer *buffer_tail; 150 151 /* 152 * The descriptor containing the branch address of the first 153 * descriptor that has not yet been filled by the device. 154 */ 155 struct descriptor *last; 156 157 /* 158 * The last descriptor block in the DMA program. It contains the branch 159 * address that must be updated upon appending a new descriptor. 160 */ 161 struct descriptor *prev; 162 int prev_z; 163 164 descriptor_callback_t callback; 165 166 struct tasklet_struct tasklet; 167 }; 168 169 #define IT_HEADER_SY(v) ((v) << 0) 170 #define IT_HEADER_TCODE(v) ((v) << 4) 171 #define IT_HEADER_CHANNEL(v) ((v) << 8) 172 #define IT_HEADER_TAG(v) ((v) << 14) 173 #define IT_HEADER_SPEED(v) ((v) << 16) 174 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16) 175 176 struct iso_context { 177 struct fw_iso_context base; 178 struct context context; 179 void *header; 180 size_t header_length; 181 unsigned long flushing_completions; 182 u32 mc_buffer_bus; 183 u16 mc_completed; 184 u16 last_timestamp; 185 u8 sync; 186 u8 tags; 187 }; 188 189 #define CONFIG_ROM_SIZE 1024 190 191 struct fw_ohci { 192 struct fw_card card; 193 194 __iomem char *registers; 195 int node_id; 196 int generation; 197 int request_generation; /* for timestamping incoming requests */ 198 unsigned quirks; 199 unsigned int pri_req_max; 200 u32 bus_time; 201 bool bus_time_running; 202 bool is_root; 203 bool csr_state_setclear_abdicate; 204 int n_ir; 205 int n_it; 206 /* 207 * Spinlock for accessing fw_ohci data. Never call out of 208 * this driver with this lock held. 209 */ 210 spinlock_t lock; 211 212 struct mutex phy_reg_mutex; 213 214 void *misc_buffer; 215 dma_addr_t misc_buffer_bus; 216 217 struct ar_context ar_request_ctx; 218 struct ar_context ar_response_ctx; 219 struct context at_request_ctx; 220 struct context at_response_ctx; 221 222 u32 it_context_support; 223 u32 it_context_mask; /* unoccupied IT contexts */ 224 struct iso_context *it_context_list; 225 u64 ir_context_channels; /* unoccupied channels */ 226 u32 ir_context_support; 227 u32 ir_context_mask; /* unoccupied IR contexts */ 228 struct iso_context *ir_context_list; 229 u64 mc_channels; /* channels in use by the multichannel IR context */ 230 bool mc_allocated; 231 232 __be32 *config_rom; 233 dma_addr_t config_rom_bus; 234 __be32 *next_config_rom; 235 dma_addr_t next_config_rom_bus; 236 __be32 next_header; 237 238 __le32 *self_id; 239 dma_addr_t self_id_bus; 240 struct work_struct bus_reset_work; 241 242 u32 self_id_buffer[512]; 243 }; 244 245 static struct workqueue_struct *selfid_workqueue; 246 247 static inline struct fw_ohci *fw_ohci(struct fw_card *card) 248 { 249 return container_of(card, struct fw_ohci, card); 250 } 251 252 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 253 #define IR_CONTEXT_BUFFER_FILL 0x80000000 254 #define IR_CONTEXT_ISOCH_HEADER 0x40000000 255 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 256 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 257 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 258 259 #define CONTEXT_RUN 0x8000 260 #define CONTEXT_WAKE 0x1000 261 #define CONTEXT_DEAD 0x0800 262 #define CONTEXT_ACTIVE 0x0400 263 264 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf 265 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 266 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 267 268 #define OHCI1394_REGISTER_SIZE 0x800 269 #define OHCI1394_PCI_HCI_Control 0x40 270 #define SELF_ID_BUF_SIZE 0x800 271 #define OHCI_TCODE_PHY_PACKET 0x0e 272 #define OHCI_VERSION_1_1 0x010010 273 274 static char ohci_driver_name[] = KBUILD_MODNAME; 275 276 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd 277 #define PCI_DEVICE_ID_AGERE_FW643 0x5901 278 #define PCI_DEVICE_ID_CREATIVE_SB1394 0x4001 279 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380 280 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009 281 #define PCI_DEVICE_ID_TI_TSB12LV26 0x8020 282 #define PCI_DEVICE_ID_TI_TSB82AA2 0x8025 283 #define PCI_DEVICE_ID_VIA_VT630X 0x3044 284 #define PCI_REV_ID_VIA_VT6306 0x46 285 286 #define QUIRK_CYCLE_TIMER 0x1 287 #define QUIRK_RESET_PACKET 0x2 288 #define QUIRK_BE_HEADERS 0x4 289 #define QUIRK_NO_1394A 0x8 290 #define QUIRK_NO_MSI 0x10 291 #define QUIRK_TI_SLLZ059 0x20 292 #define QUIRK_IR_WAKE 0x40 293 #define QUIRK_PHY_LCTRL_TIMEOUT 0x80 294 295 /* In case of multiple matches in ohci_quirks[], only the first one is used. */ 296 static const struct { 297 unsigned short vendor, device, revision, flags; 298 } ohci_quirks[] = { 299 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID, 300 QUIRK_CYCLE_TIMER}, 301 302 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID, 303 QUIRK_BE_HEADERS}, 304 305 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6, 306 QUIRK_PHY_LCTRL_TIMEOUT | QUIRK_NO_MSI}, 307 308 {PCI_VENDOR_ID_ATT, PCI_ANY_ID, PCI_ANY_ID, 309 QUIRK_PHY_LCTRL_TIMEOUT}, 310 311 {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID, 312 QUIRK_RESET_PACKET}, 313 314 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID, 315 QUIRK_NO_MSI}, 316 317 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID, 318 QUIRK_CYCLE_TIMER}, 319 320 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID, 321 QUIRK_NO_MSI}, 322 323 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID, 324 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, 325 326 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID, 327 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A}, 328 329 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID, 330 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059}, 331 332 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID, 333 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059}, 334 335 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID, 336 QUIRK_RESET_PACKET}, 337 338 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306, 339 QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE}, 340 341 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID, 342 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, 343 }; 344 345 /* This overrides anything that was found in ohci_quirks[]. */ 346 static int param_quirks; 347 module_param_named(quirks, param_quirks, int, 0644); 348 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0" 349 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER) 350 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET) 351 ", AR/selfID endianness = " __stringify(QUIRK_BE_HEADERS) 352 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A) 353 ", disable MSI = " __stringify(QUIRK_NO_MSI) 354 ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059) 355 ", IR wake unreliable = " __stringify(QUIRK_IR_WAKE) 356 ", phy LCtrl timeout = " __stringify(QUIRK_PHY_LCTRL_TIMEOUT) 357 ")"); 358 359 #define OHCI_PARAM_DEBUG_AT_AR 1 360 #define OHCI_PARAM_DEBUG_SELFIDS 2 361 #define OHCI_PARAM_DEBUG_IRQS 4 362 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */ 363 364 static int param_debug; 365 module_param_named(debug, param_debug, int, 0644); 366 MODULE_PARM_DESC(debug, "Verbose logging (default = 0" 367 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR) 368 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS) 369 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS) 370 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS) 371 ", or a combination, or all = -1)"); 372 373 static void log_irqs(struct fw_ohci *ohci, u32 evt) 374 { 375 if (likely(!(param_debug & 376 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS)))) 377 return; 378 379 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) && 380 !(evt & OHCI1394_busReset)) 381 return; 382 383 ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt, 384 evt & OHCI1394_selfIDComplete ? " selfID" : "", 385 evt & OHCI1394_RQPkt ? " AR_req" : "", 386 evt & OHCI1394_RSPkt ? " AR_resp" : "", 387 evt & OHCI1394_reqTxComplete ? " AT_req" : "", 388 evt & OHCI1394_respTxComplete ? " AT_resp" : "", 389 evt & OHCI1394_isochRx ? " IR" : "", 390 evt & OHCI1394_isochTx ? " IT" : "", 391 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", 392 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", 393 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "", 394 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "", 395 evt & OHCI1394_regAccessFail ? " regAccessFail" : "", 396 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "", 397 evt & OHCI1394_busReset ? " busReset" : "", 398 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | 399 OHCI1394_RSPkt | OHCI1394_reqTxComplete | 400 OHCI1394_respTxComplete | OHCI1394_isochRx | 401 OHCI1394_isochTx | OHCI1394_postedWriteErr | 402 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds | 403 OHCI1394_cycleInconsistent | 404 OHCI1394_regAccessFail | OHCI1394_busReset) 405 ? " ?" : ""); 406 } 407 408 static const char *speed[] = { 409 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta", 410 }; 411 static const char *power[] = { 412 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W", 413 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W", 414 }; 415 static const char port[] = { '.', '-', 'p', 'c', }; 416 417 static char _p(u32 *s, int shift) 418 { 419 return port[*s >> shift & 3]; 420 } 421 422 static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count) 423 { 424 u32 *s; 425 426 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) 427 return; 428 429 ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n", 430 self_id_count, generation, ohci->node_id); 431 432 for (s = ohci->self_id_buffer; self_id_count--; ++s) 433 if ((*s & 1 << 23) == 0) 434 ohci_notice(ohci, 435 "selfID 0: %08x, phy %d [%c%c%c] %s gc=%d %s %s%s%s\n", 436 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2), 437 speed[*s >> 14 & 3], *s >> 16 & 63, 438 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", 439 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); 440 else 441 ohci_notice(ohci, 442 "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n", 443 *s, *s >> 24 & 63, 444 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10), 445 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2)); 446 } 447 448 static const char *evts[] = { 449 [0x00] = "evt_no_status", [0x01] = "-reserved-", 450 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack", 451 [0x04] = "evt_underrun", [0x05] = "evt_overrun", 452 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read", 453 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset", 454 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err", 455 [0x0c] = "-reserved-", [0x0d] = "-reserved-", 456 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed", 457 [0x10] = "-reserved-", [0x11] = "ack_complete", 458 [0x12] = "ack_pending ", [0x13] = "-reserved-", 459 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A", 460 [0x16] = "ack_busy_B", [0x17] = "-reserved-", 461 [0x18] = "-reserved-", [0x19] = "-reserved-", 462 [0x1a] = "-reserved-", [0x1b] = "ack_tardy", 463 [0x1c] = "-reserved-", [0x1d] = "ack_data_error", 464 [0x1e] = "ack_type_error", [0x1f] = "-reserved-", 465 [0x20] = "pending/cancelled", 466 }; 467 static const char *tcodes[] = { 468 [0x0] = "QW req", [0x1] = "BW req", 469 [0x2] = "W resp", [0x3] = "-reserved-", 470 [0x4] = "QR req", [0x5] = "BR req", 471 [0x6] = "QR resp", [0x7] = "BR resp", 472 [0x8] = "cycle start", [0x9] = "Lk req", 473 [0xa] = "async stream packet", [0xb] = "Lk resp", 474 [0xc] = "-reserved-", [0xd] = "-reserved-", 475 [0xe] = "link internal", [0xf] = "-reserved-", 476 }; 477 478 static void log_ar_at_event(struct fw_ohci *ohci, 479 char dir, int speed, u32 *header, int evt) 480 { 481 int tcode = header[0] >> 4 & 0xf; 482 char specific[12]; 483 484 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR))) 485 return; 486 487 if (unlikely(evt >= ARRAY_SIZE(evts))) 488 evt = 0x1f; 489 490 if (evt == OHCI1394_evt_bus_reset) { 491 ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n", 492 dir, (header[2] >> 16) & 0xff); 493 return; 494 } 495 496 switch (tcode) { 497 case 0x0: case 0x6: case 0x8: 498 snprintf(specific, sizeof(specific), " = %08x", 499 be32_to_cpu((__force __be32)header[3])); 500 break; 501 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb: 502 snprintf(specific, sizeof(specific), " %x,%x", 503 header[3] >> 16, header[3] & 0xffff); 504 break; 505 default: 506 specific[0] = '\0'; 507 } 508 509 switch (tcode) { 510 case 0xa: 511 ohci_notice(ohci, "A%c %s, %s\n", 512 dir, evts[evt], tcodes[tcode]); 513 break; 514 case 0xe: 515 ohci_notice(ohci, "A%c %s, PHY %08x %08x\n", 516 dir, evts[evt], header[1], header[2]); 517 break; 518 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9: 519 ohci_notice(ohci, 520 "A%c spd %x tl %02x, %04x -> %04x, %s, %s, %04x%08x%s\n", 521 dir, speed, header[0] >> 10 & 0x3f, 522 header[1] >> 16, header[0] >> 16, evts[evt], 523 tcodes[tcode], header[1] & 0xffff, header[2], specific); 524 break; 525 default: 526 ohci_notice(ohci, 527 "A%c spd %x tl %02x, %04x -> %04x, %s, %s%s\n", 528 dir, speed, header[0] >> 10 & 0x3f, 529 header[1] >> 16, header[0] >> 16, evts[evt], 530 tcodes[tcode], specific); 531 } 532 } 533 534 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) 535 { 536 writel(data, ohci->registers + offset); 537 } 538 539 static inline u32 reg_read(const struct fw_ohci *ohci, int offset) 540 { 541 return readl(ohci->registers + offset); 542 } 543 544 static inline void flush_writes(const struct fw_ohci *ohci) 545 { 546 /* Do a dummy read to flush writes. */ 547 reg_read(ohci, OHCI1394_Version); 548 } 549 550 /* 551 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and 552 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex. 553 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg() 554 * directly. Exceptions are intrinsically serialized contexts like pci_probe. 555 */ 556 static int read_phy_reg(struct fw_ohci *ohci, int addr) 557 { 558 u32 val; 559 int i; 560 561 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); 562 for (i = 0; i < 3 + 100; i++) { 563 val = reg_read(ohci, OHCI1394_PhyControl); 564 if (!~val) 565 return -ENODEV; /* Card was ejected. */ 566 567 if (val & OHCI1394_PhyControl_ReadDone) 568 return OHCI1394_PhyControl_ReadData(val); 569 570 /* 571 * Try a few times without waiting. Sleeping is necessary 572 * only when the link/PHY interface is busy. 573 */ 574 if (i >= 3) 575 msleep(1); 576 } 577 ohci_err(ohci, "failed to read phy reg %d\n", addr); 578 dump_stack(); 579 580 return -EBUSY; 581 } 582 583 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val) 584 { 585 int i; 586 587 reg_write(ohci, OHCI1394_PhyControl, 588 OHCI1394_PhyControl_Write(addr, val)); 589 for (i = 0; i < 3 + 100; i++) { 590 val = reg_read(ohci, OHCI1394_PhyControl); 591 if (!~val) 592 return -ENODEV; /* Card was ejected. */ 593 594 if (!(val & OHCI1394_PhyControl_WritePending)) 595 return 0; 596 597 if (i >= 3) 598 msleep(1); 599 } 600 ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val); 601 dump_stack(); 602 603 return -EBUSY; 604 } 605 606 static int update_phy_reg(struct fw_ohci *ohci, int addr, 607 int clear_bits, int set_bits) 608 { 609 int ret = read_phy_reg(ohci, addr); 610 if (ret < 0) 611 return ret; 612 613 /* 614 * The interrupt status bits are cleared by writing a one bit. 615 * Avoid clearing them unless explicitly requested in set_bits. 616 */ 617 if (addr == 5) 618 clear_bits |= PHY_INT_STATUS_BITS; 619 620 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits); 621 } 622 623 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr) 624 { 625 int ret; 626 627 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5); 628 if (ret < 0) 629 return ret; 630 631 return read_phy_reg(ohci, addr); 632 } 633 634 static int ohci_read_phy_reg(struct fw_card *card, int addr) 635 { 636 struct fw_ohci *ohci = fw_ohci(card); 637 int ret; 638 639 mutex_lock(&ohci->phy_reg_mutex); 640 ret = read_phy_reg(ohci, addr); 641 mutex_unlock(&ohci->phy_reg_mutex); 642 643 return ret; 644 } 645 646 static int ohci_update_phy_reg(struct fw_card *card, int addr, 647 int clear_bits, int set_bits) 648 { 649 struct fw_ohci *ohci = fw_ohci(card); 650 int ret; 651 652 mutex_lock(&ohci->phy_reg_mutex); 653 ret = update_phy_reg(ohci, addr, clear_bits, set_bits); 654 mutex_unlock(&ohci->phy_reg_mutex); 655 656 return ret; 657 } 658 659 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i) 660 { 661 return page_private(ctx->pages[i]); 662 } 663 664 static void ar_context_link_page(struct ar_context *ctx, unsigned int index) 665 { 666 struct descriptor *d; 667 668 d = &ctx->descriptors[index]; 669 d->branch_address &= cpu_to_le32(~0xf); 670 d->res_count = cpu_to_le16(PAGE_SIZE); 671 d->transfer_status = 0; 672 673 wmb(); /* finish init of new descriptors before branch_address update */ 674 d = &ctx->descriptors[ctx->last_buffer_index]; 675 d->branch_address |= cpu_to_le32(1); 676 677 ctx->last_buffer_index = index; 678 679 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 680 } 681 682 static void ar_context_release(struct ar_context *ctx) 683 { 684 unsigned int i; 685 686 if (ctx->buffer) 687 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES); 688 689 for (i = 0; i < AR_BUFFERS; i++) 690 if (ctx->pages[i]) { 691 dma_unmap_page(ctx->ohci->card.device, 692 ar_buffer_bus(ctx, i), 693 PAGE_SIZE, DMA_FROM_DEVICE); 694 __free_page(ctx->pages[i]); 695 } 696 } 697 698 static void ar_context_abort(struct ar_context *ctx, const char *error_msg) 699 { 700 struct fw_ohci *ohci = ctx->ohci; 701 702 if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) { 703 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 704 flush_writes(ohci); 705 706 ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg); 707 } 708 /* FIXME: restart? */ 709 } 710 711 static inline unsigned int ar_next_buffer_index(unsigned int index) 712 { 713 return (index + 1) % AR_BUFFERS; 714 } 715 716 static inline unsigned int ar_prev_buffer_index(unsigned int index) 717 { 718 return (index - 1 + AR_BUFFERS) % AR_BUFFERS; 719 } 720 721 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx) 722 { 723 return ar_next_buffer_index(ctx->last_buffer_index); 724 } 725 726 /* 727 * We search for the buffer that contains the last AR packet DMA data written 728 * by the controller. 729 */ 730 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx, 731 unsigned int *buffer_offset) 732 { 733 unsigned int i, next_i, last = ctx->last_buffer_index; 734 __le16 res_count, next_res_count; 735 736 i = ar_first_buffer_index(ctx); 737 res_count = ACCESS_ONCE(ctx->descriptors[i].res_count); 738 739 /* A buffer that is not yet completely filled must be the last one. */ 740 while (i != last && res_count == 0) { 741 742 /* Peek at the next descriptor. */ 743 next_i = ar_next_buffer_index(i); 744 rmb(); /* read descriptors in order */ 745 next_res_count = ACCESS_ONCE( 746 ctx->descriptors[next_i].res_count); 747 /* 748 * If the next descriptor is still empty, we must stop at this 749 * descriptor. 750 */ 751 if (next_res_count == cpu_to_le16(PAGE_SIZE)) { 752 /* 753 * The exception is when the DMA data for one packet is 754 * split over three buffers; in this case, the middle 755 * buffer's descriptor might be never updated by the 756 * controller and look still empty, and we have to peek 757 * at the third one. 758 */ 759 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) { 760 next_i = ar_next_buffer_index(next_i); 761 rmb(); 762 next_res_count = ACCESS_ONCE( 763 ctx->descriptors[next_i].res_count); 764 if (next_res_count != cpu_to_le16(PAGE_SIZE)) 765 goto next_buffer_is_active; 766 } 767 768 break; 769 } 770 771 next_buffer_is_active: 772 i = next_i; 773 res_count = next_res_count; 774 } 775 776 rmb(); /* read res_count before the DMA data */ 777 778 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count); 779 if (*buffer_offset > PAGE_SIZE) { 780 *buffer_offset = 0; 781 ar_context_abort(ctx, "corrupted descriptor"); 782 } 783 784 return i; 785 } 786 787 static void ar_sync_buffers_for_cpu(struct ar_context *ctx, 788 unsigned int end_buffer_index, 789 unsigned int end_buffer_offset) 790 { 791 unsigned int i; 792 793 i = ar_first_buffer_index(ctx); 794 while (i != end_buffer_index) { 795 dma_sync_single_for_cpu(ctx->ohci->card.device, 796 ar_buffer_bus(ctx, i), 797 PAGE_SIZE, DMA_FROM_DEVICE); 798 i = ar_next_buffer_index(i); 799 } 800 if (end_buffer_offset > 0) 801 dma_sync_single_for_cpu(ctx->ohci->card.device, 802 ar_buffer_bus(ctx, i), 803 end_buffer_offset, DMA_FROM_DEVICE); 804 } 805 806 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) 807 #define cond_le32_to_cpu(v) \ 808 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v)) 809 #else 810 #define cond_le32_to_cpu(v) le32_to_cpu(v) 811 #endif 812 813 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) 814 { 815 struct fw_ohci *ohci = ctx->ohci; 816 struct fw_packet p; 817 u32 status, length, tcode; 818 int evt; 819 820 p.header[0] = cond_le32_to_cpu(buffer[0]); 821 p.header[1] = cond_le32_to_cpu(buffer[1]); 822 p.header[2] = cond_le32_to_cpu(buffer[2]); 823 824 tcode = (p.header[0] >> 4) & 0x0f; 825 switch (tcode) { 826 case TCODE_WRITE_QUADLET_REQUEST: 827 case TCODE_READ_QUADLET_RESPONSE: 828 p.header[3] = (__force __u32) buffer[3]; 829 p.header_length = 16; 830 p.payload_length = 0; 831 break; 832 833 case TCODE_READ_BLOCK_REQUEST : 834 p.header[3] = cond_le32_to_cpu(buffer[3]); 835 p.header_length = 16; 836 p.payload_length = 0; 837 break; 838 839 case TCODE_WRITE_BLOCK_REQUEST: 840 case TCODE_READ_BLOCK_RESPONSE: 841 case TCODE_LOCK_REQUEST: 842 case TCODE_LOCK_RESPONSE: 843 p.header[3] = cond_le32_to_cpu(buffer[3]); 844 p.header_length = 16; 845 p.payload_length = p.header[3] >> 16; 846 if (p.payload_length > MAX_ASYNC_PAYLOAD) { 847 ar_context_abort(ctx, "invalid packet length"); 848 return NULL; 849 } 850 break; 851 852 case TCODE_WRITE_RESPONSE: 853 case TCODE_READ_QUADLET_REQUEST: 854 case OHCI_TCODE_PHY_PACKET: 855 p.header_length = 12; 856 p.payload_length = 0; 857 break; 858 859 default: 860 ar_context_abort(ctx, "invalid tcode"); 861 return NULL; 862 } 863 864 p.payload = (void *) buffer + p.header_length; 865 866 /* FIXME: What to do about evt_* errors? */ 867 length = (p.header_length + p.payload_length + 3) / 4; 868 status = cond_le32_to_cpu(buffer[length]); 869 evt = (status >> 16) & 0x1f; 870 871 p.ack = evt - 16; 872 p.speed = (status >> 21) & 0x7; 873 p.timestamp = status & 0xffff; 874 p.generation = ohci->request_generation; 875 876 log_ar_at_event(ohci, 'R', p.speed, p.header, evt); 877 878 /* 879 * Several controllers, notably from NEC and VIA, forget to 880 * write ack_complete status at PHY packet reception. 881 */ 882 if (evt == OHCI1394_evt_no_status && 883 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4)) 884 p.ack = ACK_COMPLETE; 885 886 /* 887 * The OHCI bus reset handler synthesizes a PHY packet with 888 * the new generation number when a bus reset happens (see 889 * section 8.4.2.3). This helps us determine when a request 890 * was received and make sure we send the response in the same 891 * generation. We only need this for requests; for responses 892 * we use the unique tlabel for finding the matching 893 * request. 894 * 895 * Alas some chips sometimes emit bus reset packets with a 896 * wrong generation. We set the correct generation for these 897 * at a slightly incorrect time (in bus_reset_work). 898 */ 899 if (evt == OHCI1394_evt_bus_reset) { 900 if (!(ohci->quirks & QUIRK_RESET_PACKET)) 901 ohci->request_generation = (p.header[2] >> 16) & 0xff; 902 } else if (ctx == &ohci->ar_request_ctx) { 903 fw_core_handle_request(&ohci->card, &p); 904 } else { 905 fw_core_handle_response(&ohci->card, &p); 906 } 907 908 return buffer + length + 1; 909 } 910 911 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end) 912 { 913 void *next; 914 915 while (p < end) { 916 next = handle_ar_packet(ctx, p); 917 if (!next) 918 return p; 919 p = next; 920 } 921 922 return p; 923 } 924 925 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer) 926 { 927 unsigned int i; 928 929 i = ar_first_buffer_index(ctx); 930 while (i != end_buffer) { 931 dma_sync_single_for_device(ctx->ohci->card.device, 932 ar_buffer_bus(ctx, i), 933 PAGE_SIZE, DMA_FROM_DEVICE); 934 ar_context_link_page(ctx, i); 935 i = ar_next_buffer_index(i); 936 } 937 } 938 939 static void ar_context_tasklet(unsigned long data) 940 { 941 struct ar_context *ctx = (struct ar_context *)data; 942 unsigned int end_buffer_index, end_buffer_offset; 943 void *p, *end; 944 945 p = ctx->pointer; 946 if (!p) 947 return; 948 949 end_buffer_index = ar_search_last_active_buffer(ctx, 950 &end_buffer_offset); 951 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset); 952 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset; 953 954 if (end_buffer_index < ar_first_buffer_index(ctx)) { 955 /* 956 * The filled part of the overall buffer wraps around; handle 957 * all packets up to the buffer end here. If the last packet 958 * wraps around, its tail will be visible after the buffer end 959 * because the buffer start pages are mapped there again. 960 */ 961 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE; 962 p = handle_ar_packets(ctx, p, buffer_end); 963 if (p < buffer_end) 964 goto error; 965 /* adjust p to point back into the actual buffer */ 966 p -= AR_BUFFERS * PAGE_SIZE; 967 } 968 969 p = handle_ar_packets(ctx, p, end); 970 if (p != end) { 971 if (p > end) 972 ar_context_abort(ctx, "inconsistent descriptor"); 973 goto error; 974 } 975 976 ctx->pointer = p; 977 ar_recycle_buffers(ctx, end_buffer_index); 978 979 return; 980 981 error: 982 ctx->pointer = NULL; 983 } 984 985 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, 986 unsigned int descriptors_offset, u32 regs) 987 { 988 unsigned int i; 989 dma_addr_t dma_addr; 990 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES]; 991 struct descriptor *d; 992 993 ctx->regs = regs; 994 ctx->ohci = ohci; 995 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); 996 997 for (i = 0; i < AR_BUFFERS; i++) { 998 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32); 999 if (!ctx->pages[i]) 1000 goto out_of_memory; 1001 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i], 1002 0, PAGE_SIZE, DMA_FROM_DEVICE); 1003 if (dma_mapping_error(ohci->card.device, dma_addr)) { 1004 __free_page(ctx->pages[i]); 1005 ctx->pages[i] = NULL; 1006 goto out_of_memory; 1007 } 1008 set_page_private(ctx->pages[i], dma_addr); 1009 } 1010 1011 for (i = 0; i < AR_BUFFERS; i++) 1012 pages[i] = ctx->pages[i]; 1013 for (i = 0; i < AR_WRAPAROUND_PAGES; i++) 1014 pages[AR_BUFFERS + i] = ctx->pages[i]; 1015 ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES, 1016 -1, PAGE_KERNEL); 1017 if (!ctx->buffer) 1018 goto out_of_memory; 1019 1020 ctx->descriptors = ohci->misc_buffer + descriptors_offset; 1021 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset; 1022 1023 for (i = 0; i < AR_BUFFERS; i++) { 1024 d = &ctx->descriptors[i]; 1025 d->req_count = cpu_to_le16(PAGE_SIZE); 1026 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 1027 DESCRIPTOR_STATUS | 1028 DESCRIPTOR_BRANCH_ALWAYS); 1029 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i)); 1030 d->branch_address = cpu_to_le32(ctx->descriptors_bus + 1031 ar_next_buffer_index(i) * sizeof(struct descriptor)); 1032 } 1033 1034 return 0; 1035 1036 out_of_memory: 1037 ar_context_release(ctx); 1038 1039 return -ENOMEM; 1040 } 1041 1042 static void ar_context_run(struct ar_context *ctx) 1043 { 1044 unsigned int i; 1045 1046 for (i = 0; i < AR_BUFFERS; i++) 1047 ar_context_link_page(ctx, i); 1048 1049 ctx->pointer = ctx->buffer; 1050 1051 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1); 1052 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); 1053 } 1054 1055 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z) 1056 { 1057 __le16 branch; 1058 1059 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS); 1060 1061 /* figure out which descriptor the branch address goes in */ 1062 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 1063 return d; 1064 else 1065 return d + z - 1; 1066 } 1067 1068 static void context_tasklet(unsigned long data) 1069 { 1070 struct context *ctx = (struct context *) data; 1071 struct descriptor *d, *last; 1072 u32 address; 1073 int z; 1074 struct descriptor_buffer *desc; 1075 1076 desc = list_entry(ctx->buffer_list.next, 1077 struct descriptor_buffer, list); 1078 last = ctx->last; 1079 while (last->branch_address != 0) { 1080 struct descriptor_buffer *old_desc = desc; 1081 address = le32_to_cpu(last->branch_address); 1082 z = address & 0xf; 1083 address &= ~0xf; 1084 ctx->current_bus = address; 1085 1086 /* If the branch address points to a buffer outside of the 1087 * current buffer, advance to the next buffer. */ 1088 if (address < desc->buffer_bus || 1089 address >= desc->buffer_bus + desc->used) 1090 desc = list_entry(desc->list.next, 1091 struct descriptor_buffer, list); 1092 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d); 1093 last = find_branch_descriptor(d, z); 1094 1095 if (!ctx->callback(ctx, d, last)) 1096 break; 1097 1098 if (old_desc != desc) { 1099 /* If we've advanced to the next buffer, move the 1100 * previous buffer to the free list. */ 1101 unsigned long flags; 1102 old_desc->used = 0; 1103 spin_lock_irqsave(&ctx->ohci->lock, flags); 1104 list_move_tail(&old_desc->list, &ctx->buffer_list); 1105 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1106 } 1107 ctx->last = last; 1108 } 1109 } 1110 1111 /* 1112 * Allocate a new buffer and add it to the list of free buffers for this 1113 * context. Must be called with ohci->lock held. 1114 */ 1115 static int context_add_buffer(struct context *ctx) 1116 { 1117 struct descriptor_buffer *desc; 1118 dma_addr_t uninitialized_var(bus_addr); 1119 int offset; 1120 1121 /* 1122 * 16MB of descriptors should be far more than enough for any DMA 1123 * program. This will catch run-away userspace or DoS attacks. 1124 */ 1125 if (ctx->total_allocation >= 16*1024*1024) 1126 return -ENOMEM; 1127 1128 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE, 1129 &bus_addr, GFP_ATOMIC); 1130 if (!desc) 1131 return -ENOMEM; 1132 1133 offset = (void *)&desc->buffer - (void *)desc; 1134 desc->buffer_size = PAGE_SIZE - offset; 1135 desc->buffer_bus = bus_addr + offset; 1136 desc->used = 0; 1137 1138 list_add_tail(&desc->list, &ctx->buffer_list); 1139 ctx->total_allocation += PAGE_SIZE; 1140 1141 return 0; 1142 } 1143 1144 static int context_init(struct context *ctx, struct fw_ohci *ohci, 1145 u32 regs, descriptor_callback_t callback) 1146 { 1147 ctx->ohci = ohci; 1148 ctx->regs = regs; 1149 ctx->total_allocation = 0; 1150 1151 INIT_LIST_HEAD(&ctx->buffer_list); 1152 if (context_add_buffer(ctx) < 0) 1153 return -ENOMEM; 1154 1155 ctx->buffer_tail = list_entry(ctx->buffer_list.next, 1156 struct descriptor_buffer, list); 1157 1158 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); 1159 ctx->callback = callback; 1160 1161 /* 1162 * We put a dummy descriptor in the buffer that has a NULL 1163 * branch address and looks like it's been sent. That way we 1164 * have a descriptor to append DMA programs to. 1165 */ 1166 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer)); 1167 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST); 1168 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011); 1169 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer); 1170 ctx->last = ctx->buffer_tail->buffer; 1171 ctx->prev = ctx->buffer_tail->buffer; 1172 ctx->prev_z = 1; 1173 1174 return 0; 1175 } 1176 1177 static void context_release(struct context *ctx) 1178 { 1179 struct fw_card *card = &ctx->ohci->card; 1180 struct descriptor_buffer *desc, *tmp; 1181 1182 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list) 1183 dma_free_coherent(card->device, PAGE_SIZE, desc, 1184 desc->buffer_bus - 1185 ((void *)&desc->buffer - (void *)desc)); 1186 } 1187 1188 /* Must be called with ohci->lock held */ 1189 static struct descriptor *context_get_descriptors(struct context *ctx, 1190 int z, dma_addr_t *d_bus) 1191 { 1192 struct descriptor *d = NULL; 1193 struct descriptor_buffer *desc = ctx->buffer_tail; 1194 1195 if (z * sizeof(*d) > desc->buffer_size) 1196 return NULL; 1197 1198 if (z * sizeof(*d) > desc->buffer_size - desc->used) { 1199 /* No room for the descriptor in this buffer, so advance to the 1200 * next one. */ 1201 1202 if (desc->list.next == &ctx->buffer_list) { 1203 /* If there is no free buffer next in the list, 1204 * allocate one. */ 1205 if (context_add_buffer(ctx) < 0) 1206 return NULL; 1207 } 1208 desc = list_entry(desc->list.next, 1209 struct descriptor_buffer, list); 1210 ctx->buffer_tail = desc; 1211 } 1212 1213 d = desc->buffer + desc->used / sizeof(*d); 1214 memset(d, 0, z * sizeof(*d)); 1215 *d_bus = desc->buffer_bus + desc->used; 1216 1217 return d; 1218 } 1219 1220 static void context_run(struct context *ctx, u32 extra) 1221 { 1222 struct fw_ohci *ohci = ctx->ohci; 1223 1224 reg_write(ohci, COMMAND_PTR(ctx->regs), 1225 le32_to_cpu(ctx->last->branch_address)); 1226 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); 1227 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); 1228 ctx->running = true; 1229 flush_writes(ohci); 1230 } 1231 1232 static void context_append(struct context *ctx, 1233 struct descriptor *d, int z, int extra) 1234 { 1235 dma_addr_t d_bus; 1236 struct descriptor_buffer *desc = ctx->buffer_tail; 1237 struct descriptor *d_branch; 1238 1239 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d); 1240 1241 desc->used += (z + extra) * sizeof(*d); 1242 1243 wmb(); /* finish init of new descriptors before branch_address update */ 1244 1245 d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z); 1246 d_branch->branch_address = cpu_to_le32(d_bus | z); 1247 1248 /* 1249 * VT6306 incorrectly checks only the single descriptor at the 1250 * CommandPtr when the wake bit is written, so if it's a 1251 * multi-descriptor block starting with an INPUT_MORE, put a copy of 1252 * the branch address in the first descriptor. 1253 * 1254 * Not doing this for transmit contexts since not sure how it interacts 1255 * with skip addresses. 1256 */ 1257 if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) && 1258 d_branch != ctx->prev && 1259 (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) == 1260 cpu_to_le16(DESCRIPTOR_INPUT_MORE)) { 1261 ctx->prev->branch_address = cpu_to_le32(d_bus | z); 1262 } 1263 1264 ctx->prev = d; 1265 ctx->prev_z = z; 1266 } 1267 1268 static void context_stop(struct context *ctx) 1269 { 1270 struct fw_ohci *ohci = ctx->ohci; 1271 u32 reg; 1272 int i; 1273 1274 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 1275 ctx->running = false; 1276 1277 for (i = 0; i < 1000; i++) { 1278 reg = reg_read(ohci, CONTROL_SET(ctx->regs)); 1279 if ((reg & CONTEXT_ACTIVE) == 0) 1280 return; 1281 1282 if (i) 1283 udelay(10); 1284 } 1285 ohci_err(ohci, "DMA context still active (0x%08x)\n", reg); 1286 } 1287 1288 struct driver_data { 1289 u8 inline_data[8]; 1290 struct fw_packet *packet; 1291 }; 1292 1293 /* 1294 * This function apppends a packet to the DMA queue for transmission. 1295 * Must always be called with the ochi->lock held to ensure proper 1296 * generation handling and locking around packet queue manipulation. 1297 */ 1298 static int at_context_queue_packet(struct context *ctx, 1299 struct fw_packet *packet) 1300 { 1301 struct fw_ohci *ohci = ctx->ohci; 1302 dma_addr_t d_bus, uninitialized_var(payload_bus); 1303 struct driver_data *driver_data; 1304 struct descriptor *d, *last; 1305 __le32 *header; 1306 int z, tcode; 1307 1308 d = context_get_descriptors(ctx, 4, &d_bus); 1309 if (d == NULL) { 1310 packet->ack = RCODE_SEND_ERROR; 1311 return -1; 1312 } 1313 1314 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 1315 d[0].res_count = cpu_to_le16(packet->timestamp); 1316 1317 /* 1318 * The DMA format for asynchronous link packets is different 1319 * from the IEEE1394 layout, so shift the fields around 1320 * accordingly. 1321 */ 1322 1323 tcode = (packet->header[0] >> 4) & 0x0f; 1324 header = (__le32 *) &d[1]; 1325 switch (tcode) { 1326 case TCODE_WRITE_QUADLET_REQUEST: 1327 case TCODE_WRITE_BLOCK_REQUEST: 1328 case TCODE_WRITE_RESPONSE: 1329 case TCODE_READ_QUADLET_REQUEST: 1330 case TCODE_READ_BLOCK_REQUEST: 1331 case TCODE_READ_QUADLET_RESPONSE: 1332 case TCODE_READ_BLOCK_RESPONSE: 1333 case TCODE_LOCK_REQUEST: 1334 case TCODE_LOCK_RESPONSE: 1335 header[0] = cpu_to_le32((packet->header[0] & 0xffff) | 1336 (packet->speed << 16)); 1337 header[1] = cpu_to_le32((packet->header[1] & 0xffff) | 1338 (packet->header[0] & 0xffff0000)); 1339 header[2] = cpu_to_le32(packet->header[2]); 1340 1341 if (TCODE_IS_BLOCK_PACKET(tcode)) 1342 header[3] = cpu_to_le32(packet->header[3]); 1343 else 1344 header[3] = (__force __le32) packet->header[3]; 1345 1346 d[0].req_count = cpu_to_le16(packet->header_length); 1347 break; 1348 1349 case TCODE_LINK_INTERNAL: 1350 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) | 1351 (packet->speed << 16)); 1352 header[1] = cpu_to_le32(packet->header[1]); 1353 header[2] = cpu_to_le32(packet->header[2]); 1354 d[0].req_count = cpu_to_le16(12); 1355 1356 if (is_ping_packet(&packet->header[1])) 1357 d[0].control |= cpu_to_le16(DESCRIPTOR_PING); 1358 break; 1359 1360 case TCODE_STREAM_DATA: 1361 header[0] = cpu_to_le32((packet->header[0] & 0xffff) | 1362 (packet->speed << 16)); 1363 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000); 1364 d[0].req_count = cpu_to_le16(8); 1365 break; 1366 1367 default: 1368 /* BUG(); */ 1369 packet->ack = RCODE_SEND_ERROR; 1370 return -1; 1371 } 1372 1373 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor)); 1374 driver_data = (struct driver_data *) &d[3]; 1375 driver_data->packet = packet; 1376 packet->driver_data = driver_data; 1377 1378 if (packet->payload_length > 0) { 1379 if (packet->payload_length > sizeof(driver_data->inline_data)) { 1380 payload_bus = dma_map_single(ohci->card.device, 1381 packet->payload, 1382 packet->payload_length, 1383 DMA_TO_DEVICE); 1384 if (dma_mapping_error(ohci->card.device, payload_bus)) { 1385 packet->ack = RCODE_SEND_ERROR; 1386 return -1; 1387 } 1388 packet->payload_bus = payload_bus; 1389 packet->payload_mapped = true; 1390 } else { 1391 memcpy(driver_data->inline_data, packet->payload, 1392 packet->payload_length); 1393 payload_bus = d_bus + 3 * sizeof(*d); 1394 } 1395 1396 d[2].req_count = cpu_to_le16(packet->payload_length); 1397 d[2].data_address = cpu_to_le32(payload_bus); 1398 last = &d[2]; 1399 z = 3; 1400 } else { 1401 last = &d[0]; 1402 z = 2; 1403 } 1404 1405 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 1406 DESCRIPTOR_IRQ_ALWAYS | 1407 DESCRIPTOR_BRANCH_ALWAYS); 1408 1409 /* FIXME: Document how the locking works. */ 1410 if (ohci->generation != packet->generation) { 1411 if (packet->payload_mapped) 1412 dma_unmap_single(ohci->card.device, payload_bus, 1413 packet->payload_length, DMA_TO_DEVICE); 1414 packet->ack = RCODE_GENERATION; 1415 return -1; 1416 } 1417 1418 context_append(ctx, d, z, 4 - z); 1419 1420 if (ctx->running) 1421 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 1422 else 1423 context_run(ctx, 0); 1424 1425 return 0; 1426 } 1427 1428 static void at_context_flush(struct context *ctx) 1429 { 1430 tasklet_disable(&ctx->tasklet); 1431 1432 ctx->flushing = true; 1433 context_tasklet((unsigned long)ctx); 1434 ctx->flushing = false; 1435 1436 tasklet_enable(&ctx->tasklet); 1437 } 1438 1439 static int handle_at_packet(struct context *context, 1440 struct descriptor *d, 1441 struct descriptor *last) 1442 { 1443 struct driver_data *driver_data; 1444 struct fw_packet *packet; 1445 struct fw_ohci *ohci = context->ohci; 1446 int evt; 1447 1448 if (last->transfer_status == 0 && !context->flushing) 1449 /* This descriptor isn't done yet, stop iteration. */ 1450 return 0; 1451 1452 driver_data = (struct driver_data *) &d[3]; 1453 packet = driver_data->packet; 1454 if (packet == NULL) 1455 /* This packet was cancelled, just continue. */ 1456 return 1; 1457 1458 if (packet->payload_mapped) 1459 dma_unmap_single(ohci->card.device, packet->payload_bus, 1460 packet->payload_length, DMA_TO_DEVICE); 1461 1462 evt = le16_to_cpu(last->transfer_status) & 0x1f; 1463 packet->timestamp = le16_to_cpu(last->res_count); 1464 1465 log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt); 1466 1467 switch (evt) { 1468 case OHCI1394_evt_timeout: 1469 /* Async response transmit timed out. */ 1470 packet->ack = RCODE_CANCELLED; 1471 break; 1472 1473 case OHCI1394_evt_flushed: 1474 /* 1475 * The packet was flushed should give same error as 1476 * when we try to use a stale generation count. 1477 */ 1478 packet->ack = RCODE_GENERATION; 1479 break; 1480 1481 case OHCI1394_evt_missing_ack: 1482 if (context->flushing) 1483 packet->ack = RCODE_GENERATION; 1484 else { 1485 /* 1486 * Using a valid (current) generation count, but the 1487 * node is not on the bus or not sending acks. 1488 */ 1489 packet->ack = RCODE_NO_ACK; 1490 } 1491 break; 1492 1493 case ACK_COMPLETE + 0x10: 1494 case ACK_PENDING + 0x10: 1495 case ACK_BUSY_X + 0x10: 1496 case ACK_BUSY_A + 0x10: 1497 case ACK_BUSY_B + 0x10: 1498 case ACK_DATA_ERROR + 0x10: 1499 case ACK_TYPE_ERROR + 0x10: 1500 packet->ack = evt - 0x10; 1501 break; 1502 1503 case OHCI1394_evt_no_status: 1504 if (context->flushing) { 1505 packet->ack = RCODE_GENERATION; 1506 break; 1507 } 1508 /* fall through */ 1509 1510 default: 1511 packet->ack = RCODE_SEND_ERROR; 1512 break; 1513 } 1514 1515 packet->callback(packet, &ohci->card, packet->ack); 1516 1517 return 1; 1518 } 1519 1520 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff) 1521 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f) 1522 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff) 1523 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff) 1524 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff) 1525 1526 static void handle_local_rom(struct fw_ohci *ohci, 1527 struct fw_packet *packet, u32 csr) 1528 { 1529 struct fw_packet response; 1530 int tcode, length, i; 1531 1532 tcode = HEADER_GET_TCODE(packet->header[0]); 1533 if (TCODE_IS_BLOCK_PACKET(tcode)) 1534 length = HEADER_GET_DATA_LENGTH(packet->header[3]); 1535 else 1536 length = 4; 1537 1538 i = csr - CSR_CONFIG_ROM; 1539 if (i + length > CONFIG_ROM_SIZE) { 1540 fw_fill_response(&response, packet->header, 1541 RCODE_ADDRESS_ERROR, NULL, 0); 1542 } else if (!TCODE_IS_READ_REQUEST(tcode)) { 1543 fw_fill_response(&response, packet->header, 1544 RCODE_TYPE_ERROR, NULL, 0); 1545 } else { 1546 fw_fill_response(&response, packet->header, RCODE_COMPLETE, 1547 (void *) ohci->config_rom + i, length); 1548 } 1549 1550 fw_core_handle_response(&ohci->card, &response); 1551 } 1552 1553 static void handle_local_lock(struct fw_ohci *ohci, 1554 struct fw_packet *packet, u32 csr) 1555 { 1556 struct fw_packet response; 1557 int tcode, length, ext_tcode, sel, try; 1558 __be32 *payload, lock_old; 1559 u32 lock_arg, lock_data; 1560 1561 tcode = HEADER_GET_TCODE(packet->header[0]); 1562 length = HEADER_GET_DATA_LENGTH(packet->header[3]); 1563 payload = packet->payload; 1564 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]); 1565 1566 if (tcode == TCODE_LOCK_REQUEST && 1567 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { 1568 lock_arg = be32_to_cpu(payload[0]); 1569 lock_data = be32_to_cpu(payload[1]); 1570 } else if (tcode == TCODE_READ_QUADLET_REQUEST) { 1571 lock_arg = 0; 1572 lock_data = 0; 1573 } else { 1574 fw_fill_response(&response, packet->header, 1575 RCODE_TYPE_ERROR, NULL, 0); 1576 goto out; 1577 } 1578 1579 sel = (csr - CSR_BUS_MANAGER_ID) / 4; 1580 reg_write(ohci, OHCI1394_CSRData, lock_data); 1581 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); 1582 reg_write(ohci, OHCI1394_CSRControl, sel); 1583 1584 for (try = 0; try < 20; try++) 1585 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) { 1586 lock_old = cpu_to_be32(reg_read(ohci, 1587 OHCI1394_CSRData)); 1588 fw_fill_response(&response, packet->header, 1589 RCODE_COMPLETE, 1590 &lock_old, sizeof(lock_old)); 1591 goto out; 1592 } 1593 1594 ohci_err(ohci, "swap not done (CSR lock timeout)\n"); 1595 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0); 1596 1597 out: 1598 fw_core_handle_response(&ohci->card, &response); 1599 } 1600 1601 static void handle_local_request(struct context *ctx, struct fw_packet *packet) 1602 { 1603 u64 offset, csr; 1604 1605 if (ctx == &ctx->ohci->at_request_ctx) { 1606 packet->ack = ACK_PENDING; 1607 packet->callback(packet, &ctx->ohci->card, packet->ack); 1608 } 1609 1610 offset = 1611 ((unsigned long long) 1612 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) | 1613 packet->header[2]; 1614 csr = offset - CSR_REGISTER_BASE; 1615 1616 /* Handle config rom reads. */ 1617 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) 1618 handle_local_rom(ctx->ohci, packet, csr); 1619 else switch (csr) { 1620 case CSR_BUS_MANAGER_ID: 1621 case CSR_BANDWIDTH_AVAILABLE: 1622 case CSR_CHANNELS_AVAILABLE_HI: 1623 case CSR_CHANNELS_AVAILABLE_LO: 1624 handle_local_lock(ctx->ohci, packet, csr); 1625 break; 1626 default: 1627 if (ctx == &ctx->ohci->at_request_ctx) 1628 fw_core_handle_request(&ctx->ohci->card, packet); 1629 else 1630 fw_core_handle_response(&ctx->ohci->card, packet); 1631 break; 1632 } 1633 1634 if (ctx == &ctx->ohci->at_response_ctx) { 1635 packet->ack = ACK_COMPLETE; 1636 packet->callback(packet, &ctx->ohci->card, packet->ack); 1637 } 1638 } 1639 1640 static void at_context_transmit(struct context *ctx, struct fw_packet *packet) 1641 { 1642 unsigned long flags; 1643 int ret; 1644 1645 spin_lock_irqsave(&ctx->ohci->lock, flags); 1646 1647 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id && 1648 ctx->ohci->generation == packet->generation) { 1649 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1650 handle_local_request(ctx, packet); 1651 return; 1652 } 1653 1654 ret = at_context_queue_packet(ctx, packet); 1655 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1656 1657 if (ret < 0) 1658 packet->callback(packet, &ctx->ohci->card, packet->ack); 1659 1660 } 1661 1662 static void detect_dead_context(struct fw_ohci *ohci, 1663 const char *name, unsigned int regs) 1664 { 1665 u32 ctl; 1666 1667 ctl = reg_read(ohci, CONTROL_SET(regs)); 1668 if (ctl & CONTEXT_DEAD) 1669 ohci_err(ohci, "DMA context %s has stopped, error code: %s\n", 1670 name, evts[ctl & 0x1f]); 1671 } 1672 1673 static void handle_dead_contexts(struct fw_ohci *ohci) 1674 { 1675 unsigned int i; 1676 char name[8]; 1677 1678 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase); 1679 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase); 1680 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase); 1681 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase); 1682 for (i = 0; i < 32; ++i) { 1683 if (!(ohci->it_context_support & (1 << i))) 1684 continue; 1685 sprintf(name, "IT%u", i); 1686 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i)); 1687 } 1688 for (i = 0; i < 32; ++i) { 1689 if (!(ohci->ir_context_support & (1 << i))) 1690 continue; 1691 sprintf(name, "IR%u", i); 1692 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i)); 1693 } 1694 /* TODO: maybe try to flush and restart the dead contexts */ 1695 } 1696 1697 static u32 cycle_timer_ticks(u32 cycle_timer) 1698 { 1699 u32 ticks; 1700 1701 ticks = cycle_timer & 0xfff; 1702 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff); 1703 ticks += (3072 * 8000) * (cycle_timer >> 25); 1704 1705 return ticks; 1706 } 1707 1708 /* 1709 * Some controllers exhibit one or more of the following bugs when updating the 1710 * iso cycle timer register: 1711 * - When the lowest six bits are wrapping around to zero, a read that happens 1712 * at the same time will return garbage in the lowest ten bits. 1713 * - When the cycleOffset field wraps around to zero, the cycleCount field is 1714 * not incremented for about 60 ns. 1715 * - Occasionally, the entire register reads zero. 1716 * 1717 * To catch these, we read the register three times and ensure that the 1718 * difference between each two consecutive reads is approximately the same, i.e. 1719 * less than twice the other. Furthermore, any negative difference indicates an 1720 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to 1721 * execute, so we have enough precision to compute the ratio of the differences.) 1722 */ 1723 static u32 get_cycle_time(struct fw_ohci *ohci) 1724 { 1725 u32 c0, c1, c2; 1726 u32 t0, t1, t2; 1727 s32 diff01, diff12; 1728 int i; 1729 1730 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1731 1732 if (ohci->quirks & QUIRK_CYCLE_TIMER) { 1733 i = 0; 1734 c1 = c2; 1735 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1736 do { 1737 c0 = c1; 1738 c1 = c2; 1739 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1740 t0 = cycle_timer_ticks(c0); 1741 t1 = cycle_timer_ticks(c1); 1742 t2 = cycle_timer_ticks(c2); 1743 diff01 = t1 - t0; 1744 diff12 = t2 - t1; 1745 } while ((diff01 <= 0 || diff12 <= 0 || 1746 diff01 / diff12 >= 2 || diff12 / diff01 >= 2) 1747 && i++ < 20); 1748 } 1749 1750 return c2; 1751 } 1752 1753 /* 1754 * This function has to be called at least every 64 seconds. The bus_time 1755 * field stores not only the upper 25 bits of the BUS_TIME register but also 1756 * the most significant bit of the cycle timer in bit 6 so that we can detect 1757 * changes in this bit. 1758 */ 1759 static u32 update_bus_time(struct fw_ohci *ohci) 1760 { 1761 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25; 1762 1763 if (unlikely(!ohci->bus_time_running)) { 1764 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds); 1765 ohci->bus_time = (lower_32_bits(get_seconds()) & ~0x7f) | 1766 (cycle_time_seconds & 0x40); 1767 ohci->bus_time_running = true; 1768 } 1769 1770 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40)) 1771 ohci->bus_time += 0x40; 1772 1773 return ohci->bus_time | cycle_time_seconds; 1774 } 1775 1776 static int get_status_for_port(struct fw_ohci *ohci, int port_index) 1777 { 1778 int reg; 1779 1780 mutex_lock(&ohci->phy_reg_mutex); 1781 reg = write_phy_reg(ohci, 7, port_index); 1782 if (reg >= 0) 1783 reg = read_phy_reg(ohci, 8); 1784 mutex_unlock(&ohci->phy_reg_mutex); 1785 if (reg < 0) 1786 return reg; 1787 1788 switch (reg & 0x0f) { 1789 case 0x06: 1790 return 2; /* is child node (connected to parent node) */ 1791 case 0x0e: 1792 return 3; /* is parent node (connected to child node) */ 1793 } 1794 return 1; /* not connected */ 1795 } 1796 1797 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id, 1798 int self_id_count) 1799 { 1800 int i; 1801 u32 entry; 1802 1803 for (i = 0; i < self_id_count; i++) { 1804 entry = ohci->self_id_buffer[i]; 1805 if ((self_id & 0xff000000) == (entry & 0xff000000)) 1806 return -1; 1807 if ((self_id & 0xff000000) < (entry & 0xff000000)) 1808 return i; 1809 } 1810 return i; 1811 } 1812 1813 static int initiated_reset(struct fw_ohci *ohci) 1814 { 1815 int reg; 1816 int ret = 0; 1817 1818 mutex_lock(&ohci->phy_reg_mutex); 1819 reg = write_phy_reg(ohci, 7, 0xe0); /* Select page 7 */ 1820 if (reg >= 0) { 1821 reg = read_phy_reg(ohci, 8); 1822 reg |= 0x40; 1823 reg = write_phy_reg(ohci, 8, reg); /* set PMODE bit */ 1824 if (reg >= 0) { 1825 reg = read_phy_reg(ohci, 12); /* read register 12 */ 1826 if (reg >= 0) { 1827 if ((reg & 0x08) == 0x08) { 1828 /* bit 3 indicates "initiated reset" */ 1829 ret = 0x2; 1830 } 1831 } 1832 } 1833 } 1834 mutex_unlock(&ohci->phy_reg_mutex); 1835 return ret; 1836 } 1837 1838 /* 1839 * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally 1840 * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059. 1841 * Construct the selfID from phy register contents. 1842 */ 1843 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count) 1844 { 1845 int reg, i, pos, status; 1846 /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */ 1847 u32 self_id = 0x8040c800; 1848 1849 reg = reg_read(ohci, OHCI1394_NodeID); 1850 if (!(reg & OHCI1394_NodeID_idValid)) { 1851 ohci_notice(ohci, 1852 "node ID not valid, new bus reset in progress\n"); 1853 return -EBUSY; 1854 } 1855 self_id |= ((reg & 0x3f) << 24); /* phy ID */ 1856 1857 reg = ohci_read_phy_reg(&ohci->card, 4); 1858 if (reg < 0) 1859 return reg; 1860 self_id |= ((reg & 0x07) << 8); /* power class */ 1861 1862 reg = ohci_read_phy_reg(&ohci->card, 1); 1863 if (reg < 0) 1864 return reg; 1865 self_id |= ((reg & 0x3f) << 16); /* gap count */ 1866 1867 for (i = 0; i < 3; i++) { 1868 status = get_status_for_port(ohci, i); 1869 if (status < 0) 1870 return status; 1871 self_id |= ((status & 0x3) << (6 - (i * 2))); 1872 } 1873 1874 self_id |= initiated_reset(ohci); 1875 1876 pos = get_self_id_pos(ohci, self_id, self_id_count); 1877 if (pos >= 0) { 1878 memmove(&(ohci->self_id_buffer[pos+1]), 1879 &(ohci->self_id_buffer[pos]), 1880 (self_id_count - pos) * sizeof(*ohci->self_id_buffer)); 1881 ohci->self_id_buffer[pos] = self_id; 1882 self_id_count++; 1883 } 1884 return self_id_count; 1885 } 1886 1887 static void bus_reset_work(struct work_struct *work) 1888 { 1889 struct fw_ohci *ohci = 1890 container_of(work, struct fw_ohci, bus_reset_work); 1891 int self_id_count, generation, new_generation, i, j; 1892 u32 reg; 1893 void *free_rom = NULL; 1894 dma_addr_t free_rom_bus = 0; 1895 bool is_new_root; 1896 1897 reg = reg_read(ohci, OHCI1394_NodeID); 1898 if (!(reg & OHCI1394_NodeID_idValid)) { 1899 ohci_notice(ohci, 1900 "node ID not valid, new bus reset in progress\n"); 1901 return; 1902 } 1903 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { 1904 ohci_notice(ohci, "malconfigured bus\n"); 1905 return; 1906 } 1907 ohci->node_id = reg & (OHCI1394_NodeID_busNumber | 1908 OHCI1394_NodeID_nodeNumber); 1909 1910 is_new_root = (reg & OHCI1394_NodeID_root) != 0; 1911 if (!(ohci->is_root && is_new_root)) 1912 reg_write(ohci, OHCI1394_LinkControlSet, 1913 OHCI1394_LinkControl_cycleMaster); 1914 ohci->is_root = is_new_root; 1915 1916 reg = reg_read(ohci, OHCI1394_SelfIDCount); 1917 if (reg & OHCI1394_SelfIDCount_selfIDError) { 1918 ohci_notice(ohci, "self ID receive error\n"); 1919 return; 1920 } 1921 /* 1922 * The count in the SelfIDCount register is the number of 1923 * bytes in the self ID receive buffer. Since we also receive 1924 * the inverted quadlets and a header quadlet, we shift one 1925 * bit extra to get the actual number of self IDs. 1926 */ 1927 self_id_count = (reg >> 3) & 0xff; 1928 1929 if (self_id_count > 252) { 1930 ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg); 1931 return; 1932 } 1933 1934 generation = (cond_le32_to_cpu(ohci->self_id[0]) >> 16) & 0xff; 1935 rmb(); 1936 1937 for (i = 1, j = 0; j < self_id_count; i += 2, j++) { 1938 u32 id = cond_le32_to_cpu(ohci->self_id[i]); 1939 u32 id2 = cond_le32_to_cpu(ohci->self_id[i + 1]); 1940 1941 if (id != ~id2) { 1942 /* 1943 * If the invalid data looks like a cycle start packet, 1944 * it's likely to be the result of the cycle master 1945 * having a wrong gap count. In this case, the self IDs 1946 * so far are valid and should be processed so that the 1947 * bus manager can then correct the gap count. 1948 */ 1949 if (id == 0xffff008f) { 1950 ohci_notice(ohci, "ignoring spurious self IDs\n"); 1951 self_id_count = j; 1952 break; 1953 } 1954 1955 ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n", 1956 j, self_id_count, id, id2); 1957 return; 1958 } 1959 ohci->self_id_buffer[j] = id; 1960 } 1961 1962 if (ohci->quirks & QUIRK_TI_SLLZ059) { 1963 self_id_count = find_and_insert_self_id(ohci, self_id_count); 1964 if (self_id_count < 0) { 1965 ohci_notice(ohci, 1966 "could not construct local self ID\n"); 1967 return; 1968 } 1969 } 1970 1971 if (self_id_count == 0) { 1972 ohci_notice(ohci, "no self IDs\n"); 1973 return; 1974 } 1975 rmb(); 1976 1977 /* 1978 * Check the consistency of the self IDs we just read. The 1979 * problem we face is that a new bus reset can start while we 1980 * read out the self IDs from the DMA buffer. If this happens, 1981 * the DMA buffer will be overwritten with new self IDs and we 1982 * will read out inconsistent data. The OHCI specification 1983 * (section 11.2) recommends a technique similar to 1984 * linux/seqlock.h, where we remember the generation of the 1985 * self IDs in the buffer before reading them out and compare 1986 * it to the current generation after reading them out. If 1987 * the two generations match we know we have a consistent set 1988 * of self IDs. 1989 */ 1990 1991 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; 1992 if (new_generation != generation) { 1993 ohci_notice(ohci, "new bus reset, discarding self ids\n"); 1994 return; 1995 } 1996 1997 /* FIXME: Document how the locking works. */ 1998 spin_lock_irq(&ohci->lock); 1999 2000 ohci->generation = -1; /* prevent AT packet queueing */ 2001 context_stop(&ohci->at_request_ctx); 2002 context_stop(&ohci->at_response_ctx); 2003 2004 spin_unlock_irq(&ohci->lock); 2005 2006 /* 2007 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent 2008 * packets in the AT queues and software needs to drain them. 2009 * Some OHCI 1.1 controllers (JMicron) apparently require this too. 2010 */ 2011 at_context_flush(&ohci->at_request_ctx); 2012 at_context_flush(&ohci->at_response_ctx); 2013 2014 spin_lock_irq(&ohci->lock); 2015 2016 ohci->generation = generation; 2017 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); 2018 2019 if (ohci->quirks & QUIRK_RESET_PACKET) 2020 ohci->request_generation = generation; 2021 2022 /* 2023 * This next bit is unrelated to the AT context stuff but we 2024 * have to do it under the spinlock also. If a new config rom 2025 * was set up before this reset, the old one is now no longer 2026 * in use and we can free it. Update the config rom pointers 2027 * to point to the current config rom and clear the 2028 * next_config_rom pointer so a new update can take place. 2029 */ 2030 2031 if (ohci->next_config_rom != NULL) { 2032 if (ohci->next_config_rom != ohci->config_rom) { 2033 free_rom = ohci->config_rom; 2034 free_rom_bus = ohci->config_rom_bus; 2035 } 2036 ohci->config_rom = ohci->next_config_rom; 2037 ohci->config_rom_bus = ohci->next_config_rom_bus; 2038 ohci->next_config_rom = NULL; 2039 2040 /* 2041 * Restore config_rom image and manually update 2042 * config_rom registers. Writing the header quadlet 2043 * will indicate that the config rom is ready, so we 2044 * do that last. 2045 */ 2046 reg_write(ohci, OHCI1394_BusOptions, 2047 be32_to_cpu(ohci->config_rom[2])); 2048 ohci->config_rom[0] = ohci->next_header; 2049 reg_write(ohci, OHCI1394_ConfigROMhdr, 2050 be32_to_cpu(ohci->next_header)); 2051 } 2052 2053 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA 2054 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0); 2055 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0); 2056 #endif 2057 2058 spin_unlock_irq(&ohci->lock); 2059 2060 if (free_rom) 2061 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2062 free_rom, free_rom_bus); 2063 2064 log_selfids(ohci, generation, self_id_count); 2065 2066 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, 2067 self_id_count, ohci->self_id_buffer, 2068 ohci->csr_state_setclear_abdicate); 2069 ohci->csr_state_setclear_abdicate = false; 2070 } 2071 2072 static irqreturn_t irq_handler(int irq, void *data) 2073 { 2074 struct fw_ohci *ohci = data; 2075 u32 event, iso_event; 2076 int i; 2077 2078 event = reg_read(ohci, OHCI1394_IntEventClear); 2079 2080 if (!event || !~event) 2081 return IRQ_NONE; 2082 2083 /* 2084 * busReset and postedWriteErr must not be cleared yet 2085 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1) 2086 */ 2087 reg_write(ohci, OHCI1394_IntEventClear, 2088 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr)); 2089 log_irqs(ohci, event); 2090 2091 if (event & OHCI1394_selfIDComplete) 2092 queue_work(selfid_workqueue, &ohci->bus_reset_work); 2093 2094 if (event & OHCI1394_RQPkt) 2095 tasklet_schedule(&ohci->ar_request_ctx.tasklet); 2096 2097 if (event & OHCI1394_RSPkt) 2098 tasklet_schedule(&ohci->ar_response_ctx.tasklet); 2099 2100 if (event & OHCI1394_reqTxComplete) 2101 tasklet_schedule(&ohci->at_request_ctx.tasklet); 2102 2103 if (event & OHCI1394_respTxComplete) 2104 tasklet_schedule(&ohci->at_response_ctx.tasklet); 2105 2106 if (event & OHCI1394_isochRx) { 2107 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); 2108 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); 2109 2110 while (iso_event) { 2111 i = ffs(iso_event) - 1; 2112 tasklet_schedule( 2113 &ohci->ir_context_list[i].context.tasklet); 2114 iso_event &= ~(1 << i); 2115 } 2116 } 2117 2118 if (event & OHCI1394_isochTx) { 2119 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); 2120 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); 2121 2122 while (iso_event) { 2123 i = ffs(iso_event) - 1; 2124 tasklet_schedule( 2125 &ohci->it_context_list[i].context.tasklet); 2126 iso_event &= ~(1 << i); 2127 } 2128 } 2129 2130 if (unlikely(event & OHCI1394_regAccessFail)) 2131 ohci_err(ohci, "register access failure\n"); 2132 2133 if (unlikely(event & OHCI1394_postedWriteErr)) { 2134 reg_read(ohci, OHCI1394_PostedWriteAddressHi); 2135 reg_read(ohci, OHCI1394_PostedWriteAddressLo); 2136 reg_write(ohci, OHCI1394_IntEventClear, 2137 OHCI1394_postedWriteErr); 2138 if (printk_ratelimit()) 2139 ohci_err(ohci, "PCI posted write error\n"); 2140 } 2141 2142 if (unlikely(event & OHCI1394_cycleTooLong)) { 2143 if (printk_ratelimit()) 2144 ohci_notice(ohci, "isochronous cycle too long\n"); 2145 reg_write(ohci, OHCI1394_LinkControlSet, 2146 OHCI1394_LinkControl_cycleMaster); 2147 } 2148 2149 if (unlikely(event & OHCI1394_cycleInconsistent)) { 2150 /* 2151 * We need to clear this event bit in order to make 2152 * cycleMatch isochronous I/O work. In theory we should 2153 * stop active cycleMatch iso contexts now and restart 2154 * them at least two cycles later. (FIXME?) 2155 */ 2156 if (printk_ratelimit()) 2157 ohci_notice(ohci, "isochronous cycle inconsistent\n"); 2158 } 2159 2160 if (unlikely(event & OHCI1394_unrecoverableError)) 2161 handle_dead_contexts(ohci); 2162 2163 if (event & OHCI1394_cycle64Seconds) { 2164 spin_lock(&ohci->lock); 2165 update_bus_time(ohci); 2166 spin_unlock(&ohci->lock); 2167 } else 2168 flush_writes(ohci); 2169 2170 return IRQ_HANDLED; 2171 } 2172 2173 static int software_reset(struct fw_ohci *ohci) 2174 { 2175 u32 val; 2176 int i; 2177 2178 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); 2179 for (i = 0; i < 500; i++) { 2180 val = reg_read(ohci, OHCI1394_HCControlSet); 2181 if (!~val) 2182 return -ENODEV; /* Card was ejected. */ 2183 2184 if (!(val & OHCI1394_HCControl_softReset)) 2185 return 0; 2186 2187 msleep(1); 2188 } 2189 2190 return -EBUSY; 2191 } 2192 2193 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length) 2194 { 2195 size_t size = length * 4; 2196 2197 memcpy(dest, src, size); 2198 if (size < CONFIG_ROM_SIZE) 2199 memset(&dest[length], 0, CONFIG_ROM_SIZE - size); 2200 } 2201 2202 static int configure_1394a_enhancements(struct fw_ohci *ohci) 2203 { 2204 bool enable_1394a; 2205 int ret, clear, set, offset; 2206 2207 /* Check if the driver should configure link and PHY. */ 2208 if (!(reg_read(ohci, OHCI1394_HCControlSet) & 2209 OHCI1394_HCControl_programPhyEnable)) 2210 return 0; 2211 2212 /* Paranoia: check whether the PHY supports 1394a, too. */ 2213 enable_1394a = false; 2214 ret = read_phy_reg(ohci, 2); 2215 if (ret < 0) 2216 return ret; 2217 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) { 2218 ret = read_paged_phy_reg(ohci, 1, 8); 2219 if (ret < 0) 2220 return ret; 2221 if (ret >= 1) 2222 enable_1394a = true; 2223 } 2224 2225 if (ohci->quirks & QUIRK_NO_1394A) 2226 enable_1394a = false; 2227 2228 /* Configure PHY and link consistently. */ 2229 if (enable_1394a) { 2230 clear = 0; 2231 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2232 } else { 2233 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2234 set = 0; 2235 } 2236 ret = update_phy_reg(ohci, 5, clear, set); 2237 if (ret < 0) 2238 return ret; 2239 2240 if (enable_1394a) 2241 offset = OHCI1394_HCControlSet; 2242 else 2243 offset = OHCI1394_HCControlClear; 2244 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable); 2245 2246 /* Clean up: configuration has been taken care of. */ 2247 reg_write(ohci, OHCI1394_HCControlClear, 2248 OHCI1394_HCControl_programPhyEnable); 2249 2250 return 0; 2251 } 2252 2253 static int probe_tsb41ba3d(struct fw_ohci *ohci) 2254 { 2255 /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */ 2256 static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, }; 2257 int reg, i; 2258 2259 reg = read_phy_reg(ohci, 2); 2260 if (reg < 0) 2261 return reg; 2262 if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS) 2263 return 0; 2264 2265 for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) { 2266 reg = read_paged_phy_reg(ohci, 1, i + 10); 2267 if (reg < 0) 2268 return reg; 2269 if (reg != id[i]) 2270 return 0; 2271 } 2272 return 1; 2273 } 2274 2275 static int ohci_enable(struct fw_card *card, 2276 const __be32 *config_rom, size_t length) 2277 { 2278 struct fw_ohci *ohci = fw_ohci(card); 2279 u32 lps, version, irqs; 2280 int i, ret; 2281 2282 if (software_reset(ohci)) { 2283 ohci_err(ohci, "failed to reset ohci card\n"); 2284 return -EBUSY; 2285 } 2286 2287 /* 2288 * Now enable LPS, which we need in order to start accessing 2289 * most of the registers. In fact, on some cards (ALI M5251), 2290 * accessing registers in the SClk domain without LPS enabled 2291 * will lock up the machine. Wait 50msec to make sure we have 2292 * full link enabled. However, with some cards (well, at least 2293 * a JMicron PCIe card), we have to try again sometimes. 2294 * 2295 * TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but 2296 * cannot actually use the phy at that time. These need tens of 2297 * millisecods pause between LPS write and first phy access too. 2298 * 2299 * But do not wait for 50msec on Agere/LSI cards. Their phy 2300 * arbitration state machine may time out during such a long wait. 2301 */ 2302 2303 reg_write(ohci, OHCI1394_HCControlSet, 2304 OHCI1394_HCControl_LPS | 2305 OHCI1394_HCControl_postedWriteEnable); 2306 flush_writes(ohci); 2307 2308 if (!(ohci->quirks & QUIRK_PHY_LCTRL_TIMEOUT)) 2309 msleep(50); 2310 2311 for (lps = 0, i = 0; !lps && i < 150; i++) { 2312 msleep(1); 2313 lps = reg_read(ohci, OHCI1394_HCControlSet) & 2314 OHCI1394_HCControl_LPS; 2315 } 2316 2317 if (!lps) { 2318 ohci_err(ohci, "failed to set Link Power Status\n"); 2319 return -EIO; 2320 } 2321 2322 if (ohci->quirks & QUIRK_TI_SLLZ059) { 2323 ret = probe_tsb41ba3d(ohci); 2324 if (ret < 0) 2325 return ret; 2326 if (ret) 2327 ohci_notice(ohci, "local TSB41BA3D phy\n"); 2328 else 2329 ohci->quirks &= ~QUIRK_TI_SLLZ059; 2330 } 2331 2332 reg_write(ohci, OHCI1394_HCControlClear, 2333 OHCI1394_HCControl_noByteSwapData); 2334 2335 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); 2336 reg_write(ohci, OHCI1394_LinkControlSet, 2337 OHCI1394_LinkControl_cycleTimerEnable | 2338 OHCI1394_LinkControl_cycleMaster); 2339 2340 reg_write(ohci, OHCI1394_ATRetries, 2341 OHCI1394_MAX_AT_REQ_RETRIES | 2342 (OHCI1394_MAX_AT_RESP_RETRIES << 4) | 2343 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) | 2344 (200 << 16)); 2345 2346 ohci->bus_time_running = false; 2347 2348 for (i = 0; i < 32; i++) 2349 if (ohci->ir_context_support & (1 << i)) 2350 reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i), 2351 IR_CONTEXT_MULTI_CHANNEL_MODE); 2352 2353 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 2354 if (version >= OHCI_VERSION_1_1) { 2355 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi, 2356 0xfffffffe); 2357 card->broadcast_channel_auto_allocated = true; 2358 } 2359 2360 /* Get implemented bits of the priority arbitration request counter. */ 2361 reg_write(ohci, OHCI1394_FairnessControl, 0x3f); 2362 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f; 2363 reg_write(ohci, OHCI1394_FairnessControl, 0); 2364 card->priority_budget_implemented = ohci->pri_req_max != 0; 2365 2366 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000); 2367 reg_write(ohci, OHCI1394_IntEventClear, ~0); 2368 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 2369 2370 ret = configure_1394a_enhancements(ohci); 2371 if (ret < 0) 2372 return ret; 2373 2374 /* Activate link_on bit and contender bit in our self ID packets.*/ 2375 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER); 2376 if (ret < 0) 2377 return ret; 2378 2379 /* 2380 * When the link is not yet enabled, the atomic config rom 2381 * update mechanism described below in ohci_set_config_rom() 2382 * is not active. We have to update ConfigRomHeader and 2383 * BusOptions manually, and the write to ConfigROMmap takes 2384 * effect immediately. We tie this to the enabling of the 2385 * link, so we have a valid config rom before enabling - the 2386 * OHCI requires that ConfigROMhdr and BusOptions have valid 2387 * values before enabling. 2388 * 2389 * However, when the ConfigROMmap is written, some controllers 2390 * always read back quadlets 0 and 2 from the config rom to 2391 * the ConfigRomHeader and BusOptions registers on bus reset. 2392 * They shouldn't do that in this initial case where the link 2393 * isn't enabled. This means we have to use the same 2394 * workaround here, setting the bus header to 0 and then write 2395 * the right values in the bus reset tasklet. 2396 */ 2397 2398 if (config_rom) { 2399 ohci->next_config_rom = 2400 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2401 &ohci->next_config_rom_bus, 2402 GFP_KERNEL); 2403 if (ohci->next_config_rom == NULL) 2404 return -ENOMEM; 2405 2406 copy_config_rom(ohci->next_config_rom, config_rom, length); 2407 } else { 2408 /* 2409 * In the suspend case, config_rom is NULL, which 2410 * means that we just reuse the old config rom. 2411 */ 2412 ohci->next_config_rom = ohci->config_rom; 2413 ohci->next_config_rom_bus = ohci->config_rom_bus; 2414 } 2415 2416 ohci->next_header = ohci->next_config_rom[0]; 2417 ohci->next_config_rom[0] = 0; 2418 reg_write(ohci, OHCI1394_ConfigROMhdr, 0); 2419 reg_write(ohci, OHCI1394_BusOptions, 2420 be32_to_cpu(ohci->next_config_rom[2])); 2421 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2422 2423 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); 2424 2425 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete | 2426 OHCI1394_RQPkt | OHCI1394_RSPkt | 2427 OHCI1394_isochTx | OHCI1394_isochRx | 2428 OHCI1394_postedWriteErr | 2429 OHCI1394_selfIDComplete | 2430 OHCI1394_regAccessFail | 2431 OHCI1394_cycleInconsistent | 2432 OHCI1394_unrecoverableError | 2433 OHCI1394_cycleTooLong | 2434 OHCI1394_masterIntEnable; 2435 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS) 2436 irqs |= OHCI1394_busReset; 2437 reg_write(ohci, OHCI1394_IntMaskSet, irqs); 2438 2439 reg_write(ohci, OHCI1394_HCControlSet, 2440 OHCI1394_HCControl_linkEnable | 2441 OHCI1394_HCControl_BIBimageValid); 2442 2443 reg_write(ohci, OHCI1394_LinkControlSet, 2444 OHCI1394_LinkControl_rcvSelfID | 2445 OHCI1394_LinkControl_rcvPhyPkt); 2446 2447 ar_context_run(&ohci->ar_request_ctx); 2448 ar_context_run(&ohci->ar_response_ctx); 2449 2450 flush_writes(ohci); 2451 2452 /* We are ready to go, reset bus to finish initialization. */ 2453 fw_schedule_bus_reset(&ohci->card, false, true); 2454 2455 return 0; 2456 } 2457 2458 static int ohci_set_config_rom(struct fw_card *card, 2459 const __be32 *config_rom, size_t length) 2460 { 2461 struct fw_ohci *ohci; 2462 __be32 *next_config_rom; 2463 dma_addr_t uninitialized_var(next_config_rom_bus); 2464 2465 ohci = fw_ohci(card); 2466 2467 /* 2468 * When the OHCI controller is enabled, the config rom update 2469 * mechanism is a bit tricky, but easy enough to use. See 2470 * section 5.5.6 in the OHCI specification. 2471 * 2472 * The OHCI controller caches the new config rom address in a 2473 * shadow register (ConfigROMmapNext) and needs a bus reset 2474 * for the changes to take place. When the bus reset is 2475 * detected, the controller loads the new values for the 2476 * ConfigRomHeader and BusOptions registers from the specified 2477 * config rom and loads ConfigROMmap from the ConfigROMmapNext 2478 * shadow register. All automatically and atomically. 2479 * 2480 * Now, there's a twist to this story. The automatic load of 2481 * ConfigRomHeader and BusOptions doesn't honor the 2482 * noByteSwapData bit, so with a be32 config rom, the 2483 * controller will load be32 values in to these registers 2484 * during the atomic update, even on litte endian 2485 * architectures. The workaround we use is to put a 0 in the 2486 * header quadlet; 0 is endian agnostic and means that the 2487 * config rom isn't ready yet. In the bus reset tasklet we 2488 * then set up the real values for the two registers. 2489 * 2490 * We use ohci->lock to avoid racing with the code that sets 2491 * ohci->next_config_rom to NULL (see bus_reset_work). 2492 */ 2493 2494 next_config_rom = 2495 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2496 &next_config_rom_bus, GFP_KERNEL); 2497 if (next_config_rom == NULL) 2498 return -ENOMEM; 2499 2500 spin_lock_irq(&ohci->lock); 2501 2502 /* 2503 * If there is not an already pending config_rom update, 2504 * push our new allocation into the ohci->next_config_rom 2505 * and then mark the local variable as null so that we 2506 * won't deallocate the new buffer. 2507 * 2508 * OTOH, if there is a pending config_rom update, just 2509 * use that buffer with the new config_rom data, and 2510 * let this routine free the unused DMA allocation. 2511 */ 2512 2513 if (ohci->next_config_rom == NULL) { 2514 ohci->next_config_rom = next_config_rom; 2515 ohci->next_config_rom_bus = next_config_rom_bus; 2516 next_config_rom = NULL; 2517 } 2518 2519 copy_config_rom(ohci->next_config_rom, config_rom, length); 2520 2521 ohci->next_header = config_rom[0]; 2522 ohci->next_config_rom[0] = 0; 2523 2524 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2525 2526 spin_unlock_irq(&ohci->lock); 2527 2528 /* If we didn't use the DMA allocation, delete it. */ 2529 if (next_config_rom != NULL) 2530 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2531 next_config_rom, next_config_rom_bus); 2532 2533 /* 2534 * Now initiate a bus reset to have the changes take 2535 * effect. We clean up the old config rom memory and DMA 2536 * mappings in the bus reset tasklet, since the OHCI 2537 * controller could need to access it before the bus reset 2538 * takes effect. 2539 */ 2540 2541 fw_schedule_bus_reset(&ohci->card, true, true); 2542 2543 return 0; 2544 } 2545 2546 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) 2547 { 2548 struct fw_ohci *ohci = fw_ohci(card); 2549 2550 at_context_transmit(&ohci->at_request_ctx, packet); 2551 } 2552 2553 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) 2554 { 2555 struct fw_ohci *ohci = fw_ohci(card); 2556 2557 at_context_transmit(&ohci->at_response_ctx, packet); 2558 } 2559 2560 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) 2561 { 2562 struct fw_ohci *ohci = fw_ohci(card); 2563 struct context *ctx = &ohci->at_request_ctx; 2564 struct driver_data *driver_data = packet->driver_data; 2565 int ret = -ENOENT; 2566 2567 tasklet_disable(&ctx->tasklet); 2568 2569 if (packet->ack != 0) 2570 goto out; 2571 2572 if (packet->payload_mapped) 2573 dma_unmap_single(ohci->card.device, packet->payload_bus, 2574 packet->payload_length, DMA_TO_DEVICE); 2575 2576 log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20); 2577 driver_data->packet = NULL; 2578 packet->ack = RCODE_CANCELLED; 2579 packet->callback(packet, &ohci->card, packet->ack); 2580 ret = 0; 2581 out: 2582 tasklet_enable(&ctx->tasklet); 2583 2584 return ret; 2585 } 2586 2587 static int ohci_enable_phys_dma(struct fw_card *card, 2588 int node_id, int generation) 2589 { 2590 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA 2591 return 0; 2592 #else 2593 struct fw_ohci *ohci = fw_ohci(card); 2594 unsigned long flags; 2595 int n, ret = 0; 2596 2597 /* 2598 * FIXME: Make sure this bitmask is cleared when we clear the busReset 2599 * interrupt bit. Clear physReqResourceAllBuses on bus reset. 2600 */ 2601 2602 spin_lock_irqsave(&ohci->lock, flags); 2603 2604 if (ohci->generation != generation) { 2605 ret = -ESTALE; 2606 goto out; 2607 } 2608 2609 /* 2610 * Note, if the node ID contains a non-local bus ID, physical DMA is 2611 * enabled for _all_ nodes on remote buses. 2612 */ 2613 2614 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; 2615 if (n < 32) 2616 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); 2617 else 2618 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); 2619 2620 flush_writes(ohci); 2621 out: 2622 spin_unlock_irqrestore(&ohci->lock, flags); 2623 2624 return ret; 2625 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */ 2626 } 2627 2628 static u32 ohci_read_csr(struct fw_card *card, int csr_offset) 2629 { 2630 struct fw_ohci *ohci = fw_ohci(card); 2631 unsigned long flags; 2632 u32 value; 2633 2634 switch (csr_offset) { 2635 case CSR_STATE_CLEAR: 2636 case CSR_STATE_SET: 2637 if (ohci->is_root && 2638 (reg_read(ohci, OHCI1394_LinkControlSet) & 2639 OHCI1394_LinkControl_cycleMaster)) 2640 value = CSR_STATE_BIT_CMSTR; 2641 else 2642 value = 0; 2643 if (ohci->csr_state_setclear_abdicate) 2644 value |= CSR_STATE_BIT_ABDICATE; 2645 2646 return value; 2647 2648 case CSR_NODE_IDS: 2649 return reg_read(ohci, OHCI1394_NodeID) << 16; 2650 2651 case CSR_CYCLE_TIME: 2652 return get_cycle_time(ohci); 2653 2654 case CSR_BUS_TIME: 2655 /* 2656 * We might be called just after the cycle timer has wrapped 2657 * around but just before the cycle64Seconds handler, so we 2658 * better check here, too, if the bus time needs to be updated. 2659 */ 2660 spin_lock_irqsave(&ohci->lock, flags); 2661 value = update_bus_time(ohci); 2662 spin_unlock_irqrestore(&ohci->lock, flags); 2663 return value; 2664 2665 case CSR_BUSY_TIMEOUT: 2666 value = reg_read(ohci, OHCI1394_ATRetries); 2667 return (value >> 4) & 0x0ffff00f; 2668 2669 case CSR_PRIORITY_BUDGET: 2670 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) | 2671 (ohci->pri_req_max << 8); 2672 2673 default: 2674 WARN_ON(1); 2675 return 0; 2676 } 2677 } 2678 2679 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value) 2680 { 2681 struct fw_ohci *ohci = fw_ohci(card); 2682 unsigned long flags; 2683 2684 switch (csr_offset) { 2685 case CSR_STATE_CLEAR: 2686 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2687 reg_write(ohci, OHCI1394_LinkControlClear, 2688 OHCI1394_LinkControl_cycleMaster); 2689 flush_writes(ohci); 2690 } 2691 if (value & CSR_STATE_BIT_ABDICATE) 2692 ohci->csr_state_setclear_abdicate = false; 2693 break; 2694 2695 case CSR_STATE_SET: 2696 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2697 reg_write(ohci, OHCI1394_LinkControlSet, 2698 OHCI1394_LinkControl_cycleMaster); 2699 flush_writes(ohci); 2700 } 2701 if (value & CSR_STATE_BIT_ABDICATE) 2702 ohci->csr_state_setclear_abdicate = true; 2703 break; 2704 2705 case CSR_NODE_IDS: 2706 reg_write(ohci, OHCI1394_NodeID, value >> 16); 2707 flush_writes(ohci); 2708 break; 2709 2710 case CSR_CYCLE_TIME: 2711 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value); 2712 reg_write(ohci, OHCI1394_IntEventSet, 2713 OHCI1394_cycleInconsistent); 2714 flush_writes(ohci); 2715 break; 2716 2717 case CSR_BUS_TIME: 2718 spin_lock_irqsave(&ohci->lock, flags); 2719 ohci->bus_time = (update_bus_time(ohci) & 0x40) | 2720 (value & ~0x7f); 2721 spin_unlock_irqrestore(&ohci->lock, flags); 2722 break; 2723 2724 case CSR_BUSY_TIMEOUT: 2725 value = (value & 0xf) | ((value & 0xf) << 4) | 2726 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4); 2727 reg_write(ohci, OHCI1394_ATRetries, value); 2728 flush_writes(ohci); 2729 break; 2730 2731 case CSR_PRIORITY_BUDGET: 2732 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f); 2733 flush_writes(ohci); 2734 break; 2735 2736 default: 2737 WARN_ON(1); 2738 break; 2739 } 2740 } 2741 2742 static void flush_iso_completions(struct iso_context *ctx) 2743 { 2744 ctx->base.callback.sc(&ctx->base, ctx->last_timestamp, 2745 ctx->header_length, ctx->header, 2746 ctx->base.callback_data); 2747 ctx->header_length = 0; 2748 } 2749 2750 static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr) 2751 { 2752 u32 *ctx_hdr; 2753 2754 if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) { 2755 if (ctx->base.drop_overflow_headers) 2756 return; 2757 flush_iso_completions(ctx); 2758 } 2759 2760 ctx_hdr = ctx->header + ctx->header_length; 2761 ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]); 2762 2763 /* 2764 * The two iso header quadlets are byteswapped to little 2765 * endian by the controller, but we want to present them 2766 * as big endian for consistency with the bus endianness. 2767 */ 2768 if (ctx->base.header_size > 0) 2769 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */ 2770 if (ctx->base.header_size > 4) 2771 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */ 2772 if (ctx->base.header_size > 8) 2773 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8); 2774 ctx->header_length += ctx->base.header_size; 2775 } 2776 2777 static int handle_ir_packet_per_buffer(struct context *context, 2778 struct descriptor *d, 2779 struct descriptor *last) 2780 { 2781 struct iso_context *ctx = 2782 container_of(context, struct iso_context, context); 2783 struct descriptor *pd; 2784 u32 buffer_dma; 2785 2786 for (pd = d; pd <= last; pd++) 2787 if (pd->transfer_status) 2788 break; 2789 if (pd > last) 2790 /* Descriptor(s) not done yet, stop iteration */ 2791 return 0; 2792 2793 while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) { 2794 d++; 2795 buffer_dma = le32_to_cpu(d->data_address); 2796 dma_sync_single_range_for_cpu(context->ohci->card.device, 2797 buffer_dma & PAGE_MASK, 2798 buffer_dma & ~PAGE_MASK, 2799 le16_to_cpu(d->req_count), 2800 DMA_FROM_DEVICE); 2801 } 2802 2803 copy_iso_headers(ctx, (u32 *) (last + 1)); 2804 2805 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) 2806 flush_iso_completions(ctx); 2807 2808 return 1; 2809 } 2810 2811 /* d == last because each descriptor block is only a single descriptor. */ 2812 static int handle_ir_buffer_fill(struct context *context, 2813 struct descriptor *d, 2814 struct descriptor *last) 2815 { 2816 struct iso_context *ctx = 2817 container_of(context, struct iso_context, context); 2818 unsigned int req_count, res_count, completed; 2819 u32 buffer_dma; 2820 2821 req_count = le16_to_cpu(last->req_count); 2822 res_count = le16_to_cpu(ACCESS_ONCE(last->res_count)); 2823 completed = req_count - res_count; 2824 buffer_dma = le32_to_cpu(last->data_address); 2825 2826 if (completed > 0) { 2827 ctx->mc_buffer_bus = buffer_dma; 2828 ctx->mc_completed = completed; 2829 } 2830 2831 if (res_count != 0) 2832 /* Descriptor(s) not done yet, stop iteration */ 2833 return 0; 2834 2835 dma_sync_single_range_for_cpu(context->ohci->card.device, 2836 buffer_dma & PAGE_MASK, 2837 buffer_dma & ~PAGE_MASK, 2838 completed, DMA_FROM_DEVICE); 2839 2840 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) { 2841 ctx->base.callback.mc(&ctx->base, 2842 buffer_dma + completed, 2843 ctx->base.callback_data); 2844 ctx->mc_completed = 0; 2845 } 2846 2847 return 1; 2848 } 2849 2850 static void flush_ir_buffer_fill(struct iso_context *ctx) 2851 { 2852 dma_sync_single_range_for_cpu(ctx->context.ohci->card.device, 2853 ctx->mc_buffer_bus & PAGE_MASK, 2854 ctx->mc_buffer_bus & ~PAGE_MASK, 2855 ctx->mc_completed, DMA_FROM_DEVICE); 2856 2857 ctx->base.callback.mc(&ctx->base, 2858 ctx->mc_buffer_bus + ctx->mc_completed, 2859 ctx->base.callback_data); 2860 ctx->mc_completed = 0; 2861 } 2862 2863 static inline void sync_it_packet_for_cpu(struct context *context, 2864 struct descriptor *pd) 2865 { 2866 __le16 control; 2867 u32 buffer_dma; 2868 2869 /* only packets beginning with OUTPUT_MORE* have data buffers */ 2870 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 2871 return; 2872 2873 /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */ 2874 pd += 2; 2875 2876 /* 2877 * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's 2878 * data buffer is in the context program's coherent page and must not 2879 * be synced. 2880 */ 2881 if ((le32_to_cpu(pd->data_address) & PAGE_MASK) == 2882 (context->current_bus & PAGE_MASK)) { 2883 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 2884 return; 2885 pd++; 2886 } 2887 2888 do { 2889 buffer_dma = le32_to_cpu(pd->data_address); 2890 dma_sync_single_range_for_cpu(context->ohci->card.device, 2891 buffer_dma & PAGE_MASK, 2892 buffer_dma & ~PAGE_MASK, 2893 le16_to_cpu(pd->req_count), 2894 DMA_TO_DEVICE); 2895 control = pd->control; 2896 pd++; 2897 } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))); 2898 } 2899 2900 static int handle_it_packet(struct context *context, 2901 struct descriptor *d, 2902 struct descriptor *last) 2903 { 2904 struct iso_context *ctx = 2905 container_of(context, struct iso_context, context); 2906 struct descriptor *pd; 2907 __be32 *ctx_hdr; 2908 2909 for (pd = d; pd <= last; pd++) 2910 if (pd->transfer_status) 2911 break; 2912 if (pd > last) 2913 /* Descriptor(s) not done yet, stop iteration */ 2914 return 0; 2915 2916 sync_it_packet_for_cpu(context, d); 2917 2918 if (ctx->header_length + 4 > PAGE_SIZE) { 2919 if (ctx->base.drop_overflow_headers) 2920 return 1; 2921 flush_iso_completions(ctx); 2922 } 2923 2924 ctx_hdr = ctx->header + ctx->header_length; 2925 ctx->last_timestamp = le16_to_cpu(last->res_count); 2926 /* Present this value as big-endian to match the receive code */ 2927 *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) | 2928 le16_to_cpu(pd->res_count)); 2929 ctx->header_length += 4; 2930 2931 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) 2932 flush_iso_completions(ctx); 2933 2934 return 1; 2935 } 2936 2937 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels) 2938 { 2939 u32 hi = channels >> 32, lo = channels; 2940 2941 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi); 2942 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo); 2943 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi); 2944 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo); 2945 mmiowb(); 2946 ohci->mc_channels = channels; 2947 } 2948 2949 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card, 2950 int type, int channel, size_t header_size) 2951 { 2952 struct fw_ohci *ohci = fw_ohci(card); 2953 struct iso_context *uninitialized_var(ctx); 2954 descriptor_callback_t uninitialized_var(callback); 2955 u64 *uninitialized_var(channels); 2956 u32 *uninitialized_var(mask), uninitialized_var(regs); 2957 int index, ret = -EBUSY; 2958 2959 spin_lock_irq(&ohci->lock); 2960 2961 switch (type) { 2962 case FW_ISO_CONTEXT_TRANSMIT: 2963 mask = &ohci->it_context_mask; 2964 callback = handle_it_packet; 2965 index = ffs(*mask) - 1; 2966 if (index >= 0) { 2967 *mask &= ~(1 << index); 2968 regs = OHCI1394_IsoXmitContextBase(index); 2969 ctx = &ohci->it_context_list[index]; 2970 } 2971 break; 2972 2973 case FW_ISO_CONTEXT_RECEIVE: 2974 channels = &ohci->ir_context_channels; 2975 mask = &ohci->ir_context_mask; 2976 callback = handle_ir_packet_per_buffer; 2977 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1; 2978 if (index >= 0) { 2979 *channels &= ~(1ULL << channel); 2980 *mask &= ~(1 << index); 2981 regs = OHCI1394_IsoRcvContextBase(index); 2982 ctx = &ohci->ir_context_list[index]; 2983 } 2984 break; 2985 2986 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2987 mask = &ohci->ir_context_mask; 2988 callback = handle_ir_buffer_fill; 2989 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1; 2990 if (index >= 0) { 2991 ohci->mc_allocated = true; 2992 *mask &= ~(1 << index); 2993 regs = OHCI1394_IsoRcvContextBase(index); 2994 ctx = &ohci->ir_context_list[index]; 2995 } 2996 break; 2997 2998 default: 2999 index = -1; 3000 ret = -ENOSYS; 3001 } 3002 3003 spin_unlock_irq(&ohci->lock); 3004 3005 if (index < 0) 3006 return ERR_PTR(ret); 3007 3008 memset(ctx, 0, sizeof(*ctx)); 3009 ctx->header_length = 0; 3010 ctx->header = (void *) __get_free_page(GFP_KERNEL); 3011 if (ctx->header == NULL) { 3012 ret = -ENOMEM; 3013 goto out; 3014 } 3015 ret = context_init(&ctx->context, ohci, regs, callback); 3016 if (ret < 0) 3017 goto out_with_header; 3018 3019 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) { 3020 set_multichannel_mask(ohci, 0); 3021 ctx->mc_completed = 0; 3022 } 3023 3024 return &ctx->base; 3025 3026 out_with_header: 3027 free_page((unsigned long)ctx->header); 3028 out: 3029 spin_lock_irq(&ohci->lock); 3030 3031 switch (type) { 3032 case FW_ISO_CONTEXT_RECEIVE: 3033 *channels |= 1ULL << channel; 3034 break; 3035 3036 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3037 ohci->mc_allocated = false; 3038 break; 3039 } 3040 *mask |= 1 << index; 3041 3042 spin_unlock_irq(&ohci->lock); 3043 3044 return ERR_PTR(ret); 3045 } 3046 3047 static int ohci_start_iso(struct fw_iso_context *base, 3048 s32 cycle, u32 sync, u32 tags) 3049 { 3050 struct iso_context *ctx = container_of(base, struct iso_context, base); 3051 struct fw_ohci *ohci = ctx->context.ohci; 3052 u32 control = IR_CONTEXT_ISOCH_HEADER, match; 3053 int index; 3054 3055 /* the controller cannot start without any queued packets */ 3056 if (ctx->context.last->branch_address == 0) 3057 return -ENODATA; 3058 3059 switch (ctx->base.type) { 3060 case FW_ISO_CONTEXT_TRANSMIT: 3061 index = ctx - ohci->it_context_list; 3062 match = 0; 3063 if (cycle >= 0) 3064 match = IT_CONTEXT_CYCLE_MATCH_ENABLE | 3065 (cycle & 0x7fff) << 16; 3066 3067 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); 3068 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); 3069 context_run(&ctx->context, match); 3070 break; 3071 3072 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3073 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE; 3074 /* fall through */ 3075 case FW_ISO_CONTEXT_RECEIVE: 3076 index = ctx - ohci->ir_context_list; 3077 match = (tags << 28) | (sync << 8) | ctx->base.channel; 3078 if (cycle >= 0) { 3079 match |= (cycle & 0x07fff) << 12; 3080 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE; 3081 } 3082 3083 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); 3084 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); 3085 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match); 3086 context_run(&ctx->context, control); 3087 3088 ctx->sync = sync; 3089 ctx->tags = tags; 3090 3091 break; 3092 } 3093 3094 return 0; 3095 } 3096 3097 static int ohci_stop_iso(struct fw_iso_context *base) 3098 { 3099 struct fw_ohci *ohci = fw_ohci(base->card); 3100 struct iso_context *ctx = container_of(base, struct iso_context, base); 3101 int index; 3102 3103 switch (ctx->base.type) { 3104 case FW_ISO_CONTEXT_TRANSMIT: 3105 index = ctx - ohci->it_context_list; 3106 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); 3107 break; 3108 3109 case FW_ISO_CONTEXT_RECEIVE: 3110 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3111 index = ctx - ohci->ir_context_list; 3112 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); 3113 break; 3114 } 3115 flush_writes(ohci); 3116 context_stop(&ctx->context); 3117 tasklet_kill(&ctx->context.tasklet); 3118 3119 return 0; 3120 } 3121 3122 static void ohci_free_iso_context(struct fw_iso_context *base) 3123 { 3124 struct fw_ohci *ohci = fw_ohci(base->card); 3125 struct iso_context *ctx = container_of(base, struct iso_context, base); 3126 unsigned long flags; 3127 int index; 3128 3129 ohci_stop_iso(base); 3130 context_release(&ctx->context); 3131 free_page((unsigned long)ctx->header); 3132 3133 spin_lock_irqsave(&ohci->lock, flags); 3134 3135 switch (base->type) { 3136 case FW_ISO_CONTEXT_TRANSMIT: 3137 index = ctx - ohci->it_context_list; 3138 ohci->it_context_mask |= 1 << index; 3139 break; 3140 3141 case FW_ISO_CONTEXT_RECEIVE: 3142 index = ctx - ohci->ir_context_list; 3143 ohci->ir_context_mask |= 1 << index; 3144 ohci->ir_context_channels |= 1ULL << base->channel; 3145 break; 3146 3147 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3148 index = ctx - ohci->ir_context_list; 3149 ohci->ir_context_mask |= 1 << index; 3150 ohci->ir_context_channels |= ohci->mc_channels; 3151 ohci->mc_channels = 0; 3152 ohci->mc_allocated = false; 3153 break; 3154 } 3155 3156 spin_unlock_irqrestore(&ohci->lock, flags); 3157 } 3158 3159 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels) 3160 { 3161 struct fw_ohci *ohci = fw_ohci(base->card); 3162 unsigned long flags; 3163 int ret; 3164 3165 switch (base->type) { 3166 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3167 3168 spin_lock_irqsave(&ohci->lock, flags); 3169 3170 /* Don't allow multichannel to grab other contexts' channels. */ 3171 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) { 3172 *channels = ohci->ir_context_channels; 3173 ret = -EBUSY; 3174 } else { 3175 set_multichannel_mask(ohci, *channels); 3176 ret = 0; 3177 } 3178 3179 spin_unlock_irqrestore(&ohci->lock, flags); 3180 3181 break; 3182 default: 3183 ret = -EINVAL; 3184 } 3185 3186 return ret; 3187 } 3188 3189 #ifdef CONFIG_PM 3190 static void ohci_resume_iso_dma(struct fw_ohci *ohci) 3191 { 3192 int i; 3193 struct iso_context *ctx; 3194 3195 for (i = 0 ; i < ohci->n_ir ; i++) { 3196 ctx = &ohci->ir_context_list[i]; 3197 if (ctx->context.running) 3198 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 3199 } 3200 3201 for (i = 0 ; i < ohci->n_it ; i++) { 3202 ctx = &ohci->it_context_list[i]; 3203 if (ctx->context.running) 3204 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 3205 } 3206 } 3207 #endif 3208 3209 static int queue_iso_transmit(struct iso_context *ctx, 3210 struct fw_iso_packet *packet, 3211 struct fw_iso_buffer *buffer, 3212 unsigned long payload) 3213 { 3214 struct descriptor *d, *last, *pd; 3215 struct fw_iso_packet *p; 3216 __le32 *header; 3217 dma_addr_t d_bus, page_bus; 3218 u32 z, header_z, payload_z, irq; 3219 u32 payload_index, payload_end_index, next_page_index; 3220 int page, end_page, i, length, offset; 3221 3222 p = packet; 3223 payload_index = payload; 3224 3225 if (p->skip) 3226 z = 1; 3227 else 3228 z = 2; 3229 if (p->header_length > 0) 3230 z++; 3231 3232 /* Determine the first page the payload isn't contained in. */ 3233 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; 3234 if (p->payload_length > 0) 3235 payload_z = end_page - (payload_index >> PAGE_SHIFT); 3236 else 3237 payload_z = 0; 3238 3239 z += payload_z; 3240 3241 /* Get header size in number of descriptors. */ 3242 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d)); 3243 3244 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); 3245 if (d == NULL) 3246 return -ENOMEM; 3247 3248 if (!p->skip) { 3249 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 3250 d[0].req_count = cpu_to_le16(8); 3251 /* 3252 * Link the skip address to this descriptor itself. This causes 3253 * a context to skip a cycle whenever lost cycles or FIFO 3254 * overruns occur, without dropping the data. The application 3255 * should then decide whether this is an error condition or not. 3256 * FIXME: Make the context's cycle-lost behaviour configurable? 3257 */ 3258 d[0].branch_address = cpu_to_le32(d_bus | z); 3259 3260 header = (__le32 *) &d[1]; 3261 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) | 3262 IT_HEADER_TAG(p->tag) | 3263 IT_HEADER_TCODE(TCODE_STREAM_DATA) | 3264 IT_HEADER_CHANNEL(ctx->base.channel) | 3265 IT_HEADER_SPEED(ctx->base.speed)); 3266 header[1] = 3267 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length + 3268 p->payload_length)); 3269 } 3270 3271 if (p->header_length > 0) { 3272 d[2].req_count = cpu_to_le16(p->header_length); 3273 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d)); 3274 memcpy(&d[z], p->header, p->header_length); 3275 } 3276 3277 pd = d + z - payload_z; 3278 payload_end_index = payload_index + p->payload_length; 3279 for (i = 0; i < payload_z; i++) { 3280 page = payload_index >> PAGE_SHIFT; 3281 offset = payload_index & ~PAGE_MASK; 3282 next_page_index = (page + 1) << PAGE_SHIFT; 3283 length = 3284 min(next_page_index, payload_end_index) - payload_index; 3285 pd[i].req_count = cpu_to_le16(length); 3286 3287 page_bus = page_private(buffer->pages[page]); 3288 pd[i].data_address = cpu_to_le32(page_bus + offset); 3289 3290 dma_sync_single_range_for_device(ctx->context.ohci->card.device, 3291 page_bus, offset, length, 3292 DMA_TO_DEVICE); 3293 3294 payload_index += length; 3295 } 3296 3297 if (p->interrupt) 3298 irq = DESCRIPTOR_IRQ_ALWAYS; 3299 else 3300 irq = DESCRIPTOR_NO_IRQ; 3301 3302 last = z == 2 ? d : d + z - 1; 3303 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 3304 DESCRIPTOR_STATUS | 3305 DESCRIPTOR_BRANCH_ALWAYS | 3306 irq); 3307 3308 context_append(&ctx->context, d, z, header_z); 3309 3310 return 0; 3311 } 3312 3313 static int queue_iso_packet_per_buffer(struct iso_context *ctx, 3314 struct fw_iso_packet *packet, 3315 struct fw_iso_buffer *buffer, 3316 unsigned long payload) 3317 { 3318 struct device *device = ctx->context.ohci->card.device; 3319 struct descriptor *d, *pd; 3320 dma_addr_t d_bus, page_bus; 3321 u32 z, header_z, rest; 3322 int i, j, length; 3323 int page, offset, packet_count, header_size, payload_per_buffer; 3324 3325 /* 3326 * The OHCI controller puts the isochronous header and trailer in the 3327 * buffer, so we need at least 8 bytes. 3328 */ 3329 packet_count = packet->header_length / ctx->base.header_size; 3330 header_size = max(ctx->base.header_size, (size_t)8); 3331 3332 /* Get header size in number of descriptors. */ 3333 header_z = DIV_ROUND_UP(header_size, sizeof(*d)); 3334 page = payload >> PAGE_SHIFT; 3335 offset = payload & ~PAGE_MASK; 3336 payload_per_buffer = packet->payload_length / packet_count; 3337 3338 for (i = 0; i < packet_count; i++) { 3339 /* d points to the header descriptor */ 3340 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1; 3341 d = context_get_descriptors(&ctx->context, 3342 z + header_z, &d_bus); 3343 if (d == NULL) 3344 return -ENOMEM; 3345 3346 d->control = cpu_to_le16(DESCRIPTOR_STATUS | 3347 DESCRIPTOR_INPUT_MORE); 3348 if (packet->skip && i == 0) 3349 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3350 d->req_count = cpu_to_le16(header_size); 3351 d->res_count = d->req_count; 3352 d->transfer_status = 0; 3353 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d))); 3354 3355 rest = payload_per_buffer; 3356 pd = d; 3357 for (j = 1; j < z; j++) { 3358 pd++; 3359 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3360 DESCRIPTOR_INPUT_MORE); 3361 3362 if (offset + rest < PAGE_SIZE) 3363 length = rest; 3364 else 3365 length = PAGE_SIZE - offset; 3366 pd->req_count = cpu_to_le16(length); 3367 pd->res_count = pd->req_count; 3368 pd->transfer_status = 0; 3369 3370 page_bus = page_private(buffer->pages[page]); 3371 pd->data_address = cpu_to_le32(page_bus + offset); 3372 3373 dma_sync_single_range_for_device(device, page_bus, 3374 offset, length, 3375 DMA_FROM_DEVICE); 3376 3377 offset = (offset + length) & ~PAGE_MASK; 3378 rest -= length; 3379 if (offset == 0) 3380 page++; 3381 } 3382 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3383 DESCRIPTOR_INPUT_LAST | 3384 DESCRIPTOR_BRANCH_ALWAYS); 3385 if (packet->interrupt && i == packet_count - 1) 3386 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3387 3388 context_append(&ctx->context, d, z, header_z); 3389 } 3390 3391 return 0; 3392 } 3393 3394 static int queue_iso_buffer_fill(struct iso_context *ctx, 3395 struct fw_iso_packet *packet, 3396 struct fw_iso_buffer *buffer, 3397 unsigned long payload) 3398 { 3399 struct descriptor *d; 3400 dma_addr_t d_bus, page_bus; 3401 int page, offset, rest, z, i, length; 3402 3403 page = payload >> PAGE_SHIFT; 3404 offset = payload & ~PAGE_MASK; 3405 rest = packet->payload_length; 3406 3407 /* We need one descriptor for each page in the buffer. */ 3408 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE); 3409 3410 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count)) 3411 return -EFAULT; 3412 3413 for (i = 0; i < z; i++) { 3414 d = context_get_descriptors(&ctx->context, 1, &d_bus); 3415 if (d == NULL) 3416 return -ENOMEM; 3417 3418 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 3419 DESCRIPTOR_BRANCH_ALWAYS); 3420 if (packet->skip && i == 0) 3421 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3422 if (packet->interrupt && i == z - 1) 3423 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3424 3425 if (offset + rest < PAGE_SIZE) 3426 length = rest; 3427 else 3428 length = PAGE_SIZE - offset; 3429 d->req_count = cpu_to_le16(length); 3430 d->res_count = d->req_count; 3431 d->transfer_status = 0; 3432 3433 page_bus = page_private(buffer->pages[page]); 3434 d->data_address = cpu_to_le32(page_bus + offset); 3435 3436 dma_sync_single_range_for_device(ctx->context.ohci->card.device, 3437 page_bus, offset, length, 3438 DMA_FROM_DEVICE); 3439 3440 rest -= length; 3441 offset = 0; 3442 page++; 3443 3444 context_append(&ctx->context, d, 1, 0); 3445 } 3446 3447 return 0; 3448 } 3449 3450 static int ohci_queue_iso(struct fw_iso_context *base, 3451 struct fw_iso_packet *packet, 3452 struct fw_iso_buffer *buffer, 3453 unsigned long payload) 3454 { 3455 struct iso_context *ctx = container_of(base, struct iso_context, base); 3456 unsigned long flags; 3457 int ret = -ENOSYS; 3458 3459 spin_lock_irqsave(&ctx->context.ohci->lock, flags); 3460 switch (base->type) { 3461 case FW_ISO_CONTEXT_TRANSMIT: 3462 ret = queue_iso_transmit(ctx, packet, buffer, payload); 3463 break; 3464 case FW_ISO_CONTEXT_RECEIVE: 3465 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload); 3466 break; 3467 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3468 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload); 3469 break; 3470 } 3471 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags); 3472 3473 return ret; 3474 } 3475 3476 static void ohci_flush_queue_iso(struct fw_iso_context *base) 3477 { 3478 struct context *ctx = 3479 &container_of(base, struct iso_context, base)->context; 3480 3481 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 3482 } 3483 3484 static int ohci_flush_iso_completions(struct fw_iso_context *base) 3485 { 3486 struct iso_context *ctx = container_of(base, struct iso_context, base); 3487 int ret = 0; 3488 3489 tasklet_disable(&ctx->context.tasklet); 3490 3491 if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) { 3492 context_tasklet((unsigned long)&ctx->context); 3493 3494 switch (base->type) { 3495 case FW_ISO_CONTEXT_TRANSMIT: 3496 case FW_ISO_CONTEXT_RECEIVE: 3497 if (ctx->header_length != 0) 3498 flush_iso_completions(ctx); 3499 break; 3500 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3501 if (ctx->mc_completed != 0) 3502 flush_ir_buffer_fill(ctx); 3503 break; 3504 default: 3505 ret = -ENOSYS; 3506 } 3507 3508 clear_bit_unlock(0, &ctx->flushing_completions); 3509 smp_mb__after_clear_bit(); 3510 } 3511 3512 tasklet_enable(&ctx->context.tasklet); 3513 3514 return ret; 3515 } 3516 3517 static const struct fw_card_driver ohci_driver = { 3518 .enable = ohci_enable, 3519 .read_phy_reg = ohci_read_phy_reg, 3520 .update_phy_reg = ohci_update_phy_reg, 3521 .set_config_rom = ohci_set_config_rom, 3522 .send_request = ohci_send_request, 3523 .send_response = ohci_send_response, 3524 .cancel_packet = ohci_cancel_packet, 3525 .enable_phys_dma = ohci_enable_phys_dma, 3526 .read_csr = ohci_read_csr, 3527 .write_csr = ohci_write_csr, 3528 3529 .allocate_iso_context = ohci_allocate_iso_context, 3530 .free_iso_context = ohci_free_iso_context, 3531 .set_iso_channels = ohci_set_iso_channels, 3532 .queue_iso = ohci_queue_iso, 3533 .flush_queue_iso = ohci_flush_queue_iso, 3534 .flush_iso_completions = ohci_flush_iso_completions, 3535 .start_iso = ohci_start_iso, 3536 .stop_iso = ohci_stop_iso, 3537 }; 3538 3539 #ifdef CONFIG_PPC_PMAC 3540 static void pmac_ohci_on(struct pci_dev *dev) 3541 { 3542 if (machine_is(powermac)) { 3543 struct device_node *ofn = pci_device_to_OF_node(dev); 3544 3545 if (ofn) { 3546 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1); 3547 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1); 3548 } 3549 } 3550 } 3551 3552 static void pmac_ohci_off(struct pci_dev *dev) 3553 { 3554 if (machine_is(powermac)) { 3555 struct device_node *ofn = pci_device_to_OF_node(dev); 3556 3557 if (ofn) { 3558 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0); 3559 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0); 3560 } 3561 } 3562 } 3563 #else 3564 static inline void pmac_ohci_on(struct pci_dev *dev) {} 3565 static inline void pmac_ohci_off(struct pci_dev *dev) {} 3566 #endif /* CONFIG_PPC_PMAC */ 3567 3568 static int pci_probe(struct pci_dev *dev, 3569 const struct pci_device_id *ent) 3570 { 3571 struct fw_ohci *ohci; 3572 u32 bus_options, max_receive, link_speed, version; 3573 u64 guid; 3574 int i, err; 3575 size_t size; 3576 3577 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) { 3578 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n"); 3579 return -ENOSYS; 3580 } 3581 3582 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL); 3583 if (ohci == NULL) { 3584 err = -ENOMEM; 3585 goto fail; 3586 } 3587 3588 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); 3589 3590 pmac_ohci_on(dev); 3591 3592 err = pci_enable_device(dev); 3593 if (err) { 3594 dev_err(&dev->dev, "failed to enable OHCI hardware\n"); 3595 goto fail_free; 3596 } 3597 3598 pci_set_master(dev); 3599 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); 3600 pci_set_drvdata(dev, ohci); 3601 3602 spin_lock_init(&ohci->lock); 3603 mutex_init(&ohci->phy_reg_mutex); 3604 3605 INIT_WORK(&ohci->bus_reset_work, bus_reset_work); 3606 3607 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) || 3608 pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) { 3609 ohci_err(ohci, "invalid MMIO resource\n"); 3610 err = -ENXIO; 3611 goto fail_disable; 3612 } 3613 3614 err = pci_request_region(dev, 0, ohci_driver_name); 3615 if (err) { 3616 ohci_err(ohci, "MMIO resource unavailable\n"); 3617 goto fail_disable; 3618 } 3619 3620 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE); 3621 if (ohci->registers == NULL) { 3622 ohci_err(ohci, "failed to remap registers\n"); 3623 err = -ENXIO; 3624 goto fail_iomem; 3625 } 3626 3627 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++) 3628 if ((ohci_quirks[i].vendor == dev->vendor) && 3629 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID || 3630 ohci_quirks[i].device == dev->device) && 3631 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID || 3632 ohci_quirks[i].revision >= dev->revision)) { 3633 ohci->quirks = ohci_quirks[i].flags; 3634 break; 3635 } 3636 if (param_quirks) 3637 ohci->quirks = param_quirks; 3638 3639 /* 3640 * Because dma_alloc_coherent() allocates at least one page, 3641 * we save space by using a common buffer for the AR request/ 3642 * response descriptors and the self IDs buffer. 3643 */ 3644 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4); 3645 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2); 3646 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device, 3647 PAGE_SIZE, 3648 &ohci->misc_buffer_bus, 3649 GFP_KERNEL); 3650 if (!ohci->misc_buffer) { 3651 err = -ENOMEM; 3652 goto fail_iounmap; 3653 } 3654 3655 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0, 3656 OHCI1394_AsReqRcvContextControlSet); 3657 if (err < 0) 3658 goto fail_misc_buf; 3659 3660 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4, 3661 OHCI1394_AsRspRcvContextControlSet); 3662 if (err < 0) 3663 goto fail_arreq_ctx; 3664 3665 err = context_init(&ohci->at_request_ctx, ohci, 3666 OHCI1394_AsReqTrContextControlSet, handle_at_packet); 3667 if (err < 0) 3668 goto fail_arrsp_ctx; 3669 3670 err = context_init(&ohci->at_response_ctx, ohci, 3671 OHCI1394_AsRspTrContextControlSet, handle_at_packet); 3672 if (err < 0) 3673 goto fail_atreq_ctx; 3674 3675 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); 3676 ohci->ir_context_channels = ~0ULL; 3677 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); 3678 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); 3679 ohci->ir_context_mask = ohci->ir_context_support; 3680 ohci->n_ir = hweight32(ohci->ir_context_mask); 3681 size = sizeof(struct iso_context) * ohci->n_ir; 3682 ohci->ir_context_list = kzalloc(size, GFP_KERNEL); 3683 3684 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); 3685 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); 3686 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); 3687 ohci->it_context_mask = ohci->it_context_support; 3688 ohci->n_it = hweight32(ohci->it_context_mask); 3689 size = sizeof(struct iso_context) * ohci->n_it; 3690 ohci->it_context_list = kzalloc(size, GFP_KERNEL); 3691 3692 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) { 3693 err = -ENOMEM; 3694 goto fail_contexts; 3695 } 3696 3697 ohci->self_id = ohci->misc_buffer + PAGE_SIZE/2; 3698 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2; 3699 3700 bus_options = reg_read(ohci, OHCI1394_BusOptions); 3701 max_receive = (bus_options >> 12) & 0xf; 3702 link_speed = bus_options & 0x7; 3703 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | 3704 reg_read(ohci, OHCI1394_GUIDLo); 3705 3706 if (!(ohci->quirks & QUIRK_NO_MSI)) 3707 pci_enable_msi(dev); 3708 if (request_irq(dev->irq, irq_handler, 3709 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED, 3710 ohci_driver_name, ohci)) { 3711 ohci_err(ohci, "failed to allocate interrupt %d\n", dev->irq); 3712 err = -EIO; 3713 goto fail_msi; 3714 } 3715 3716 err = fw_card_add(&ohci->card, max_receive, link_speed, guid); 3717 if (err) 3718 goto fail_irq; 3719 3720 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 3721 ohci_notice(ohci, 3722 "added OHCI v%x.%x device as card %d, " 3723 "%d IR + %d IT contexts, quirks 0x%x\n", 3724 version >> 16, version & 0xff, ohci->card.index, 3725 ohci->n_ir, ohci->n_it, ohci->quirks); 3726 3727 return 0; 3728 3729 fail_irq: 3730 free_irq(dev->irq, ohci); 3731 fail_msi: 3732 pci_disable_msi(dev); 3733 fail_contexts: 3734 kfree(ohci->ir_context_list); 3735 kfree(ohci->it_context_list); 3736 context_release(&ohci->at_response_ctx); 3737 fail_atreq_ctx: 3738 context_release(&ohci->at_request_ctx); 3739 fail_arrsp_ctx: 3740 ar_context_release(&ohci->ar_response_ctx); 3741 fail_arreq_ctx: 3742 ar_context_release(&ohci->ar_request_ctx); 3743 fail_misc_buf: 3744 dma_free_coherent(ohci->card.device, PAGE_SIZE, 3745 ohci->misc_buffer, ohci->misc_buffer_bus); 3746 fail_iounmap: 3747 pci_iounmap(dev, ohci->registers); 3748 fail_iomem: 3749 pci_release_region(dev, 0); 3750 fail_disable: 3751 pci_disable_device(dev); 3752 fail_free: 3753 kfree(ohci); 3754 pmac_ohci_off(dev); 3755 fail: 3756 return err; 3757 } 3758 3759 static void pci_remove(struct pci_dev *dev) 3760 { 3761 struct fw_ohci *ohci = pci_get_drvdata(dev); 3762 3763 /* 3764 * If the removal is happening from the suspend state, LPS won't be 3765 * enabled and host registers (eg., IntMaskClear) won't be accessible. 3766 */ 3767 if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) { 3768 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 3769 flush_writes(ohci); 3770 } 3771 cancel_work_sync(&ohci->bus_reset_work); 3772 fw_core_remove_card(&ohci->card); 3773 3774 /* 3775 * FIXME: Fail all pending packets here, now that the upper 3776 * layers can't queue any more. 3777 */ 3778 3779 software_reset(ohci); 3780 free_irq(dev->irq, ohci); 3781 3782 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom) 3783 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 3784 ohci->next_config_rom, ohci->next_config_rom_bus); 3785 if (ohci->config_rom) 3786 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 3787 ohci->config_rom, ohci->config_rom_bus); 3788 ar_context_release(&ohci->ar_request_ctx); 3789 ar_context_release(&ohci->ar_response_ctx); 3790 dma_free_coherent(ohci->card.device, PAGE_SIZE, 3791 ohci->misc_buffer, ohci->misc_buffer_bus); 3792 context_release(&ohci->at_request_ctx); 3793 context_release(&ohci->at_response_ctx); 3794 kfree(ohci->it_context_list); 3795 kfree(ohci->ir_context_list); 3796 pci_disable_msi(dev); 3797 pci_iounmap(dev, ohci->registers); 3798 pci_release_region(dev, 0); 3799 pci_disable_device(dev); 3800 kfree(ohci); 3801 pmac_ohci_off(dev); 3802 3803 dev_notice(&dev->dev, "removed fw-ohci device\n"); 3804 } 3805 3806 #ifdef CONFIG_PM 3807 static int pci_suspend(struct pci_dev *dev, pm_message_t state) 3808 { 3809 struct fw_ohci *ohci = pci_get_drvdata(dev); 3810 int err; 3811 3812 software_reset(ohci); 3813 err = pci_save_state(dev); 3814 if (err) { 3815 ohci_err(ohci, "pci_save_state failed\n"); 3816 return err; 3817 } 3818 err = pci_set_power_state(dev, pci_choose_state(dev, state)); 3819 if (err) 3820 ohci_err(ohci, "pci_set_power_state failed with %d\n", err); 3821 pmac_ohci_off(dev); 3822 3823 return 0; 3824 } 3825 3826 static int pci_resume(struct pci_dev *dev) 3827 { 3828 struct fw_ohci *ohci = pci_get_drvdata(dev); 3829 int err; 3830 3831 pmac_ohci_on(dev); 3832 pci_set_power_state(dev, PCI_D0); 3833 pci_restore_state(dev); 3834 err = pci_enable_device(dev); 3835 if (err) { 3836 ohci_err(ohci, "pci_enable_device failed\n"); 3837 return err; 3838 } 3839 3840 /* Some systems don't setup GUID register on resume from ram */ 3841 if (!reg_read(ohci, OHCI1394_GUIDLo) && 3842 !reg_read(ohci, OHCI1394_GUIDHi)) { 3843 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid); 3844 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32)); 3845 } 3846 3847 err = ohci_enable(&ohci->card, NULL, 0); 3848 if (err) 3849 return err; 3850 3851 ohci_resume_iso_dma(ohci); 3852 3853 return 0; 3854 } 3855 #endif 3856 3857 static const struct pci_device_id pci_table[] = { 3858 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, 3859 { } 3860 }; 3861 3862 MODULE_DEVICE_TABLE(pci, pci_table); 3863 3864 static struct pci_driver fw_ohci_pci_driver = { 3865 .name = ohci_driver_name, 3866 .id_table = pci_table, 3867 .probe = pci_probe, 3868 .remove = pci_remove, 3869 #ifdef CONFIG_PM 3870 .resume = pci_resume, 3871 .suspend = pci_suspend, 3872 #endif 3873 }; 3874 3875 static int __init fw_ohci_init(void) 3876 { 3877 selfid_workqueue = alloc_workqueue(KBUILD_MODNAME, WQ_MEM_RECLAIM, 0); 3878 if (!selfid_workqueue) 3879 return -ENOMEM; 3880 3881 return pci_register_driver(&fw_ohci_pci_driver); 3882 } 3883 3884 static void __exit fw_ohci_cleanup(void) 3885 { 3886 pci_unregister_driver(&fw_ohci_pci_driver); 3887 destroy_workqueue(selfid_workqueue); 3888 } 3889 3890 module_init(fw_ohci_init); 3891 module_exit(fw_ohci_cleanup); 3892 3893 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); 3894 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); 3895 MODULE_LICENSE("GPL"); 3896 3897 /* Provide a module alias so root-on-sbp2 initrds don't break. */ 3898 MODULE_ALIAS("ohci1394"); 3899