1 /* 2 * Driver for OHCI 1394 controllers 3 * 4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software Foundation, 18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 */ 20 21 #include <linux/bitops.h> 22 #include <linux/bug.h> 23 #include <linux/compiler.h> 24 #include <linux/delay.h> 25 #include <linux/device.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/firewire.h> 28 #include <linux/firewire-constants.h> 29 #include <linux/init.h> 30 #include <linux/interrupt.h> 31 #include <linux/io.h> 32 #include <linux/kernel.h> 33 #include <linux/list.h> 34 #include <linux/mm.h> 35 #include <linux/module.h> 36 #include <linux/moduleparam.h> 37 #include <linux/mutex.h> 38 #include <linux/pci.h> 39 #include <linux/pci_ids.h> 40 #include <linux/slab.h> 41 #include <linux/spinlock.h> 42 #include <linux/string.h> 43 #include <linux/time.h> 44 #include <linux/vmalloc.h> 45 46 #include <asm/byteorder.h> 47 #include <asm/page.h> 48 #include <asm/system.h> 49 50 #ifdef CONFIG_PPC_PMAC 51 #include <asm/pmac_feature.h> 52 #endif 53 54 #include "core.h" 55 #include "ohci.h" 56 57 #define DESCRIPTOR_OUTPUT_MORE 0 58 #define DESCRIPTOR_OUTPUT_LAST (1 << 12) 59 #define DESCRIPTOR_INPUT_MORE (2 << 12) 60 #define DESCRIPTOR_INPUT_LAST (3 << 12) 61 #define DESCRIPTOR_STATUS (1 << 11) 62 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8) 63 #define DESCRIPTOR_PING (1 << 7) 64 #define DESCRIPTOR_YY (1 << 6) 65 #define DESCRIPTOR_NO_IRQ (0 << 4) 66 #define DESCRIPTOR_IRQ_ERROR (1 << 4) 67 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4) 68 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2) 69 #define DESCRIPTOR_WAIT (3 << 0) 70 71 struct descriptor { 72 __le16 req_count; 73 __le16 control; 74 __le32 data_address; 75 __le32 branch_address; 76 __le16 res_count; 77 __le16 transfer_status; 78 } __attribute__((aligned(16))); 79 80 #define CONTROL_SET(regs) (regs) 81 #define CONTROL_CLEAR(regs) ((regs) + 4) 82 #define COMMAND_PTR(regs) ((regs) + 12) 83 #define CONTEXT_MATCH(regs) ((regs) + 16) 84 85 #define AR_BUFFER_SIZE (32*1024) 86 #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE) 87 /* we need at least two pages for proper list management */ 88 #define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2) 89 90 #define MAX_ASYNC_PAYLOAD 4096 91 #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4) 92 #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE) 93 94 struct ar_context { 95 struct fw_ohci *ohci; 96 struct page *pages[AR_BUFFERS]; 97 void *buffer; 98 struct descriptor *descriptors; 99 dma_addr_t descriptors_bus; 100 void *pointer; 101 unsigned int last_buffer_index; 102 u32 regs; 103 struct tasklet_struct tasklet; 104 }; 105 106 struct context; 107 108 typedef int (*descriptor_callback_t)(struct context *ctx, 109 struct descriptor *d, 110 struct descriptor *last); 111 112 /* 113 * A buffer that contains a block of DMA-able coherent memory used for 114 * storing a portion of a DMA descriptor program. 115 */ 116 struct descriptor_buffer { 117 struct list_head list; 118 dma_addr_t buffer_bus; 119 size_t buffer_size; 120 size_t used; 121 struct descriptor buffer[0]; 122 }; 123 124 struct context { 125 struct fw_ohci *ohci; 126 u32 regs; 127 int total_allocation; 128 bool running; 129 bool flushing; 130 131 /* 132 * List of page-sized buffers for storing DMA descriptors. 133 * Head of list contains buffers in use and tail of list contains 134 * free buffers. 135 */ 136 struct list_head buffer_list; 137 138 /* 139 * Pointer to a buffer inside buffer_list that contains the tail 140 * end of the current DMA program. 141 */ 142 struct descriptor_buffer *buffer_tail; 143 144 /* 145 * The descriptor containing the branch address of the first 146 * descriptor that has not yet been filled by the device. 147 */ 148 struct descriptor *last; 149 150 /* 151 * The last descriptor in the DMA program. It contains the branch 152 * address that must be updated upon appending a new descriptor. 153 */ 154 struct descriptor *prev; 155 156 descriptor_callback_t callback; 157 158 struct tasklet_struct tasklet; 159 }; 160 161 #define IT_HEADER_SY(v) ((v) << 0) 162 #define IT_HEADER_TCODE(v) ((v) << 4) 163 #define IT_HEADER_CHANNEL(v) ((v) << 8) 164 #define IT_HEADER_TAG(v) ((v) << 14) 165 #define IT_HEADER_SPEED(v) ((v) << 16) 166 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16) 167 168 struct iso_context { 169 struct fw_iso_context base; 170 struct context context; 171 int excess_bytes; 172 void *header; 173 size_t header_length; 174 175 u8 sync; 176 u8 tags; 177 }; 178 179 #define CONFIG_ROM_SIZE 1024 180 181 struct fw_ohci { 182 struct fw_card card; 183 184 __iomem char *registers; 185 int node_id; 186 int generation; 187 int request_generation; /* for timestamping incoming requests */ 188 unsigned quirks; 189 unsigned int pri_req_max; 190 u32 bus_time; 191 bool is_root; 192 bool csr_state_setclear_abdicate; 193 int n_ir; 194 int n_it; 195 /* 196 * Spinlock for accessing fw_ohci data. Never call out of 197 * this driver with this lock held. 198 */ 199 spinlock_t lock; 200 201 struct mutex phy_reg_mutex; 202 203 void *misc_buffer; 204 dma_addr_t misc_buffer_bus; 205 206 struct ar_context ar_request_ctx; 207 struct ar_context ar_response_ctx; 208 struct context at_request_ctx; 209 struct context at_response_ctx; 210 211 u32 it_context_support; 212 u32 it_context_mask; /* unoccupied IT contexts */ 213 struct iso_context *it_context_list; 214 u64 ir_context_channels; /* unoccupied channels */ 215 u32 ir_context_support; 216 u32 ir_context_mask; /* unoccupied IR contexts */ 217 struct iso_context *ir_context_list; 218 u64 mc_channels; /* channels in use by the multichannel IR context */ 219 bool mc_allocated; 220 221 __be32 *config_rom; 222 dma_addr_t config_rom_bus; 223 __be32 *next_config_rom; 224 dma_addr_t next_config_rom_bus; 225 __be32 next_header; 226 227 __le32 *self_id_cpu; 228 dma_addr_t self_id_bus; 229 struct tasklet_struct bus_reset_tasklet; 230 231 u32 self_id_buffer[512]; 232 }; 233 234 static inline struct fw_ohci *fw_ohci(struct fw_card *card) 235 { 236 return container_of(card, struct fw_ohci, card); 237 } 238 239 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 240 #define IR_CONTEXT_BUFFER_FILL 0x80000000 241 #define IR_CONTEXT_ISOCH_HEADER 0x40000000 242 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 243 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 244 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 245 246 #define CONTEXT_RUN 0x8000 247 #define CONTEXT_WAKE 0x1000 248 #define CONTEXT_DEAD 0x0800 249 #define CONTEXT_ACTIVE 0x0400 250 251 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf 252 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 253 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 254 255 #define OHCI1394_REGISTER_SIZE 0x800 256 #define OHCI_LOOP_COUNT 500 257 #define OHCI1394_PCI_HCI_Control 0x40 258 #define SELF_ID_BUF_SIZE 0x800 259 #define OHCI_TCODE_PHY_PACKET 0x0e 260 #define OHCI_VERSION_1_1 0x010010 261 262 static char ohci_driver_name[] = KBUILD_MODNAME; 263 264 #define PCI_DEVICE_ID_AGERE_FW643 0x5901 265 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380 266 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009 267 268 #define QUIRK_CYCLE_TIMER 1 269 #define QUIRK_RESET_PACKET 2 270 #define QUIRK_BE_HEADERS 4 271 #define QUIRK_NO_1394A 8 272 #define QUIRK_NO_MSI 16 273 274 /* In case of multiple matches in ohci_quirks[], only the first one is used. */ 275 static const struct { 276 unsigned short vendor, device, revision, flags; 277 } ohci_quirks[] = { 278 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID, 279 QUIRK_CYCLE_TIMER}, 280 281 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID, 282 QUIRK_BE_HEADERS}, 283 284 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6, 285 QUIRK_NO_MSI}, 286 287 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID, 288 QUIRK_NO_MSI}, 289 290 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID, 291 QUIRK_CYCLE_TIMER}, 292 293 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID, 294 QUIRK_CYCLE_TIMER}, 295 296 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID, 297 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A}, 298 299 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID, 300 QUIRK_RESET_PACKET}, 301 302 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID, 303 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, 304 }; 305 306 /* This overrides anything that was found in ohci_quirks[]. */ 307 static int param_quirks; 308 module_param_named(quirks, param_quirks, int, 0644); 309 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0" 310 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER) 311 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET) 312 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS) 313 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A) 314 ", disable MSI = " __stringify(QUIRK_NO_MSI) 315 ")"); 316 317 #define OHCI_PARAM_DEBUG_AT_AR 1 318 #define OHCI_PARAM_DEBUG_SELFIDS 2 319 #define OHCI_PARAM_DEBUG_IRQS 4 320 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */ 321 322 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG 323 324 static int param_debug; 325 module_param_named(debug, param_debug, int, 0644); 326 MODULE_PARM_DESC(debug, "Verbose logging (default = 0" 327 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR) 328 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS) 329 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS) 330 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS) 331 ", or a combination, or all = -1)"); 332 333 static void log_irqs(u32 evt) 334 { 335 if (likely(!(param_debug & 336 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS)))) 337 return; 338 339 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) && 340 !(evt & OHCI1394_busReset)) 341 return; 342 343 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt, 344 evt & OHCI1394_selfIDComplete ? " selfID" : "", 345 evt & OHCI1394_RQPkt ? " AR_req" : "", 346 evt & OHCI1394_RSPkt ? " AR_resp" : "", 347 evt & OHCI1394_reqTxComplete ? " AT_req" : "", 348 evt & OHCI1394_respTxComplete ? " AT_resp" : "", 349 evt & OHCI1394_isochRx ? " IR" : "", 350 evt & OHCI1394_isochTx ? " IT" : "", 351 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", 352 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", 353 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "", 354 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "", 355 evt & OHCI1394_regAccessFail ? " regAccessFail" : "", 356 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "", 357 evt & OHCI1394_busReset ? " busReset" : "", 358 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | 359 OHCI1394_RSPkt | OHCI1394_reqTxComplete | 360 OHCI1394_respTxComplete | OHCI1394_isochRx | 361 OHCI1394_isochTx | OHCI1394_postedWriteErr | 362 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds | 363 OHCI1394_cycleInconsistent | 364 OHCI1394_regAccessFail | OHCI1394_busReset) 365 ? " ?" : ""); 366 } 367 368 static const char *speed[] = { 369 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta", 370 }; 371 static const char *power[] = { 372 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W", 373 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W", 374 }; 375 static const char port[] = { '.', '-', 'p', 'c', }; 376 377 static char _p(u32 *s, int shift) 378 { 379 return port[*s >> shift & 3]; 380 } 381 382 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s) 383 { 384 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) 385 return; 386 387 fw_notify("%d selfIDs, generation %d, local node ID %04x\n", 388 self_id_count, generation, node_id); 389 390 for (; self_id_count--; ++s) 391 if ((*s & 1 << 23) == 0) 392 fw_notify("selfID 0: %08x, phy %d [%c%c%c] " 393 "%s gc=%d %s %s%s%s\n", 394 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2), 395 speed[*s >> 14 & 3], *s >> 16 & 63, 396 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", 397 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); 398 else 399 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n", 400 *s, *s >> 24 & 63, 401 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10), 402 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2)); 403 } 404 405 static const char *evts[] = { 406 [0x00] = "evt_no_status", [0x01] = "-reserved-", 407 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack", 408 [0x04] = "evt_underrun", [0x05] = "evt_overrun", 409 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read", 410 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset", 411 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err", 412 [0x0c] = "-reserved-", [0x0d] = "-reserved-", 413 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed", 414 [0x10] = "-reserved-", [0x11] = "ack_complete", 415 [0x12] = "ack_pending ", [0x13] = "-reserved-", 416 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A", 417 [0x16] = "ack_busy_B", [0x17] = "-reserved-", 418 [0x18] = "-reserved-", [0x19] = "-reserved-", 419 [0x1a] = "-reserved-", [0x1b] = "ack_tardy", 420 [0x1c] = "-reserved-", [0x1d] = "ack_data_error", 421 [0x1e] = "ack_type_error", [0x1f] = "-reserved-", 422 [0x20] = "pending/cancelled", 423 }; 424 static const char *tcodes[] = { 425 [0x0] = "QW req", [0x1] = "BW req", 426 [0x2] = "W resp", [0x3] = "-reserved-", 427 [0x4] = "QR req", [0x5] = "BR req", 428 [0x6] = "QR resp", [0x7] = "BR resp", 429 [0x8] = "cycle start", [0x9] = "Lk req", 430 [0xa] = "async stream packet", [0xb] = "Lk resp", 431 [0xc] = "-reserved-", [0xd] = "-reserved-", 432 [0xe] = "link internal", [0xf] = "-reserved-", 433 }; 434 435 static void log_ar_at_event(char dir, int speed, u32 *header, int evt) 436 { 437 int tcode = header[0] >> 4 & 0xf; 438 char specific[12]; 439 440 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR))) 441 return; 442 443 if (unlikely(evt >= ARRAY_SIZE(evts))) 444 evt = 0x1f; 445 446 if (evt == OHCI1394_evt_bus_reset) { 447 fw_notify("A%c evt_bus_reset, generation %d\n", 448 dir, (header[2] >> 16) & 0xff); 449 return; 450 } 451 452 switch (tcode) { 453 case 0x0: case 0x6: case 0x8: 454 snprintf(specific, sizeof(specific), " = %08x", 455 be32_to_cpu((__force __be32)header[3])); 456 break; 457 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb: 458 snprintf(specific, sizeof(specific), " %x,%x", 459 header[3] >> 16, header[3] & 0xffff); 460 break; 461 default: 462 specific[0] = '\0'; 463 } 464 465 switch (tcode) { 466 case 0xa: 467 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]); 468 break; 469 case 0xe: 470 fw_notify("A%c %s, PHY %08x %08x\n", 471 dir, evts[evt], header[1], header[2]); 472 break; 473 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9: 474 fw_notify("A%c spd %x tl %02x, " 475 "%04x -> %04x, %s, " 476 "%s, %04x%08x%s\n", 477 dir, speed, header[0] >> 10 & 0x3f, 478 header[1] >> 16, header[0] >> 16, evts[evt], 479 tcodes[tcode], header[1] & 0xffff, header[2], specific); 480 break; 481 default: 482 fw_notify("A%c spd %x tl %02x, " 483 "%04x -> %04x, %s, " 484 "%s%s\n", 485 dir, speed, header[0] >> 10 & 0x3f, 486 header[1] >> 16, header[0] >> 16, evts[evt], 487 tcodes[tcode], specific); 488 } 489 } 490 491 #else 492 493 #define param_debug 0 494 static inline void log_irqs(u32 evt) {} 495 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {} 496 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {} 497 498 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */ 499 500 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) 501 { 502 writel(data, ohci->registers + offset); 503 } 504 505 static inline u32 reg_read(const struct fw_ohci *ohci, int offset) 506 { 507 return readl(ohci->registers + offset); 508 } 509 510 static inline void flush_writes(const struct fw_ohci *ohci) 511 { 512 /* Do a dummy read to flush writes. */ 513 reg_read(ohci, OHCI1394_Version); 514 } 515 516 static int read_phy_reg(struct fw_ohci *ohci, int addr) 517 { 518 u32 val; 519 int i; 520 521 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); 522 for (i = 0; i < 3 + 100; i++) { 523 val = reg_read(ohci, OHCI1394_PhyControl); 524 if (val & OHCI1394_PhyControl_ReadDone) 525 return OHCI1394_PhyControl_ReadData(val); 526 527 /* 528 * Try a few times without waiting. Sleeping is necessary 529 * only when the link/PHY interface is busy. 530 */ 531 if (i >= 3) 532 msleep(1); 533 } 534 fw_error("failed to read phy reg\n"); 535 536 return -EBUSY; 537 } 538 539 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val) 540 { 541 int i; 542 543 reg_write(ohci, OHCI1394_PhyControl, 544 OHCI1394_PhyControl_Write(addr, val)); 545 for (i = 0; i < 3 + 100; i++) { 546 val = reg_read(ohci, OHCI1394_PhyControl); 547 if (!(val & OHCI1394_PhyControl_WritePending)) 548 return 0; 549 550 if (i >= 3) 551 msleep(1); 552 } 553 fw_error("failed to write phy reg\n"); 554 555 return -EBUSY; 556 } 557 558 static int update_phy_reg(struct fw_ohci *ohci, int addr, 559 int clear_bits, int set_bits) 560 { 561 int ret = read_phy_reg(ohci, addr); 562 if (ret < 0) 563 return ret; 564 565 /* 566 * The interrupt status bits are cleared by writing a one bit. 567 * Avoid clearing them unless explicitly requested in set_bits. 568 */ 569 if (addr == 5) 570 clear_bits |= PHY_INT_STATUS_BITS; 571 572 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits); 573 } 574 575 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr) 576 { 577 int ret; 578 579 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5); 580 if (ret < 0) 581 return ret; 582 583 return read_phy_reg(ohci, addr); 584 } 585 586 static int ohci_read_phy_reg(struct fw_card *card, int addr) 587 { 588 struct fw_ohci *ohci = fw_ohci(card); 589 int ret; 590 591 mutex_lock(&ohci->phy_reg_mutex); 592 ret = read_phy_reg(ohci, addr); 593 mutex_unlock(&ohci->phy_reg_mutex); 594 595 return ret; 596 } 597 598 static int ohci_update_phy_reg(struct fw_card *card, int addr, 599 int clear_bits, int set_bits) 600 { 601 struct fw_ohci *ohci = fw_ohci(card); 602 int ret; 603 604 mutex_lock(&ohci->phy_reg_mutex); 605 ret = update_phy_reg(ohci, addr, clear_bits, set_bits); 606 mutex_unlock(&ohci->phy_reg_mutex); 607 608 return ret; 609 } 610 611 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i) 612 { 613 return page_private(ctx->pages[i]); 614 } 615 616 static void ar_context_link_page(struct ar_context *ctx, unsigned int index) 617 { 618 struct descriptor *d; 619 620 d = &ctx->descriptors[index]; 621 d->branch_address &= cpu_to_le32(~0xf); 622 d->res_count = cpu_to_le16(PAGE_SIZE); 623 d->transfer_status = 0; 624 625 wmb(); /* finish init of new descriptors before branch_address update */ 626 d = &ctx->descriptors[ctx->last_buffer_index]; 627 d->branch_address |= cpu_to_le32(1); 628 629 ctx->last_buffer_index = index; 630 631 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 632 flush_writes(ctx->ohci); 633 } 634 635 static void ar_context_release(struct ar_context *ctx) 636 { 637 unsigned int i; 638 639 if (ctx->buffer) 640 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES); 641 642 for (i = 0; i < AR_BUFFERS; i++) 643 if (ctx->pages[i]) { 644 dma_unmap_page(ctx->ohci->card.device, 645 ar_buffer_bus(ctx, i), 646 PAGE_SIZE, DMA_FROM_DEVICE); 647 __free_page(ctx->pages[i]); 648 } 649 } 650 651 static void ar_context_abort(struct ar_context *ctx, const char *error_msg) 652 { 653 if (reg_read(ctx->ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) { 654 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 655 flush_writes(ctx->ohci); 656 657 fw_error("AR error: %s; DMA stopped\n", error_msg); 658 } 659 /* FIXME: restart? */ 660 } 661 662 static inline unsigned int ar_next_buffer_index(unsigned int index) 663 { 664 return (index + 1) % AR_BUFFERS; 665 } 666 667 static inline unsigned int ar_prev_buffer_index(unsigned int index) 668 { 669 return (index - 1 + AR_BUFFERS) % AR_BUFFERS; 670 } 671 672 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx) 673 { 674 return ar_next_buffer_index(ctx->last_buffer_index); 675 } 676 677 /* 678 * We search for the buffer that contains the last AR packet DMA data written 679 * by the controller. 680 */ 681 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx, 682 unsigned int *buffer_offset) 683 { 684 unsigned int i, next_i, last = ctx->last_buffer_index; 685 __le16 res_count, next_res_count; 686 687 i = ar_first_buffer_index(ctx); 688 res_count = ACCESS_ONCE(ctx->descriptors[i].res_count); 689 690 /* A buffer that is not yet completely filled must be the last one. */ 691 while (i != last && res_count == 0) { 692 693 /* Peek at the next descriptor. */ 694 next_i = ar_next_buffer_index(i); 695 rmb(); /* read descriptors in order */ 696 next_res_count = ACCESS_ONCE( 697 ctx->descriptors[next_i].res_count); 698 /* 699 * If the next descriptor is still empty, we must stop at this 700 * descriptor. 701 */ 702 if (next_res_count == cpu_to_le16(PAGE_SIZE)) { 703 /* 704 * The exception is when the DMA data for one packet is 705 * split over three buffers; in this case, the middle 706 * buffer's descriptor might be never updated by the 707 * controller and look still empty, and we have to peek 708 * at the third one. 709 */ 710 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) { 711 next_i = ar_next_buffer_index(next_i); 712 rmb(); 713 next_res_count = ACCESS_ONCE( 714 ctx->descriptors[next_i].res_count); 715 if (next_res_count != cpu_to_le16(PAGE_SIZE)) 716 goto next_buffer_is_active; 717 } 718 719 break; 720 } 721 722 next_buffer_is_active: 723 i = next_i; 724 res_count = next_res_count; 725 } 726 727 rmb(); /* read res_count before the DMA data */ 728 729 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count); 730 if (*buffer_offset > PAGE_SIZE) { 731 *buffer_offset = 0; 732 ar_context_abort(ctx, "corrupted descriptor"); 733 } 734 735 return i; 736 } 737 738 static void ar_sync_buffers_for_cpu(struct ar_context *ctx, 739 unsigned int end_buffer_index, 740 unsigned int end_buffer_offset) 741 { 742 unsigned int i; 743 744 i = ar_first_buffer_index(ctx); 745 while (i != end_buffer_index) { 746 dma_sync_single_for_cpu(ctx->ohci->card.device, 747 ar_buffer_bus(ctx, i), 748 PAGE_SIZE, DMA_FROM_DEVICE); 749 i = ar_next_buffer_index(i); 750 } 751 if (end_buffer_offset > 0) 752 dma_sync_single_for_cpu(ctx->ohci->card.device, 753 ar_buffer_bus(ctx, i), 754 end_buffer_offset, DMA_FROM_DEVICE); 755 } 756 757 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) 758 #define cond_le32_to_cpu(v) \ 759 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v)) 760 #else 761 #define cond_le32_to_cpu(v) le32_to_cpu(v) 762 #endif 763 764 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) 765 { 766 struct fw_ohci *ohci = ctx->ohci; 767 struct fw_packet p; 768 u32 status, length, tcode; 769 int evt; 770 771 p.header[0] = cond_le32_to_cpu(buffer[0]); 772 p.header[1] = cond_le32_to_cpu(buffer[1]); 773 p.header[2] = cond_le32_to_cpu(buffer[2]); 774 775 tcode = (p.header[0] >> 4) & 0x0f; 776 switch (tcode) { 777 case TCODE_WRITE_QUADLET_REQUEST: 778 case TCODE_READ_QUADLET_RESPONSE: 779 p.header[3] = (__force __u32) buffer[3]; 780 p.header_length = 16; 781 p.payload_length = 0; 782 break; 783 784 case TCODE_READ_BLOCK_REQUEST : 785 p.header[3] = cond_le32_to_cpu(buffer[3]); 786 p.header_length = 16; 787 p.payload_length = 0; 788 break; 789 790 case TCODE_WRITE_BLOCK_REQUEST: 791 case TCODE_READ_BLOCK_RESPONSE: 792 case TCODE_LOCK_REQUEST: 793 case TCODE_LOCK_RESPONSE: 794 p.header[3] = cond_le32_to_cpu(buffer[3]); 795 p.header_length = 16; 796 p.payload_length = p.header[3] >> 16; 797 if (p.payload_length > MAX_ASYNC_PAYLOAD) { 798 ar_context_abort(ctx, "invalid packet length"); 799 return NULL; 800 } 801 break; 802 803 case TCODE_WRITE_RESPONSE: 804 case TCODE_READ_QUADLET_REQUEST: 805 case OHCI_TCODE_PHY_PACKET: 806 p.header_length = 12; 807 p.payload_length = 0; 808 break; 809 810 default: 811 ar_context_abort(ctx, "invalid tcode"); 812 return NULL; 813 } 814 815 p.payload = (void *) buffer + p.header_length; 816 817 /* FIXME: What to do about evt_* errors? */ 818 length = (p.header_length + p.payload_length + 3) / 4; 819 status = cond_le32_to_cpu(buffer[length]); 820 evt = (status >> 16) & 0x1f; 821 822 p.ack = evt - 16; 823 p.speed = (status >> 21) & 0x7; 824 p.timestamp = status & 0xffff; 825 p.generation = ohci->request_generation; 826 827 log_ar_at_event('R', p.speed, p.header, evt); 828 829 /* 830 * Several controllers, notably from NEC and VIA, forget to 831 * write ack_complete status at PHY packet reception. 832 */ 833 if (evt == OHCI1394_evt_no_status && 834 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4)) 835 p.ack = ACK_COMPLETE; 836 837 /* 838 * The OHCI bus reset handler synthesizes a PHY packet with 839 * the new generation number when a bus reset happens (see 840 * section 8.4.2.3). This helps us determine when a request 841 * was received and make sure we send the response in the same 842 * generation. We only need this for requests; for responses 843 * we use the unique tlabel for finding the matching 844 * request. 845 * 846 * Alas some chips sometimes emit bus reset packets with a 847 * wrong generation. We set the correct generation for these 848 * at a slightly incorrect time (in bus_reset_tasklet). 849 */ 850 if (evt == OHCI1394_evt_bus_reset) { 851 if (!(ohci->quirks & QUIRK_RESET_PACKET)) 852 ohci->request_generation = (p.header[2] >> 16) & 0xff; 853 } else if (ctx == &ohci->ar_request_ctx) { 854 fw_core_handle_request(&ohci->card, &p); 855 } else { 856 fw_core_handle_response(&ohci->card, &p); 857 } 858 859 return buffer + length + 1; 860 } 861 862 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end) 863 { 864 void *next; 865 866 while (p < end) { 867 next = handle_ar_packet(ctx, p); 868 if (!next) 869 return p; 870 p = next; 871 } 872 873 return p; 874 } 875 876 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer) 877 { 878 unsigned int i; 879 880 i = ar_first_buffer_index(ctx); 881 while (i != end_buffer) { 882 dma_sync_single_for_device(ctx->ohci->card.device, 883 ar_buffer_bus(ctx, i), 884 PAGE_SIZE, DMA_FROM_DEVICE); 885 ar_context_link_page(ctx, i); 886 i = ar_next_buffer_index(i); 887 } 888 } 889 890 static void ar_context_tasklet(unsigned long data) 891 { 892 struct ar_context *ctx = (struct ar_context *)data; 893 unsigned int end_buffer_index, end_buffer_offset; 894 void *p, *end; 895 896 p = ctx->pointer; 897 if (!p) 898 return; 899 900 end_buffer_index = ar_search_last_active_buffer(ctx, 901 &end_buffer_offset); 902 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset); 903 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset; 904 905 if (end_buffer_index < ar_first_buffer_index(ctx)) { 906 /* 907 * The filled part of the overall buffer wraps around; handle 908 * all packets up to the buffer end here. If the last packet 909 * wraps around, its tail will be visible after the buffer end 910 * because the buffer start pages are mapped there again. 911 */ 912 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE; 913 p = handle_ar_packets(ctx, p, buffer_end); 914 if (p < buffer_end) 915 goto error; 916 /* adjust p to point back into the actual buffer */ 917 p -= AR_BUFFERS * PAGE_SIZE; 918 } 919 920 p = handle_ar_packets(ctx, p, end); 921 if (p != end) { 922 if (p > end) 923 ar_context_abort(ctx, "inconsistent descriptor"); 924 goto error; 925 } 926 927 ctx->pointer = p; 928 ar_recycle_buffers(ctx, end_buffer_index); 929 930 return; 931 932 error: 933 ctx->pointer = NULL; 934 } 935 936 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, 937 unsigned int descriptors_offset, u32 regs) 938 { 939 unsigned int i; 940 dma_addr_t dma_addr; 941 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES]; 942 struct descriptor *d; 943 944 ctx->regs = regs; 945 ctx->ohci = ohci; 946 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); 947 948 for (i = 0; i < AR_BUFFERS; i++) { 949 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32); 950 if (!ctx->pages[i]) 951 goto out_of_memory; 952 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i], 953 0, PAGE_SIZE, DMA_FROM_DEVICE); 954 if (dma_mapping_error(ohci->card.device, dma_addr)) { 955 __free_page(ctx->pages[i]); 956 ctx->pages[i] = NULL; 957 goto out_of_memory; 958 } 959 set_page_private(ctx->pages[i], dma_addr); 960 } 961 962 for (i = 0; i < AR_BUFFERS; i++) 963 pages[i] = ctx->pages[i]; 964 for (i = 0; i < AR_WRAPAROUND_PAGES; i++) 965 pages[AR_BUFFERS + i] = ctx->pages[i]; 966 ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES, 967 -1, PAGE_KERNEL); 968 if (!ctx->buffer) 969 goto out_of_memory; 970 971 ctx->descriptors = ohci->misc_buffer + descriptors_offset; 972 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset; 973 974 for (i = 0; i < AR_BUFFERS; i++) { 975 d = &ctx->descriptors[i]; 976 d->req_count = cpu_to_le16(PAGE_SIZE); 977 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 978 DESCRIPTOR_STATUS | 979 DESCRIPTOR_BRANCH_ALWAYS); 980 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i)); 981 d->branch_address = cpu_to_le32(ctx->descriptors_bus + 982 ar_next_buffer_index(i) * sizeof(struct descriptor)); 983 } 984 985 return 0; 986 987 out_of_memory: 988 ar_context_release(ctx); 989 990 return -ENOMEM; 991 } 992 993 static void ar_context_run(struct ar_context *ctx) 994 { 995 unsigned int i; 996 997 for (i = 0; i < AR_BUFFERS; i++) 998 ar_context_link_page(ctx, i); 999 1000 ctx->pointer = ctx->buffer; 1001 1002 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1); 1003 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); 1004 flush_writes(ctx->ohci); 1005 } 1006 1007 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z) 1008 { 1009 int b, key; 1010 1011 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2; 1012 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8; 1013 1014 /* figure out which descriptor the branch address goes in */ 1015 if (z == 2 && (b == 3 || key == 2)) 1016 return d; 1017 else 1018 return d + z - 1; 1019 } 1020 1021 static void context_tasklet(unsigned long data) 1022 { 1023 struct context *ctx = (struct context *) data; 1024 struct descriptor *d, *last; 1025 u32 address; 1026 int z; 1027 struct descriptor_buffer *desc; 1028 1029 desc = list_entry(ctx->buffer_list.next, 1030 struct descriptor_buffer, list); 1031 last = ctx->last; 1032 while (last->branch_address != 0) { 1033 struct descriptor_buffer *old_desc = desc; 1034 address = le32_to_cpu(last->branch_address); 1035 z = address & 0xf; 1036 address &= ~0xf; 1037 1038 /* If the branch address points to a buffer outside of the 1039 * current buffer, advance to the next buffer. */ 1040 if (address < desc->buffer_bus || 1041 address >= desc->buffer_bus + desc->used) 1042 desc = list_entry(desc->list.next, 1043 struct descriptor_buffer, list); 1044 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d); 1045 last = find_branch_descriptor(d, z); 1046 1047 if (!ctx->callback(ctx, d, last)) 1048 break; 1049 1050 if (old_desc != desc) { 1051 /* If we've advanced to the next buffer, move the 1052 * previous buffer to the free list. */ 1053 unsigned long flags; 1054 old_desc->used = 0; 1055 spin_lock_irqsave(&ctx->ohci->lock, flags); 1056 list_move_tail(&old_desc->list, &ctx->buffer_list); 1057 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1058 } 1059 ctx->last = last; 1060 } 1061 } 1062 1063 /* 1064 * Allocate a new buffer and add it to the list of free buffers for this 1065 * context. Must be called with ohci->lock held. 1066 */ 1067 static int context_add_buffer(struct context *ctx) 1068 { 1069 struct descriptor_buffer *desc; 1070 dma_addr_t uninitialized_var(bus_addr); 1071 int offset; 1072 1073 /* 1074 * 16MB of descriptors should be far more than enough for any DMA 1075 * program. This will catch run-away userspace or DoS attacks. 1076 */ 1077 if (ctx->total_allocation >= 16*1024*1024) 1078 return -ENOMEM; 1079 1080 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE, 1081 &bus_addr, GFP_ATOMIC); 1082 if (!desc) 1083 return -ENOMEM; 1084 1085 offset = (void *)&desc->buffer - (void *)desc; 1086 desc->buffer_size = PAGE_SIZE - offset; 1087 desc->buffer_bus = bus_addr + offset; 1088 desc->used = 0; 1089 1090 list_add_tail(&desc->list, &ctx->buffer_list); 1091 ctx->total_allocation += PAGE_SIZE; 1092 1093 return 0; 1094 } 1095 1096 static int context_init(struct context *ctx, struct fw_ohci *ohci, 1097 u32 regs, descriptor_callback_t callback) 1098 { 1099 ctx->ohci = ohci; 1100 ctx->regs = regs; 1101 ctx->total_allocation = 0; 1102 1103 INIT_LIST_HEAD(&ctx->buffer_list); 1104 if (context_add_buffer(ctx) < 0) 1105 return -ENOMEM; 1106 1107 ctx->buffer_tail = list_entry(ctx->buffer_list.next, 1108 struct descriptor_buffer, list); 1109 1110 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); 1111 ctx->callback = callback; 1112 1113 /* 1114 * We put a dummy descriptor in the buffer that has a NULL 1115 * branch address and looks like it's been sent. That way we 1116 * have a descriptor to append DMA programs to. 1117 */ 1118 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer)); 1119 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST); 1120 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011); 1121 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer); 1122 ctx->last = ctx->buffer_tail->buffer; 1123 ctx->prev = ctx->buffer_tail->buffer; 1124 1125 return 0; 1126 } 1127 1128 static void context_release(struct context *ctx) 1129 { 1130 struct fw_card *card = &ctx->ohci->card; 1131 struct descriptor_buffer *desc, *tmp; 1132 1133 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list) 1134 dma_free_coherent(card->device, PAGE_SIZE, desc, 1135 desc->buffer_bus - 1136 ((void *)&desc->buffer - (void *)desc)); 1137 } 1138 1139 /* Must be called with ohci->lock held */ 1140 static struct descriptor *context_get_descriptors(struct context *ctx, 1141 int z, dma_addr_t *d_bus) 1142 { 1143 struct descriptor *d = NULL; 1144 struct descriptor_buffer *desc = ctx->buffer_tail; 1145 1146 if (z * sizeof(*d) > desc->buffer_size) 1147 return NULL; 1148 1149 if (z * sizeof(*d) > desc->buffer_size - desc->used) { 1150 /* No room for the descriptor in this buffer, so advance to the 1151 * next one. */ 1152 1153 if (desc->list.next == &ctx->buffer_list) { 1154 /* If there is no free buffer next in the list, 1155 * allocate one. */ 1156 if (context_add_buffer(ctx) < 0) 1157 return NULL; 1158 } 1159 desc = list_entry(desc->list.next, 1160 struct descriptor_buffer, list); 1161 ctx->buffer_tail = desc; 1162 } 1163 1164 d = desc->buffer + desc->used / sizeof(*d); 1165 memset(d, 0, z * sizeof(*d)); 1166 *d_bus = desc->buffer_bus + desc->used; 1167 1168 return d; 1169 } 1170 1171 static void context_run(struct context *ctx, u32 extra) 1172 { 1173 struct fw_ohci *ohci = ctx->ohci; 1174 1175 reg_write(ohci, COMMAND_PTR(ctx->regs), 1176 le32_to_cpu(ctx->last->branch_address)); 1177 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); 1178 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); 1179 ctx->running = true; 1180 flush_writes(ohci); 1181 } 1182 1183 static void context_append(struct context *ctx, 1184 struct descriptor *d, int z, int extra) 1185 { 1186 dma_addr_t d_bus; 1187 struct descriptor_buffer *desc = ctx->buffer_tail; 1188 1189 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d); 1190 1191 desc->used += (z + extra) * sizeof(*d); 1192 1193 wmb(); /* finish init of new descriptors before branch_address update */ 1194 ctx->prev->branch_address = cpu_to_le32(d_bus | z); 1195 ctx->prev = find_branch_descriptor(d, z); 1196 1197 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 1198 flush_writes(ctx->ohci); 1199 } 1200 1201 static void context_stop(struct context *ctx) 1202 { 1203 u32 reg; 1204 int i; 1205 1206 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 1207 ctx->running = false; 1208 flush_writes(ctx->ohci); 1209 1210 for (i = 0; i < 10; i++) { 1211 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs)); 1212 if ((reg & CONTEXT_ACTIVE) == 0) 1213 return; 1214 1215 mdelay(1); 1216 } 1217 fw_error("Error: DMA context still active (0x%08x)\n", reg); 1218 } 1219 1220 struct driver_data { 1221 struct fw_packet *packet; 1222 }; 1223 1224 /* 1225 * This function apppends a packet to the DMA queue for transmission. 1226 * Must always be called with the ochi->lock held to ensure proper 1227 * generation handling and locking around packet queue manipulation. 1228 */ 1229 static int at_context_queue_packet(struct context *ctx, 1230 struct fw_packet *packet) 1231 { 1232 struct fw_ohci *ohci = ctx->ohci; 1233 dma_addr_t d_bus, uninitialized_var(payload_bus); 1234 struct driver_data *driver_data; 1235 struct descriptor *d, *last; 1236 __le32 *header; 1237 int z, tcode; 1238 1239 d = context_get_descriptors(ctx, 4, &d_bus); 1240 if (d == NULL) { 1241 packet->ack = RCODE_SEND_ERROR; 1242 return -1; 1243 } 1244 1245 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 1246 d[0].res_count = cpu_to_le16(packet->timestamp); 1247 1248 /* 1249 * The DMA format for asyncronous link packets is different 1250 * from the IEEE1394 layout, so shift the fields around 1251 * accordingly. 1252 */ 1253 1254 tcode = (packet->header[0] >> 4) & 0x0f; 1255 header = (__le32 *) &d[1]; 1256 switch (tcode) { 1257 case TCODE_WRITE_QUADLET_REQUEST: 1258 case TCODE_WRITE_BLOCK_REQUEST: 1259 case TCODE_WRITE_RESPONSE: 1260 case TCODE_READ_QUADLET_REQUEST: 1261 case TCODE_READ_BLOCK_REQUEST: 1262 case TCODE_READ_QUADLET_RESPONSE: 1263 case TCODE_READ_BLOCK_RESPONSE: 1264 case TCODE_LOCK_REQUEST: 1265 case TCODE_LOCK_RESPONSE: 1266 header[0] = cpu_to_le32((packet->header[0] & 0xffff) | 1267 (packet->speed << 16)); 1268 header[1] = cpu_to_le32((packet->header[1] & 0xffff) | 1269 (packet->header[0] & 0xffff0000)); 1270 header[2] = cpu_to_le32(packet->header[2]); 1271 1272 if (TCODE_IS_BLOCK_PACKET(tcode)) 1273 header[3] = cpu_to_le32(packet->header[3]); 1274 else 1275 header[3] = (__force __le32) packet->header[3]; 1276 1277 d[0].req_count = cpu_to_le16(packet->header_length); 1278 break; 1279 1280 case TCODE_LINK_INTERNAL: 1281 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) | 1282 (packet->speed << 16)); 1283 header[1] = cpu_to_le32(packet->header[1]); 1284 header[2] = cpu_to_le32(packet->header[2]); 1285 d[0].req_count = cpu_to_le16(12); 1286 1287 if (is_ping_packet(&packet->header[1])) 1288 d[0].control |= cpu_to_le16(DESCRIPTOR_PING); 1289 break; 1290 1291 case TCODE_STREAM_DATA: 1292 header[0] = cpu_to_le32((packet->header[0] & 0xffff) | 1293 (packet->speed << 16)); 1294 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000); 1295 d[0].req_count = cpu_to_le16(8); 1296 break; 1297 1298 default: 1299 /* BUG(); */ 1300 packet->ack = RCODE_SEND_ERROR; 1301 return -1; 1302 } 1303 1304 driver_data = (struct driver_data *) &d[3]; 1305 driver_data->packet = packet; 1306 packet->driver_data = driver_data; 1307 1308 if (packet->payload_length > 0) { 1309 payload_bus = 1310 dma_map_single(ohci->card.device, packet->payload, 1311 packet->payload_length, DMA_TO_DEVICE); 1312 if (dma_mapping_error(ohci->card.device, payload_bus)) { 1313 packet->ack = RCODE_SEND_ERROR; 1314 return -1; 1315 } 1316 packet->payload_bus = payload_bus; 1317 packet->payload_mapped = true; 1318 1319 d[2].req_count = cpu_to_le16(packet->payload_length); 1320 d[2].data_address = cpu_to_le32(payload_bus); 1321 last = &d[2]; 1322 z = 3; 1323 } else { 1324 last = &d[0]; 1325 z = 2; 1326 } 1327 1328 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 1329 DESCRIPTOR_IRQ_ALWAYS | 1330 DESCRIPTOR_BRANCH_ALWAYS); 1331 1332 /* FIXME: Document how the locking works. */ 1333 if (ohci->generation != packet->generation) { 1334 if (packet->payload_mapped) 1335 dma_unmap_single(ohci->card.device, payload_bus, 1336 packet->payload_length, DMA_TO_DEVICE); 1337 packet->ack = RCODE_GENERATION; 1338 return -1; 1339 } 1340 1341 context_append(ctx, d, z, 4 - z); 1342 1343 if (!ctx->running) 1344 context_run(ctx, 0); 1345 1346 return 0; 1347 } 1348 1349 static void at_context_flush(struct context *ctx) 1350 { 1351 tasklet_disable(&ctx->tasklet); 1352 1353 ctx->flushing = true; 1354 context_tasklet((unsigned long)ctx); 1355 ctx->flushing = false; 1356 1357 tasklet_enable(&ctx->tasklet); 1358 } 1359 1360 static int handle_at_packet(struct context *context, 1361 struct descriptor *d, 1362 struct descriptor *last) 1363 { 1364 struct driver_data *driver_data; 1365 struct fw_packet *packet; 1366 struct fw_ohci *ohci = context->ohci; 1367 int evt; 1368 1369 if (last->transfer_status == 0 && !context->flushing) 1370 /* This descriptor isn't done yet, stop iteration. */ 1371 return 0; 1372 1373 driver_data = (struct driver_data *) &d[3]; 1374 packet = driver_data->packet; 1375 if (packet == NULL) 1376 /* This packet was cancelled, just continue. */ 1377 return 1; 1378 1379 if (packet->payload_mapped) 1380 dma_unmap_single(ohci->card.device, packet->payload_bus, 1381 packet->payload_length, DMA_TO_DEVICE); 1382 1383 evt = le16_to_cpu(last->transfer_status) & 0x1f; 1384 packet->timestamp = le16_to_cpu(last->res_count); 1385 1386 log_ar_at_event('T', packet->speed, packet->header, evt); 1387 1388 switch (evt) { 1389 case OHCI1394_evt_timeout: 1390 /* Async response transmit timed out. */ 1391 packet->ack = RCODE_CANCELLED; 1392 break; 1393 1394 case OHCI1394_evt_flushed: 1395 /* 1396 * The packet was flushed should give same error as 1397 * when we try to use a stale generation count. 1398 */ 1399 packet->ack = RCODE_GENERATION; 1400 break; 1401 1402 case OHCI1394_evt_missing_ack: 1403 if (context->flushing) 1404 packet->ack = RCODE_GENERATION; 1405 else { 1406 /* 1407 * Using a valid (current) generation count, but the 1408 * node is not on the bus or not sending acks. 1409 */ 1410 packet->ack = RCODE_NO_ACK; 1411 } 1412 break; 1413 1414 case ACK_COMPLETE + 0x10: 1415 case ACK_PENDING + 0x10: 1416 case ACK_BUSY_X + 0x10: 1417 case ACK_BUSY_A + 0x10: 1418 case ACK_BUSY_B + 0x10: 1419 case ACK_DATA_ERROR + 0x10: 1420 case ACK_TYPE_ERROR + 0x10: 1421 packet->ack = evt - 0x10; 1422 break; 1423 1424 case OHCI1394_evt_no_status: 1425 if (context->flushing) { 1426 packet->ack = RCODE_GENERATION; 1427 break; 1428 } 1429 /* fall through */ 1430 1431 default: 1432 packet->ack = RCODE_SEND_ERROR; 1433 break; 1434 } 1435 1436 packet->callback(packet, &ohci->card, packet->ack); 1437 1438 return 1; 1439 } 1440 1441 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff) 1442 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f) 1443 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff) 1444 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff) 1445 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff) 1446 1447 static void handle_local_rom(struct fw_ohci *ohci, 1448 struct fw_packet *packet, u32 csr) 1449 { 1450 struct fw_packet response; 1451 int tcode, length, i; 1452 1453 tcode = HEADER_GET_TCODE(packet->header[0]); 1454 if (TCODE_IS_BLOCK_PACKET(tcode)) 1455 length = HEADER_GET_DATA_LENGTH(packet->header[3]); 1456 else 1457 length = 4; 1458 1459 i = csr - CSR_CONFIG_ROM; 1460 if (i + length > CONFIG_ROM_SIZE) { 1461 fw_fill_response(&response, packet->header, 1462 RCODE_ADDRESS_ERROR, NULL, 0); 1463 } else if (!TCODE_IS_READ_REQUEST(tcode)) { 1464 fw_fill_response(&response, packet->header, 1465 RCODE_TYPE_ERROR, NULL, 0); 1466 } else { 1467 fw_fill_response(&response, packet->header, RCODE_COMPLETE, 1468 (void *) ohci->config_rom + i, length); 1469 } 1470 1471 fw_core_handle_response(&ohci->card, &response); 1472 } 1473 1474 static void handle_local_lock(struct fw_ohci *ohci, 1475 struct fw_packet *packet, u32 csr) 1476 { 1477 struct fw_packet response; 1478 int tcode, length, ext_tcode, sel, try; 1479 __be32 *payload, lock_old; 1480 u32 lock_arg, lock_data; 1481 1482 tcode = HEADER_GET_TCODE(packet->header[0]); 1483 length = HEADER_GET_DATA_LENGTH(packet->header[3]); 1484 payload = packet->payload; 1485 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]); 1486 1487 if (tcode == TCODE_LOCK_REQUEST && 1488 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { 1489 lock_arg = be32_to_cpu(payload[0]); 1490 lock_data = be32_to_cpu(payload[1]); 1491 } else if (tcode == TCODE_READ_QUADLET_REQUEST) { 1492 lock_arg = 0; 1493 lock_data = 0; 1494 } else { 1495 fw_fill_response(&response, packet->header, 1496 RCODE_TYPE_ERROR, NULL, 0); 1497 goto out; 1498 } 1499 1500 sel = (csr - CSR_BUS_MANAGER_ID) / 4; 1501 reg_write(ohci, OHCI1394_CSRData, lock_data); 1502 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); 1503 reg_write(ohci, OHCI1394_CSRControl, sel); 1504 1505 for (try = 0; try < 20; try++) 1506 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) { 1507 lock_old = cpu_to_be32(reg_read(ohci, 1508 OHCI1394_CSRData)); 1509 fw_fill_response(&response, packet->header, 1510 RCODE_COMPLETE, 1511 &lock_old, sizeof(lock_old)); 1512 goto out; 1513 } 1514 1515 fw_error("swap not done (CSR lock timeout)\n"); 1516 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0); 1517 1518 out: 1519 fw_core_handle_response(&ohci->card, &response); 1520 } 1521 1522 static void handle_local_request(struct context *ctx, struct fw_packet *packet) 1523 { 1524 u64 offset, csr; 1525 1526 if (ctx == &ctx->ohci->at_request_ctx) { 1527 packet->ack = ACK_PENDING; 1528 packet->callback(packet, &ctx->ohci->card, packet->ack); 1529 } 1530 1531 offset = 1532 ((unsigned long long) 1533 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) | 1534 packet->header[2]; 1535 csr = offset - CSR_REGISTER_BASE; 1536 1537 /* Handle config rom reads. */ 1538 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) 1539 handle_local_rom(ctx->ohci, packet, csr); 1540 else switch (csr) { 1541 case CSR_BUS_MANAGER_ID: 1542 case CSR_BANDWIDTH_AVAILABLE: 1543 case CSR_CHANNELS_AVAILABLE_HI: 1544 case CSR_CHANNELS_AVAILABLE_LO: 1545 handle_local_lock(ctx->ohci, packet, csr); 1546 break; 1547 default: 1548 if (ctx == &ctx->ohci->at_request_ctx) 1549 fw_core_handle_request(&ctx->ohci->card, packet); 1550 else 1551 fw_core_handle_response(&ctx->ohci->card, packet); 1552 break; 1553 } 1554 1555 if (ctx == &ctx->ohci->at_response_ctx) { 1556 packet->ack = ACK_COMPLETE; 1557 packet->callback(packet, &ctx->ohci->card, packet->ack); 1558 } 1559 } 1560 1561 static void at_context_transmit(struct context *ctx, struct fw_packet *packet) 1562 { 1563 unsigned long flags; 1564 int ret; 1565 1566 spin_lock_irqsave(&ctx->ohci->lock, flags); 1567 1568 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id && 1569 ctx->ohci->generation == packet->generation) { 1570 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1571 handle_local_request(ctx, packet); 1572 return; 1573 } 1574 1575 ret = at_context_queue_packet(ctx, packet); 1576 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1577 1578 if (ret < 0) 1579 packet->callback(packet, &ctx->ohci->card, packet->ack); 1580 1581 } 1582 1583 static void detect_dead_context(struct fw_ohci *ohci, 1584 const char *name, unsigned int regs) 1585 { 1586 u32 ctl; 1587 1588 ctl = reg_read(ohci, CONTROL_SET(regs)); 1589 if (ctl & CONTEXT_DEAD) { 1590 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG 1591 fw_error("DMA context %s has stopped, error code: %s\n", 1592 name, evts[ctl & 0x1f]); 1593 #else 1594 fw_error("DMA context %s has stopped, error code: %#x\n", 1595 name, ctl & 0x1f); 1596 #endif 1597 } 1598 } 1599 1600 static void handle_dead_contexts(struct fw_ohci *ohci) 1601 { 1602 unsigned int i; 1603 char name[8]; 1604 1605 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase); 1606 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase); 1607 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase); 1608 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase); 1609 for (i = 0; i < 32; ++i) { 1610 if (!(ohci->it_context_support & (1 << i))) 1611 continue; 1612 sprintf(name, "IT%u", i); 1613 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i)); 1614 } 1615 for (i = 0; i < 32; ++i) { 1616 if (!(ohci->ir_context_support & (1 << i))) 1617 continue; 1618 sprintf(name, "IR%u", i); 1619 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i)); 1620 } 1621 /* TODO: maybe try to flush and restart the dead contexts */ 1622 } 1623 1624 static u32 cycle_timer_ticks(u32 cycle_timer) 1625 { 1626 u32 ticks; 1627 1628 ticks = cycle_timer & 0xfff; 1629 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff); 1630 ticks += (3072 * 8000) * (cycle_timer >> 25); 1631 1632 return ticks; 1633 } 1634 1635 /* 1636 * Some controllers exhibit one or more of the following bugs when updating the 1637 * iso cycle timer register: 1638 * - When the lowest six bits are wrapping around to zero, a read that happens 1639 * at the same time will return garbage in the lowest ten bits. 1640 * - When the cycleOffset field wraps around to zero, the cycleCount field is 1641 * not incremented for about 60 ns. 1642 * - Occasionally, the entire register reads zero. 1643 * 1644 * To catch these, we read the register three times and ensure that the 1645 * difference between each two consecutive reads is approximately the same, i.e. 1646 * less than twice the other. Furthermore, any negative difference indicates an 1647 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to 1648 * execute, so we have enough precision to compute the ratio of the differences.) 1649 */ 1650 static u32 get_cycle_time(struct fw_ohci *ohci) 1651 { 1652 u32 c0, c1, c2; 1653 u32 t0, t1, t2; 1654 s32 diff01, diff12; 1655 int i; 1656 1657 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1658 1659 if (ohci->quirks & QUIRK_CYCLE_TIMER) { 1660 i = 0; 1661 c1 = c2; 1662 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1663 do { 1664 c0 = c1; 1665 c1 = c2; 1666 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1667 t0 = cycle_timer_ticks(c0); 1668 t1 = cycle_timer_ticks(c1); 1669 t2 = cycle_timer_ticks(c2); 1670 diff01 = t1 - t0; 1671 diff12 = t2 - t1; 1672 } while ((diff01 <= 0 || diff12 <= 0 || 1673 diff01 / diff12 >= 2 || diff12 / diff01 >= 2) 1674 && i++ < 20); 1675 } 1676 1677 return c2; 1678 } 1679 1680 /* 1681 * This function has to be called at least every 64 seconds. The bus_time 1682 * field stores not only the upper 25 bits of the BUS_TIME register but also 1683 * the most significant bit of the cycle timer in bit 6 so that we can detect 1684 * changes in this bit. 1685 */ 1686 static u32 update_bus_time(struct fw_ohci *ohci) 1687 { 1688 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25; 1689 1690 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40)) 1691 ohci->bus_time += 0x40; 1692 1693 return ohci->bus_time | cycle_time_seconds; 1694 } 1695 1696 static void bus_reset_tasklet(unsigned long data) 1697 { 1698 struct fw_ohci *ohci = (struct fw_ohci *)data; 1699 int self_id_count, i, j, reg; 1700 int generation, new_generation; 1701 unsigned long flags; 1702 void *free_rom = NULL; 1703 dma_addr_t free_rom_bus = 0; 1704 bool is_new_root; 1705 1706 reg = reg_read(ohci, OHCI1394_NodeID); 1707 if (!(reg & OHCI1394_NodeID_idValid)) { 1708 fw_notify("node ID not valid, new bus reset in progress\n"); 1709 return; 1710 } 1711 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { 1712 fw_notify("malconfigured bus\n"); 1713 return; 1714 } 1715 ohci->node_id = reg & (OHCI1394_NodeID_busNumber | 1716 OHCI1394_NodeID_nodeNumber); 1717 1718 is_new_root = (reg & OHCI1394_NodeID_root) != 0; 1719 if (!(ohci->is_root && is_new_root)) 1720 reg_write(ohci, OHCI1394_LinkControlSet, 1721 OHCI1394_LinkControl_cycleMaster); 1722 ohci->is_root = is_new_root; 1723 1724 reg = reg_read(ohci, OHCI1394_SelfIDCount); 1725 if (reg & OHCI1394_SelfIDCount_selfIDError) { 1726 fw_notify("inconsistent self IDs\n"); 1727 return; 1728 } 1729 /* 1730 * The count in the SelfIDCount register is the number of 1731 * bytes in the self ID receive buffer. Since we also receive 1732 * the inverted quadlets and a header quadlet, we shift one 1733 * bit extra to get the actual number of self IDs. 1734 */ 1735 self_id_count = (reg >> 3) & 0xff; 1736 if (self_id_count == 0 || self_id_count > 252) { 1737 fw_notify("inconsistent self IDs\n"); 1738 return; 1739 } 1740 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff; 1741 rmb(); 1742 1743 for (i = 1, j = 0; j < self_id_count; i += 2, j++) { 1744 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) { 1745 fw_notify("inconsistent self IDs\n"); 1746 return; 1747 } 1748 ohci->self_id_buffer[j] = 1749 cond_le32_to_cpu(ohci->self_id_cpu[i]); 1750 } 1751 rmb(); 1752 1753 /* 1754 * Check the consistency of the self IDs we just read. The 1755 * problem we face is that a new bus reset can start while we 1756 * read out the self IDs from the DMA buffer. If this happens, 1757 * the DMA buffer will be overwritten with new self IDs and we 1758 * will read out inconsistent data. The OHCI specification 1759 * (section 11.2) recommends a technique similar to 1760 * linux/seqlock.h, where we remember the generation of the 1761 * self IDs in the buffer before reading them out and compare 1762 * it to the current generation after reading them out. If 1763 * the two generations match we know we have a consistent set 1764 * of self IDs. 1765 */ 1766 1767 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; 1768 if (new_generation != generation) { 1769 fw_notify("recursive bus reset detected, " 1770 "discarding self ids\n"); 1771 return; 1772 } 1773 1774 /* FIXME: Document how the locking works. */ 1775 spin_lock_irqsave(&ohci->lock, flags); 1776 1777 ohci->generation = -1; /* prevent AT packet queueing */ 1778 context_stop(&ohci->at_request_ctx); 1779 context_stop(&ohci->at_response_ctx); 1780 1781 spin_unlock_irqrestore(&ohci->lock, flags); 1782 1783 /* 1784 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent 1785 * packets in the AT queues and software needs to drain them. 1786 * Some OHCI 1.1 controllers (JMicron) apparently require this too. 1787 */ 1788 at_context_flush(&ohci->at_request_ctx); 1789 at_context_flush(&ohci->at_response_ctx); 1790 1791 spin_lock_irqsave(&ohci->lock, flags); 1792 1793 ohci->generation = generation; 1794 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); 1795 1796 if (ohci->quirks & QUIRK_RESET_PACKET) 1797 ohci->request_generation = generation; 1798 1799 /* 1800 * This next bit is unrelated to the AT context stuff but we 1801 * have to do it under the spinlock also. If a new config rom 1802 * was set up before this reset, the old one is now no longer 1803 * in use and we can free it. Update the config rom pointers 1804 * to point to the current config rom and clear the 1805 * next_config_rom pointer so a new update can take place. 1806 */ 1807 1808 if (ohci->next_config_rom != NULL) { 1809 if (ohci->next_config_rom != ohci->config_rom) { 1810 free_rom = ohci->config_rom; 1811 free_rom_bus = ohci->config_rom_bus; 1812 } 1813 ohci->config_rom = ohci->next_config_rom; 1814 ohci->config_rom_bus = ohci->next_config_rom_bus; 1815 ohci->next_config_rom = NULL; 1816 1817 /* 1818 * Restore config_rom image and manually update 1819 * config_rom registers. Writing the header quadlet 1820 * will indicate that the config rom is ready, so we 1821 * do that last. 1822 */ 1823 reg_write(ohci, OHCI1394_BusOptions, 1824 be32_to_cpu(ohci->config_rom[2])); 1825 ohci->config_rom[0] = ohci->next_header; 1826 reg_write(ohci, OHCI1394_ConfigROMhdr, 1827 be32_to_cpu(ohci->next_header)); 1828 } 1829 1830 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA 1831 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0); 1832 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0); 1833 #endif 1834 1835 spin_unlock_irqrestore(&ohci->lock, flags); 1836 1837 if (free_rom) 1838 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 1839 free_rom, free_rom_bus); 1840 1841 log_selfids(ohci->node_id, generation, 1842 self_id_count, ohci->self_id_buffer); 1843 1844 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, 1845 self_id_count, ohci->self_id_buffer, 1846 ohci->csr_state_setclear_abdicate); 1847 ohci->csr_state_setclear_abdicate = false; 1848 } 1849 1850 static irqreturn_t irq_handler(int irq, void *data) 1851 { 1852 struct fw_ohci *ohci = data; 1853 u32 event, iso_event; 1854 int i; 1855 1856 event = reg_read(ohci, OHCI1394_IntEventClear); 1857 1858 if (!event || !~event) 1859 return IRQ_NONE; 1860 1861 /* 1862 * busReset and postedWriteErr must not be cleared yet 1863 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1) 1864 */ 1865 reg_write(ohci, OHCI1394_IntEventClear, 1866 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr)); 1867 log_irqs(event); 1868 1869 if (event & OHCI1394_selfIDComplete) 1870 tasklet_schedule(&ohci->bus_reset_tasklet); 1871 1872 if (event & OHCI1394_RQPkt) 1873 tasklet_schedule(&ohci->ar_request_ctx.tasklet); 1874 1875 if (event & OHCI1394_RSPkt) 1876 tasklet_schedule(&ohci->ar_response_ctx.tasklet); 1877 1878 if (event & OHCI1394_reqTxComplete) 1879 tasklet_schedule(&ohci->at_request_ctx.tasklet); 1880 1881 if (event & OHCI1394_respTxComplete) 1882 tasklet_schedule(&ohci->at_response_ctx.tasklet); 1883 1884 if (event & OHCI1394_isochRx) { 1885 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); 1886 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); 1887 1888 while (iso_event) { 1889 i = ffs(iso_event) - 1; 1890 tasklet_schedule( 1891 &ohci->ir_context_list[i].context.tasklet); 1892 iso_event &= ~(1 << i); 1893 } 1894 } 1895 1896 if (event & OHCI1394_isochTx) { 1897 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); 1898 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); 1899 1900 while (iso_event) { 1901 i = ffs(iso_event) - 1; 1902 tasklet_schedule( 1903 &ohci->it_context_list[i].context.tasklet); 1904 iso_event &= ~(1 << i); 1905 } 1906 } 1907 1908 if (unlikely(event & OHCI1394_regAccessFail)) 1909 fw_error("Register access failure - " 1910 "please notify linux1394-devel@lists.sf.net\n"); 1911 1912 if (unlikely(event & OHCI1394_postedWriteErr)) { 1913 reg_read(ohci, OHCI1394_PostedWriteAddressHi); 1914 reg_read(ohci, OHCI1394_PostedWriteAddressLo); 1915 reg_write(ohci, OHCI1394_IntEventClear, 1916 OHCI1394_postedWriteErr); 1917 fw_error("PCI posted write error\n"); 1918 } 1919 1920 if (unlikely(event & OHCI1394_cycleTooLong)) { 1921 if (printk_ratelimit()) 1922 fw_notify("isochronous cycle too long\n"); 1923 reg_write(ohci, OHCI1394_LinkControlSet, 1924 OHCI1394_LinkControl_cycleMaster); 1925 } 1926 1927 if (unlikely(event & OHCI1394_cycleInconsistent)) { 1928 /* 1929 * We need to clear this event bit in order to make 1930 * cycleMatch isochronous I/O work. In theory we should 1931 * stop active cycleMatch iso contexts now and restart 1932 * them at least two cycles later. (FIXME?) 1933 */ 1934 if (printk_ratelimit()) 1935 fw_notify("isochronous cycle inconsistent\n"); 1936 } 1937 1938 if (unlikely(event & OHCI1394_unrecoverableError)) 1939 handle_dead_contexts(ohci); 1940 1941 if (event & OHCI1394_cycle64Seconds) { 1942 spin_lock(&ohci->lock); 1943 update_bus_time(ohci); 1944 spin_unlock(&ohci->lock); 1945 } else 1946 flush_writes(ohci); 1947 1948 return IRQ_HANDLED; 1949 } 1950 1951 static int software_reset(struct fw_ohci *ohci) 1952 { 1953 int i; 1954 1955 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); 1956 1957 for (i = 0; i < OHCI_LOOP_COUNT; i++) { 1958 if ((reg_read(ohci, OHCI1394_HCControlSet) & 1959 OHCI1394_HCControl_softReset) == 0) 1960 return 0; 1961 msleep(1); 1962 } 1963 1964 return -EBUSY; 1965 } 1966 1967 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length) 1968 { 1969 size_t size = length * 4; 1970 1971 memcpy(dest, src, size); 1972 if (size < CONFIG_ROM_SIZE) 1973 memset(&dest[length], 0, CONFIG_ROM_SIZE - size); 1974 } 1975 1976 static int configure_1394a_enhancements(struct fw_ohci *ohci) 1977 { 1978 bool enable_1394a; 1979 int ret, clear, set, offset; 1980 1981 /* Check if the driver should configure link and PHY. */ 1982 if (!(reg_read(ohci, OHCI1394_HCControlSet) & 1983 OHCI1394_HCControl_programPhyEnable)) 1984 return 0; 1985 1986 /* Paranoia: check whether the PHY supports 1394a, too. */ 1987 enable_1394a = false; 1988 ret = read_phy_reg(ohci, 2); 1989 if (ret < 0) 1990 return ret; 1991 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) { 1992 ret = read_paged_phy_reg(ohci, 1, 8); 1993 if (ret < 0) 1994 return ret; 1995 if (ret >= 1) 1996 enable_1394a = true; 1997 } 1998 1999 if (ohci->quirks & QUIRK_NO_1394A) 2000 enable_1394a = false; 2001 2002 /* Configure PHY and link consistently. */ 2003 if (enable_1394a) { 2004 clear = 0; 2005 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2006 } else { 2007 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2008 set = 0; 2009 } 2010 ret = update_phy_reg(ohci, 5, clear, set); 2011 if (ret < 0) 2012 return ret; 2013 2014 if (enable_1394a) 2015 offset = OHCI1394_HCControlSet; 2016 else 2017 offset = OHCI1394_HCControlClear; 2018 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable); 2019 2020 /* Clean up: configuration has been taken care of. */ 2021 reg_write(ohci, OHCI1394_HCControlClear, 2022 OHCI1394_HCControl_programPhyEnable); 2023 2024 return 0; 2025 } 2026 2027 static int ohci_enable(struct fw_card *card, 2028 const __be32 *config_rom, size_t length) 2029 { 2030 struct fw_ohci *ohci = fw_ohci(card); 2031 struct pci_dev *dev = to_pci_dev(card->device); 2032 u32 lps, seconds, version, irqs; 2033 int i, ret; 2034 2035 if (software_reset(ohci)) { 2036 fw_error("Failed to reset ohci card.\n"); 2037 return -EBUSY; 2038 } 2039 2040 /* 2041 * Now enable LPS, which we need in order to start accessing 2042 * most of the registers. In fact, on some cards (ALI M5251), 2043 * accessing registers in the SClk domain without LPS enabled 2044 * will lock up the machine. Wait 50msec to make sure we have 2045 * full link enabled. However, with some cards (well, at least 2046 * a JMicron PCIe card), we have to try again sometimes. 2047 */ 2048 reg_write(ohci, OHCI1394_HCControlSet, 2049 OHCI1394_HCControl_LPS | 2050 OHCI1394_HCControl_postedWriteEnable); 2051 flush_writes(ohci); 2052 2053 for (lps = 0, i = 0; !lps && i < 3; i++) { 2054 msleep(50); 2055 lps = reg_read(ohci, OHCI1394_HCControlSet) & 2056 OHCI1394_HCControl_LPS; 2057 } 2058 2059 if (!lps) { 2060 fw_error("Failed to set Link Power Status\n"); 2061 return -EIO; 2062 } 2063 2064 reg_write(ohci, OHCI1394_HCControlClear, 2065 OHCI1394_HCControl_noByteSwapData); 2066 2067 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); 2068 reg_write(ohci, OHCI1394_LinkControlSet, 2069 OHCI1394_LinkControl_rcvSelfID | 2070 OHCI1394_LinkControl_rcvPhyPkt | 2071 OHCI1394_LinkControl_cycleTimerEnable | 2072 OHCI1394_LinkControl_cycleMaster); 2073 2074 reg_write(ohci, OHCI1394_ATRetries, 2075 OHCI1394_MAX_AT_REQ_RETRIES | 2076 (OHCI1394_MAX_AT_RESP_RETRIES << 4) | 2077 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) | 2078 (200 << 16)); 2079 2080 seconds = lower_32_bits(get_seconds()); 2081 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25); 2082 ohci->bus_time = seconds & ~0x3f; 2083 2084 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 2085 if (version >= OHCI_VERSION_1_1) { 2086 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi, 2087 0xfffffffe); 2088 card->broadcast_channel_auto_allocated = true; 2089 } 2090 2091 /* Get implemented bits of the priority arbitration request counter. */ 2092 reg_write(ohci, OHCI1394_FairnessControl, 0x3f); 2093 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f; 2094 reg_write(ohci, OHCI1394_FairnessControl, 0); 2095 card->priority_budget_implemented = ohci->pri_req_max != 0; 2096 2097 ar_context_run(&ohci->ar_request_ctx); 2098 ar_context_run(&ohci->ar_response_ctx); 2099 2100 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000); 2101 reg_write(ohci, OHCI1394_IntEventClear, ~0); 2102 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 2103 2104 ret = configure_1394a_enhancements(ohci); 2105 if (ret < 0) 2106 return ret; 2107 2108 /* Activate link_on bit and contender bit in our self ID packets.*/ 2109 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER); 2110 if (ret < 0) 2111 return ret; 2112 2113 /* 2114 * When the link is not yet enabled, the atomic config rom 2115 * update mechanism described below in ohci_set_config_rom() 2116 * is not active. We have to update ConfigRomHeader and 2117 * BusOptions manually, and the write to ConfigROMmap takes 2118 * effect immediately. We tie this to the enabling of the 2119 * link, so we have a valid config rom before enabling - the 2120 * OHCI requires that ConfigROMhdr and BusOptions have valid 2121 * values before enabling. 2122 * 2123 * However, when the ConfigROMmap is written, some controllers 2124 * always read back quadlets 0 and 2 from the config rom to 2125 * the ConfigRomHeader and BusOptions registers on bus reset. 2126 * They shouldn't do that in this initial case where the link 2127 * isn't enabled. This means we have to use the same 2128 * workaround here, setting the bus header to 0 and then write 2129 * the right values in the bus reset tasklet. 2130 */ 2131 2132 if (config_rom) { 2133 ohci->next_config_rom = 2134 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2135 &ohci->next_config_rom_bus, 2136 GFP_KERNEL); 2137 if (ohci->next_config_rom == NULL) 2138 return -ENOMEM; 2139 2140 copy_config_rom(ohci->next_config_rom, config_rom, length); 2141 } else { 2142 /* 2143 * In the suspend case, config_rom is NULL, which 2144 * means that we just reuse the old config rom. 2145 */ 2146 ohci->next_config_rom = ohci->config_rom; 2147 ohci->next_config_rom_bus = ohci->config_rom_bus; 2148 } 2149 2150 ohci->next_header = ohci->next_config_rom[0]; 2151 ohci->next_config_rom[0] = 0; 2152 reg_write(ohci, OHCI1394_ConfigROMhdr, 0); 2153 reg_write(ohci, OHCI1394_BusOptions, 2154 be32_to_cpu(ohci->next_config_rom[2])); 2155 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2156 2157 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); 2158 2159 if (!(ohci->quirks & QUIRK_NO_MSI)) 2160 pci_enable_msi(dev); 2161 if (request_irq(dev->irq, irq_handler, 2162 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED, 2163 ohci_driver_name, ohci)) { 2164 fw_error("Failed to allocate interrupt %d.\n", dev->irq); 2165 pci_disable_msi(dev); 2166 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2167 ohci->config_rom, ohci->config_rom_bus); 2168 return -EIO; 2169 } 2170 2171 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete | 2172 OHCI1394_RQPkt | OHCI1394_RSPkt | 2173 OHCI1394_isochTx | OHCI1394_isochRx | 2174 OHCI1394_postedWriteErr | 2175 OHCI1394_selfIDComplete | 2176 OHCI1394_regAccessFail | 2177 OHCI1394_cycle64Seconds | 2178 OHCI1394_cycleInconsistent | 2179 OHCI1394_unrecoverableError | 2180 OHCI1394_cycleTooLong | 2181 OHCI1394_masterIntEnable; 2182 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS) 2183 irqs |= OHCI1394_busReset; 2184 reg_write(ohci, OHCI1394_IntMaskSet, irqs); 2185 2186 reg_write(ohci, OHCI1394_HCControlSet, 2187 OHCI1394_HCControl_linkEnable | 2188 OHCI1394_HCControl_BIBimageValid); 2189 flush_writes(ohci); 2190 2191 /* We are ready to go, reset bus to finish initialization. */ 2192 fw_schedule_bus_reset(&ohci->card, false, true); 2193 2194 return 0; 2195 } 2196 2197 static int ohci_set_config_rom(struct fw_card *card, 2198 const __be32 *config_rom, size_t length) 2199 { 2200 struct fw_ohci *ohci; 2201 unsigned long flags; 2202 int ret = -EBUSY; 2203 __be32 *next_config_rom; 2204 dma_addr_t uninitialized_var(next_config_rom_bus); 2205 2206 ohci = fw_ohci(card); 2207 2208 /* 2209 * When the OHCI controller is enabled, the config rom update 2210 * mechanism is a bit tricky, but easy enough to use. See 2211 * section 5.5.6 in the OHCI specification. 2212 * 2213 * The OHCI controller caches the new config rom address in a 2214 * shadow register (ConfigROMmapNext) and needs a bus reset 2215 * for the changes to take place. When the bus reset is 2216 * detected, the controller loads the new values for the 2217 * ConfigRomHeader and BusOptions registers from the specified 2218 * config rom and loads ConfigROMmap from the ConfigROMmapNext 2219 * shadow register. All automatically and atomically. 2220 * 2221 * Now, there's a twist to this story. The automatic load of 2222 * ConfigRomHeader and BusOptions doesn't honor the 2223 * noByteSwapData bit, so with a be32 config rom, the 2224 * controller will load be32 values in to these registers 2225 * during the atomic update, even on litte endian 2226 * architectures. The workaround we use is to put a 0 in the 2227 * header quadlet; 0 is endian agnostic and means that the 2228 * config rom isn't ready yet. In the bus reset tasklet we 2229 * then set up the real values for the two registers. 2230 * 2231 * We use ohci->lock to avoid racing with the code that sets 2232 * ohci->next_config_rom to NULL (see bus_reset_tasklet). 2233 */ 2234 2235 next_config_rom = 2236 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2237 &next_config_rom_bus, GFP_KERNEL); 2238 if (next_config_rom == NULL) 2239 return -ENOMEM; 2240 2241 spin_lock_irqsave(&ohci->lock, flags); 2242 2243 if (ohci->next_config_rom == NULL) { 2244 ohci->next_config_rom = next_config_rom; 2245 ohci->next_config_rom_bus = next_config_rom_bus; 2246 2247 copy_config_rom(ohci->next_config_rom, config_rom, length); 2248 2249 ohci->next_header = config_rom[0]; 2250 ohci->next_config_rom[0] = 0; 2251 2252 reg_write(ohci, OHCI1394_ConfigROMmap, 2253 ohci->next_config_rom_bus); 2254 ret = 0; 2255 } 2256 2257 spin_unlock_irqrestore(&ohci->lock, flags); 2258 2259 /* 2260 * Now initiate a bus reset to have the changes take 2261 * effect. We clean up the old config rom memory and DMA 2262 * mappings in the bus reset tasklet, since the OHCI 2263 * controller could need to access it before the bus reset 2264 * takes effect. 2265 */ 2266 if (ret == 0) 2267 fw_schedule_bus_reset(&ohci->card, true, true); 2268 else 2269 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2270 next_config_rom, next_config_rom_bus); 2271 2272 return ret; 2273 } 2274 2275 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) 2276 { 2277 struct fw_ohci *ohci = fw_ohci(card); 2278 2279 at_context_transmit(&ohci->at_request_ctx, packet); 2280 } 2281 2282 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) 2283 { 2284 struct fw_ohci *ohci = fw_ohci(card); 2285 2286 at_context_transmit(&ohci->at_response_ctx, packet); 2287 } 2288 2289 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) 2290 { 2291 struct fw_ohci *ohci = fw_ohci(card); 2292 struct context *ctx = &ohci->at_request_ctx; 2293 struct driver_data *driver_data = packet->driver_data; 2294 int ret = -ENOENT; 2295 2296 tasklet_disable(&ctx->tasklet); 2297 2298 if (packet->ack != 0) 2299 goto out; 2300 2301 if (packet->payload_mapped) 2302 dma_unmap_single(ohci->card.device, packet->payload_bus, 2303 packet->payload_length, DMA_TO_DEVICE); 2304 2305 log_ar_at_event('T', packet->speed, packet->header, 0x20); 2306 driver_data->packet = NULL; 2307 packet->ack = RCODE_CANCELLED; 2308 packet->callback(packet, &ohci->card, packet->ack); 2309 ret = 0; 2310 out: 2311 tasklet_enable(&ctx->tasklet); 2312 2313 return ret; 2314 } 2315 2316 static int ohci_enable_phys_dma(struct fw_card *card, 2317 int node_id, int generation) 2318 { 2319 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA 2320 return 0; 2321 #else 2322 struct fw_ohci *ohci = fw_ohci(card); 2323 unsigned long flags; 2324 int n, ret = 0; 2325 2326 /* 2327 * FIXME: Make sure this bitmask is cleared when we clear the busReset 2328 * interrupt bit. Clear physReqResourceAllBuses on bus reset. 2329 */ 2330 2331 spin_lock_irqsave(&ohci->lock, flags); 2332 2333 if (ohci->generation != generation) { 2334 ret = -ESTALE; 2335 goto out; 2336 } 2337 2338 /* 2339 * Note, if the node ID contains a non-local bus ID, physical DMA is 2340 * enabled for _all_ nodes on remote buses. 2341 */ 2342 2343 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; 2344 if (n < 32) 2345 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); 2346 else 2347 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); 2348 2349 flush_writes(ohci); 2350 out: 2351 spin_unlock_irqrestore(&ohci->lock, flags); 2352 2353 return ret; 2354 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */ 2355 } 2356 2357 static u32 ohci_read_csr(struct fw_card *card, int csr_offset) 2358 { 2359 struct fw_ohci *ohci = fw_ohci(card); 2360 unsigned long flags; 2361 u32 value; 2362 2363 switch (csr_offset) { 2364 case CSR_STATE_CLEAR: 2365 case CSR_STATE_SET: 2366 if (ohci->is_root && 2367 (reg_read(ohci, OHCI1394_LinkControlSet) & 2368 OHCI1394_LinkControl_cycleMaster)) 2369 value = CSR_STATE_BIT_CMSTR; 2370 else 2371 value = 0; 2372 if (ohci->csr_state_setclear_abdicate) 2373 value |= CSR_STATE_BIT_ABDICATE; 2374 2375 return value; 2376 2377 case CSR_NODE_IDS: 2378 return reg_read(ohci, OHCI1394_NodeID) << 16; 2379 2380 case CSR_CYCLE_TIME: 2381 return get_cycle_time(ohci); 2382 2383 case CSR_BUS_TIME: 2384 /* 2385 * We might be called just after the cycle timer has wrapped 2386 * around but just before the cycle64Seconds handler, so we 2387 * better check here, too, if the bus time needs to be updated. 2388 */ 2389 spin_lock_irqsave(&ohci->lock, flags); 2390 value = update_bus_time(ohci); 2391 spin_unlock_irqrestore(&ohci->lock, flags); 2392 return value; 2393 2394 case CSR_BUSY_TIMEOUT: 2395 value = reg_read(ohci, OHCI1394_ATRetries); 2396 return (value >> 4) & 0x0ffff00f; 2397 2398 case CSR_PRIORITY_BUDGET: 2399 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) | 2400 (ohci->pri_req_max << 8); 2401 2402 default: 2403 WARN_ON(1); 2404 return 0; 2405 } 2406 } 2407 2408 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value) 2409 { 2410 struct fw_ohci *ohci = fw_ohci(card); 2411 unsigned long flags; 2412 2413 switch (csr_offset) { 2414 case CSR_STATE_CLEAR: 2415 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2416 reg_write(ohci, OHCI1394_LinkControlClear, 2417 OHCI1394_LinkControl_cycleMaster); 2418 flush_writes(ohci); 2419 } 2420 if (value & CSR_STATE_BIT_ABDICATE) 2421 ohci->csr_state_setclear_abdicate = false; 2422 break; 2423 2424 case CSR_STATE_SET: 2425 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2426 reg_write(ohci, OHCI1394_LinkControlSet, 2427 OHCI1394_LinkControl_cycleMaster); 2428 flush_writes(ohci); 2429 } 2430 if (value & CSR_STATE_BIT_ABDICATE) 2431 ohci->csr_state_setclear_abdicate = true; 2432 break; 2433 2434 case CSR_NODE_IDS: 2435 reg_write(ohci, OHCI1394_NodeID, value >> 16); 2436 flush_writes(ohci); 2437 break; 2438 2439 case CSR_CYCLE_TIME: 2440 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value); 2441 reg_write(ohci, OHCI1394_IntEventSet, 2442 OHCI1394_cycleInconsistent); 2443 flush_writes(ohci); 2444 break; 2445 2446 case CSR_BUS_TIME: 2447 spin_lock_irqsave(&ohci->lock, flags); 2448 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f); 2449 spin_unlock_irqrestore(&ohci->lock, flags); 2450 break; 2451 2452 case CSR_BUSY_TIMEOUT: 2453 value = (value & 0xf) | ((value & 0xf) << 4) | 2454 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4); 2455 reg_write(ohci, OHCI1394_ATRetries, value); 2456 flush_writes(ohci); 2457 break; 2458 2459 case CSR_PRIORITY_BUDGET: 2460 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f); 2461 flush_writes(ohci); 2462 break; 2463 2464 default: 2465 WARN_ON(1); 2466 break; 2467 } 2468 } 2469 2470 static void copy_iso_headers(struct iso_context *ctx, void *p) 2471 { 2472 int i = ctx->header_length; 2473 2474 if (i + ctx->base.header_size > PAGE_SIZE) 2475 return; 2476 2477 /* 2478 * The iso header is byteswapped to little endian by 2479 * the controller, but the remaining header quadlets 2480 * are big endian. We want to present all the headers 2481 * as big endian, so we have to swap the first quadlet. 2482 */ 2483 if (ctx->base.header_size > 0) 2484 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4)); 2485 if (ctx->base.header_size > 4) 2486 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p); 2487 if (ctx->base.header_size > 8) 2488 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8); 2489 ctx->header_length += ctx->base.header_size; 2490 } 2491 2492 static int handle_ir_packet_per_buffer(struct context *context, 2493 struct descriptor *d, 2494 struct descriptor *last) 2495 { 2496 struct iso_context *ctx = 2497 container_of(context, struct iso_context, context); 2498 struct descriptor *pd; 2499 __le32 *ir_header; 2500 void *p; 2501 2502 for (pd = d; pd <= last; pd++) 2503 if (pd->transfer_status) 2504 break; 2505 if (pd > last) 2506 /* Descriptor(s) not done yet, stop iteration */ 2507 return 0; 2508 2509 p = last + 1; 2510 copy_iso_headers(ctx, p); 2511 2512 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) { 2513 ir_header = (__le32 *) p; 2514 ctx->base.callback.sc(&ctx->base, 2515 le32_to_cpu(ir_header[0]) & 0xffff, 2516 ctx->header_length, ctx->header, 2517 ctx->base.callback_data); 2518 ctx->header_length = 0; 2519 } 2520 2521 return 1; 2522 } 2523 2524 /* d == last because each descriptor block is only a single descriptor. */ 2525 static int handle_ir_buffer_fill(struct context *context, 2526 struct descriptor *d, 2527 struct descriptor *last) 2528 { 2529 struct iso_context *ctx = 2530 container_of(context, struct iso_context, context); 2531 2532 if (!last->transfer_status) 2533 /* Descriptor(s) not done yet, stop iteration */ 2534 return 0; 2535 2536 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) 2537 ctx->base.callback.mc(&ctx->base, 2538 le32_to_cpu(last->data_address) + 2539 le16_to_cpu(last->req_count) - 2540 le16_to_cpu(last->res_count), 2541 ctx->base.callback_data); 2542 2543 return 1; 2544 } 2545 2546 static int handle_it_packet(struct context *context, 2547 struct descriptor *d, 2548 struct descriptor *last) 2549 { 2550 struct iso_context *ctx = 2551 container_of(context, struct iso_context, context); 2552 int i; 2553 struct descriptor *pd; 2554 2555 for (pd = d; pd <= last; pd++) 2556 if (pd->transfer_status) 2557 break; 2558 if (pd > last) 2559 /* Descriptor(s) not done yet, stop iteration */ 2560 return 0; 2561 2562 i = ctx->header_length; 2563 if (i + 4 < PAGE_SIZE) { 2564 /* Present this value as big-endian to match the receive code */ 2565 *(__be32 *)(ctx->header + i) = cpu_to_be32( 2566 ((u32)le16_to_cpu(pd->transfer_status) << 16) | 2567 le16_to_cpu(pd->res_count)); 2568 ctx->header_length += 4; 2569 } 2570 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) { 2571 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count), 2572 ctx->header_length, ctx->header, 2573 ctx->base.callback_data); 2574 ctx->header_length = 0; 2575 } 2576 return 1; 2577 } 2578 2579 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels) 2580 { 2581 u32 hi = channels >> 32, lo = channels; 2582 2583 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi); 2584 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo); 2585 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi); 2586 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo); 2587 mmiowb(); 2588 ohci->mc_channels = channels; 2589 } 2590 2591 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card, 2592 int type, int channel, size_t header_size) 2593 { 2594 struct fw_ohci *ohci = fw_ohci(card); 2595 struct iso_context *uninitialized_var(ctx); 2596 descriptor_callback_t uninitialized_var(callback); 2597 u64 *uninitialized_var(channels); 2598 u32 *uninitialized_var(mask), uninitialized_var(regs); 2599 unsigned long flags; 2600 int index, ret = -EBUSY; 2601 2602 spin_lock_irqsave(&ohci->lock, flags); 2603 2604 switch (type) { 2605 case FW_ISO_CONTEXT_TRANSMIT: 2606 mask = &ohci->it_context_mask; 2607 callback = handle_it_packet; 2608 index = ffs(*mask) - 1; 2609 if (index >= 0) { 2610 *mask &= ~(1 << index); 2611 regs = OHCI1394_IsoXmitContextBase(index); 2612 ctx = &ohci->it_context_list[index]; 2613 } 2614 break; 2615 2616 case FW_ISO_CONTEXT_RECEIVE: 2617 channels = &ohci->ir_context_channels; 2618 mask = &ohci->ir_context_mask; 2619 callback = handle_ir_packet_per_buffer; 2620 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1; 2621 if (index >= 0) { 2622 *channels &= ~(1ULL << channel); 2623 *mask &= ~(1 << index); 2624 regs = OHCI1394_IsoRcvContextBase(index); 2625 ctx = &ohci->ir_context_list[index]; 2626 } 2627 break; 2628 2629 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2630 mask = &ohci->ir_context_mask; 2631 callback = handle_ir_buffer_fill; 2632 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1; 2633 if (index >= 0) { 2634 ohci->mc_allocated = true; 2635 *mask &= ~(1 << index); 2636 regs = OHCI1394_IsoRcvContextBase(index); 2637 ctx = &ohci->ir_context_list[index]; 2638 } 2639 break; 2640 2641 default: 2642 index = -1; 2643 ret = -ENOSYS; 2644 } 2645 2646 spin_unlock_irqrestore(&ohci->lock, flags); 2647 2648 if (index < 0) 2649 return ERR_PTR(ret); 2650 2651 memset(ctx, 0, sizeof(*ctx)); 2652 ctx->header_length = 0; 2653 ctx->header = (void *) __get_free_page(GFP_KERNEL); 2654 if (ctx->header == NULL) { 2655 ret = -ENOMEM; 2656 goto out; 2657 } 2658 ret = context_init(&ctx->context, ohci, regs, callback); 2659 if (ret < 0) 2660 goto out_with_header; 2661 2662 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) 2663 set_multichannel_mask(ohci, 0); 2664 2665 return &ctx->base; 2666 2667 out_with_header: 2668 free_page((unsigned long)ctx->header); 2669 out: 2670 spin_lock_irqsave(&ohci->lock, flags); 2671 2672 switch (type) { 2673 case FW_ISO_CONTEXT_RECEIVE: 2674 *channels |= 1ULL << channel; 2675 break; 2676 2677 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2678 ohci->mc_allocated = false; 2679 break; 2680 } 2681 *mask |= 1 << index; 2682 2683 spin_unlock_irqrestore(&ohci->lock, flags); 2684 2685 return ERR_PTR(ret); 2686 } 2687 2688 static int ohci_start_iso(struct fw_iso_context *base, 2689 s32 cycle, u32 sync, u32 tags) 2690 { 2691 struct iso_context *ctx = container_of(base, struct iso_context, base); 2692 struct fw_ohci *ohci = ctx->context.ohci; 2693 u32 control = IR_CONTEXT_ISOCH_HEADER, match; 2694 int index; 2695 2696 /* the controller cannot start without any queued packets */ 2697 if (ctx->context.last->branch_address == 0) 2698 return -ENODATA; 2699 2700 switch (ctx->base.type) { 2701 case FW_ISO_CONTEXT_TRANSMIT: 2702 index = ctx - ohci->it_context_list; 2703 match = 0; 2704 if (cycle >= 0) 2705 match = IT_CONTEXT_CYCLE_MATCH_ENABLE | 2706 (cycle & 0x7fff) << 16; 2707 2708 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); 2709 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); 2710 context_run(&ctx->context, match); 2711 break; 2712 2713 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2714 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE; 2715 /* fall through */ 2716 case FW_ISO_CONTEXT_RECEIVE: 2717 index = ctx - ohci->ir_context_list; 2718 match = (tags << 28) | (sync << 8) | ctx->base.channel; 2719 if (cycle >= 0) { 2720 match |= (cycle & 0x07fff) << 12; 2721 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE; 2722 } 2723 2724 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); 2725 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); 2726 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match); 2727 context_run(&ctx->context, control); 2728 2729 ctx->sync = sync; 2730 ctx->tags = tags; 2731 2732 break; 2733 } 2734 2735 return 0; 2736 } 2737 2738 static int ohci_stop_iso(struct fw_iso_context *base) 2739 { 2740 struct fw_ohci *ohci = fw_ohci(base->card); 2741 struct iso_context *ctx = container_of(base, struct iso_context, base); 2742 int index; 2743 2744 switch (ctx->base.type) { 2745 case FW_ISO_CONTEXT_TRANSMIT: 2746 index = ctx - ohci->it_context_list; 2747 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); 2748 break; 2749 2750 case FW_ISO_CONTEXT_RECEIVE: 2751 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2752 index = ctx - ohci->ir_context_list; 2753 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); 2754 break; 2755 } 2756 flush_writes(ohci); 2757 context_stop(&ctx->context); 2758 tasklet_kill(&ctx->context.tasklet); 2759 2760 return 0; 2761 } 2762 2763 static void ohci_free_iso_context(struct fw_iso_context *base) 2764 { 2765 struct fw_ohci *ohci = fw_ohci(base->card); 2766 struct iso_context *ctx = container_of(base, struct iso_context, base); 2767 unsigned long flags; 2768 int index; 2769 2770 ohci_stop_iso(base); 2771 context_release(&ctx->context); 2772 free_page((unsigned long)ctx->header); 2773 2774 spin_lock_irqsave(&ohci->lock, flags); 2775 2776 switch (base->type) { 2777 case FW_ISO_CONTEXT_TRANSMIT: 2778 index = ctx - ohci->it_context_list; 2779 ohci->it_context_mask |= 1 << index; 2780 break; 2781 2782 case FW_ISO_CONTEXT_RECEIVE: 2783 index = ctx - ohci->ir_context_list; 2784 ohci->ir_context_mask |= 1 << index; 2785 ohci->ir_context_channels |= 1ULL << base->channel; 2786 break; 2787 2788 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2789 index = ctx - ohci->ir_context_list; 2790 ohci->ir_context_mask |= 1 << index; 2791 ohci->ir_context_channels |= ohci->mc_channels; 2792 ohci->mc_channels = 0; 2793 ohci->mc_allocated = false; 2794 break; 2795 } 2796 2797 spin_unlock_irqrestore(&ohci->lock, flags); 2798 } 2799 2800 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels) 2801 { 2802 struct fw_ohci *ohci = fw_ohci(base->card); 2803 unsigned long flags; 2804 int ret; 2805 2806 switch (base->type) { 2807 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2808 2809 spin_lock_irqsave(&ohci->lock, flags); 2810 2811 /* Don't allow multichannel to grab other contexts' channels. */ 2812 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) { 2813 *channels = ohci->ir_context_channels; 2814 ret = -EBUSY; 2815 } else { 2816 set_multichannel_mask(ohci, *channels); 2817 ret = 0; 2818 } 2819 2820 spin_unlock_irqrestore(&ohci->lock, flags); 2821 2822 break; 2823 default: 2824 ret = -EINVAL; 2825 } 2826 2827 return ret; 2828 } 2829 2830 #ifdef CONFIG_PM 2831 static void ohci_resume_iso_dma(struct fw_ohci *ohci) 2832 { 2833 int i; 2834 struct iso_context *ctx; 2835 2836 for (i = 0 ; i < ohci->n_ir ; i++) { 2837 ctx = &ohci->ir_context_list[i]; 2838 if (ctx->context.running) 2839 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 2840 } 2841 2842 for (i = 0 ; i < ohci->n_it ; i++) { 2843 ctx = &ohci->it_context_list[i]; 2844 if (ctx->context.running) 2845 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 2846 } 2847 } 2848 #endif 2849 2850 static int queue_iso_transmit(struct iso_context *ctx, 2851 struct fw_iso_packet *packet, 2852 struct fw_iso_buffer *buffer, 2853 unsigned long payload) 2854 { 2855 struct descriptor *d, *last, *pd; 2856 struct fw_iso_packet *p; 2857 __le32 *header; 2858 dma_addr_t d_bus, page_bus; 2859 u32 z, header_z, payload_z, irq; 2860 u32 payload_index, payload_end_index, next_page_index; 2861 int page, end_page, i, length, offset; 2862 2863 p = packet; 2864 payload_index = payload; 2865 2866 if (p->skip) 2867 z = 1; 2868 else 2869 z = 2; 2870 if (p->header_length > 0) 2871 z++; 2872 2873 /* Determine the first page the payload isn't contained in. */ 2874 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; 2875 if (p->payload_length > 0) 2876 payload_z = end_page - (payload_index >> PAGE_SHIFT); 2877 else 2878 payload_z = 0; 2879 2880 z += payload_z; 2881 2882 /* Get header size in number of descriptors. */ 2883 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d)); 2884 2885 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); 2886 if (d == NULL) 2887 return -ENOMEM; 2888 2889 if (!p->skip) { 2890 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 2891 d[0].req_count = cpu_to_le16(8); 2892 /* 2893 * Link the skip address to this descriptor itself. This causes 2894 * a context to skip a cycle whenever lost cycles or FIFO 2895 * overruns occur, without dropping the data. The application 2896 * should then decide whether this is an error condition or not. 2897 * FIXME: Make the context's cycle-lost behaviour configurable? 2898 */ 2899 d[0].branch_address = cpu_to_le32(d_bus | z); 2900 2901 header = (__le32 *) &d[1]; 2902 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) | 2903 IT_HEADER_TAG(p->tag) | 2904 IT_HEADER_TCODE(TCODE_STREAM_DATA) | 2905 IT_HEADER_CHANNEL(ctx->base.channel) | 2906 IT_HEADER_SPEED(ctx->base.speed)); 2907 header[1] = 2908 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length + 2909 p->payload_length)); 2910 } 2911 2912 if (p->header_length > 0) { 2913 d[2].req_count = cpu_to_le16(p->header_length); 2914 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d)); 2915 memcpy(&d[z], p->header, p->header_length); 2916 } 2917 2918 pd = d + z - payload_z; 2919 payload_end_index = payload_index + p->payload_length; 2920 for (i = 0; i < payload_z; i++) { 2921 page = payload_index >> PAGE_SHIFT; 2922 offset = payload_index & ~PAGE_MASK; 2923 next_page_index = (page + 1) << PAGE_SHIFT; 2924 length = 2925 min(next_page_index, payload_end_index) - payload_index; 2926 pd[i].req_count = cpu_to_le16(length); 2927 2928 page_bus = page_private(buffer->pages[page]); 2929 pd[i].data_address = cpu_to_le32(page_bus + offset); 2930 2931 payload_index += length; 2932 } 2933 2934 if (p->interrupt) 2935 irq = DESCRIPTOR_IRQ_ALWAYS; 2936 else 2937 irq = DESCRIPTOR_NO_IRQ; 2938 2939 last = z == 2 ? d : d + z - 1; 2940 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 2941 DESCRIPTOR_STATUS | 2942 DESCRIPTOR_BRANCH_ALWAYS | 2943 irq); 2944 2945 context_append(&ctx->context, d, z, header_z); 2946 2947 return 0; 2948 } 2949 2950 static int queue_iso_packet_per_buffer(struct iso_context *ctx, 2951 struct fw_iso_packet *packet, 2952 struct fw_iso_buffer *buffer, 2953 unsigned long payload) 2954 { 2955 struct descriptor *d, *pd; 2956 dma_addr_t d_bus, page_bus; 2957 u32 z, header_z, rest; 2958 int i, j, length; 2959 int page, offset, packet_count, header_size, payload_per_buffer; 2960 2961 /* 2962 * The OHCI controller puts the isochronous header and trailer in the 2963 * buffer, so we need at least 8 bytes. 2964 */ 2965 packet_count = packet->header_length / ctx->base.header_size; 2966 header_size = max(ctx->base.header_size, (size_t)8); 2967 2968 /* Get header size in number of descriptors. */ 2969 header_z = DIV_ROUND_UP(header_size, sizeof(*d)); 2970 page = payload >> PAGE_SHIFT; 2971 offset = payload & ~PAGE_MASK; 2972 payload_per_buffer = packet->payload_length / packet_count; 2973 2974 for (i = 0; i < packet_count; i++) { 2975 /* d points to the header descriptor */ 2976 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1; 2977 d = context_get_descriptors(&ctx->context, 2978 z + header_z, &d_bus); 2979 if (d == NULL) 2980 return -ENOMEM; 2981 2982 d->control = cpu_to_le16(DESCRIPTOR_STATUS | 2983 DESCRIPTOR_INPUT_MORE); 2984 if (packet->skip && i == 0) 2985 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 2986 d->req_count = cpu_to_le16(header_size); 2987 d->res_count = d->req_count; 2988 d->transfer_status = 0; 2989 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d))); 2990 2991 rest = payload_per_buffer; 2992 pd = d; 2993 for (j = 1; j < z; j++) { 2994 pd++; 2995 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 2996 DESCRIPTOR_INPUT_MORE); 2997 2998 if (offset + rest < PAGE_SIZE) 2999 length = rest; 3000 else 3001 length = PAGE_SIZE - offset; 3002 pd->req_count = cpu_to_le16(length); 3003 pd->res_count = pd->req_count; 3004 pd->transfer_status = 0; 3005 3006 page_bus = page_private(buffer->pages[page]); 3007 pd->data_address = cpu_to_le32(page_bus + offset); 3008 3009 offset = (offset + length) & ~PAGE_MASK; 3010 rest -= length; 3011 if (offset == 0) 3012 page++; 3013 } 3014 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3015 DESCRIPTOR_INPUT_LAST | 3016 DESCRIPTOR_BRANCH_ALWAYS); 3017 if (packet->interrupt && i == packet_count - 1) 3018 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3019 3020 context_append(&ctx->context, d, z, header_z); 3021 } 3022 3023 return 0; 3024 } 3025 3026 static int queue_iso_buffer_fill(struct iso_context *ctx, 3027 struct fw_iso_packet *packet, 3028 struct fw_iso_buffer *buffer, 3029 unsigned long payload) 3030 { 3031 struct descriptor *d; 3032 dma_addr_t d_bus, page_bus; 3033 int page, offset, rest, z, i, length; 3034 3035 page = payload >> PAGE_SHIFT; 3036 offset = payload & ~PAGE_MASK; 3037 rest = packet->payload_length; 3038 3039 /* We need one descriptor for each page in the buffer. */ 3040 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE); 3041 3042 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count)) 3043 return -EFAULT; 3044 3045 for (i = 0; i < z; i++) { 3046 d = context_get_descriptors(&ctx->context, 1, &d_bus); 3047 if (d == NULL) 3048 return -ENOMEM; 3049 3050 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 3051 DESCRIPTOR_BRANCH_ALWAYS); 3052 if (packet->skip && i == 0) 3053 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3054 if (packet->interrupt && i == z - 1) 3055 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3056 3057 if (offset + rest < PAGE_SIZE) 3058 length = rest; 3059 else 3060 length = PAGE_SIZE - offset; 3061 d->req_count = cpu_to_le16(length); 3062 d->res_count = d->req_count; 3063 d->transfer_status = 0; 3064 3065 page_bus = page_private(buffer->pages[page]); 3066 d->data_address = cpu_to_le32(page_bus + offset); 3067 3068 rest -= length; 3069 offset = 0; 3070 page++; 3071 3072 context_append(&ctx->context, d, 1, 0); 3073 } 3074 3075 return 0; 3076 } 3077 3078 static int ohci_queue_iso(struct fw_iso_context *base, 3079 struct fw_iso_packet *packet, 3080 struct fw_iso_buffer *buffer, 3081 unsigned long payload) 3082 { 3083 struct iso_context *ctx = container_of(base, struct iso_context, base); 3084 unsigned long flags; 3085 int ret = -ENOSYS; 3086 3087 spin_lock_irqsave(&ctx->context.ohci->lock, flags); 3088 switch (base->type) { 3089 case FW_ISO_CONTEXT_TRANSMIT: 3090 ret = queue_iso_transmit(ctx, packet, buffer, payload); 3091 break; 3092 case FW_ISO_CONTEXT_RECEIVE: 3093 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload); 3094 break; 3095 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3096 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload); 3097 break; 3098 } 3099 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags); 3100 3101 return ret; 3102 } 3103 3104 static const struct fw_card_driver ohci_driver = { 3105 .enable = ohci_enable, 3106 .read_phy_reg = ohci_read_phy_reg, 3107 .update_phy_reg = ohci_update_phy_reg, 3108 .set_config_rom = ohci_set_config_rom, 3109 .send_request = ohci_send_request, 3110 .send_response = ohci_send_response, 3111 .cancel_packet = ohci_cancel_packet, 3112 .enable_phys_dma = ohci_enable_phys_dma, 3113 .read_csr = ohci_read_csr, 3114 .write_csr = ohci_write_csr, 3115 3116 .allocate_iso_context = ohci_allocate_iso_context, 3117 .free_iso_context = ohci_free_iso_context, 3118 .set_iso_channels = ohci_set_iso_channels, 3119 .queue_iso = ohci_queue_iso, 3120 .start_iso = ohci_start_iso, 3121 .stop_iso = ohci_stop_iso, 3122 }; 3123 3124 #ifdef CONFIG_PPC_PMAC 3125 static void pmac_ohci_on(struct pci_dev *dev) 3126 { 3127 if (machine_is(powermac)) { 3128 struct device_node *ofn = pci_device_to_OF_node(dev); 3129 3130 if (ofn) { 3131 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1); 3132 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1); 3133 } 3134 } 3135 } 3136 3137 static void pmac_ohci_off(struct pci_dev *dev) 3138 { 3139 if (machine_is(powermac)) { 3140 struct device_node *ofn = pci_device_to_OF_node(dev); 3141 3142 if (ofn) { 3143 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0); 3144 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0); 3145 } 3146 } 3147 } 3148 #else 3149 static inline void pmac_ohci_on(struct pci_dev *dev) {} 3150 static inline void pmac_ohci_off(struct pci_dev *dev) {} 3151 #endif /* CONFIG_PPC_PMAC */ 3152 3153 static int __devinit pci_probe(struct pci_dev *dev, 3154 const struct pci_device_id *ent) 3155 { 3156 struct fw_ohci *ohci; 3157 u32 bus_options, max_receive, link_speed, version; 3158 u64 guid; 3159 int i, err; 3160 size_t size; 3161 3162 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL); 3163 if (ohci == NULL) { 3164 err = -ENOMEM; 3165 goto fail; 3166 } 3167 3168 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); 3169 3170 pmac_ohci_on(dev); 3171 3172 err = pci_enable_device(dev); 3173 if (err) { 3174 fw_error("Failed to enable OHCI hardware\n"); 3175 goto fail_free; 3176 } 3177 3178 pci_set_master(dev); 3179 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); 3180 pci_set_drvdata(dev, ohci); 3181 3182 spin_lock_init(&ohci->lock); 3183 mutex_init(&ohci->phy_reg_mutex); 3184 3185 tasklet_init(&ohci->bus_reset_tasklet, 3186 bus_reset_tasklet, (unsigned long)ohci); 3187 3188 err = pci_request_region(dev, 0, ohci_driver_name); 3189 if (err) { 3190 fw_error("MMIO resource unavailable\n"); 3191 goto fail_disable; 3192 } 3193 3194 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE); 3195 if (ohci->registers == NULL) { 3196 fw_error("Failed to remap registers\n"); 3197 err = -ENXIO; 3198 goto fail_iomem; 3199 } 3200 3201 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++) 3202 if ((ohci_quirks[i].vendor == dev->vendor) && 3203 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID || 3204 ohci_quirks[i].device == dev->device) && 3205 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID || 3206 ohci_quirks[i].revision >= dev->revision)) { 3207 ohci->quirks = ohci_quirks[i].flags; 3208 break; 3209 } 3210 if (param_quirks) 3211 ohci->quirks = param_quirks; 3212 3213 /* 3214 * Because dma_alloc_coherent() allocates at least one page, 3215 * we save space by using a common buffer for the AR request/ 3216 * response descriptors and the self IDs buffer. 3217 */ 3218 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4); 3219 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2); 3220 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device, 3221 PAGE_SIZE, 3222 &ohci->misc_buffer_bus, 3223 GFP_KERNEL); 3224 if (!ohci->misc_buffer) { 3225 err = -ENOMEM; 3226 goto fail_iounmap; 3227 } 3228 3229 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0, 3230 OHCI1394_AsReqRcvContextControlSet); 3231 if (err < 0) 3232 goto fail_misc_buf; 3233 3234 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4, 3235 OHCI1394_AsRspRcvContextControlSet); 3236 if (err < 0) 3237 goto fail_arreq_ctx; 3238 3239 err = context_init(&ohci->at_request_ctx, ohci, 3240 OHCI1394_AsReqTrContextControlSet, handle_at_packet); 3241 if (err < 0) 3242 goto fail_arrsp_ctx; 3243 3244 err = context_init(&ohci->at_response_ctx, ohci, 3245 OHCI1394_AsRspTrContextControlSet, handle_at_packet); 3246 if (err < 0) 3247 goto fail_atreq_ctx; 3248 3249 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); 3250 ohci->ir_context_channels = ~0ULL; 3251 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); 3252 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); 3253 ohci->ir_context_mask = ohci->ir_context_support; 3254 ohci->n_ir = hweight32(ohci->ir_context_mask); 3255 size = sizeof(struct iso_context) * ohci->n_ir; 3256 ohci->ir_context_list = kzalloc(size, GFP_KERNEL); 3257 3258 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); 3259 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); 3260 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); 3261 ohci->it_context_mask = ohci->it_context_support; 3262 ohci->n_it = hweight32(ohci->it_context_mask); 3263 size = sizeof(struct iso_context) * ohci->n_it; 3264 ohci->it_context_list = kzalloc(size, GFP_KERNEL); 3265 3266 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) { 3267 err = -ENOMEM; 3268 goto fail_contexts; 3269 } 3270 3271 ohci->self_id_cpu = ohci->misc_buffer + PAGE_SIZE/2; 3272 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2; 3273 3274 bus_options = reg_read(ohci, OHCI1394_BusOptions); 3275 max_receive = (bus_options >> 12) & 0xf; 3276 link_speed = bus_options & 0x7; 3277 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | 3278 reg_read(ohci, OHCI1394_GUIDLo); 3279 3280 err = fw_card_add(&ohci->card, max_receive, link_speed, guid); 3281 if (err) 3282 goto fail_contexts; 3283 3284 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 3285 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, " 3286 "%d IR + %d IT contexts, quirks 0x%x\n", 3287 dev_name(&dev->dev), version >> 16, version & 0xff, 3288 ohci->n_ir, ohci->n_it, ohci->quirks); 3289 3290 return 0; 3291 3292 fail_contexts: 3293 kfree(ohci->ir_context_list); 3294 kfree(ohci->it_context_list); 3295 context_release(&ohci->at_response_ctx); 3296 fail_atreq_ctx: 3297 context_release(&ohci->at_request_ctx); 3298 fail_arrsp_ctx: 3299 ar_context_release(&ohci->ar_response_ctx); 3300 fail_arreq_ctx: 3301 ar_context_release(&ohci->ar_request_ctx); 3302 fail_misc_buf: 3303 dma_free_coherent(ohci->card.device, PAGE_SIZE, 3304 ohci->misc_buffer, ohci->misc_buffer_bus); 3305 fail_iounmap: 3306 pci_iounmap(dev, ohci->registers); 3307 fail_iomem: 3308 pci_release_region(dev, 0); 3309 fail_disable: 3310 pci_disable_device(dev); 3311 fail_free: 3312 kfree(ohci); 3313 pmac_ohci_off(dev); 3314 fail: 3315 if (err == -ENOMEM) 3316 fw_error("Out of memory\n"); 3317 3318 return err; 3319 } 3320 3321 static void pci_remove(struct pci_dev *dev) 3322 { 3323 struct fw_ohci *ohci; 3324 3325 ohci = pci_get_drvdata(dev); 3326 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 3327 flush_writes(ohci); 3328 fw_core_remove_card(&ohci->card); 3329 3330 /* 3331 * FIXME: Fail all pending packets here, now that the upper 3332 * layers can't queue any more. 3333 */ 3334 3335 software_reset(ohci); 3336 free_irq(dev->irq, ohci); 3337 3338 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom) 3339 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 3340 ohci->next_config_rom, ohci->next_config_rom_bus); 3341 if (ohci->config_rom) 3342 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 3343 ohci->config_rom, ohci->config_rom_bus); 3344 ar_context_release(&ohci->ar_request_ctx); 3345 ar_context_release(&ohci->ar_response_ctx); 3346 dma_free_coherent(ohci->card.device, PAGE_SIZE, 3347 ohci->misc_buffer, ohci->misc_buffer_bus); 3348 context_release(&ohci->at_request_ctx); 3349 context_release(&ohci->at_response_ctx); 3350 kfree(ohci->it_context_list); 3351 kfree(ohci->ir_context_list); 3352 pci_disable_msi(dev); 3353 pci_iounmap(dev, ohci->registers); 3354 pci_release_region(dev, 0); 3355 pci_disable_device(dev); 3356 kfree(ohci); 3357 pmac_ohci_off(dev); 3358 3359 fw_notify("Removed fw-ohci device.\n"); 3360 } 3361 3362 #ifdef CONFIG_PM 3363 static int pci_suspend(struct pci_dev *dev, pm_message_t state) 3364 { 3365 struct fw_ohci *ohci = pci_get_drvdata(dev); 3366 int err; 3367 3368 software_reset(ohci); 3369 free_irq(dev->irq, ohci); 3370 pci_disable_msi(dev); 3371 err = pci_save_state(dev); 3372 if (err) { 3373 fw_error("pci_save_state failed\n"); 3374 return err; 3375 } 3376 err = pci_set_power_state(dev, pci_choose_state(dev, state)); 3377 if (err) 3378 fw_error("pci_set_power_state failed with %d\n", err); 3379 pmac_ohci_off(dev); 3380 3381 return 0; 3382 } 3383 3384 static int pci_resume(struct pci_dev *dev) 3385 { 3386 struct fw_ohci *ohci = pci_get_drvdata(dev); 3387 int err; 3388 3389 pmac_ohci_on(dev); 3390 pci_set_power_state(dev, PCI_D0); 3391 pci_restore_state(dev); 3392 err = pci_enable_device(dev); 3393 if (err) { 3394 fw_error("pci_enable_device failed\n"); 3395 return err; 3396 } 3397 3398 /* Some systems don't setup GUID register on resume from ram */ 3399 if (!reg_read(ohci, OHCI1394_GUIDLo) && 3400 !reg_read(ohci, OHCI1394_GUIDHi)) { 3401 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid); 3402 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32)); 3403 } 3404 3405 err = ohci_enable(&ohci->card, NULL, 0); 3406 if (err) 3407 return err; 3408 3409 ohci_resume_iso_dma(ohci); 3410 3411 return 0; 3412 } 3413 #endif 3414 3415 static const struct pci_device_id pci_table[] = { 3416 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, 3417 { } 3418 }; 3419 3420 MODULE_DEVICE_TABLE(pci, pci_table); 3421 3422 static struct pci_driver fw_ohci_pci_driver = { 3423 .name = ohci_driver_name, 3424 .id_table = pci_table, 3425 .probe = pci_probe, 3426 .remove = pci_remove, 3427 #ifdef CONFIG_PM 3428 .resume = pci_resume, 3429 .suspend = pci_suspend, 3430 #endif 3431 }; 3432 3433 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); 3434 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); 3435 MODULE_LICENSE("GPL"); 3436 3437 /* Provide a module alias so root-on-sbp2 initrds don't break. */ 3438 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE 3439 MODULE_ALIAS("ohci1394"); 3440 #endif 3441 3442 static int __init fw_ohci_init(void) 3443 { 3444 return pci_register_driver(&fw_ohci_pci_driver); 3445 } 3446 3447 static void __exit fw_ohci_cleanup(void) 3448 { 3449 pci_unregister_driver(&fw_ohci_pci_driver); 3450 } 3451 3452 module_init(fw_ohci_init); 3453 module_exit(fw_ohci_cleanup); 3454