1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for OHCI 1394 controllers 4 * 5 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/bug.h> 10 #include <linux/compiler.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/firewire.h> 15 #include <linux/firewire-constants.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/mm.h> 22 #include <linux/module.h> 23 #include <linux/moduleparam.h> 24 #include <linux/mutex.h> 25 #include <linux/pci.h> 26 #include <linux/pci_ids.h> 27 #include <linux/slab.h> 28 #include <linux/spinlock.h> 29 #include <linux/string.h> 30 #include <linux/time.h> 31 #include <linux/vmalloc.h> 32 #include <linux/workqueue.h> 33 34 #include <asm/byteorder.h> 35 #include <asm/page.h> 36 37 #ifdef CONFIG_PPC_PMAC 38 #include <asm/pmac_feature.h> 39 #endif 40 41 #include "core.h" 42 #include "ohci.h" 43 44 #define ohci_info(ohci, f, args...) dev_info(ohci->card.device, f, ##args) 45 #define ohci_notice(ohci, f, args...) dev_notice(ohci->card.device, f, ##args) 46 #define ohci_err(ohci, f, args...) dev_err(ohci->card.device, f, ##args) 47 48 #define DESCRIPTOR_OUTPUT_MORE 0 49 #define DESCRIPTOR_OUTPUT_LAST (1 << 12) 50 #define DESCRIPTOR_INPUT_MORE (2 << 12) 51 #define DESCRIPTOR_INPUT_LAST (3 << 12) 52 #define DESCRIPTOR_STATUS (1 << 11) 53 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8) 54 #define DESCRIPTOR_PING (1 << 7) 55 #define DESCRIPTOR_YY (1 << 6) 56 #define DESCRIPTOR_NO_IRQ (0 << 4) 57 #define DESCRIPTOR_IRQ_ERROR (1 << 4) 58 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4) 59 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2) 60 #define DESCRIPTOR_WAIT (3 << 0) 61 62 #define DESCRIPTOR_CMD (0xf << 12) 63 64 struct descriptor { 65 __le16 req_count; 66 __le16 control; 67 __le32 data_address; 68 __le32 branch_address; 69 __le16 res_count; 70 __le16 transfer_status; 71 } __attribute__((aligned(16))); 72 73 #define CONTROL_SET(regs) (regs) 74 #define CONTROL_CLEAR(regs) ((regs) + 4) 75 #define COMMAND_PTR(regs) ((regs) + 12) 76 #define CONTEXT_MATCH(regs) ((regs) + 16) 77 78 #define AR_BUFFER_SIZE (32*1024) 79 #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE) 80 /* we need at least two pages for proper list management */ 81 #define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2) 82 83 #define MAX_ASYNC_PAYLOAD 4096 84 #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4) 85 #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE) 86 87 struct ar_context { 88 struct fw_ohci *ohci; 89 struct page *pages[AR_BUFFERS]; 90 void *buffer; 91 struct descriptor *descriptors; 92 dma_addr_t descriptors_bus; 93 void *pointer; 94 unsigned int last_buffer_index; 95 u32 regs; 96 struct tasklet_struct tasklet; 97 }; 98 99 struct context; 100 101 typedef int (*descriptor_callback_t)(struct context *ctx, 102 struct descriptor *d, 103 struct descriptor *last); 104 105 /* 106 * A buffer that contains a block of DMA-able coherent memory used for 107 * storing a portion of a DMA descriptor program. 108 */ 109 struct descriptor_buffer { 110 struct list_head list; 111 dma_addr_t buffer_bus; 112 size_t buffer_size; 113 size_t used; 114 struct descriptor buffer[]; 115 }; 116 117 struct context { 118 struct fw_ohci *ohci; 119 u32 regs; 120 int total_allocation; 121 u32 current_bus; 122 bool running; 123 bool flushing; 124 125 /* 126 * List of page-sized buffers for storing DMA descriptors. 127 * Head of list contains buffers in use and tail of list contains 128 * free buffers. 129 */ 130 struct list_head buffer_list; 131 132 /* 133 * Pointer to a buffer inside buffer_list that contains the tail 134 * end of the current DMA program. 135 */ 136 struct descriptor_buffer *buffer_tail; 137 138 /* 139 * The descriptor containing the branch address of the first 140 * descriptor that has not yet been filled by the device. 141 */ 142 struct descriptor *last; 143 144 /* 145 * The last descriptor block in the DMA program. It contains the branch 146 * address that must be updated upon appending a new descriptor. 147 */ 148 struct descriptor *prev; 149 int prev_z; 150 151 descriptor_callback_t callback; 152 153 struct tasklet_struct tasklet; 154 }; 155 156 #define IT_HEADER_SY(v) ((v) << 0) 157 #define IT_HEADER_TCODE(v) ((v) << 4) 158 #define IT_HEADER_CHANNEL(v) ((v) << 8) 159 #define IT_HEADER_TAG(v) ((v) << 14) 160 #define IT_HEADER_SPEED(v) ((v) << 16) 161 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16) 162 163 struct iso_context { 164 struct fw_iso_context base; 165 struct context context; 166 void *header; 167 size_t header_length; 168 unsigned long flushing_completions; 169 u32 mc_buffer_bus; 170 u16 mc_completed; 171 u16 last_timestamp; 172 u8 sync; 173 u8 tags; 174 }; 175 176 #define CONFIG_ROM_SIZE 1024 177 178 struct fw_ohci { 179 struct fw_card card; 180 181 __iomem char *registers; 182 int node_id; 183 int generation; 184 int request_generation; /* for timestamping incoming requests */ 185 unsigned quirks; 186 unsigned int pri_req_max; 187 u32 bus_time; 188 bool bus_time_running; 189 bool is_root; 190 bool csr_state_setclear_abdicate; 191 int n_ir; 192 int n_it; 193 /* 194 * Spinlock for accessing fw_ohci data. Never call out of 195 * this driver with this lock held. 196 */ 197 spinlock_t lock; 198 199 struct mutex phy_reg_mutex; 200 201 void *misc_buffer; 202 dma_addr_t misc_buffer_bus; 203 204 struct ar_context ar_request_ctx; 205 struct ar_context ar_response_ctx; 206 struct context at_request_ctx; 207 struct context at_response_ctx; 208 209 u32 it_context_support; 210 u32 it_context_mask; /* unoccupied IT contexts */ 211 struct iso_context *it_context_list; 212 u64 ir_context_channels; /* unoccupied channels */ 213 u32 ir_context_support; 214 u32 ir_context_mask; /* unoccupied IR contexts */ 215 struct iso_context *ir_context_list; 216 u64 mc_channels; /* channels in use by the multichannel IR context */ 217 bool mc_allocated; 218 219 __be32 *config_rom; 220 dma_addr_t config_rom_bus; 221 __be32 *next_config_rom; 222 dma_addr_t next_config_rom_bus; 223 __be32 next_header; 224 225 __le32 *self_id; 226 dma_addr_t self_id_bus; 227 struct work_struct bus_reset_work; 228 229 u32 self_id_buffer[512]; 230 }; 231 232 static struct workqueue_struct *selfid_workqueue; 233 234 static inline struct fw_ohci *fw_ohci(struct fw_card *card) 235 { 236 return container_of(card, struct fw_ohci, card); 237 } 238 239 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 240 #define IR_CONTEXT_BUFFER_FILL 0x80000000 241 #define IR_CONTEXT_ISOCH_HEADER 0x40000000 242 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 243 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 244 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 245 246 #define CONTEXT_RUN 0x8000 247 #define CONTEXT_WAKE 0x1000 248 #define CONTEXT_DEAD 0x0800 249 #define CONTEXT_ACTIVE 0x0400 250 251 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf 252 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 253 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 254 255 #define OHCI1394_REGISTER_SIZE 0x800 256 #define OHCI1394_PCI_HCI_Control 0x40 257 #define SELF_ID_BUF_SIZE 0x800 258 #define OHCI_TCODE_PHY_PACKET 0x0e 259 #define OHCI_VERSION_1_1 0x010010 260 261 static char ohci_driver_name[] = KBUILD_MODNAME; 262 263 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd 264 #define PCI_DEVICE_ID_AGERE_FW643 0x5901 265 #define PCI_DEVICE_ID_CREATIVE_SB1394 0x4001 266 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380 267 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009 268 #define PCI_DEVICE_ID_TI_TSB12LV26 0x8020 269 #define PCI_DEVICE_ID_TI_TSB82AA2 0x8025 270 #define PCI_DEVICE_ID_VIA_VT630X 0x3044 271 #define PCI_REV_ID_VIA_VT6306 0x46 272 #define PCI_DEVICE_ID_VIA_VT6315 0x3403 273 274 #define QUIRK_CYCLE_TIMER 0x1 275 #define QUIRK_RESET_PACKET 0x2 276 #define QUIRK_BE_HEADERS 0x4 277 #define QUIRK_NO_1394A 0x8 278 #define QUIRK_NO_MSI 0x10 279 #define QUIRK_TI_SLLZ059 0x20 280 #define QUIRK_IR_WAKE 0x40 281 282 /* In case of multiple matches in ohci_quirks[], only the first one is used. */ 283 static const struct { 284 unsigned short vendor, device, revision, flags; 285 } ohci_quirks[] = { 286 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID, 287 QUIRK_CYCLE_TIMER}, 288 289 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID, 290 QUIRK_BE_HEADERS}, 291 292 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6, 293 QUIRK_NO_MSI}, 294 295 {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID, 296 QUIRK_RESET_PACKET}, 297 298 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID, 299 QUIRK_NO_MSI}, 300 301 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID, 302 QUIRK_CYCLE_TIMER}, 303 304 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID, 305 QUIRK_NO_MSI}, 306 307 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID, 308 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, 309 310 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID, 311 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A}, 312 313 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID, 314 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059}, 315 316 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID, 317 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059}, 318 319 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID, 320 QUIRK_RESET_PACKET}, 321 322 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306, 323 QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE}, 324 325 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, 0, 326 QUIRK_CYCLE_TIMER /* FIXME: necessary? */ | QUIRK_NO_MSI}, 327 328 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, PCI_ANY_ID, 329 QUIRK_NO_MSI}, 330 331 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID, 332 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, 333 }; 334 335 /* This overrides anything that was found in ohci_quirks[]. */ 336 static int param_quirks; 337 module_param_named(quirks, param_quirks, int, 0644); 338 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0" 339 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER) 340 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET) 341 ", AR/selfID endianness = " __stringify(QUIRK_BE_HEADERS) 342 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A) 343 ", disable MSI = " __stringify(QUIRK_NO_MSI) 344 ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059) 345 ", IR wake unreliable = " __stringify(QUIRK_IR_WAKE) 346 ")"); 347 348 #define OHCI_PARAM_DEBUG_AT_AR 1 349 #define OHCI_PARAM_DEBUG_SELFIDS 2 350 #define OHCI_PARAM_DEBUG_IRQS 4 351 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */ 352 353 static int param_debug; 354 module_param_named(debug, param_debug, int, 0644); 355 MODULE_PARM_DESC(debug, "Verbose logging (default = 0" 356 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR) 357 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS) 358 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS) 359 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS) 360 ", or a combination, or all = -1)"); 361 362 static bool param_remote_dma; 363 module_param_named(remote_dma, param_remote_dma, bool, 0444); 364 MODULE_PARM_DESC(remote_dma, "Enable unfiltered remote DMA (default = N)"); 365 366 static void log_irqs(struct fw_ohci *ohci, u32 evt) 367 { 368 if (likely(!(param_debug & 369 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS)))) 370 return; 371 372 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) && 373 !(evt & OHCI1394_busReset)) 374 return; 375 376 ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt, 377 evt & OHCI1394_selfIDComplete ? " selfID" : "", 378 evt & OHCI1394_RQPkt ? " AR_req" : "", 379 evt & OHCI1394_RSPkt ? " AR_resp" : "", 380 evt & OHCI1394_reqTxComplete ? " AT_req" : "", 381 evt & OHCI1394_respTxComplete ? " AT_resp" : "", 382 evt & OHCI1394_isochRx ? " IR" : "", 383 evt & OHCI1394_isochTx ? " IT" : "", 384 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", 385 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", 386 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "", 387 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "", 388 evt & OHCI1394_regAccessFail ? " regAccessFail" : "", 389 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "", 390 evt & OHCI1394_busReset ? " busReset" : "", 391 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | 392 OHCI1394_RSPkt | OHCI1394_reqTxComplete | 393 OHCI1394_respTxComplete | OHCI1394_isochRx | 394 OHCI1394_isochTx | OHCI1394_postedWriteErr | 395 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds | 396 OHCI1394_cycleInconsistent | 397 OHCI1394_regAccessFail | OHCI1394_busReset) 398 ? " ?" : ""); 399 } 400 401 static const char *speed[] = { 402 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta", 403 }; 404 static const char *power[] = { 405 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W", 406 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W", 407 }; 408 static const char port[] = { '.', '-', 'p', 'c', }; 409 410 static char _p(u32 *s, int shift) 411 { 412 return port[*s >> shift & 3]; 413 } 414 415 static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count) 416 { 417 u32 *s; 418 419 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) 420 return; 421 422 ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n", 423 self_id_count, generation, ohci->node_id); 424 425 for (s = ohci->self_id_buffer; self_id_count--; ++s) 426 if ((*s & 1 << 23) == 0) 427 ohci_notice(ohci, 428 "selfID 0: %08x, phy %d [%c%c%c] %s gc=%d %s %s%s%s\n", 429 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2), 430 speed[*s >> 14 & 3], *s >> 16 & 63, 431 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", 432 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); 433 else 434 ohci_notice(ohci, 435 "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n", 436 *s, *s >> 24 & 63, 437 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10), 438 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2)); 439 } 440 441 static const char *evts[] = { 442 [0x00] = "evt_no_status", [0x01] = "-reserved-", 443 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack", 444 [0x04] = "evt_underrun", [0x05] = "evt_overrun", 445 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read", 446 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset", 447 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err", 448 [0x0c] = "-reserved-", [0x0d] = "-reserved-", 449 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed", 450 [0x10] = "-reserved-", [0x11] = "ack_complete", 451 [0x12] = "ack_pending ", [0x13] = "-reserved-", 452 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A", 453 [0x16] = "ack_busy_B", [0x17] = "-reserved-", 454 [0x18] = "-reserved-", [0x19] = "-reserved-", 455 [0x1a] = "-reserved-", [0x1b] = "ack_tardy", 456 [0x1c] = "-reserved-", [0x1d] = "ack_data_error", 457 [0x1e] = "ack_type_error", [0x1f] = "-reserved-", 458 [0x20] = "pending/cancelled", 459 }; 460 static const char *tcodes[] = { 461 [0x0] = "QW req", [0x1] = "BW req", 462 [0x2] = "W resp", [0x3] = "-reserved-", 463 [0x4] = "QR req", [0x5] = "BR req", 464 [0x6] = "QR resp", [0x7] = "BR resp", 465 [0x8] = "cycle start", [0x9] = "Lk req", 466 [0xa] = "async stream packet", [0xb] = "Lk resp", 467 [0xc] = "-reserved-", [0xd] = "-reserved-", 468 [0xe] = "link internal", [0xf] = "-reserved-", 469 }; 470 471 static void log_ar_at_event(struct fw_ohci *ohci, 472 char dir, int speed, u32 *header, int evt) 473 { 474 int tcode = header[0] >> 4 & 0xf; 475 char specific[12]; 476 477 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR))) 478 return; 479 480 if (unlikely(evt >= ARRAY_SIZE(evts))) 481 evt = 0x1f; 482 483 if (evt == OHCI1394_evt_bus_reset) { 484 ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n", 485 dir, (header[2] >> 16) & 0xff); 486 return; 487 } 488 489 switch (tcode) { 490 case 0x0: case 0x6: case 0x8: 491 snprintf(specific, sizeof(specific), " = %08x", 492 be32_to_cpu((__force __be32)header[3])); 493 break; 494 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb: 495 snprintf(specific, sizeof(specific), " %x,%x", 496 header[3] >> 16, header[3] & 0xffff); 497 break; 498 default: 499 specific[0] = '\0'; 500 } 501 502 switch (tcode) { 503 case 0xa: 504 ohci_notice(ohci, "A%c %s, %s\n", 505 dir, evts[evt], tcodes[tcode]); 506 break; 507 case 0xe: 508 ohci_notice(ohci, "A%c %s, PHY %08x %08x\n", 509 dir, evts[evt], header[1], header[2]); 510 break; 511 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9: 512 ohci_notice(ohci, 513 "A%c spd %x tl %02x, %04x -> %04x, %s, %s, %04x%08x%s\n", 514 dir, speed, header[0] >> 10 & 0x3f, 515 header[1] >> 16, header[0] >> 16, evts[evt], 516 tcodes[tcode], header[1] & 0xffff, header[2], specific); 517 break; 518 default: 519 ohci_notice(ohci, 520 "A%c spd %x tl %02x, %04x -> %04x, %s, %s%s\n", 521 dir, speed, header[0] >> 10 & 0x3f, 522 header[1] >> 16, header[0] >> 16, evts[evt], 523 tcodes[tcode], specific); 524 } 525 } 526 527 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) 528 { 529 writel(data, ohci->registers + offset); 530 } 531 532 static inline u32 reg_read(const struct fw_ohci *ohci, int offset) 533 { 534 return readl(ohci->registers + offset); 535 } 536 537 static inline void flush_writes(const struct fw_ohci *ohci) 538 { 539 /* Do a dummy read to flush writes. */ 540 reg_read(ohci, OHCI1394_Version); 541 } 542 543 /* 544 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and 545 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex. 546 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg() 547 * directly. Exceptions are intrinsically serialized contexts like pci_probe. 548 */ 549 static int read_phy_reg(struct fw_ohci *ohci, int addr) 550 { 551 u32 val; 552 int i; 553 554 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); 555 for (i = 0; i < 3 + 100; i++) { 556 val = reg_read(ohci, OHCI1394_PhyControl); 557 if (!~val) 558 return -ENODEV; /* Card was ejected. */ 559 560 if (val & OHCI1394_PhyControl_ReadDone) 561 return OHCI1394_PhyControl_ReadData(val); 562 563 /* 564 * Try a few times without waiting. Sleeping is necessary 565 * only when the link/PHY interface is busy. 566 */ 567 if (i >= 3) 568 msleep(1); 569 } 570 ohci_err(ohci, "failed to read phy reg %d\n", addr); 571 dump_stack(); 572 573 return -EBUSY; 574 } 575 576 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val) 577 { 578 int i; 579 580 reg_write(ohci, OHCI1394_PhyControl, 581 OHCI1394_PhyControl_Write(addr, val)); 582 for (i = 0; i < 3 + 100; i++) { 583 val = reg_read(ohci, OHCI1394_PhyControl); 584 if (!~val) 585 return -ENODEV; /* Card was ejected. */ 586 587 if (!(val & OHCI1394_PhyControl_WritePending)) 588 return 0; 589 590 if (i >= 3) 591 msleep(1); 592 } 593 ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val); 594 dump_stack(); 595 596 return -EBUSY; 597 } 598 599 static int update_phy_reg(struct fw_ohci *ohci, int addr, 600 int clear_bits, int set_bits) 601 { 602 int ret = read_phy_reg(ohci, addr); 603 if (ret < 0) 604 return ret; 605 606 /* 607 * The interrupt status bits are cleared by writing a one bit. 608 * Avoid clearing them unless explicitly requested in set_bits. 609 */ 610 if (addr == 5) 611 clear_bits |= PHY_INT_STATUS_BITS; 612 613 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits); 614 } 615 616 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr) 617 { 618 int ret; 619 620 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5); 621 if (ret < 0) 622 return ret; 623 624 return read_phy_reg(ohci, addr); 625 } 626 627 static int ohci_read_phy_reg(struct fw_card *card, int addr) 628 { 629 struct fw_ohci *ohci = fw_ohci(card); 630 int ret; 631 632 mutex_lock(&ohci->phy_reg_mutex); 633 ret = read_phy_reg(ohci, addr); 634 mutex_unlock(&ohci->phy_reg_mutex); 635 636 return ret; 637 } 638 639 static int ohci_update_phy_reg(struct fw_card *card, int addr, 640 int clear_bits, int set_bits) 641 { 642 struct fw_ohci *ohci = fw_ohci(card); 643 int ret; 644 645 mutex_lock(&ohci->phy_reg_mutex); 646 ret = update_phy_reg(ohci, addr, clear_bits, set_bits); 647 mutex_unlock(&ohci->phy_reg_mutex); 648 649 return ret; 650 } 651 652 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i) 653 { 654 return page_private(ctx->pages[i]); 655 } 656 657 static void ar_context_link_page(struct ar_context *ctx, unsigned int index) 658 { 659 struct descriptor *d; 660 661 d = &ctx->descriptors[index]; 662 d->branch_address &= cpu_to_le32(~0xf); 663 d->res_count = cpu_to_le16(PAGE_SIZE); 664 d->transfer_status = 0; 665 666 wmb(); /* finish init of new descriptors before branch_address update */ 667 d = &ctx->descriptors[ctx->last_buffer_index]; 668 d->branch_address |= cpu_to_le32(1); 669 670 ctx->last_buffer_index = index; 671 672 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 673 } 674 675 static void ar_context_release(struct ar_context *ctx) 676 { 677 struct device *dev = ctx->ohci->card.device; 678 unsigned int i; 679 680 if (!ctx->buffer) 681 return; 682 683 vunmap(ctx->buffer); 684 685 for (i = 0; i < AR_BUFFERS; i++) { 686 if (ctx->pages[i]) 687 dma_free_pages(dev, PAGE_SIZE, ctx->pages[i], 688 ar_buffer_bus(ctx, i), DMA_FROM_DEVICE); 689 } 690 } 691 692 static void ar_context_abort(struct ar_context *ctx, const char *error_msg) 693 { 694 struct fw_ohci *ohci = ctx->ohci; 695 696 if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) { 697 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 698 flush_writes(ohci); 699 700 ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg); 701 } 702 /* FIXME: restart? */ 703 } 704 705 static inline unsigned int ar_next_buffer_index(unsigned int index) 706 { 707 return (index + 1) % AR_BUFFERS; 708 } 709 710 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx) 711 { 712 return ar_next_buffer_index(ctx->last_buffer_index); 713 } 714 715 /* 716 * We search for the buffer that contains the last AR packet DMA data written 717 * by the controller. 718 */ 719 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx, 720 unsigned int *buffer_offset) 721 { 722 unsigned int i, next_i, last = ctx->last_buffer_index; 723 __le16 res_count, next_res_count; 724 725 i = ar_first_buffer_index(ctx); 726 res_count = READ_ONCE(ctx->descriptors[i].res_count); 727 728 /* A buffer that is not yet completely filled must be the last one. */ 729 while (i != last && res_count == 0) { 730 731 /* Peek at the next descriptor. */ 732 next_i = ar_next_buffer_index(i); 733 rmb(); /* read descriptors in order */ 734 next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count); 735 /* 736 * If the next descriptor is still empty, we must stop at this 737 * descriptor. 738 */ 739 if (next_res_count == cpu_to_le16(PAGE_SIZE)) { 740 /* 741 * The exception is when the DMA data for one packet is 742 * split over three buffers; in this case, the middle 743 * buffer's descriptor might be never updated by the 744 * controller and look still empty, and we have to peek 745 * at the third one. 746 */ 747 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) { 748 next_i = ar_next_buffer_index(next_i); 749 rmb(); 750 next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count); 751 if (next_res_count != cpu_to_le16(PAGE_SIZE)) 752 goto next_buffer_is_active; 753 } 754 755 break; 756 } 757 758 next_buffer_is_active: 759 i = next_i; 760 res_count = next_res_count; 761 } 762 763 rmb(); /* read res_count before the DMA data */ 764 765 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count); 766 if (*buffer_offset > PAGE_SIZE) { 767 *buffer_offset = 0; 768 ar_context_abort(ctx, "corrupted descriptor"); 769 } 770 771 return i; 772 } 773 774 static void ar_sync_buffers_for_cpu(struct ar_context *ctx, 775 unsigned int end_buffer_index, 776 unsigned int end_buffer_offset) 777 { 778 unsigned int i; 779 780 i = ar_first_buffer_index(ctx); 781 while (i != end_buffer_index) { 782 dma_sync_single_for_cpu(ctx->ohci->card.device, 783 ar_buffer_bus(ctx, i), 784 PAGE_SIZE, DMA_FROM_DEVICE); 785 i = ar_next_buffer_index(i); 786 } 787 if (end_buffer_offset > 0) 788 dma_sync_single_for_cpu(ctx->ohci->card.device, 789 ar_buffer_bus(ctx, i), 790 end_buffer_offset, DMA_FROM_DEVICE); 791 } 792 793 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) 794 #define cond_le32_to_cpu(v) \ 795 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v)) 796 #else 797 #define cond_le32_to_cpu(v) le32_to_cpu(v) 798 #endif 799 800 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) 801 { 802 struct fw_ohci *ohci = ctx->ohci; 803 struct fw_packet p; 804 u32 status, length, tcode; 805 int evt; 806 807 p.header[0] = cond_le32_to_cpu(buffer[0]); 808 p.header[1] = cond_le32_to_cpu(buffer[1]); 809 p.header[2] = cond_le32_to_cpu(buffer[2]); 810 811 tcode = (p.header[0] >> 4) & 0x0f; 812 switch (tcode) { 813 case TCODE_WRITE_QUADLET_REQUEST: 814 case TCODE_READ_QUADLET_RESPONSE: 815 p.header[3] = (__force __u32) buffer[3]; 816 p.header_length = 16; 817 p.payload_length = 0; 818 break; 819 820 case TCODE_READ_BLOCK_REQUEST : 821 p.header[3] = cond_le32_to_cpu(buffer[3]); 822 p.header_length = 16; 823 p.payload_length = 0; 824 break; 825 826 case TCODE_WRITE_BLOCK_REQUEST: 827 case TCODE_READ_BLOCK_RESPONSE: 828 case TCODE_LOCK_REQUEST: 829 case TCODE_LOCK_RESPONSE: 830 p.header[3] = cond_le32_to_cpu(buffer[3]); 831 p.header_length = 16; 832 p.payload_length = p.header[3] >> 16; 833 if (p.payload_length > MAX_ASYNC_PAYLOAD) { 834 ar_context_abort(ctx, "invalid packet length"); 835 return NULL; 836 } 837 break; 838 839 case TCODE_WRITE_RESPONSE: 840 case TCODE_READ_QUADLET_REQUEST: 841 case OHCI_TCODE_PHY_PACKET: 842 p.header_length = 12; 843 p.payload_length = 0; 844 break; 845 846 default: 847 ar_context_abort(ctx, "invalid tcode"); 848 return NULL; 849 } 850 851 p.payload = (void *) buffer + p.header_length; 852 853 /* FIXME: What to do about evt_* errors? */ 854 length = (p.header_length + p.payload_length + 3) / 4; 855 status = cond_le32_to_cpu(buffer[length]); 856 evt = (status >> 16) & 0x1f; 857 858 p.ack = evt - 16; 859 p.speed = (status >> 21) & 0x7; 860 p.timestamp = status & 0xffff; 861 p.generation = ohci->request_generation; 862 863 log_ar_at_event(ohci, 'R', p.speed, p.header, evt); 864 865 /* 866 * Several controllers, notably from NEC and VIA, forget to 867 * write ack_complete status at PHY packet reception. 868 */ 869 if (evt == OHCI1394_evt_no_status && 870 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4)) 871 p.ack = ACK_COMPLETE; 872 873 /* 874 * The OHCI bus reset handler synthesizes a PHY packet with 875 * the new generation number when a bus reset happens (see 876 * section 8.4.2.3). This helps us determine when a request 877 * was received and make sure we send the response in the same 878 * generation. We only need this for requests; for responses 879 * we use the unique tlabel for finding the matching 880 * request. 881 * 882 * Alas some chips sometimes emit bus reset packets with a 883 * wrong generation. We set the correct generation for these 884 * at a slightly incorrect time (in bus_reset_work). 885 */ 886 if (evt == OHCI1394_evt_bus_reset) { 887 if (!(ohci->quirks & QUIRK_RESET_PACKET)) 888 ohci->request_generation = (p.header[2] >> 16) & 0xff; 889 } else if (ctx == &ohci->ar_request_ctx) { 890 fw_core_handle_request(&ohci->card, &p); 891 } else { 892 fw_core_handle_response(&ohci->card, &p); 893 } 894 895 return buffer + length + 1; 896 } 897 898 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end) 899 { 900 void *next; 901 902 while (p < end) { 903 next = handle_ar_packet(ctx, p); 904 if (!next) 905 return p; 906 p = next; 907 } 908 909 return p; 910 } 911 912 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer) 913 { 914 unsigned int i; 915 916 i = ar_first_buffer_index(ctx); 917 while (i != end_buffer) { 918 dma_sync_single_for_device(ctx->ohci->card.device, 919 ar_buffer_bus(ctx, i), 920 PAGE_SIZE, DMA_FROM_DEVICE); 921 ar_context_link_page(ctx, i); 922 i = ar_next_buffer_index(i); 923 } 924 } 925 926 static void ar_context_tasklet(unsigned long data) 927 { 928 struct ar_context *ctx = (struct ar_context *)data; 929 unsigned int end_buffer_index, end_buffer_offset; 930 void *p, *end; 931 932 p = ctx->pointer; 933 if (!p) 934 return; 935 936 end_buffer_index = ar_search_last_active_buffer(ctx, 937 &end_buffer_offset); 938 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset); 939 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset; 940 941 if (end_buffer_index < ar_first_buffer_index(ctx)) { 942 /* 943 * The filled part of the overall buffer wraps around; handle 944 * all packets up to the buffer end here. If the last packet 945 * wraps around, its tail will be visible after the buffer end 946 * because the buffer start pages are mapped there again. 947 */ 948 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE; 949 p = handle_ar_packets(ctx, p, buffer_end); 950 if (p < buffer_end) 951 goto error; 952 /* adjust p to point back into the actual buffer */ 953 p -= AR_BUFFERS * PAGE_SIZE; 954 } 955 956 p = handle_ar_packets(ctx, p, end); 957 if (p != end) { 958 if (p > end) 959 ar_context_abort(ctx, "inconsistent descriptor"); 960 goto error; 961 } 962 963 ctx->pointer = p; 964 ar_recycle_buffers(ctx, end_buffer_index); 965 966 return; 967 968 error: 969 ctx->pointer = NULL; 970 } 971 972 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, 973 unsigned int descriptors_offset, u32 regs) 974 { 975 struct device *dev = ohci->card.device; 976 unsigned int i; 977 dma_addr_t dma_addr; 978 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES]; 979 struct descriptor *d; 980 981 ctx->regs = regs; 982 ctx->ohci = ohci; 983 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); 984 985 for (i = 0; i < AR_BUFFERS; i++) { 986 ctx->pages[i] = dma_alloc_pages(dev, PAGE_SIZE, &dma_addr, 987 DMA_FROM_DEVICE, GFP_KERNEL); 988 if (!ctx->pages[i]) 989 goto out_of_memory; 990 set_page_private(ctx->pages[i], dma_addr); 991 dma_sync_single_for_device(dev, dma_addr, PAGE_SIZE, 992 DMA_FROM_DEVICE); 993 } 994 995 for (i = 0; i < AR_BUFFERS; i++) 996 pages[i] = ctx->pages[i]; 997 for (i = 0; i < AR_WRAPAROUND_PAGES; i++) 998 pages[AR_BUFFERS + i] = ctx->pages[i]; 999 ctx->buffer = vmap(pages, ARRAY_SIZE(pages), VM_MAP, PAGE_KERNEL); 1000 if (!ctx->buffer) 1001 goto out_of_memory; 1002 1003 ctx->descriptors = ohci->misc_buffer + descriptors_offset; 1004 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset; 1005 1006 for (i = 0; i < AR_BUFFERS; i++) { 1007 d = &ctx->descriptors[i]; 1008 d->req_count = cpu_to_le16(PAGE_SIZE); 1009 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 1010 DESCRIPTOR_STATUS | 1011 DESCRIPTOR_BRANCH_ALWAYS); 1012 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i)); 1013 d->branch_address = cpu_to_le32(ctx->descriptors_bus + 1014 ar_next_buffer_index(i) * sizeof(struct descriptor)); 1015 } 1016 1017 return 0; 1018 1019 out_of_memory: 1020 ar_context_release(ctx); 1021 1022 return -ENOMEM; 1023 } 1024 1025 static void ar_context_run(struct ar_context *ctx) 1026 { 1027 unsigned int i; 1028 1029 for (i = 0; i < AR_BUFFERS; i++) 1030 ar_context_link_page(ctx, i); 1031 1032 ctx->pointer = ctx->buffer; 1033 1034 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1); 1035 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); 1036 } 1037 1038 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z) 1039 { 1040 __le16 branch; 1041 1042 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS); 1043 1044 /* figure out which descriptor the branch address goes in */ 1045 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 1046 return d; 1047 else 1048 return d + z - 1; 1049 } 1050 1051 static void context_tasklet(unsigned long data) 1052 { 1053 struct context *ctx = (struct context *) data; 1054 struct descriptor *d, *last; 1055 u32 address; 1056 int z; 1057 struct descriptor_buffer *desc; 1058 1059 desc = list_entry(ctx->buffer_list.next, 1060 struct descriptor_buffer, list); 1061 last = ctx->last; 1062 while (last->branch_address != 0) { 1063 struct descriptor_buffer *old_desc = desc; 1064 address = le32_to_cpu(last->branch_address); 1065 z = address & 0xf; 1066 address &= ~0xf; 1067 ctx->current_bus = address; 1068 1069 /* If the branch address points to a buffer outside of the 1070 * current buffer, advance to the next buffer. */ 1071 if (address < desc->buffer_bus || 1072 address >= desc->buffer_bus + desc->used) 1073 desc = list_entry(desc->list.next, 1074 struct descriptor_buffer, list); 1075 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d); 1076 last = find_branch_descriptor(d, z); 1077 1078 if (!ctx->callback(ctx, d, last)) 1079 break; 1080 1081 if (old_desc != desc) { 1082 /* If we've advanced to the next buffer, move the 1083 * previous buffer to the free list. */ 1084 unsigned long flags; 1085 old_desc->used = 0; 1086 spin_lock_irqsave(&ctx->ohci->lock, flags); 1087 list_move_tail(&old_desc->list, &ctx->buffer_list); 1088 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1089 } 1090 ctx->last = last; 1091 } 1092 } 1093 1094 /* 1095 * Allocate a new buffer and add it to the list of free buffers for this 1096 * context. Must be called with ohci->lock held. 1097 */ 1098 static int context_add_buffer(struct context *ctx) 1099 { 1100 struct descriptor_buffer *desc; 1101 dma_addr_t bus_addr; 1102 int offset; 1103 1104 /* 1105 * 16MB of descriptors should be far more than enough for any DMA 1106 * program. This will catch run-away userspace or DoS attacks. 1107 */ 1108 if (ctx->total_allocation >= 16*1024*1024) 1109 return -ENOMEM; 1110 1111 desc = dmam_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE, &bus_addr, GFP_ATOMIC); 1112 if (!desc) 1113 return -ENOMEM; 1114 1115 offset = (void *)&desc->buffer - (void *)desc; 1116 /* 1117 * Some controllers, like JMicron ones, always issue 0x20-byte DMA reads 1118 * for descriptors, even 0x10-byte ones. This can cause page faults when 1119 * an IOMMU is in use and the oversized read crosses a page boundary. 1120 * Work around this by always leaving at least 0x10 bytes of padding. 1121 */ 1122 desc->buffer_size = PAGE_SIZE - offset - 0x10; 1123 desc->buffer_bus = bus_addr + offset; 1124 desc->used = 0; 1125 1126 list_add_tail(&desc->list, &ctx->buffer_list); 1127 ctx->total_allocation += PAGE_SIZE; 1128 1129 return 0; 1130 } 1131 1132 static int context_init(struct context *ctx, struct fw_ohci *ohci, 1133 u32 regs, descriptor_callback_t callback) 1134 { 1135 ctx->ohci = ohci; 1136 ctx->regs = regs; 1137 ctx->total_allocation = 0; 1138 1139 INIT_LIST_HEAD(&ctx->buffer_list); 1140 if (context_add_buffer(ctx) < 0) 1141 return -ENOMEM; 1142 1143 ctx->buffer_tail = list_entry(ctx->buffer_list.next, 1144 struct descriptor_buffer, list); 1145 1146 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); 1147 ctx->callback = callback; 1148 1149 /* 1150 * We put a dummy descriptor in the buffer that has a NULL 1151 * branch address and looks like it's been sent. That way we 1152 * have a descriptor to append DMA programs to. 1153 */ 1154 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer)); 1155 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST); 1156 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011); 1157 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer); 1158 ctx->last = ctx->buffer_tail->buffer; 1159 ctx->prev = ctx->buffer_tail->buffer; 1160 ctx->prev_z = 1; 1161 1162 return 0; 1163 } 1164 1165 static void context_release(struct context *ctx) 1166 { 1167 struct fw_card *card = &ctx->ohci->card; 1168 struct descriptor_buffer *desc, *tmp; 1169 1170 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list) { 1171 dmam_free_coherent(card->device, PAGE_SIZE, desc, 1172 desc->buffer_bus - ((void *)&desc->buffer - (void *)desc)); 1173 } 1174 } 1175 1176 /* Must be called with ohci->lock held */ 1177 static struct descriptor *context_get_descriptors(struct context *ctx, 1178 int z, dma_addr_t *d_bus) 1179 { 1180 struct descriptor *d = NULL; 1181 struct descriptor_buffer *desc = ctx->buffer_tail; 1182 1183 if (z * sizeof(*d) > desc->buffer_size) 1184 return NULL; 1185 1186 if (z * sizeof(*d) > desc->buffer_size - desc->used) { 1187 /* No room for the descriptor in this buffer, so advance to the 1188 * next one. */ 1189 1190 if (desc->list.next == &ctx->buffer_list) { 1191 /* If there is no free buffer next in the list, 1192 * allocate one. */ 1193 if (context_add_buffer(ctx) < 0) 1194 return NULL; 1195 } 1196 desc = list_entry(desc->list.next, 1197 struct descriptor_buffer, list); 1198 ctx->buffer_tail = desc; 1199 } 1200 1201 d = desc->buffer + desc->used / sizeof(*d); 1202 memset(d, 0, z * sizeof(*d)); 1203 *d_bus = desc->buffer_bus + desc->used; 1204 1205 return d; 1206 } 1207 1208 static void context_run(struct context *ctx, u32 extra) 1209 { 1210 struct fw_ohci *ohci = ctx->ohci; 1211 1212 reg_write(ohci, COMMAND_PTR(ctx->regs), 1213 le32_to_cpu(ctx->last->branch_address)); 1214 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); 1215 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); 1216 ctx->running = true; 1217 flush_writes(ohci); 1218 } 1219 1220 static void context_append(struct context *ctx, 1221 struct descriptor *d, int z, int extra) 1222 { 1223 dma_addr_t d_bus; 1224 struct descriptor_buffer *desc = ctx->buffer_tail; 1225 struct descriptor *d_branch; 1226 1227 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d); 1228 1229 desc->used += (z + extra) * sizeof(*d); 1230 1231 wmb(); /* finish init of new descriptors before branch_address update */ 1232 1233 d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z); 1234 d_branch->branch_address = cpu_to_le32(d_bus | z); 1235 1236 /* 1237 * VT6306 incorrectly checks only the single descriptor at the 1238 * CommandPtr when the wake bit is written, so if it's a 1239 * multi-descriptor block starting with an INPUT_MORE, put a copy of 1240 * the branch address in the first descriptor. 1241 * 1242 * Not doing this for transmit contexts since not sure how it interacts 1243 * with skip addresses. 1244 */ 1245 if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) && 1246 d_branch != ctx->prev && 1247 (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) == 1248 cpu_to_le16(DESCRIPTOR_INPUT_MORE)) { 1249 ctx->prev->branch_address = cpu_to_le32(d_bus | z); 1250 } 1251 1252 ctx->prev = d; 1253 ctx->prev_z = z; 1254 } 1255 1256 static void context_stop(struct context *ctx) 1257 { 1258 struct fw_ohci *ohci = ctx->ohci; 1259 u32 reg; 1260 int i; 1261 1262 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 1263 ctx->running = false; 1264 1265 for (i = 0; i < 1000; i++) { 1266 reg = reg_read(ohci, CONTROL_SET(ctx->regs)); 1267 if ((reg & CONTEXT_ACTIVE) == 0) 1268 return; 1269 1270 if (i) 1271 udelay(10); 1272 } 1273 ohci_err(ohci, "DMA context still active (0x%08x)\n", reg); 1274 } 1275 1276 struct driver_data { 1277 u8 inline_data[8]; 1278 struct fw_packet *packet; 1279 }; 1280 1281 /* 1282 * This function apppends a packet to the DMA queue for transmission. 1283 * Must always be called with the ochi->lock held to ensure proper 1284 * generation handling and locking around packet queue manipulation. 1285 */ 1286 static int at_context_queue_packet(struct context *ctx, 1287 struct fw_packet *packet) 1288 { 1289 struct fw_ohci *ohci = ctx->ohci; 1290 dma_addr_t d_bus, payload_bus; 1291 struct driver_data *driver_data; 1292 struct descriptor *d, *last; 1293 __le32 *header; 1294 int z, tcode; 1295 1296 d = context_get_descriptors(ctx, 4, &d_bus); 1297 if (d == NULL) { 1298 packet->ack = RCODE_SEND_ERROR; 1299 return -1; 1300 } 1301 1302 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 1303 d[0].res_count = cpu_to_le16(packet->timestamp); 1304 1305 /* 1306 * The DMA format for asynchronous link packets is different 1307 * from the IEEE1394 layout, so shift the fields around 1308 * accordingly. 1309 */ 1310 1311 tcode = (packet->header[0] >> 4) & 0x0f; 1312 header = (__le32 *) &d[1]; 1313 switch (tcode) { 1314 case TCODE_WRITE_QUADLET_REQUEST: 1315 case TCODE_WRITE_BLOCK_REQUEST: 1316 case TCODE_WRITE_RESPONSE: 1317 case TCODE_READ_QUADLET_REQUEST: 1318 case TCODE_READ_BLOCK_REQUEST: 1319 case TCODE_READ_QUADLET_RESPONSE: 1320 case TCODE_READ_BLOCK_RESPONSE: 1321 case TCODE_LOCK_REQUEST: 1322 case TCODE_LOCK_RESPONSE: 1323 header[0] = cpu_to_le32((packet->header[0] & 0xffff) | 1324 (packet->speed << 16)); 1325 header[1] = cpu_to_le32((packet->header[1] & 0xffff) | 1326 (packet->header[0] & 0xffff0000)); 1327 header[2] = cpu_to_le32(packet->header[2]); 1328 1329 if (TCODE_IS_BLOCK_PACKET(tcode)) 1330 header[3] = cpu_to_le32(packet->header[3]); 1331 else 1332 header[3] = (__force __le32) packet->header[3]; 1333 1334 d[0].req_count = cpu_to_le16(packet->header_length); 1335 break; 1336 1337 case TCODE_LINK_INTERNAL: 1338 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) | 1339 (packet->speed << 16)); 1340 header[1] = cpu_to_le32(packet->header[1]); 1341 header[2] = cpu_to_le32(packet->header[2]); 1342 d[0].req_count = cpu_to_le16(12); 1343 1344 if (is_ping_packet(&packet->header[1])) 1345 d[0].control |= cpu_to_le16(DESCRIPTOR_PING); 1346 break; 1347 1348 case TCODE_STREAM_DATA: 1349 header[0] = cpu_to_le32((packet->header[0] & 0xffff) | 1350 (packet->speed << 16)); 1351 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000); 1352 d[0].req_count = cpu_to_le16(8); 1353 break; 1354 1355 default: 1356 /* BUG(); */ 1357 packet->ack = RCODE_SEND_ERROR; 1358 return -1; 1359 } 1360 1361 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor)); 1362 driver_data = (struct driver_data *) &d[3]; 1363 driver_data->packet = packet; 1364 packet->driver_data = driver_data; 1365 1366 if (packet->payload_length > 0) { 1367 if (packet->payload_length > sizeof(driver_data->inline_data)) { 1368 payload_bus = dma_map_single(ohci->card.device, 1369 packet->payload, 1370 packet->payload_length, 1371 DMA_TO_DEVICE); 1372 if (dma_mapping_error(ohci->card.device, payload_bus)) { 1373 packet->ack = RCODE_SEND_ERROR; 1374 return -1; 1375 } 1376 packet->payload_bus = payload_bus; 1377 packet->payload_mapped = true; 1378 } else { 1379 memcpy(driver_data->inline_data, packet->payload, 1380 packet->payload_length); 1381 payload_bus = d_bus + 3 * sizeof(*d); 1382 } 1383 1384 d[2].req_count = cpu_to_le16(packet->payload_length); 1385 d[2].data_address = cpu_to_le32(payload_bus); 1386 last = &d[2]; 1387 z = 3; 1388 } else { 1389 last = &d[0]; 1390 z = 2; 1391 } 1392 1393 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 1394 DESCRIPTOR_IRQ_ALWAYS | 1395 DESCRIPTOR_BRANCH_ALWAYS); 1396 1397 /* FIXME: Document how the locking works. */ 1398 if (ohci->generation != packet->generation) { 1399 if (packet->payload_mapped) 1400 dma_unmap_single(ohci->card.device, payload_bus, 1401 packet->payload_length, DMA_TO_DEVICE); 1402 packet->ack = RCODE_GENERATION; 1403 return -1; 1404 } 1405 1406 context_append(ctx, d, z, 4 - z); 1407 1408 if (ctx->running) 1409 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 1410 else 1411 context_run(ctx, 0); 1412 1413 return 0; 1414 } 1415 1416 static void at_context_flush(struct context *ctx) 1417 { 1418 tasklet_disable(&ctx->tasklet); 1419 1420 ctx->flushing = true; 1421 context_tasklet((unsigned long)ctx); 1422 ctx->flushing = false; 1423 1424 tasklet_enable(&ctx->tasklet); 1425 } 1426 1427 static int handle_at_packet(struct context *context, 1428 struct descriptor *d, 1429 struct descriptor *last) 1430 { 1431 struct driver_data *driver_data; 1432 struct fw_packet *packet; 1433 struct fw_ohci *ohci = context->ohci; 1434 int evt; 1435 1436 if (last->transfer_status == 0 && !context->flushing) 1437 /* This descriptor isn't done yet, stop iteration. */ 1438 return 0; 1439 1440 driver_data = (struct driver_data *) &d[3]; 1441 packet = driver_data->packet; 1442 if (packet == NULL) 1443 /* This packet was cancelled, just continue. */ 1444 return 1; 1445 1446 if (packet->payload_mapped) 1447 dma_unmap_single(ohci->card.device, packet->payload_bus, 1448 packet->payload_length, DMA_TO_DEVICE); 1449 1450 evt = le16_to_cpu(last->transfer_status) & 0x1f; 1451 packet->timestamp = le16_to_cpu(last->res_count); 1452 1453 log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt); 1454 1455 switch (evt) { 1456 case OHCI1394_evt_timeout: 1457 /* Async response transmit timed out. */ 1458 packet->ack = RCODE_CANCELLED; 1459 break; 1460 1461 case OHCI1394_evt_flushed: 1462 /* 1463 * The packet was flushed should give same error as 1464 * when we try to use a stale generation count. 1465 */ 1466 packet->ack = RCODE_GENERATION; 1467 break; 1468 1469 case OHCI1394_evt_missing_ack: 1470 if (context->flushing) 1471 packet->ack = RCODE_GENERATION; 1472 else { 1473 /* 1474 * Using a valid (current) generation count, but the 1475 * node is not on the bus or not sending acks. 1476 */ 1477 packet->ack = RCODE_NO_ACK; 1478 } 1479 break; 1480 1481 case ACK_COMPLETE + 0x10: 1482 case ACK_PENDING + 0x10: 1483 case ACK_BUSY_X + 0x10: 1484 case ACK_BUSY_A + 0x10: 1485 case ACK_BUSY_B + 0x10: 1486 case ACK_DATA_ERROR + 0x10: 1487 case ACK_TYPE_ERROR + 0x10: 1488 packet->ack = evt - 0x10; 1489 break; 1490 1491 case OHCI1394_evt_no_status: 1492 if (context->flushing) { 1493 packet->ack = RCODE_GENERATION; 1494 break; 1495 } 1496 fallthrough; 1497 1498 default: 1499 packet->ack = RCODE_SEND_ERROR; 1500 break; 1501 } 1502 1503 packet->callback(packet, &ohci->card, packet->ack); 1504 1505 return 1; 1506 } 1507 1508 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff) 1509 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f) 1510 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff) 1511 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff) 1512 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff) 1513 1514 static void handle_local_rom(struct fw_ohci *ohci, 1515 struct fw_packet *packet, u32 csr) 1516 { 1517 struct fw_packet response; 1518 int tcode, length, i; 1519 1520 tcode = HEADER_GET_TCODE(packet->header[0]); 1521 if (TCODE_IS_BLOCK_PACKET(tcode)) 1522 length = HEADER_GET_DATA_LENGTH(packet->header[3]); 1523 else 1524 length = 4; 1525 1526 i = csr - CSR_CONFIG_ROM; 1527 if (i + length > CONFIG_ROM_SIZE) { 1528 fw_fill_response(&response, packet->header, 1529 RCODE_ADDRESS_ERROR, NULL, 0); 1530 } else if (!TCODE_IS_READ_REQUEST(tcode)) { 1531 fw_fill_response(&response, packet->header, 1532 RCODE_TYPE_ERROR, NULL, 0); 1533 } else { 1534 fw_fill_response(&response, packet->header, RCODE_COMPLETE, 1535 (void *) ohci->config_rom + i, length); 1536 } 1537 1538 fw_core_handle_response(&ohci->card, &response); 1539 } 1540 1541 static void handle_local_lock(struct fw_ohci *ohci, 1542 struct fw_packet *packet, u32 csr) 1543 { 1544 struct fw_packet response; 1545 int tcode, length, ext_tcode, sel, try; 1546 __be32 *payload, lock_old; 1547 u32 lock_arg, lock_data; 1548 1549 tcode = HEADER_GET_TCODE(packet->header[0]); 1550 length = HEADER_GET_DATA_LENGTH(packet->header[3]); 1551 payload = packet->payload; 1552 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]); 1553 1554 if (tcode == TCODE_LOCK_REQUEST && 1555 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { 1556 lock_arg = be32_to_cpu(payload[0]); 1557 lock_data = be32_to_cpu(payload[1]); 1558 } else if (tcode == TCODE_READ_QUADLET_REQUEST) { 1559 lock_arg = 0; 1560 lock_data = 0; 1561 } else { 1562 fw_fill_response(&response, packet->header, 1563 RCODE_TYPE_ERROR, NULL, 0); 1564 goto out; 1565 } 1566 1567 sel = (csr - CSR_BUS_MANAGER_ID) / 4; 1568 reg_write(ohci, OHCI1394_CSRData, lock_data); 1569 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); 1570 reg_write(ohci, OHCI1394_CSRControl, sel); 1571 1572 for (try = 0; try < 20; try++) 1573 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) { 1574 lock_old = cpu_to_be32(reg_read(ohci, 1575 OHCI1394_CSRData)); 1576 fw_fill_response(&response, packet->header, 1577 RCODE_COMPLETE, 1578 &lock_old, sizeof(lock_old)); 1579 goto out; 1580 } 1581 1582 ohci_err(ohci, "swap not done (CSR lock timeout)\n"); 1583 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0); 1584 1585 out: 1586 fw_core_handle_response(&ohci->card, &response); 1587 } 1588 1589 static void handle_local_request(struct context *ctx, struct fw_packet *packet) 1590 { 1591 u64 offset, csr; 1592 1593 if (ctx == &ctx->ohci->at_request_ctx) { 1594 packet->ack = ACK_PENDING; 1595 packet->callback(packet, &ctx->ohci->card, packet->ack); 1596 } 1597 1598 offset = 1599 ((unsigned long long) 1600 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) | 1601 packet->header[2]; 1602 csr = offset - CSR_REGISTER_BASE; 1603 1604 /* Handle config rom reads. */ 1605 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) 1606 handle_local_rom(ctx->ohci, packet, csr); 1607 else switch (csr) { 1608 case CSR_BUS_MANAGER_ID: 1609 case CSR_BANDWIDTH_AVAILABLE: 1610 case CSR_CHANNELS_AVAILABLE_HI: 1611 case CSR_CHANNELS_AVAILABLE_LO: 1612 handle_local_lock(ctx->ohci, packet, csr); 1613 break; 1614 default: 1615 if (ctx == &ctx->ohci->at_request_ctx) 1616 fw_core_handle_request(&ctx->ohci->card, packet); 1617 else 1618 fw_core_handle_response(&ctx->ohci->card, packet); 1619 break; 1620 } 1621 1622 if (ctx == &ctx->ohci->at_response_ctx) { 1623 packet->ack = ACK_COMPLETE; 1624 packet->callback(packet, &ctx->ohci->card, packet->ack); 1625 } 1626 } 1627 1628 static u32 get_cycle_time(struct fw_ohci *ohci); 1629 1630 static void at_context_transmit(struct context *ctx, struct fw_packet *packet) 1631 { 1632 unsigned long flags; 1633 int ret; 1634 1635 spin_lock_irqsave(&ctx->ohci->lock, flags); 1636 1637 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id && 1638 ctx->ohci->generation == packet->generation) { 1639 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1640 1641 // Timestamping on behalf of the hardware. 1642 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ctx->ohci)); 1643 1644 handle_local_request(ctx, packet); 1645 return; 1646 } 1647 1648 ret = at_context_queue_packet(ctx, packet); 1649 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1650 1651 if (ret < 0) { 1652 // Timestamping on behalf of the hardware. 1653 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ctx->ohci)); 1654 1655 packet->callback(packet, &ctx->ohci->card, packet->ack); 1656 } 1657 } 1658 1659 static void detect_dead_context(struct fw_ohci *ohci, 1660 const char *name, unsigned int regs) 1661 { 1662 u32 ctl; 1663 1664 ctl = reg_read(ohci, CONTROL_SET(regs)); 1665 if (ctl & CONTEXT_DEAD) 1666 ohci_err(ohci, "DMA context %s has stopped, error code: %s\n", 1667 name, evts[ctl & 0x1f]); 1668 } 1669 1670 static void handle_dead_contexts(struct fw_ohci *ohci) 1671 { 1672 unsigned int i; 1673 char name[8]; 1674 1675 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase); 1676 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase); 1677 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase); 1678 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase); 1679 for (i = 0; i < 32; ++i) { 1680 if (!(ohci->it_context_support & (1 << i))) 1681 continue; 1682 sprintf(name, "IT%u", i); 1683 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i)); 1684 } 1685 for (i = 0; i < 32; ++i) { 1686 if (!(ohci->ir_context_support & (1 << i))) 1687 continue; 1688 sprintf(name, "IR%u", i); 1689 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i)); 1690 } 1691 /* TODO: maybe try to flush and restart the dead contexts */ 1692 } 1693 1694 static u32 cycle_timer_ticks(u32 cycle_timer) 1695 { 1696 u32 ticks; 1697 1698 ticks = cycle_timer & 0xfff; 1699 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff); 1700 ticks += (3072 * 8000) * (cycle_timer >> 25); 1701 1702 return ticks; 1703 } 1704 1705 /* 1706 * Some controllers exhibit one or more of the following bugs when updating the 1707 * iso cycle timer register: 1708 * - When the lowest six bits are wrapping around to zero, a read that happens 1709 * at the same time will return garbage in the lowest ten bits. 1710 * - When the cycleOffset field wraps around to zero, the cycleCount field is 1711 * not incremented for about 60 ns. 1712 * - Occasionally, the entire register reads zero. 1713 * 1714 * To catch these, we read the register three times and ensure that the 1715 * difference between each two consecutive reads is approximately the same, i.e. 1716 * less than twice the other. Furthermore, any negative difference indicates an 1717 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to 1718 * execute, so we have enough precision to compute the ratio of the differences.) 1719 */ 1720 static u32 get_cycle_time(struct fw_ohci *ohci) 1721 { 1722 u32 c0, c1, c2; 1723 u32 t0, t1, t2; 1724 s32 diff01, diff12; 1725 int i; 1726 1727 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1728 1729 if (ohci->quirks & QUIRK_CYCLE_TIMER) { 1730 i = 0; 1731 c1 = c2; 1732 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1733 do { 1734 c0 = c1; 1735 c1 = c2; 1736 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1737 t0 = cycle_timer_ticks(c0); 1738 t1 = cycle_timer_ticks(c1); 1739 t2 = cycle_timer_ticks(c2); 1740 diff01 = t1 - t0; 1741 diff12 = t2 - t1; 1742 } while ((diff01 <= 0 || diff12 <= 0 || 1743 diff01 / diff12 >= 2 || diff12 / diff01 >= 2) 1744 && i++ < 20); 1745 } 1746 1747 return c2; 1748 } 1749 1750 /* 1751 * This function has to be called at least every 64 seconds. The bus_time 1752 * field stores not only the upper 25 bits of the BUS_TIME register but also 1753 * the most significant bit of the cycle timer in bit 6 so that we can detect 1754 * changes in this bit. 1755 */ 1756 static u32 update_bus_time(struct fw_ohci *ohci) 1757 { 1758 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25; 1759 1760 if (unlikely(!ohci->bus_time_running)) { 1761 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds); 1762 ohci->bus_time = (lower_32_bits(ktime_get_seconds()) & ~0x7f) | 1763 (cycle_time_seconds & 0x40); 1764 ohci->bus_time_running = true; 1765 } 1766 1767 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40)) 1768 ohci->bus_time += 0x40; 1769 1770 return ohci->bus_time | cycle_time_seconds; 1771 } 1772 1773 static int get_status_for_port(struct fw_ohci *ohci, int port_index) 1774 { 1775 int reg; 1776 1777 mutex_lock(&ohci->phy_reg_mutex); 1778 reg = write_phy_reg(ohci, 7, port_index); 1779 if (reg >= 0) 1780 reg = read_phy_reg(ohci, 8); 1781 mutex_unlock(&ohci->phy_reg_mutex); 1782 if (reg < 0) 1783 return reg; 1784 1785 switch (reg & 0x0f) { 1786 case 0x06: 1787 return 2; /* is child node (connected to parent node) */ 1788 case 0x0e: 1789 return 3; /* is parent node (connected to child node) */ 1790 } 1791 return 1; /* not connected */ 1792 } 1793 1794 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id, 1795 int self_id_count) 1796 { 1797 int i; 1798 u32 entry; 1799 1800 for (i = 0; i < self_id_count; i++) { 1801 entry = ohci->self_id_buffer[i]; 1802 if ((self_id & 0xff000000) == (entry & 0xff000000)) 1803 return -1; 1804 if ((self_id & 0xff000000) < (entry & 0xff000000)) 1805 return i; 1806 } 1807 return i; 1808 } 1809 1810 static int initiated_reset(struct fw_ohci *ohci) 1811 { 1812 int reg; 1813 int ret = 0; 1814 1815 mutex_lock(&ohci->phy_reg_mutex); 1816 reg = write_phy_reg(ohci, 7, 0xe0); /* Select page 7 */ 1817 if (reg >= 0) { 1818 reg = read_phy_reg(ohci, 8); 1819 reg |= 0x40; 1820 reg = write_phy_reg(ohci, 8, reg); /* set PMODE bit */ 1821 if (reg >= 0) { 1822 reg = read_phy_reg(ohci, 12); /* read register 12 */ 1823 if (reg >= 0) { 1824 if ((reg & 0x08) == 0x08) { 1825 /* bit 3 indicates "initiated reset" */ 1826 ret = 0x2; 1827 } 1828 } 1829 } 1830 } 1831 mutex_unlock(&ohci->phy_reg_mutex); 1832 return ret; 1833 } 1834 1835 /* 1836 * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally 1837 * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059. 1838 * Construct the selfID from phy register contents. 1839 */ 1840 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count) 1841 { 1842 int reg, i, pos, status; 1843 /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */ 1844 u32 self_id = 0x8040c800; 1845 1846 reg = reg_read(ohci, OHCI1394_NodeID); 1847 if (!(reg & OHCI1394_NodeID_idValid)) { 1848 ohci_notice(ohci, 1849 "node ID not valid, new bus reset in progress\n"); 1850 return -EBUSY; 1851 } 1852 self_id |= ((reg & 0x3f) << 24); /* phy ID */ 1853 1854 reg = ohci_read_phy_reg(&ohci->card, 4); 1855 if (reg < 0) 1856 return reg; 1857 self_id |= ((reg & 0x07) << 8); /* power class */ 1858 1859 reg = ohci_read_phy_reg(&ohci->card, 1); 1860 if (reg < 0) 1861 return reg; 1862 self_id |= ((reg & 0x3f) << 16); /* gap count */ 1863 1864 for (i = 0; i < 3; i++) { 1865 status = get_status_for_port(ohci, i); 1866 if (status < 0) 1867 return status; 1868 self_id |= ((status & 0x3) << (6 - (i * 2))); 1869 } 1870 1871 self_id |= initiated_reset(ohci); 1872 1873 pos = get_self_id_pos(ohci, self_id, self_id_count); 1874 if (pos >= 0) { 1875 memmove(&(ohci->self_id_buffer[pos+1]), 1876 &(ohci->self_id_buffer[pos]), 1877 (self_id_count - pos) * sizeof(*ohci->self_id_buffer)); 1878 ohci->self_id_buffer[pos] = self_id; 1879 self_id_count++; 1880 } 1881 return self_id_count; 1882 } 1883 1884 static void bus_reset_work(struct work_struct *work) 1885 { 1886 struct fw_ohci *ohci = 1887 container_of(work, struct fw_ohci, bus_reset_work); 1888 int self_id_count, generation, new_generation, i, j; 1889 u32 reg; 1890 void *free_rom = NULL; 1891 dma_addr_t free_rom_bus = 0; 1892 bool is_new_root; 1893 1894 reg = reg_read(ohci, OHCI1394_NodeID); 1895 if (!(reg & OHCI1394_NodeID_idValid)) { 1896 ohci_notice(ohci, 1897 "node ID not valid, new bus reset in progress\n"); 1898 return; 1899 } 1900 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { 1901 ohci_notice(ohci, "malconfigured bus\n"); 1902 return; 1903 } 1904 ohci->node_id = reg & (OHCI1394_NodeID_busNumber | 1905 OHCI1394_NodeID_nodeNumber); 1906 1907 is_new_root = (reg & OHCI1394_NodeID_root) != 0; 1908 if (!(ohci->is_root && is_new_root)) 1909 reg_write(ohci, OHCI1394_LinkControlSet, 1910 OHCI1394_LinkControl_cycleMaster); 1911 ohci->is_root = is_new_root; 1912 1913 reg = reg_read(ohci, OHCI1394_SelfIDCount); 1914 if (reg & OHCI1394_SelfIDCount_selfIDError) { 1915 ohci_notice(ohci, "self ID receive error\n"); 1916 return; 1917 } 1918 /* 1919 * The count in the SelfIDCount register is the number of 1920 * bytes in the self ID receive buffer. Since we also receive 1921 * the inverted quadlets and a header quadlet, we shift one 1922 * bit extra to get the actual number of self IDs. 1923 */ 1924 self_id_count = (reg >> 3) & 0xff; 1925 1926 if (self_id_count > 252) { 1927 ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg); 1928 return; 1929 } 1930 1931 generation = (cond_le32_to_cpu(ohci->self_id[0]) >> 16) & 0xff; 1932 rmb(); 1933 1934 for (i = 1, j = 0; j < self_id_count; i += 2, j++) { 1935 u32 id = cond_le32_to_cpu(ohci->self_id[i]); 1936 u32 id2 = cond_le32_to_cpu(ohci->self_id[i + 1]); 1937 1938 if (id != ~id2) { 1939 /* 1940 * If the invalid data looks like a cycle start packet, 1941 * it's likely to be the result of the cycle master 1942 * having a wrong gap count. In this case, the self IDs 1943 * so far are valid and should be processed so that the 1944 * bus manager can then correct the gap count. 1945 */ 1946 if (id == 0xffff008f) { 1947 ohci_notice(ohci, "ignoring spurious self IDs\n"); 1948 self_id_count = j; 1949 break; 1950 } 1951 1952 ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n", 1953 j, self_id_count, id, id2); 1954 return; 1955 } 1956 ohci->self_id_buffer[j] = id; 1957 } 1958 1959 if (ohci->quirks & QUIRK_TI_SLLZ059) { 1960 self_id_count = find_and_insert_self_id(ohci, self_id_count); 1961 if (self_id_count < 0) { 1962 ohci_notice(ohci, 1963 "could not construct local self ID\n"); 1964 return; 1965 } 1966 } 1967 1968 if (self_id_count == 0) { 1969 ohci_notice(ohci, "no self IDs\n"); 1970 return; 1971 } 1972 rmb(); 1973 1974 /* 1975 * Check the consistency of the self IDs we just read. The 1976 * problem we face is that a new bus reset can start while we 1977 * read out the self IDs from the DMA buffer. If this happens, 1978 * the DMA buffer will be overwritten with new self IDs and we 1979 * will read out inconsistent data. The OHCI specification 1980 * (section 11.2) recommends a technique similar to 1981 * linux/seqlock.h, where we remember the generation of the 1982 * self IDs in the buffer before reading them out and compare 1983 * it to the current generation after reading them out. If 1984 * the two generations match we know we have a consistent set 1985 * of self IDs. 1986 */ 1987 1988 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; 1989 if (new_generation != generation) { 1990 ohci_notice(ohci, "new bus reset, discarding self ids\n"); 1991 return; 1992 } 1993 1994 /* FIXME: Document how the locking works. */ 1995 spin_lock_irq(&ohci->lock); 1996 1997 ohci->generation = -1; /* prevent AT packet queueing */ 1998 context_stop(&ohci->at_request_ctx); 1999 context_stop(&ohci->at_response_ctx); 2000 2001 spin_unlock_irq(&ohci->lock); 2002 2003 /* 2004 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent 2005 * packets in the AT queues and software needs to drain them. 2006 * Some OHCI 1.1 controllers (JMicron) apparently require this too. 2007 */ 2008 at_context_flush(&ohci->at_request_ctx); 2009 at_context_flush(&ohci->at_response_ctx); 2010 2011 spin_lock_irq(&ohci->lock); 2012 2013 ohci->generation = generation; 2014 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); 2015 2016 if (ohci->quirks & QUIRK_RESET_PACKET) 2017 ohci->request_generation = generation; 2018 2019 /* 2020 * This next bit is unrelated to the AT context stuff but we 2021 * have to do it under the spinlock also. If a new config rom 2022 * was set up before this reset, the old one is now no longer 2023 * in use and we can free it. Update the config rom pointers 2024 * to point to the current config rom and clear the 2025 * next_config_rom pointer so a new update can take place. 2026 */ 2027 2028 if (ohci->next_config_rom != NULL) { 2029 if (ohci->next_config_rom != ohci->config_rom) { 2030 free_rom = ohci->config_rom; 2031 free_rom_bus = ohci->config_rom_bus; 2032 } 2033 ohci->config_rom = ohci->next_config_rom; 2034 ohci->config_rom_bus = ohci->next_config_rom_bus; 2035 ohci->next_config_rom = NULL; 2036 2037 /* 2038 * Restore config_rom image and manually update 2039 * config_rom registers. Writing the header quadlet 2040 * will indicate that the config rom is ready, so we 2041 * do that last. 2042 */ 2043 reg_write(ohci, OHCI1394_BusOptions, 2044 be32_to_cpu(ohci->config_rom[2])); 2045 ohci->config_rom[0] = ohci->next_header; 2046 reg_write(ohci, OHCI1394_ConfigROMhdr, 2047 be32_to_cpu(ohci->next_header)); 2048 } 2049 2050 if (param_remote_dma) { 2051 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0); 2052 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0); 2053 } 2054 2055 spin_unlock_irq(&ohci->lock); 2056 2057 if (free_rom) 2058 dmam_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, free_rom, free_rom_bus); 2059 2060 log_selfids(ohci, generation, self_id_count); 2061 2062 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, 2063 self_id_count, ohci->self_id_buffer, 2064 ohci->csr_state_setclear_abdicate); 2065 ohci->csr_state_setclear_abdicate = false; 2066 } 2067 2068 static irqreturn_t irq_handler(int irq, void *data) 2069 { 2070 struct fw_ohci *ohci = data; 2071 u32 event, iso_event; 2072 int i; 2073 2074 event = reg_read(ohci, OHCI1394_IntEventClear); 2075 2076 if (!event || !~event) 2077 return IRQ_NONE; 2078 2079 /* 2080 * busReset and postedWriteErr must not be cleared yet 2081 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1) 2082 */ 2083 reg_write(ohci, OHCI1394_IntEventClear, 2084 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr)); 2085 log_irqs(ohci, event); 2086 2087 if (event & OHCI1394_selfIDComplete) 2088 queue_work(selfid_workqueue, &ohci->bus_reset_work); 2089 2090 if (event & OHCI1394_RQPkt) 2091 tasklet_schedule(&ohci->ar_request_ctx.tasklet); 2092 2093 if (event & OHCI1394_RSPkt) 2094 tasklet_schedule(&ohci->ar_response_ctx.tasklet); 2095 2096 if (event & OHCI1394_reqTxComplete) 2097 tasklet_schedule(&ohci->at_request_ctx.tasklet); 2098 2099 if (event & OHCI1394_respTxComplete) 2100 tasklet_schedule(&ohci->at_response_ctx.tasklet); 2101 2102 if (event & OHCI1394_isochRx) { 2103 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); 2104 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); 2105 2106 while (iso_event) { 2107 i = ffs(iso_event) - 1; 2108 tasklet_schedule( 2109 &ohci->ir_context_list[i].context.tasklet); 2110 iso_event &= ~(1 << i); 2111 } 2112 } 2113 2114 if (event & OHCI1394_isochTx) { 2115 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); 2116 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); 2117 2118 while (iso_event) { 2119 i = ffs(iso_event) - 1; 2120 tasklet_schedule( 2121 &ohci->it_context_list[i].context.tasklet); 2122 iso_event &= ~(1 << i); 2123 } 2124 } 2125 2126 if (unlikely(event & OHCI1394_regAccessFail)) 2127 ohci_err(ohci, "register access failure\n"); 2128 2129 if (unlikely(event & OHCI1394_postedWriteErr)) { 2130 reg_read(ohci, OHCI1394_PostedWriteAddressHi); 2131 reg_read(ohci, OHCI1394_PostedWriteAddressLo); 2132 reg_write(ohci, OHCI1394_IntEventClear, 2133 OHCI1394_postedWriteErr); 2134 if (printk_ratelimit()) 2135 ohci_err(ohci, "PCI posted write error\n"); 2136 } 2137 2138 if (unlikely(event & OHCI1394_cycleTooLong)) { 2139 if (printk_ratelimit()) 2140 ohci_notice(ohci, "isochronous cycle too long\n"); 2141 reg_write(ohci, OHCI1394_LinkControlSet, 2142 OHCI1394_LinkControl_cycleMaster); 2143 } 2144 2145 if (unlikely(event & OHCI1394_cycleInconsistent)) { 2146 /* 2147 * We need to clear this event bit in order to make 2148 * cycleMatch isochronous I/O work. In theory we should 2149 * stop active cycleMatch iso contexts now and restart 2150 * them at least two cycles later. (FIXME?) 2151 */ 2152 if (printk_ratelimit()) 2153 ohci_notice(ohci, "isochronous cycle inconsistent\n"); 2154 } 2155 2156 if (unlikely(event & OHCI1394_unrecoverableError)) 2157 handle_dead_contexts(ohci); 2158 2159 if (event & OHCI1394_cycle64Seconds) { 2160 spin_lock(&ohci->lock); 2161 update_bus_time(ohci); 2162 spin_unlock(&ohci->lock); 2163 } else 2164 flush_writes(ohci); 2165 2166 return IRQ_HANDLED; 2167 } 2168 2169 static int software_reset(struct fw_ohci *ohci) 2170 { 2171 u32 val; 2172 int i; 2173 2174 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); 2175 for (i = 0; i < 500; i++) { 2176 val = reg_read(ohci, OHCI1394_HCControlSet); 2177 if (!~val) 2178 return -ENODEV; /* Card was ejected. */ 2179 2180 if (!(val & OHCI1394_HCControl_softReset)) 2181 return 0; 2182 2183 msleep(1); 2184 } 2185 2186 return -EBUSY; 2187 } 2188 2189 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length) 2190 { 2191 size_t size = length * 4; 2192 2193 memcpy(dest, src, size); 2194 if (size < CONFIG_ROM_SIZE) 2195 memset(&dest[length], 0, CONFIG_ROM_SIZE - size); 2196 } 2197 2198 static int configure_1394a_enhancements(struct fw_ohci *ohci) 2199 { 2200 bool enable_1394a; 2201 int ret, clear, set, offset; 2202 2203 /* Check if the driver should configure link and PHY. */ 2204 if (!(reg_read(ohci, OHCI1394_HCControlSet) & 2205 OHCI1394_HCControl_programPhyEnable)) 2206 return 0; 2207 2208 /* Paranoia: check whether the PHY supports 1394a, too. */ 2209 enable_1394a = false; 2210 ret = read_phy_reg(ohci, 2); 2211 if (ret < 0) 2212 return ret; 2213 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) { 2214 ret = read_paged_phy_reg(ohci, 1, 8); 2215 if (ret < 0) 2216 return ret; 2217 if (ret >= 1) 2218 enable_1394a = true; 2219 } 2220 2221 if (ohci->quirks & QUIRK_NO_1394A) 2222 enable_1394a = false; 2223 2224 /* Configure PHY and link consistently. */ 2225 if (enable_1394a) { 2226 clear = 0; 2227 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2228 } else { 2229 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2230 set = 0; 2231 } 2232 ret = update_phy_reg(ohci, 5, clear, set); 2233 if (ret < 0) 2234 return ret; 2235 2236 if (enable_1394a) 2237 offset = OHCI1394_HCControlSet; 2238 else 2239 offset = OHCI1394_HCControlClear; 2240 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable); 2241 2242 /* Clean up: configuration has been taken care of. */ 2243 reg_write(ohci, OHCI1394_HCControlClear, 2244 OHCI1394_HCControl_programPhyEnable); 2245 2246 return 0; 2247 } 2248 2249 static int probe_tsb41ba3d(struct fw_ohci *ohci) 2250 { 2251 /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */ 2252 static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, }; 2253 int reg, i; 2254 2255 reg = read_phy_reg(ohci, 2); 2256 if (reg < 0) 2257 return reg; 2258 if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS) 2259 return 0; 2260 2261 for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) { 2262 reg = read_paged_phy_reg(ohci, 1, i + 10); 2263 if (reg < 0) 2264 return reg; 2265 if (reg != id[i]) 2266 return 0; 2267 } 2268 return 1; 2269 } 2270 2271 static int ohci_enable(struct fw_card *card, 2272 const __be32 *config_rom, size_t length) 2273 { 2274 struct fw_ohci *ohci = fw_ohci(card); 2275 u32 lps, version, irqs; 2276 int i, ret; 2277 2278 ret = software_reset(ohci); 2279 if (ret < 0) { 2280 ohci_err(ohci, "failed to reset ohci card\n"); 2281 return ret; 2282 } 2283 2284 /* 2285 * Now enable LPS, which we need in order to start accessing 2286 * most of the registers. In fact, on some cards (ALI M5251), 2287 * accessing registers in the SClk domain without LPS enabled 2288 * will lock up the machine. Wait 50msec to make sure we have 2289 * full link enabled. However, with some cards (well, at least 2290 * a JMicron PCIe card), we have to try again sometimes. 2291 * 2292 * TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but 2293 * cannot actually use the phy at that time. These need tens of 2294 * millisecods pause between LPS write and first phy access too. 2295 */ 2296 2297 reg_write(ohci, OHCI1394_HCControlSet, 2298 OHCI1394_HCControl_LPS | 2299 OHCI1394_HCControl_postedWriteEnable); 2300 flush_writes(ohci); 2301 2302 for (lps = 0, i = 0; !lps && i < 3; i++) { 2303 msleep(50); 2304 lps = reg_read(ohci, OHCI1394_HCControlSet) & 2305 OHCI1394_HCControl_LPS; 2306 } 2307 2308 if (!lps) { 2309 ohci_err(ohci, "failed to set Link Power Status\n"); 2310 return -EIO; 2311 } 2312 2313 if (ohci->quirks & QUIRK_TI_SLLZ059) { 2314 ret = probe_tsb41ba3d(ohci); 2315 if (ret < 0) 2316 return ret; 2317 if (ret) 2318 ohci_notice(ohci, "local TSB41BA3D phy\n"); 2319 else 2320 ohci->quirks &= ~QUIRK_TI_SLLZ059; 2321 } 2322 2323 reg_write(ohci, OHCI1394_HCControlClear, 2324 OHCI1394_HCControl_noByteSwapData); 2325 2326 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); 2327 reg_write(ohci, OHCI1394_LinkControlSet, 2328 OHCI1394_LinkControl_cycleTimerEnable | 2329 OHCI1394_LinkControl_cycleMaster); 2330 2331 reg_write(ohci, OHCI1394_ATRetries, 2332 OHCI1394_MAX_AT_REQ_RETRIES | 2333 (OHCI1394_MAX_AT_RESP_RETRIES << 4) | 2334 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) | 2335 (200 << 16)); 2336 2337 ohci->bus_time_running = false; 2338 2339 for (i = 0; i < 32; i++) 2340 if (ohci->ir_context_support & (1 << i)) 2341 reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i), 2342 IR_CONTEXT_MULTI_CHANNEL_MODE); 2343 2344 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 2345 if (version >= OHCI_VERSION_1_1) { 2346 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi, 2347 0xfffffffe); 2348 card->broadcast_channel_auto_allocated = true; 2349 } 2350 2351 /* Get implemented bits of the priority arbitration request counter. */ 2352 reg_write(ohci, OHCI1394_FairnessControl, 0x3f); 2353 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f; 2354 reg_write(ohci, OHCI1394_FairnessControl, 0); 2355 card->priority_budget_implemented = ohci->pri_req_max != 0; 2356 2357 reg_write(ohci, OHCI1394_PhyUpperBound, FW_MAX_PHYSICAL_RANGE >> 16); 2358 reg_write(ohci, OHCI1394_IntEventClear, ~0); 2359 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 2360 2361 ret = configure_1394a_enhancements(ohci); 2362 if (ret < 0) 2363 return ret; 2364 2365 /* Activate link_on bit and contender bit in our self ID packets.*/ 2366 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER); 2367 if (ret < 0) 2368 return ret; 2369 2370 /* 2371 * When the link is not yet enabled, the atomic config rom 2372 * update mechanism described below in ohci_set_config_rom() 2373 * is not active. We have to update ConfigRomHeader and 2374 * BusOptions manually, and the write to ConfigROMmap takes 2375 * effect immediately. We tie this to the enabling of the 2376 * link, so we have a valid config rom before enabling - the 2377 * OHCI requires that ConfigROMhdr and BusOptions have valid 2378 * values before enabling. 2379 * 2380 * However, when the ConfigROMmap is written, some controllers 2381 * always read back quadlets 0 and 2 from the config rom to 2382 * the ConfigRomHeader and BusOptions registers on bus reset. 2383 * They shouldn't do that in this initial case where the link 2384 * isn't enabled. This means we have to use the same 2385 * workaround here, setting the bus header to 0 and then write 2386 * the right values in the bus reset tasklet. 2387 */ 2388 2389 if (config_rom) { 2390 ohci->next_config_rom = dmam_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2391 &ohci->next_config_rom_bus, GFP_KERNEL); 2392 if (ohci->next_config_rom == NULL) 2393 return -ENOMEM; 2394 2395 copy_config_rom(ohci->next_config_rom, config_rom, length); 2396 } else { 2397 /* 2398 * In the suspend case, config_rom is NULL, which 2399 * means that we just reuse the old config rom. 2400 */ 2401 ohci->next_config_rom = ohci->config_rom; 2402 ohci->next_config_rom_bus = ohci->config_rom_bus; 2403 } 2404 2405 ohci->next_header = ohci->next_config_rom[0]; 2406 ohci->next_config_rom[0] = 0; 2407 reg_write(ohci, OHCI1394_ConfigROMhdr, 0); 2408 reg_write(ohci, OHCI1394_BusOptions, 2409 be32_to_cpu(ohci->next_config_rom[2])); 2410 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2411 2412 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); 2413 2414 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete | 2415 OHCI1394_RQPkt | OHCI1394_RSPkt | 2416 OHCI1394_isochTx | OHCI1394_isochRx | 2417 OHCI1394_postedWriteErr | 2418 OHCI1394_selfIDComplete | 2419 OHCI1394_regAccessFail | 2420 OHCI1394_cycleInconsistent | 2421 OHCI1394_unrecoverableError | 2422 OHCI1394_cycleTooLong | 2423 OHCI1394_masterIntEnable; 2424 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS) 2425 irqs |= OHCI1394_busReset; 2426 reg_write(ohci, OHCI1394_IntMaskSet, irqs); 2427 2428 reg_write(ohci, OHCI1394_HCControlSet, 2429 OHCI1394_HCControl_linkEnable | 2430 OHCI1394_HCControl_BIBimageValid); 2431 2432 reg_write(ohci, OHCI1394_LinkControlSet, 2433 OHCI1394_LinkControl_rcvSelfID | 2434 OHCI1394_LinkControl_rcvPhyPkt); 2435 2436 ar_context_run(&ohci->ar_request_ctx); 2437 ar_context_run(&ohci->ar_response_ctx); 2438 2439 flush_writes(ohci); 2440 2441 /* We are ready to go, reset bus to finish initialization. */ 2442 fw_schedule_bus_reset(&ohci->card, false, true); 2443 2444 return 0; 2445 } 2446 2447 static int ohci_set_config_rom(struct fw_card *card, 2448 const __be32 *config_rom, size_t length) 2449 { 2450 struct fw_ohci *ohci; 2451 __be32 *next_config_rom; 2452 dma_addr_t next_config_rom_bus; 2453 2454 ohci = fw_ohci(card); 2455 2456 /* 2457 * When the OHCI controller is enabled, the config rom update 2458 * mechanism is a bit tricky, but easy enough to use. See 2459 * section 5.5.6 in the OHCI specification. 2460 * 2461 * The OHCI controller caches the new config rom address in a 2462 * shadow register (ConfigROMmapNext) and needs a bus reset 2463 * for the changes to take place. When the bus reset is 2464 * detected, the controller loads the new values for the 2465 * ConfigRomHeader and BusOptions registers from the specified 2466 * config rom and loads ConfigROMmap from the ConfigROMmapNext 2467 * shadow register. All automatically and atomically. 2468 * 2469 * Now, there's a twist to this story. The automatic load of 2470 * ConfigRomHeader and BusOptions doesn't honor the 2471 * noByteSwapData bit, so with a be32 config rom, the 2472 * controller will load be32 values in to these registers 2473 * during the atomic update, even on litte endian 2474 * architectures. The workaround we use is to put a 0 in the 2475 * header quadlet; 0 is endian agnostic and means that the 2476 * config rom isn't ready yet. In the bus reset tasklet we 2477 * then set up the real values for the two registers. 2478 * 2479 * We use ohci->lock to avoid racing with the code that sets 2480 * ohci->next_config_rom to NULL (see bus_reset_work). 2481 */ 2482 2483 next_config_rom = dmam_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2484 &next_config_rom_bus, GFP_KERNEL); 2485 if (next_config_rom == NULL) 2486 return -ENOMEM; 2487 2488 spin_lock_irq(&ohci->lock); 2489 2490 /* 2491 * If there is not an already pending config_rom update, 2492 * push our new allocation into the ohci->next_config_rom 2493 * and then mark the local variable as null so that we 2494 * won't deallocate the new buffer. 2495 * 2496 * OTOH, if there is a pending config_rom update, just 2497 * use that buffer with the new config_rom data, and 2498 * let this routine free the unused DMA allocation. 2499 */ 2500 2501 if (ohci->next_config_rom == NULL) { 2502 ohci->next_config_rom = next_config_rom; 2503 ohci->next_config_rom_bus = next_config_rom_bus; 2504 next_config_rom = NULL; 2505 } 2506 2507 copy_config_rom(ohci->next_config_rom, config_rom, length); 2508 2509 ohci->next_header = config_rom[0]; 2510 ohci->next_config_rom[0] = 0; 2511 2512 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2513 2514 spin_unlock_irq(&ohci->lock); 2515 2516 /* If we didn't use the DMA allocation, delete it. */ 2517 if (next_config_rom != NULL) { 2518 dmam_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, next_config_rom, 2519 next_config_rom_bus); 2520 } 2521 2522 /* 2523 * Now initiate a bus reset to have the changes take 2524 * effect. We clean up the old config rom memory and DMA 2525 * mappings in the bus reset tasklet, since the OHCI 2526 * controller could need to access it before the bus reset 2527 * takes effect. 2528 */ 2529 2530 fw_schedule_bus_reset(&ohci->card, true, true); 2531 2532 return 0; 2533 } 2534 2535 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) 2536 { 2537 struct fw_ohci *ohci = fw_ohci(card); 2538 2539 at_context_transmit(&ohci->at_request_ctx, packet); 2540 } 2541 2542 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) 2543 { 2544 struct fw_ohci *ohci = fw_ohci(card); 2545 2546 at_context_transmit(&ohci->at_response_ctx, packet); 2547 } 2548 2549 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) 2550 { 2551 struct fw_ohci *ohci = fw_ohci(card); 2552 struct context *ctx = &ohci->at_request_ctx; 2553 struct driver_data *driver_data = packet->driver_data; 2554 int ret = -ENOENT; 2555 2556 tasklet_disable_in_atomic(&ctx->tasklet); 2557 2558 if (packet->ack != 0) 2559 goto out; 2560 2561 if (packet->payload_mapped) 2562 dma_unmap_single(ohci->card.device, packet->payload_bus, 2563 packet->payload_length, DMA_TO_DEVICE); 2564 2565 log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20); 2566 driver_data->packet = NULL; 2567 packet->ack = RCODE_CANCELLED; 2568 2569 // Timestamping on behalf of the hardware. 2570 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); 2571 2572 packet->callback(packet, &ohci->card, packet->ack); 2573 ret = 0; 2574 out: 2575 tasklet_enable(&ctx->tasklet); 2576 2577 return ret; 2578 } 2579 2580 static int ohci_enable_phys_dma(struct fw_card *card, 2581 int node_id, int generation) 2582 { 2583 struct fw_ohci *ohci = fw_ohci(card); 2584 unsigned long flags; 2585 int n, ret = 0; 2586 2587 if (param_remote_dma) 2588 return 0; 2589 2590 /* 2591 * FIXME: Make sure this bitmask is cleared when we clear the busReset 2592 * interrupt bit. Clear physReqResourceAllBuses on bus reset. 2593 */ 2594 2595 spin_lock_irqsave(&ohci->lock, flags); 2596 2597 if (ohci->generation != generation) { 2598 ret = -ESTALE; 2599 goto out; 2600 } 2601 2602 /* 2603 * Note, if the node ID contains a non-local bus ID, physical DMA is 2604 * enabled for _all_ nodes on remote buses. 2605 */ 2606 2607 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; 2608 if (n < 32) 2609 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); 2610 else 2611 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); 2612 2613 flush_writes(ohci); 2614 out: 2615 spin_unlock_irqrestore(&ohci->lock, flags); 2616 2617 return ret; 2618 } 2619 2620 static u32 ohci_read_csr(struct fw_card *card, int csr_offset) 2621 { 2622 struct fw_ohci *ohci = fw_ohci(card); 2623 unsigned long flags; 2624 u32 value; 2625 2626 switch (csr_offset) { 2627 case CSR_STATE_CLEAR: 2628 case CSR_STATE_SET: 2629 if (ohci->is_root && 2630 (reg_read(ohci, OHCI1394_LinkControlSet) & 2631 OHCI1394_LinkControl_cycleMaster)) 2632 value = CSR_STATE_BIT_CMSTR; 2633 else 2634 value = 0; 2635 if (ohci->csr_state_setclear_abdicate) 2636 value |= CSR_STATE_BIT_ABDICATE; 2637 2638 return value; 2639 2640 case CSR_NODE_IDS: 2641 return reg_read(ohci, OHCI1394_NodeID) << 16; 2642 2643 case CSR_CYCLE_TIME: 2644 return get_cycle_time(ohci); 2645 2646 case CSR_BUS_TIME: 2647 /* 2648 * We might be called just after the cycle timer has wrapped 2649 * around but just before the cycle64Seconds handler, so we 2650 * better check here, too, if the bus time needs to be updated. 2651 */ 2652 spin_lock_irqsave(&ohci->lock, flags); 2653 value = update_bus_time(ohci); 2654 spin_unlock_irqrestore(&ohci->lock, flags); 2655 return value; 2656 2657 case CSR_BUSY_TIMEOUT: 2658 value = reg_read(ohci, OHCI1394_ATRetries); 2659 return (value >> 4) & 0x0ffff00f; 2660 2661 case CSR_PRIORITY_BUDGET: 2662 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) | 2663 (ohci->pri_req_max << 8); 2664 2665 default: 2666 WARN_ON(1); 2667 return 0; 2668 } 2669 } 2670 2671 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value) 2672 { 2673 struct fw_ohci *ohci = fw_ohci(card); 2674 unsigned long flags; 2675 2676 switch (csr_offset) { 2677 case CSR_STATE_CLEAR: 2678 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2679 reg_write(ohci, OHCI1394_LinkControlClear, 2680 OHCI1394_LinkControl_cycleMaster); 2681 flush_writes(ohci); 2682 } 2683 if (value & CSR_STATE_BIT_ABDICATE) 2684 ohci->csr_state_setclear_abdicate = false; 2685 break; 2686 2687 case CSR_STATE_SET: 2688 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2689 reg_write(ohci, OHCI1394_LinkControlSet, 2690 OHCI1394_LinkControl_cycleMaster); 2691 flush_writes(ohci); 2692 } 2693 if (value & CSR_STATE_BIT_ABDICATE) 2694 ohci->csr_state_setclear_abdicate = true; 2695 break; 2696 2697 case CSR_NODE_IDS: 2698 reg_write(ohci, OHCI1394_NodeID, value >> 16); 2699 flush_writes(ohci); 2700 break; 2701 2702 case CSR_CYCLE_TIME: 2703 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value); 2704 reg_write(ohci, OHCI1394_IntEventSet, 2705 OHCI1394_cycleInconsistent); 2706 flush_writes(ohci); 2707 break; 2708 2709 case CSR_BUS_TIME: 2710 spin_lock_irqsave(&ohci->lock, flags); 2711 ohci->bus_time = (update_bus_time(ohci) & 0x40) | 2712 (value & ~0x7f); 2713 spin_unlock_irqrestore(&ohci->lock, flags); 2714 break; 2715 2716 case CSR_BUSY_TIMEOUT: 2717 value = (value & 0xf) | ((value & 0xf) << 4) | 2718 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4); 2719 reg_write(ohci, OHCI1394_ATRetries, value); 2720 flush_writes(ohci); 2721 break; 2722 2723 case CSR_PRIORITY_BUDGET: 2724 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f); 2725 flush_writes(ohci); 2726 break; 2727 2728 default: 2729 WARN_ON(1); 2730 break; 2731 } 2732 } 2733 2734 static void flush_iso_completions(struct iso_context *ctx) 2735 { 2736 ctx->base.callback.sc(&ctx->base, ctx->last_timestamp, 2737 ctx->header_length, ctx->header, 2738 ctx->base.callback_data); 2739 ctx->header_length = 0; 2740 } 2741 2742 static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr) 2743 { 2744 u32 *ctx_hdr; 2745 2746 if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) { 2747 if (ctx->base.drop_overflow_headers) 2748 return; 2749 flush_iso_completions(ctx); 2750 } 2751 2752 ctx_hdr = ctx->header + ctx->header_length; 2753 ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]); 2754 2755 /* 2756 * The two iso header quadlets are byteswapped to little 2757 * endian by the controller, but we want to present them 2758 * as big endian for consistency with the bus endianness. 2759 */ 2760 if (ctx->base.header_size > 0) 2761 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */ 2762 if (ctx->base.header_size > 4) 2763 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */ 2764 if (ctx->base.header_size > 8) 2765 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8); 2766 ctx->header_length += ctx->base.header_size; 2767 } 2768 2769 static int handle_ir_packet_per_buffer(struct context *context, 2770 struct descriptor *d, 2771 struct descriptor *last) 2772 { 2773 struct iso_context *ctx = 2774 container_of(context, struct iso_context, context); 2775 struct descriptor *pd; 2776 u32 buffer_dma; 2777 2778 for (pd = d; pd <= last; pd++) 2779 if (pd->transfer_status) 2780 break; 2781 if (pd > last) 2782 /* Descriptor(s) not done yet, stop iteration */ 2783 return 0; 2784 2785 while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) { 2786 d++; 2787 buffer_dma = le32_to_cpu(d->data_address); 2788 dma_sync_single_range_for_cpu(context->ohci->card.device, 2789 buffer_dma & PAGE_MASK, 2790 buffer_dma & ~PAGE_MASK, 2791 le16_to_cpu(d->req_count), 2792 DMA_FROM_DEVICE); 2793 } 2794 2795 copy_iso_headers(ctx, (u32 *) (last + 1)); 2796 2797 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) 2798 flush_iso_completions(ctx); 2799 2800 return 1; 2801 } 2802 2803 /* d == last because each descriptor block is only a single descriptor. */ 2804 static int handle_ir_buffer_fill(struct context *context, 2805 struct descriptor *d, 2806 struct descriptor *last) 2807 { 2808 struct iso_context *ctx = 2809 container_of(context, struct iso_context, context); 2810 unsigned int req_count, res_count, completed; 2811 u32 buffer_dma; 2812 2813 req_count = le16_to_cpu(last->req_count); 2814 res_count = le16_to_cpu(READ_ONCE(last->res_count)); 2815 completed = req_count - res_count; 2816 buffer_dma = le32_to_cpu(last->data_address); 2817 2818 if (completed > 0) { 2819 ctx->mc_buffer_bus = buffer_dma; 2820 ctx->mc_completed = completed; 2821 } 2822 2823 if (res_count != 0) 2824 /* Descriptor(s) not done yet, stop iteration */ 2825 return 0; 2826 2827 dma_sync_single_range_for_cpu(context->ohci->card.device, 2828 buffer_dma & PAGE_MASK, 2829 buffer_dma & ~PAGE_MASK, 2830 completed, DMA_FROM_DEVICE); 2831 2832 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) { 2833 ctx->base.callback.mc(&ctx->base, 2834 buffer_dma + completed, 2835 ctx->base.callback_data); 2836 ctx->mc_completed = 0; 2837 } 2838 2839 return 1; 2840 } 2841 2842 static void flush_ir_buffer_fill(struct iso_context *ctx) 2843 { 2844 dma_sync_single_range_for_cpu(ctx->context.ohci->card.device, 2845 ctx->mc_buffer_bus & PAGE_MASK, 2846 ctx->mc_buffer_bus & ~PAGE_MASK, 2847 ctx->mc_completed, DMA_FROM_DEVICE); 2848 2849 ctx->base.callback.mc(&ctx->base, 2850 ctx->mc_buffer_bus + ctx->mc_completed, 2851 ctx->base.callback_data); 2852 ctx->mc_completed = 0; 2853 } 2854 2855 static inline void sync_it_packet_for_cpu(struct context *context, 2856 struct descriptor *pd) 2857 { 2858 __le16 control; 2859 u32 buffer_dma; 2860 2861 /* only packets beginning with OUTPUT_MORE* have data buffers */ 2862 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 2863 return; 2864 2865 /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */ 2866 pd += 2; 2867 2868 /* 2869 * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's 2870 * data buffer is in the context program's coherent page and must not 2871 * be synced. 2872 */ 2873 if ((le32_to_cpu(pd->data_address) & PAGE_MASK) == 2874 (context->current_bus & PAGE_MASK)) { 2875 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 2876 return; 2877 pd++; 2878 } 2879 2880 do { 2881 buffer_dma = le32_to_cpu(pd->data_address); 2882 dma_sync_single_range_for_cpu(context->ohci->card.device, 2883 buffer_dma & PAGE_MASK, 2884 buffer_dma & ~PAGE_MASK, 2885 le16_to_cpu(pd->req_count), 2886 DMA_TO_DEVICE); 2887 control = pd->control; 2888 pd++; 2889 } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))); 2890 } 2891 2892 static int handle_it_packet(struct context *context, 2893 struct descriptor *d, 2894 struct descriptor *last) 2895 { 2896 struct iso_context *ctx = 2897 container_of(context, struct iso_context, context); 2898 struct descriptor *pd; 2899 __be32 *ctx_hdr; 2900 2901 for (pd = d; pd <= last; pd++) 2902 if (pd->transfer_status) 2903 break; 2904 if (pd > last) 2905 /* Descriptor(s) not done yet, stop iteration */ 2906 return 0; 2907 2908 sync_it_packet_for_cpu(context, d); 2909 2910 if (ctx->header_length + 4 > PAGE_SIZE) { 2911 if (ctx->base.drop_overflow_headers) 2912 return 1; 2913 flush_iso_completions(ctx); 2914 } 2915 2916 ctx_hdr = ctx->header + ctx->header_length; 2917 ctx->last_timestamp = le16_to_cpu(last->res_count); 2918 /* Present this value as big-endian to match the receive code */ 2919 *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) | 2920 le16_to_cpu(pd->res_count)); 2921 ctx->header_length += 4; 2922 2923 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) 2924 flush_iso_completions(ctx); 2925 2926 return 1; 2927 } 2928 2929 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels) 2930 { 2931 u32 hi = channels >> 32, lo = channels; 2932 2933 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi); 2934 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo); 2935 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi); 2936 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo); 2937 ohci->mc_channels = channels; 2938 } 2939 2940 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card, 2941 int type, int channel, size_t header_size) 2942 { 2943 struct fw_ohci *ohci = fw_ohci(card); 2944 struct iso_context *ctx; 2945 descriptor_callback_t callback; 2946 u64 *channels; 2947 u32 *mask, regs; 2948 int index, ret = -EBUSY; 2949 2950 spin_lock_irq(&ohci->lock); 2951 2952 switch (type) { 2953 case FW_ISO_CONTEXT_TRANSMIT: 2954 mask = &ohci->it_context_mask; 2955 callback = handle_it_packet; 2956 index = ffs(*mask) - 1; 2957 if (index >= 0) { 2958 *mask &= ~(1 << index); 2959 regs = OHCI1394_IsoXmitContextBase(index); 2960 ctx = &ohci->it_context_list[index]; 2961 } 2962 break; 2963 2964 case FW_ISO_CONTEXT_RECEIVE: 2965 channels = &ohci->ir_context_channels; 2966 mask = &ohci->ir_context_mask; 2967 callback = handle_ir_packet_per_buffer; 2968 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1; 2969 if (index >= 0) { 2970 *channels &= ~(1ULL << channel); 2971 *mask &= ~(1 << index); 2972 regs = OHCI1394_IsoRcvContextBase(index); 2973 ctx = &ohci->ir_context_list[index]; 2974 } 2975 break; 2976 2977 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2978 mask = &ohci->ir_context_mask; 2979 callback = handle_ir_buffer_fill; 2980 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1; 2981 if (index >= 0) { 2982 ohci->mc_allocated = true; 2983 *mask &= ~(1 << index); 2984 regs = OHCI1394_IsoRcvContextBase(index); 2985 ctx = &ohci->ir_context_list[index]; 2986 } 2987 break; 2988 2989 default: 2990 index = -1; 2991 ret = -ENOSYS; 2992 } 2993 2994 spin_unlock_irq(&ohci->lock); 2995 2996 if (index < 0) 2997 return ERR_PTR(ret); 2998 2999 memset(ctx, 0, sizeof(*ctx)); 3000 ctx->header_length = 0; 3001 ctx->header = (void *) __get_free_page(GFP_KERNEL); 3002 if (ctx->header == NULL) { 3003 ret = -ENOMEM; 3004 goto out; 3005 } 3006 ret = context_init(&ctx->context, ohci, regs, callback); 3007 if (ret < 0) 3008 goto out_with_header; 3009 3010 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) { 3011 set_multichannel_mask(ohci, 0); 3012 ctx->mc_completed = 0; 3013 } 3014 3015 return &ctx->base; 3016 3017 out_with_header: 3018 free_page((unsigned long)ctx->header); 3019 out: 3020 spin_lock_irq(&ohci->lock); 3021 3022 switch (type) { 3023 case FW_ISO_CONTEXT_RECEIVE: 3024 *channels |= 1ULL << channel; 3025 break; 3026 3027 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3028 ohci->mc_allocated = false; 3029 break; 3030 } 3031 *mask |= 1 << index; 3032 3033 spin_unlock_irq(&ohci->lock); 3034 3035 return ERR_PTR(ret); 3036 } 3037 3038 static int ohci_start_iso(struct fw_iso_context *base, 3039 s32 cycle, u32 sync, u32 tags) 3040 { 3041 struct iso_context *ctx = container_of(base, struct iso_context, base); 3042 struct fw_ohci *ohci = ctx->context.ohci; 3043 u32 control = IR_CONTEXT_ISOCH_HEADER, match; 3044 int index; 3045 3046 /* the controller cannot start without any queued packets */ 3047 if (ctx->context.last->branch_address == 0) 3048 return -ENODATA; 3049 3050 switch (ctx->base.type) { 3051 case FW_ISO_CONTEXT_TRANSMIT: 3052 index = ctx - ohci->it_context_list; 3053 match = 0; 3054 if (cycle >= 0) 3055 match = IT_CONTEXT_CYCLE_MATCH_ENABLE | 3056 (cycle & 0x7fff) << 16; 3057 3058 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); 3059 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); 3060 context_run(&ctx->context, match); 3061 break; 3062 3063 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3064 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE; 3065 fallthrough; 3066 case FW_ISO_CONTEXT_RECEIVE: 3067 index = ctx - ohci->ir_context_list; 3068 match = (tags << 28) | (sync << 8) | ctx->base.channel; 3069 if (cycle >= 0) { 3070 match |= (cycle & 0x07fff) << 12; 3071 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE; 3072 } 3073 3074 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); 3075 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); 3076 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match); 3077 context_run(&ctx->context, control); 3078 3079 ctx->sync = sync; 3080 ctx->tags = tags; 3081 3082 break; 3083 } 3084 3085 return 0; 3086 } 3087 3088 static int ohci_stop_iso(struct fw_iso_context *base) 3089 { 3090 struct fw_ohci *ohci = fw_ohci(base->card); 3091 struct iso_context *ctx = container_of(base, struct iso_context, base); 3092 int index; 3093 3094 switch (ctx->base.type) { 3095 case FW_ISO_CONTEXT_TRANSMIT: 3096 index = ctx - ohci->it_context_list; 3097 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); 3098 break; 3099 3100 case FW_ISO_CONTEXT_RECEIVE: 3101 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3102 index = ctx - ohci->ir_context_list; 3103 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); 3104 break; 3105 } 3106 flush_writes(ohci); 3107 context_stop(&ctx->context); 3108 tasklet_kill(&ctx->context.tasklet); 3109 3110 return 0; 3111 } 3112 3113 static void ohci_free_iso_context(struct fw_iso_context *base) 3114 { 3115 struct fw_ohci *ohci = fw_ohci(base->card); 3116 struct iso_context *ctx = container_of(base, struct iso_context, base); 3117 unsigned long flags; 3118 int index; 3119 3120 ohci_stop_iso(base); 3121 context_release(&ctx->context); 3122 free_page((unsigned long)ctx->header); 3123 3124 spin_lock_irqsave(&ohci->lock, flags); 3125 3126 switch (base->type) { 3127 case FW_ISO_CONTEXT_TRANSMIT: 3128 index = ctx - ohci->it_context_list; 3129 ohci->it_context_mask |= 1 << index; 3130 break; 3131 3132 case FW_ISO_CONTEXT_RECEIVE: 3133 index = ctx - ohci->ir_context_list; 3134 ohci->ir_context_mask |= 1 << index; 3135 ohci->ir_context_channels |= 1ULL << base->channel; 3136 break; 3137 3138 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3139 index = ctx - ohci->ir_context_list; 3140 ohci->ir_context_mask |= 1 << index; 3141 ohci->ir_context_channels |= ohci->mc_channels; 3142 ohci->mc_channels = 0; 3143 ohci->mc_allocated = false; 3144 break; 3145 } 3146 3147 spin_unlock_irqrestore(&ohci->lock, flags); 3148 } 3149 3150 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels) 3151 { 3152 struct fw_ohci *ohci = fw_ohci(base->card); 3153 unsigned long flags; 3154 int ret; 3155 3156 switch (base->type) { 3157 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3158 3159 spin_lock_irqsave(&ohci->lock, flags); 3160 3161 /* Don't allow multichannel to grab other contexts' channels. */ 3162 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) { 3163 *channels = ohci->ir_context_channels; 3164 ret = -EBUSY; 3165 } else { 3166 set_multichannel_mask(ohci, *channels); 3167 ret = 0; 3168 } 3169 3170 spin_unlock_irqrestore(&ohci->lock, flags); 3171 3172 break; 3173 default: 3174 ret = -EINVAL; 3175 } 3176 3177 return ret; 3178 } 3179 3180 #ifdef CONFIG_PM 3181 static void ohci_resume_iso_dma(struct fw_ohci *ohci) 3182 { 3183 int i; 3184 struct iso_context *ctx; 3185 3186 for (i = 0 ; i < ohci->n_ir ; i++) { 3187 ctx = &ohci->ir_context_list[i]; 3188 if (ctx->context.running) 3189 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 3190 } 3191 3192 for (i = 0 ; i < ohci->n_it ; i++) { 3193 ctx = &ohci->it_context_list[i]; 3194 if (ctx->context.running) 3195 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 3196 } 3197 } 3198 #endif 3199 3200 static int queue_iso_transmit(struct iso_context *ctx, 3201 struct fw_iso_packet *packet, 3202 struct fw_iso_buffer *buffer, 3203 unsigned long payload) 3204 { 3205 struct descriptor *d, *last, *pd; 3206 struct fw_iso_packet *p; 3207 __le32 *header; 3208 dma_addr_t d_bus, page_bus; 3209 u32 z, header_z, payload_z, irq; 3210 u32 payload_index, payload_end_index, next_page_index; 3211 int page, end_page, i, length, offset; 3212 3213 p = packet; 3214 payload_index = payload; 3215 3216 if (p->skip) 3217 z = 1; 3218 else 3219 z = 2; 3220 if (p->header_length > 0) 3221 z++; 3222 3223 /* Determine the first page the payload isn't contained in. */ 3224 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; 3225 if (p->payload_length > 0) 3226 payload_z = end_page - (payload_index >> PAGE_SHIFT); 3227 else 3228 payload_z = 0; 3229 3230 z += payload_z; 3231 3232 /* Get header size in number of descriptors. */ 3233 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d)); 3234 3235 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); 3236 if (d == NULL) 3237 return -ENOMEM; 3238 3239 if (!p->skip) { 3240 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 3241 d[0].req_count = cpu_to_le16(8); 3242 /* 3243 * Link the skip address to this descriptor itself. This causes 3244 * a context to skip a cycle whenever lost cycles or FIFO 3245 * overruns occur, without dropping the data. The application 3246 * should then decide whether this is an error condition or not. 3247 * FIXME: Make the context's cycle-lost behaviour configurable? 3248 */ 3249 d[0].branch_address = cpu_to_le32(d_bus | z); 3250 3251 header = (__le32 *) &d[1]; 3252 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) | 3253 IT_HEADER_TAG(p->tag) | 3254 IT_HEADER_TCODE(TCODE_STREAM_DATA) | 3255 IT_HEADER_CHANNEL(ctx->base.channel) | 3256 IT_HEADER_SPEED(ctx->base.speed)); 3257 header[1] = 3258 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length + 3259 p->payload_length)); 3260 } 3261 3262 if (p->header_length > 0) { 3263 d[2].req_count = cpu_to_le16(p->header_length); 3264 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d)); 3265 memcpy(&d[z], p->header, p->header_length); 3266 } 3267 3268 pd = d + z - payload_z; 3269 payload_end_index = payload_index + p->payload_length; 3270 for (i = 0; i < payload_z; i++) { 3271 page = payload_index >> PAGE_SHIFT; 3272 offset = payload_index & ~PAGE_MASK; 3273 next_page_index = (page + 1) << PAGE_SHIFT; 3274 length = 3275 min(next_page_index, payload_end_index) - payload_index; 3276 pd[i].req_count = cpu_to_le16(length); 3277 3278 page_bus = page_private(buffer->pages[page]); 3279 pd[i].data_address = cpu_to_le32(page_bus + offset); 3280 3281 dma_sync_single_range_for_device(ctx->context.ohci->card.device, 3282 page_bus, offset, length, 3283 DMA_TO_DEVICE); 3284 3285 payload_index += length; 3286 } 3287 3288 if (p->interrupt) 3289 irq = DESCRIPTOR_IRQ_ALWAYS; 3290 else 3291 irq = DESCRIPTOR_NO_IRQ; 3292 3293 last = z == 2 ? d : d + z - 1; 3294 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 3295 DESCRIPTOR_STATUS | 3296 DESCRIPTOR_BRANCH_ALWAYS | 3297 irq); 3298 3299 context_append(&ctx->context, d, z, header_z); 3300 3301 return 0; 3302 } 3303 3304 static int queue_iso_packet_per_buffer(struct iso_context *ctx, 3305 struct fw_iso_packet *packet, 3306 struct fw_iso_buffer *buffer, 3307 unsigned long payload) 3308 { 3309 struct device *device = ctx->context.ohci->card.device; 3310 struct descriptor *d, *pd; 3311 dma_addr_t d_bus, page_bus; 3312 u32 z, header_z, rest; 3313 int i, j, length; 3314 int page, offset, packet_count, header_size, payload_per_buffer; 3315 3316 /* 3317 * The OHCI controller puts the isochronous header and trailer in the 3318 * buffer, so we need at least 8 bytes. 3319 */ 3320 packet_count = packet->header_length / ctx->base.header_size; 3321 header_size = max(ctx->base.header_size, (size_t)8); 3322 3323 /* Get header size in number of descriptors. */ 3324 header_z = DIV_ROUND_UP(header_size, sizeof(*d)); 3325 page = payload >> PAGE_SHIFT; 3326 offset = payload & ~PAGE_MASK; 3327 payload_per_buffer = packet->payload_length / packet_count; 3328 3329 for (i = 0; i < packet_count; i++) { 3330 /* d points to the header descriptor */ 3331 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1; 3332 d = context_get_descriptors(&ctx->context, 3333 z + header_z, &d_bus); 3334 if (d == NULL) 3335 return -ENOMEM; 3336 3337 d->control = cpu_to_le16(DESCRIPTOR_STATUS | 3338 DESCRIPTOR_INPUT_MORE); 3339 if (packet->skip && i == 0) 3340 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3341 d->req_count = cpu_to_le16(header_size); 3342 d->res_count = d->req_count; 3343 d->transfer_status = 0; 3344 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d))); 3345 3346 rest = payload_per_buffer; 3347 pd = d; 3348 for (j = 1; j < z; j++) { 3349 pd++; 3350 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3351 DESCRIPTOR_INPUT_MORE); 3352 3353 if (offset + rest < PAGE_SIZE) 3354 length = rest; 3355 else 3356 length = PAGE_SIZE - offset; 3357 pd->req_count = cpu_to_le16(length); 3358 pd->res_count = pd->req_count; 3359 pd->transfer_status = 0; 3360 3361 page_bus = page_private(buffer->pages[page]); 3362 pd->data_address = cpu_to_le32(page_bus + offset); 3363 3364 dma_sync_single_range_for_device(device, page_bus, 3365 offset, length, 3366 DMA_FROM_DEVICE); 3367 3368 offset = (offset + length) & ~PAGE_MASK; 3369 rest -= length; 3370 if (offset == 0) 3371 page++; 3372 } 3373 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3374 DESCRIPTOR_INPUT_LAST | 3375 DESCRIPTOR_BRANCH_ALWAYS); 3376 if (packet->interrupt && i == packet_count - 1) 3377 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3378 3379 context_append(&ctx->context, d, z, header_z); 3380 } 3381 3382 return 0; 3383 } 3384 3385 static int queue_iso_buffer_fill(struct iso_context *ctx, 3386 struct fw_iso_packet *packet, 3387 struct fw_iso_buffer *buffer, 3388 unsigned long payload) 3389 { 3390 struct descriptor *d; 3391 dma_addr_t d_bus, page_bus; 3392 int page, offset, rest, z, i, length; 3393 3394 page = payload >> PAGE_SHIFT; 3395 offset = payload & ~PAGE_MASK; 3396 rest = packet->payload_length; 3397 3398 /* We need one descriptor for each page in the buffer. */ 3399 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE); 3400 3401 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count)) 3402 return -EFAULT; 3403 3404 for (i = 0; i < z; i++) { 3405 d = context_get_descriptors(&ctx->context, 1, &d_bus); 3406 if (d == NULL) 3407 return -ENOMEM; 3408 3409 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 3410 DESCRIPTOR_BRANCH_ALWAYS); 3411 if (packet->skip && i == 0) 3412 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3413 if (packet->interrupt && i == z - 1) 3414 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3415 3416 if (offset + rest < PAGE_SIZE) 3417 length = rest; 3418 else 3419 length = PAGE_SIZE - offset; 3420 d->req_count = cpu_to_le16(length); 3421 d->res_count = d->req_count; 3422 d->transfer_status = 0; 3423 3424 page_bus = page_private(buffer->pages[page]); 3425 d->data_address = cpu_to_le32(page_bus + offset); 3426 3427 dma_sync_single_range_for_device(ctx->context.ohci->card.device, 3428 page_bus, offset, length, 3429 DMA_FROM_DEVICE); 3430 3431 rest -= length; 3432 offset = 0; 3433 page++; 3434 3435 context_append(&ctx->context, d, 1, 0); 3436 } 3437 3438 return 0; 3439 } 3440 3441 static int ohci_queue_iso(struct fw_iso_context *base, 3442 struct fw_iso_packet *packet, 3443 struct fw_iso_buffer *buffer, 3444 unsigned long payload) 3445 { 3446 struct iso_context *ctx = container_of(base, struct iso_context, base); 3447 unsigned long flags; 3448 int ret = -ENOSYS; 3449 3450 spin_lock_irqsave(&ctx->context.ohci->lock, flags); 3451 switch (base->type) { 3452 case FW_ISO_CONTEXT_TRANSMIT: 3453 ret = queue_iso_transmit(ctx, packet, buffer, payload); 3454 break; 3455 case FW_ISO_CONTEXT_RECEIVE: 3456 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload); 3457 break; 3458 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3459 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload); 3460 break; 3461 } 3462 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags); 3463 3464 return ret; 3465 } 3466 3467 static void ohci_flush_queue_iso(struct fw_iso_context *base) 3468 { 3469 struct context *ctx = 3470 &container_of(base, struct iso_context, base)->context; 3471 3472 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 3473 } 3474 3475 static int ohci_flush_iso_completions(struct fw_iso_context *base) 3476 { 3477 struct iso_context *ctx = container_of(base, struct iso_context, base); 3478 int ret = 0; 3479 3480 tasklet_disable_in_atomic(&ctx->context.tasklet); 3481 3482 if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) { 3483 context_tasklet((unsigned long)&ctx->context); 3484 3485 switch (base->type) { 3486 case FW_ISO_CONTEXT_TRANSMIT: 3487 case FW_ISO_CONTEXT_RECEIVE: 3488 if (ctx->header_length != 0) 3489 flush_iso_completions(ctx); 3490 break; 3491 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3492 if (ctx->mc_completed != 0) 3493 flush_ir_buffer_fill(ctx); 3494 break; 3495 default: 3496 ret = -ENOSYS; 3497 } 3498 3499 clear_bit_unlock(0, &ctx->flushing_completions); 3500 smp_mb__after_atomic(); 3501 } 3502 3503 tasklet_enable(&ctx->context.tasklet); 3504 3505 return ret; 3506 } 3507 3508 static const struct fw_card_driver ohci_driver = { 3509 .enable = ohci_enable, 3510 .read_phy_reg = ohci_read_phy_reg, 3511 .update_phy_reg = ohci_update_phy_reg, 3512 .set_config_rom = ohci_set_config_rom, 3513 .send_request = ohci_send_request, 3514 .send_response = ohci_send_response, 3515 .cancel_packet = ohci_cancel_packet, 3516 .enable_phys_dma = ohci_enable_phys_dma, 3517 .read_csr = ohci_read_csr, 3518 .write_csr = ohci_write_csr, 3519 3520 .allocate_iso_context = ohci_allocate_iso_context, 3521 .free_iso_context = ohci_free_iso_context, 3522 .set_iso_channels = ohci_set_iso_channels, 3523 .queue_iso = ohci_queue_iso, 3524 .flush_queue_iso = ohci_flush_queue_iso, 3525 .flush_iso_completions = ohci_flush_iso_completions, 3526 .start_iso = ohci_start_iso, 3527 .stop_iso = ohci_stop_iso, 3528 }; 3529 3530 #ifdef CONFIG_PPC_PMAC 3531 static void pmac_ohci_on(struct pci_dev *dev) 3532 { 3533 if (machine_is(powermac)) { 3534 struct device_node *ofn = pci_device_to_OF_node(dev); 3535 3536 if (ofn) { 3537 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1); 3538 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1); 3539 } 3540 } 3541 } 3542 3543 static void pmac_ohci_off(struct pci_dev *dev) 3544 { 3545 if (machine_is(powermac)) { 3546 struct device_node *ofn = pci_device_to_OF_node(dev); 3547 3548 if (ofn) { 3549 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0); 3550 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0); 3551 } 3552 } 3553 } 3554 #else 3555 static inline void pmac_ohci_on(struct pci_dev *dev) {} 3556 static inline void pmac_ohci_off(struct pci_dev *dev) {} 3557 #endif /* CONFIG_PPC_PMAC */ 3558 3559 static void release_ohci(struct device *dev, void *data) 3560 { 3561 struct pci_dev *pdev = to_pci_dev(dev); 3562 struct fw_ohci *ohci = pci_get_drvdata(pdev); 3563 3564 pmac_ohci_off(pdev); 3565 3566 ar_context_release(&ohci->ar_response_ctx); 3567 ar_context_release(&ohci->ar_request_ctx); 3568 3569 dev_notice(dev, "removed fw-ohci device\n"); 3570 } 3571 3572 static int pci_probe(struct pci_dev *dev, 3573 const struct pci_device_id *ent) 3574 { 3575 struct fw_ohci *ohci; 3576 u32 bus_options, max_receive, link_speed, version; 3577 u64 guid; 3578 int i, err; 3579 size_t size; 3580 3581 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) { 3582 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n"); 3583 return -ENOSYS; 3584 } 3585 3586 ohci = devres_alloc(release_ohci, sizeof(*ohci), GFP_KERNEL); 3587 if (ohci == NULL) 3588 return -ENOMEM; 3589 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); 3590 pci_set_drvdata(dev, ohci); 3591 pmac_ohci_on(dev); 3592 devres_add(&dev->dev, ohci); 3593 3594 err = pcim_enable_device(dev); 3595 if (err) { 3596 dev_err(&dev->dev, "failed to enable OHCI hardware\n"); 3597 return err; 3598 } 3599 3600 pci_set_master(dev); 3601 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); 3602 3603 spin_lock_init(&ohci->lock); 3604 mutex_init(&ohci->phy_reg_mutex); 3605 3606 INIT_WORK(&ohci->bus_reset_work, bus_reset_work); 3607 3608 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) || 3609 pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) { 3610 ohci_err(ohci, "invalid MMIO resource\n"); 3611 return -ENXIO; 3612 } 3613 3614 err = pcim_iomap_regions(dev, 1 << 0, ohci_driver_name); 3615 if (err) { 3616 ohci_err(ohci, "request and map MMIO resource unavailable\n"); 3617 return -ENXIO; 3618 } 3619 ohci->registers = pcim_iomap_table(dev)[0]; 3620 3621 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++) 3622 if ((ohci_quirks[i].vendor == dev->vendor) && 3623 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID || 3624 ohci_quirks[i].device == dev->device) && 3625 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID || 3626 ohci_quirks[i].revision >= dev->revision)) { 3627 ohci->quirks = ohci_quirks[i].flags; 3628 break; 3629 } 3630 if (param_quirks) 3631 ohci->quirks = param_quirks; 3632 3633 /* 3634 * Because dma_alloc_coherent() allocates at least one page, 3635 * we save space by using a common buffer for the AR request/ 3636 * response descriptors and the self IDs buffer. 3637 */ 3638 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4); 3639 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2); 3640 ohci->misc_buffer = dmam_alloc_coherent(&dev->dev, PAGE_SIZE, &ohci->misc_buffer_bus, 3641 GFP_KERNEL); 3642 if (!ohci->misc_buffer) 3643 return -ENOMEM; 3644 3645 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0, 3646 OHCI1394_AsReqRcvContextControlSet); 3647 if (err < 0) 3648 return err; 3649 3650 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4, 3651 OHCI1394_AsRspRcvContextControlSet); 3652 if (err < 0) 3653 return err; 3654 3655 err = context_init(&ohci->at_request_ctx, ohci, 3656 OHCI1394_AsReqTrContextControlSet, handle_at_packet); 3657 if (err < 0) 3658 return err; 3659 3660 err = context_init(&ohci->at_response_ctx, ohci, 3661 OHCI1394_AsRspTrContextControlSet, handle_at_packet); 3662 if (err < 0) 3663 return err; 3664 3665 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); 3666 ohci->ir_context_channels = ~0ULL; 3667 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); 3668 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); 3669 ohci->ir_context_mask = ohci->ir_context_support; 3670 ohci->n_ir = hweight32(ohci->ir_context_mask); 3671 size = sizeof(struct iso_context) * ohci->n_ir; 3672 ohci->ir_context_list = devm_kzalloc(&dev->dev, size, GFP_KERNEL); 3673 if (!ohci->ir_context_list) 3674 return -ENOMEM; 3675 3676 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); 3677 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); 3678 /* JMicron JMB38x often shows 0 at first read, just ignore it */ 3679 if (!ohci->it_context_support) { 3680 ohci_notice(ohci, "overriding IsoXmitIntMask\n"); 3681 ohci->it_context_support = 0xf; 3682 } 3683 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); 3684 ohci->it_context_mask = ohci->it_context_support; 3685 ohci->n_it = hweight32(ohci->it_context_mask); 3686 size = sizeof(struct iso_context) * ohci->n_it; 3687 ohci->it_context_list = devm_kzalloc(&dev->dev, size, GFP_KERNEL); 3688 if (!ohci->it_context_list) 3689 return -ENOMEM; 3690 3691 ohci->self_id = ohci->misc_buffer + PAGE_SIZE/2; 3692 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2; 3693 3694 bus_options = reg_read(ohci, OHCI1394_BusOptions); 3695 max_receive = (bus_options >> 12) & 0xf; 3696 link_speed = bus_options & 0x7; 3697 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | 3698 reg_read(ohci, OHCI1394_GUIDLo); 3699 3700 if (!(ohci->quirks & QUIRK_NO_MSI)) 3701 pci_enable_msi(dev); 3702 err = devm_request_irq(&dev->dev, dev->irq, irq_handler, 3703 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED, ohci_driver_name, ohci); 3704 if (err < 0) { 3705 ohci_err(ohci, "failed to allocate interrupt %d\n", dev->irq); 3706 goto fail_msi; 3707 } 3708 3709 err = fw_card_add(&ohci->card, max_receive, link_speed, guid); 3710 if (err) 3711 goto fail_msi; 3712 3713 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 3714 ohci_notice(ohci, 3715 "added OHCI v%x.%x device as card %d, " 3716 "%d IR + %d IT contexts, quirks 0x%x%s\n", 3717 version >> 16, version & 0xff, ohci->card.index, 3718 ohci->n_ir, ohci->n_it, ohci->quirks, 3719 reg_read(ohci, OHCI1394_PhyUpperBound) ? 3720 ", physUB" : ""); 3721 3722 return 0; 3723 3724 fail_msi: 3725 pci_disable_msi(dev); 3726 3727 return err; 3728 } 3729 3730 static void pci_remove(struct pci_dev *dev) 3731 { 3732 struct fw_ohci *ohci = pci_get_drvdata(dev); 3733 3734 /* 3735 * If the removal is happening from the suspend state, LPS won't be 3736 * enabled and host registers (eg., IntMaskClear) won't be accessible. 3737 */ 3738 if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) { 3739 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 3740 flush_writes(ohci); 3741 } 3742 cancel_work_sync(&ohci->bus_reset_work); 3743 fw_core_remove_card(&ohci->card); 3744 3745 /* 3746 * FIXME: Fail all pending packets here, now that the upper 3747 * layers can't queue any more. 3748 */ 3749 3750 software_reset(ohci); 3751 3752 pci_disable_msi(dev); 3753 3754 dev_notice(&dev->dev, "removing fw-ohci device\n"); 3755 } 3756 3757 #ifdef CONFIG_PM 3758 static int pci_suspend(struct pci_dev *dev, pm_message_t state) 3759 { 3760 struct fw_ohci *ohci = pci_get_drvdata(dev); 3761 int err; 3762 3763 software_reset(ohci); 3764 err = pci_save_state(dev); 3765 if (err) { 3766 ohci_err(ohci, "pci_save_state failed\n"); 3767 return err; 3768 } 3769 err = pci_set_power_state(dev, pci_choose_state(dev, state)); 3770 if (err) 3771 ohci_err(ohci, "pci_set_power_state failed with %d\n", err); 3772 pmac_ohci_off(dev); 3773 3774 return 0; 3775 } 3776 3777 static int pci_resume(struct pci_dev *dev) 3778 { 3779 struct fw_ohci *ohci = pci_get_drvdata(dev); 3780 int err; 3781 3782 pmac_ohci_on(dev); 3783 pci_set_power_state(dev, PCI_D0); 3784 pci_restore_state(dev); 3785 err = pci_enable_device(dev); 3786 if (err) { 3787 ohci_err(ohci, "pci_enable_device failed\n"); 3788 return err; 3789 } 3790 3791 /* Some systems don't setup GUID register on resume from ram */ 3792 if (!reg_read(ohci, OHCI1394_GUIDLo) && 3793 !reg_read(ohci, OHCI1394_GUIDHi)) { 3794 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid); 3795 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32)); 3796 } 3797 3798 err = ohci_enable(&ohci->card, NULL, 0); 3799 if (err) 3800 return err; 3801 3802 ohci_resume_iso_dma(ohci); 3803 3804 return 0; 3805 } 3806 #endif 3807 3808 static const struct pci_device_id pci_table[] = { 3809 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, 3810 { } 3811 }; 3812 3813 MODULE_DEVICE_TABLE(pci, pci_table); 3814 3815 static struct pci_driver fw_ohci_pci_driver = { 3816 .name = ohci_driver_name, 3817 .id_table = pci_table, 3818 .probe = pci_probe, 3819 .remove = pci_remove, 3820 #ifdef CONFIG_PM 3821 .resume = pci_resume, 3822 .suspend = pci_suspend, 3823 #endif 3824 }; 3825 3826 static int __init fw_ohci_init(void) 3827 { 3828 selfid_workqueue = alloc_workqueue(KBUILD_MODNAME, WQ_MEM_RECLAIM, 0); 3829 if (!selfid_workqueue) 3830 return -ENOMEM; 3831 3832 return pci_register_driver(&fw_ohci_pci_driver); 3833 } 3834 3835 static void __exit fw_ohci_cleanup(void) 3836 { 3837 pci_unregister_driver(&fw_ohci_pci_driver); 3838 destroy_workqueue(selfid_workqueue); 3839 } 3840 3841 module_init(fw_ohci_init); 3842 module_exit(fw_ohci_cleanup); 3843 3844 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); 3845 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); 3846 MODULE_LICENSE("GPL"); 3847 3848 /* Provide a module alias so root-on-sbp2 initrds don't break. */ 3849 MODULE_ALIAS("ohci1394"); 3850