1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for OHCI 1394 controllers 4 * 5 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/bug.h> 10 #include <linux/compiler.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/firewire.h> 15 #include <linux/firewire-constants.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/mm.h> 22 #include <linux/module.h> 23 #include <linux/moduleparam.h> 24 #include <linux/mutex.h> 25 #include <linux/pci.h> 26 #include <linux/pci_ids.h> 27 #include <linux/slab.h> 28 #include <linux/spinlock.h> 29 #include <linux/string.h> 30 #include <linux/time.h> 31 #include <linux/vmalloc.h> 32 #include <linux/workqueue.h> 33 34 #include <asm/byteorder.h> 35 #include <asm/page.h> 36 37 #ifdef CONFIG_PPC_PMAC 38 #include <asm/pmac_feature.h> 39 #endif 40 41 #include "core.h" 42 #include "ohci.h" 43 44 #define ohci_info(ohci, f, args...) dev_info(ohci->card.device, f, ##args) 45 #define ohci_notice(ohci, f, args...) dev_notice(ohci->card.device, f, ##args) 46 #define ohci_err(ohci, f, args...) dev_err(ohci->card.device, f, ##args) 47 48 #define DESCRIPTOR_OUTPUT_MORE 0 49 #define DESCRIPTOR_OUTPUT_LAST (1 << 12) 50 #define DESCRIPTOR_INPUT_MORE (2 << 12) 51 #define DESCRIPTOR_INPUT_LAST (3 << 12) 52 #define DESCRIPTOR_STATUS (1 << 11) 53 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8) 54 #define DESCRIPTOR_PING (1 << 7) 55 #define DESCRIPTOR_YY (1 << 6) 56 #define DESCRIPTOR_NO_IRQ (0 << 4) 57 #define DESCRIPTOR_IRQ_ERROR (1 << 4) 58 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4) 59 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2) 60 #define DESCRIPTOR_WAIT (3 << 0) 61 62 #define DESCRIPTOR_CMD (0xf << 12) 63 64 struct descriptor { 65 __le16 req_count; 66 __le16 control; 67 __le32 data_address; 68 __le32 branch_address; 69 __le16 res_count; 70 __le16 transfer_status; 71 } __attribute__((aligned(16))); 72 73 #define CONTROL_SET(regs) (regs) 74 #define CONTROL_CLEAR(regs) ((regs) + 4) 75 #define COMMAND_PTR(regs) ((regs) + 12) 76 #define CONTEXT_MATCH(regs) ((regs) + 16) 77 78 #define AR_BUFFER_SIZE (32*1024) 79 #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE) 80 /* we need at least two pages for proper list management */ 81 #define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2) 82 83 #define MAX_ASYNC_PAYLOAD 4096 84 #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4) 85 #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE) 86 87 struct ar_context { 88 struct fw_ohci *ohci; 89 struct page *pages[AR_BUFFERS]; 90 void *buffer; 91 struct descriptor *descriptors; 92 dma_addr_t descriptors_bus; 93 void *pointer; 94 unsigned int last_buffer_index; 95 u32 regs; 96 struct tasklet_struct tasklet; 97 }; 98 99 struct context; 100 101 typedef int (*descriptor_callback_t)(struct context *ctx, 102 struct descriptor *d, 103 struct descriptor *last); 104 105 /* 106 * A buffer that contains a block of DMA-able coherent memory used for 107 * storing a portion of a DMA descriptor program. 108 */ 109 struct descriptor_buffer { 110 struct list_head list; 111 dma_addr_t buffer_bus; 112 size_t buffer_size; 113 size_t used; 114 struct descriptor buffer[]; 115 }; 116 117 struct context { 118 struct fw_ohci *ohci; 119 u32 regs; 120 int total_allocation; 121 u32 current_bus; 122 bool running; 123 bool flushing; 124 125 /* 126 * List of page-sized buffers for storing DMA descriptors. 127 * Head of list contains buffers in use and tail of list contains 128 * free buffers. 129 */ 130 struct list_head buffer_list; 131 132 /* 133 * Pointer to a buffer inside buffer_list that contains the tail 134 * end of the current DMA program. 135 */ 136 struct descriptor_buffer *buffer_tail; 137 138 /* 139 * The descriptor containing the branch address of the first 140 * descriptor that has not yet been filled by the device. 141 */ 142 struct descriptor *last; 143 144 /* 145 * The last descriptor block in the DMA program. It contains the branch 146 * address that must be updated upon appending a new descriptor. 147 */ 148 struct descriptor *prev; 149 int prev_z; 150 151 descriptor_callback_t callback; 152 153 struct tasklet_struct tasklet; 154 }; 155 156 #define IT_HEADER_SY(v) ((v) << 0) 157 #define IT_HEADER_TCODE(v) ((v) << 4) 158 #define IT_HEADER_CHANNEL(v) ((v) << 8) 159 #define IT_HEADER_TAG(v) ((v) << 14) 160 #define IT_HEADER_SPEED(v) ((v) << 16) 161 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16) 162 163 struct iso_context { 164 struct fw_iso_context base; 165 struct context context; 166 void *header; 167 size_t header_length; 168 unsigned long flushing_completions; 169 u32 mc_buffer_bus; 170 u16 mc_completed; 171 u16 last_timestamp; 172 u8 sync; 173 u8 tags; 174 }; 175 176 #define CONFIG_ROM_SIZE 1024 177 178 struct fw_ohci { 179 struct fw_card card; 180 181 __iomem char *registers; 182 int node_id; 183 int generation; 184 int request_generation; /* for timestamping incoming requests */ 185 unsigned quirks; 186 unsigned int pri_req_max; 187 u32 bus_time; 188 bool bus_time_running; 189 bool is_root; 190 bool csr_state_setclear_abdicate; 191 int n_ir; 192 int n_it; 193 /* 194 * Spinlock for accessing fw_ohci data. Never call out of 195 * this driver with this lock held. 196 */ 197 spinlock_t lock; 198 199 struct mutex phy_reg_mutex; 200 201 void *misc_buffer; 202 dma_addr_t misc_buffer_bus; 203 204 struct ar_context ar_request_ctx; 205 struct ar_context ar_response_ctx; 206 struct context at_request_ctx; 207 struct context at_response_ctx; 208 209 u32 it_context_support; 210 u32 it_context_mask; /* unoccupied IT contexts */ 211 struct iso_context *it_context_list; 212 u64 ir_context_channels; /* unoccupied channels */ 213 u32 ir_context_support; 214 u32 ir_context_mask; /* unoccupied IR contexts */ 215 struct iso_context *ir_context_list; 216 u64 mc_channels; /* channels in use by the multichannel IR context */ 217 bool mc_allocated; 218 219 __be32 *config_rom; 220 dma_addr_t config_rom_bus; 221 __be32 *next_config_rom; 222 dma_addr_t next_config_rom_bus; 223 __be32 next_header; 224 225 __le32 *self_id; 226 dma_addr_t self_id_bus; 227 struct work_struct bus_reset_work; 228 229 u32 self_id_buffer[512]; 230 }; 231 232 static struct workqueue_struct *selfid_workqueue; 233 234 static inline struct fw_ohci *fw_ohci(struct fw_card *card) 235 { 236 return container_of(card, struct fw_ohci, card); 237 } 238 239 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 240 #define IR_CONTEXT_BUFFER_FILL 0x80000000 241 #define IR_CONTEXT_ISOCH_HEADER 0x40000000 242 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 243 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 244 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 245 246 #define CONTEXT_RUN 0x8000 247 #define CONTEXT_WAKE 0x1000 248 #define CONTEXT_DEAD 0x0800 249 #define CONTEXT_ACTIVE 0x0400 250 251 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf 252 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 253 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 254 255 #define OHCI1394_REGISTER_SIZE 0x800 256 #define OHCI1394_PCI_HCI_Control 0x40 257 #define SELF_ID_BUF_SIZE 0x800 258 #define OHCI_TCODE_PHY_PACKET 0x0e 259 #define OHCI_VERSION_1_1 0x010010 260 261 static char ohci_driver_name[] = KBUILD_MODNAME; 262 263 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd 264 #define PCI_DEVICE_ID_AGERE_FW643 0x5901 265 #define PCI_DEVICE_ID_CREATIVE_SB1394 0x4001 266 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380 267 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009 268 #define PCI_DEVICE_ID_TI_TSB12LV26 0x8020 269 #define PCI_DEVICE_ID_TI_TSB82AA2 0x8025 270 #define PCI_DEVICE_ID_VIA_VT630X 0x3044 271 #define PCI_REV_ID_VIA_VT6306 0x46 272 #define PCI_DEVICE_ID_VIA_VT6315 0x3403 273 274 #define QUIRK_CYCLE_TIMER 0x1 275 #define QUIRK_RESET_PACKET 0x2 276 #define QUIRK_BE_HEADERS 0x4 277 #define QUIRK_NO_1394A 0x8 278 #define QUIRK_NO_MSI 0x10 279 #define QUIRK_TI_SLLZ059 0x20 280 #define QUIRK_IR_WAKE 0x40 281 282 /* In case of multiple matches in ohci_quirks[], only the first one is used. */ 283 static const struct { 284 unsigned short vendor, device, revision, flags; 285 } ohci_quirks[] = { 286 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID, 287 QUIRK_CYCLE_TIMER}, 288 289 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID, 290 QUIRK_BE_HEADERS}, 291 292 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6, 293 QUIRK_NO_MSI}, 294 295 {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID, 296 QUIRK_RESET_PACKET}, 297 298 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID, 299 QUIRK_NO_MSI}, 300 301 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID, 302 QUIRK_CYCLE_TIMER}, 303 304 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID, 305 QUIRK_NO_MSI}, 306 307 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID, 308 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, 309 310 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID, 311 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A}, 312 313 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID, 314 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059}, 315 316 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID, 317 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059}, 318 319 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID, 320 QUIRK_RESET_PACKET}, 321 322 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306, 323 QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE}, 324 325 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, 0, 326 QUIRK_CYCLE_TIMER /* FIXME: necessary? */ | QUIRK_NO_MSI}, 327 328 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, PCI_ANY_ID, 329 QUIRK_NO_MSI}, 330 331 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID, 332 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, 333 }; 334 335 /* This overrides anything that was found in ohci_quirks[]. */ 336 static int param_quirks; 337 module_param_named(quirks, param_quirks, int, 0644); 338 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0" 339 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER) 340 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET) 341 ", AR/selfID endianness = " __stringify(QUIRK_BE_HEADERS) 342 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A) 343 ", disable MSI = " __stringify(QUIRK_NO_MSI) 344 ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059) 345 ", IR wake unreliable = " __stringify(QUIRK_IR_WAKE) 346 ")"); 347 348 #define OHCI_PARAM_DEBUG_AT_AR 1 349 #define OHCI_PARAM_DEBUG_SELFIDS 2 350 #define OHCI_PARAM_DEBUG_IRQS 4 351 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */ 352 353 static int param_debug; 354 module_param_named(debug, param_debug, int, 0644); 355 MODULE_PARM_DESC(debug, "Verbose logging (default = 0" 356 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR) 357 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS) 358 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS) 359 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS) 360 ", or a combination, or all = -1)"); 361 362 static bool param_remote_dma; 363 module_param_named(remote_dma, param_remote_dma, bool, 0444); 364 MODULE_PARM_DESC(remote_dma, "Enable unfiltered remote DMA (default = N)"); 365 366 static void log_irqs(struct fw_ohci *ohci, u32 evt) 367 { 368 if (likely(!(param_debug & 369 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS)))) 370 return; 371 372 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) && 373 !(evt & OHCI1394_busReset)) 374 return; 375 376 ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt, 377 evt & OHCI1394_selfIDComplete ? " selfID" : "", 378 evt & OHCI1394_RQPkt ? " AR_req" : "", 379 evt & OHCI1394_RSPkt ? " AR_resp" : "", 380 evt & OHCI1394_reqTxComplete ? " AT_req" : "", 381 evt & OHCI1394_respTxComplete ? " AT_resp" : "", 382 evt & OHCI1394_isochRx ? " IR" : "", 383 evt & OHCI1394_isochTx ? " IT" : "", 384 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", 385 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", 386 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "", 387 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "", 388 evt & OHCI1394_regAccessFail ? " regAccessFail" : "", 389 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "", 390 evt & OHCI1394_busReset ? " busReset" : "", 391 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | 392 OHCI1394_RSPkt | OHCI1394_reqTxComplete | 393 OHCI1394_respTxComplete | OHCI1394_isochRx | 394 OHCI1394_isochTx | OHCI1394_postedWriteErr | 395 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds | 396 OHCI1394_cycleInconsistent | 397 OHCI1394_regAccessFail | OHCI1394_busReset) 398 ? " ?" : ""); 399 } 400 401 static const char *speed[] = { 402 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta", 403 }; 404 static const char *power[] = { 405 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W", 406 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W", 407 }; 408 static const char port[] = { '.', '-', 'p', 'c', }; 409 410 static char _p(u32 *s, int shift) 411 { 412 return port[*s >> shift & 3]; 413 } 414 415 static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count) 416 { 417 u32 *s; 418 419 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) 420 return; 421 422 ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n", 423 self_id_count, generation, ohci->node_id); 424 425 for (s = ohci->self_id_buffer; self_id_count--; ++s) 426 if ((*s & 1 << 23) == 0) 427 ohci_notice(ohci, 428 "selfID 0: %08x, phy %d [%c%c%c] %s gc=%d %s %s%s%s\n", 429 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2), 430 speed[*s >> 14 & 3], *s >> 16 & 63, 431 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", 432 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); 433 else 434 ohci_notice(ohci, 435 "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n", 436 *s, *s >> 24 & 63, 437 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10), 438 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2)); 439 } 440 441 static const char *evts[] = { 442 [0x00] = "evt_no_status", [0x01] = "-reserved-", 443 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack", 444 [0x04] = "evt_underrun", [0x05] = "evt_overrun", 445 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read", 446 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset", 447 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err", 448 [0x0c] = "-reserved-", [0x0d] = "-reserved-", 449 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed", 450 [0x10] = "-reserved-", [0x11] = "ack_complete", 451 [0x12] = "ack_pending ", [0x13] = "-reserved-", 452 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A", 453 [0x16] = "ack_busy_B", [0x17] = "-reserved-", 454 [0x18] = "-reserved-", [0x19] = "-reserved-", 455 [0x1a] = "-reserved-", [0x1b] = "ack_tardy", 456 [0x1c] = "-reserved-", [0x1d] = "ack_data_error", 457 [0x1e] = "ack_type_error", [0x1f] = "-reserved-", 458 [0x20] = "pending/cancelled", 459 }; 460 static const char *tcodes[] = { 461 [0x0] = "QW req", [0x1] = "BW req", 462 [0x2] = "W resp", [0x3] = "-reserved-", 463 [0x4] = "QR req", [0x5] = "BR req", 464 [0x6] = "QR resp", [0x7] = "BR resp", 465 [0x8] = "cycle start", [0x9] = "Lk req", 466 [0xa] = "async stream packet", [0xb] = "Lk resp", 467 [0xc] = "-reserved-", [0xd] = "-reserved-", 468 [0xe] = "link internal", [0xf] = "-reserved-", 469 }; 470 471 static void log_ar_at_event(struct fw_ohci *ohci, 472 char dir, int speed, u32 *header, int evt) 473 { 474 int tcode = header[0] >> 4 & 0xf; 475 char specific[12]; 476 477 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR))) 478 return; 479 480 if (unlikely(evt >= ARRAY_SIZE(evts))) 481 evt = 0x1f; 482 483 if (evt == OHCI1394_evt_bus_reset) { 484 ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n", 485 dir, (header[2] >> 16) & 0xff); 486 return; 487 } 488 489 switch (tcode) { 490 case 0x0: case 0x6: case 0x8: 491 snprintf(specific, sizeof(specific), " = %08x", 492 be32_to_cpu((__force __be32)header[3])); 493 break; 494 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb: 495 snprintf(specific, sizeof(specific), " %x,%x", 496 header[3] >> 16, header[3] & 0xffff); 497 break; 498 default: 499 specific[0] = '\0'; 500 } 501 502 switch (tcode) { 503 case 0xa: 504 ohci_notice(ohci, "A%c %s, %s\n", 505 dir, evts[evt], tcodes[tcode]); 506 break; 507 case 0xe: 508 ohci_notice(ohci, "A%c %s, PHY %08x %08x\n", 509 dir, evts[evt], header[1], header[2]); 510 break; 511 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9: 512 ohci_notice(ohci, 513 "A%c spd %x tl %02x, %04x -> %04x, %s, %s, %04x%08x%s\n", 514 dir, speed, header[0] >> 10 & 0x3f, 515 header[1] >> 16, header[0] >> 16, evts[evt], 516 tcodes[tcode], header[1] & 0xffff, header[2], specific); 517 break; 518 default: 519 ohci_notice(ohci, 520 "A%c spd %x tl %02x, %04x -> %04x, %s, %s%s\n", 521 dir, speed, header[0] >> 10 & 0x3f, 522 header[1] >> 16, header[0] >> 16, evts[evt], 523 tcodes[tcode], specific); 524 } 525 } 526 527 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) 528 { 529 writel(data, ohci->registers + offset); 530 } 531 532 static inline u32 reg_read(const struct fw_ohci *ohci, int offset) 533 { 534 return readl(ohci->registers + offset); 535 } 536 537 static inline void flush_writes(const struct fw_ohci *ohci) 538 { 539 /* Do a dummy read to flush writes. */ 540 reg_read(ohci, OHCI1394_Version); 541 } 542 543 /* 544 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and 545 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex. 546 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg() 547 * directly. Exceptions are intrinsically serialized contexts like pci_probe. 548 */ 549 static int read_phy_reg(struct fw_ohci *ohci, int addr) 550 { 551 u32 val; 552 int i; 553 554 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); 555 for (i = 0; i < 3 + 100; i++) { 556 val = reg_read(ohci, OHCI1394_PhyControl); 557 if (!~val) 558 return -ENODEV; /* Card was ejected. */ 559 560 if (val & OHCI1394_PhyControl_ReadDone) 561 return OHCI1394_PhyControl_ReadData(val); 562 563 /* 564 * Try a few times without waiting. Sleeping is necessary 565 * only when the link/PHY interface is busy. 566 */ 567 if (i >= 3) 568 msleep(1); 569 } 570 ohci_err(ohci, "failed to read phy reg %d\n", addr); 571 dump_stack(); 572 573 return -EBUSY; 574 } 575 576 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val) 577 { 578 int i; 579 580 reg_write(ohci, OHCI1394_PhyControl, 581 OHCI1394_PhyControl_Write(addr, val)); 582 for (i = 0; i < 3 + 100; i++) { 583 val = reg_read(ohci, OHCI1394_PhyControl); 584 if (!~val) 585 return -ENODEV; /* Card was ejected. */ 586 587 if (!(val & OHCI1394_PhyControl_WritePending)) 588 return 0; 589 590 if (i >= 3) 591 msleep(1); 592 } 593 ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val); 594 dump_stack(); 595 596 return -EBUSY; 597 } 598 599 static int update_phy_reg(struct fw_ohci *ohci, int addr, 600 int clear_bits, int set_bits) 601 { 602 int ret = read_phy_reg(ohci, addr); 603 if (ret < 0) 604 return ret; 605 606 /* 607 * The interrupt status bits are cleared by writing a one bit. 608 * Avoid clearing them unless explicitly requested in set_bits. 609 */ 610 if (addr == 5) 611 clear_bits |= PHY_INT_STATUS_BITS; 612 613 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits); 614 } 615 616 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr) 617 { 618 int ret; 619 620 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5); 621 if (ret < 0) 622 return ret; 623 624 return read_phy_reg(ohci, addr); 625 } 626 627 static int ohci_read_phy_reg(struct fw_card *card, int addr) 628 { 629 struct fw_ohci *ohci = fw_ohci(card); 630 int ret; 631 632 mutex_lock(&ohci->phy_reg_mutex); 633 ret = read_phy_reg(ohci, addr); 634 mutex_unlock(&ohci->phy_reg_mutex); 635 636 return ret; 637 } 638 639 static int ohci_update_phy_reg(struct fw_card *card, int addr, 640 int clear_bits, int set_bits) 641 { 642 struct fw_ohci *ohci = fw_ohci(card); 643 int ret; 644 645 mutex_lock(&ohci->phy_reg_mutex); 646 ret = update_phy_reg(ohci, addr, clear_bits, set_bits); 647 mutex_unlock(&ohci->phy_reg_mutex); 648 649 return ret; 650 } 651 652 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i) 653 { 654 return page_private(ctx->pages[i]); 655 } 656 657 static void ar_context_link_page(struct ar_context *ctx, unsigned int index) 658 { 659 struct descriptor *d; 660 661 d = &ctx->descriptors[index]; 662 d->branch_address &= cpu_to_le32(~0xf); 663 d->res_count = cpu_to_le16(PAGE_SIZE); 664 d->transfer_status = 0; 665 666 wmb(); /* finish init of new descriptors before branch_address update */ 667 d = &ctx->descriptors[ctx->last_buffer_index]; 668 d->branch_address |= cpu_to_le32(1); 669 670 ctx->last_buffer_index = index; 671 672 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 673 } 674 675 static void ar_context_release(struct ar_context *ctx) 676 { 677 struct device *dev = ctx->ohci->card.device; 678 unsigned int i; 679 680 vunmap(ctx->buffer); 681 682 for (i = 0; i < AR_BUFFERS; i++) { 683 if (ctx->pages[i]) 684 dma_free_pages(dev, PAGE_SIZE, ctx->pages[i], 685 ar_buffer_bus(ctx, i), DMA_FROM_DEVICE); 686 } 687 } 688 689 static void ar_context_abort(struct ar_context *ctx, const char *error_msg) 690 { 691 struct fw_ohci *ohci = ctx->ohci; 692 693 if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) { 694 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 695 flush_writes(ohci); 696 697 ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg); 698 } 699 /* FIXME: restart? */ 700 } 701 702 static inline unsigned int ar_next_buffer_index(unsigned int index) 703 { 704 return (index + 1) % AR_BUFFERS; 705 } 706 707 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx) 708 { 709 return ar_next_buffer_index(ctx->last_buffer_index); 710 } 711 712 /* 713 * We search for the buffer that contains the last AR packet DMA data written 714 * by the controller. 715 */ 716 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx, 717 unsigned int *buffer_offset) 718 { 719 unsigned int i, next_i, last = ctx->last_buffer_index; 720 __le16 res_count, next_res_count; 721 722 i = ar_first_buffer_index(ctx); 723 res_count = READ_ONCE(ctx->descriptors[i].res_count); 724 725 /* A buffer that is not yet completely filled must be the last one. */ 726 while (i != last && res_count == 0) { 727 728 /* Peek at the next descriptor. */ 729 next_i = ar_next_buffer_index(i); 730 rmb(); /* read descriptors in order */ 731 next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count); 732 /* 733 * If the next descriptor is still empty, we must stop at this 734 * descriptor. 735 */ 736 if (next_res_count == cpu_to_le16(PAGE_SIZE)) { 737 /* 738 * The exception is when the DMA data for one packet is 739 * split over three buffers; in this case, the middle 740 * buffer's descriptor might be never updated by the 741 * controller and look still empty, and we have to peek 742 * at the third one. 743 */ 744 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) { 745 next_i = ar_next_buffer_index(next_i); 746 rmb(); 747 next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count); 748 if (next_res_count != cpu_to_le16(PAGE_SIZE)) 749 goto next_buffer_is_active; 750 } 751 752 break; 753 } 754 755 next_buffer_is_active: 756 i = next_i; 757 res_count = next_res_count; 758 } 759 760 rmb(); /* read res_count before the DMA data */ 761 762 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count); 763 if (*buffer_offset > PAGE_SIZE) { 764 *buffer_offset = 0; 765 ar_context_abort(ctx, "corrupted descriptor"); 766 } 767 768 return i; 769 } 770 771 static void ar_sync_buffers_for_cpu(struct ar_context *ctx, 772 unsigned int end_buffer_index, 773 unsigned int end_buffer_offset) 774 { 775 unsigned int i; 776 777 i = ar_first_buffer_index(ctx); 778 while (i != end_buffer_index) { 779 dma_sync_single_for_cpu(ctx->ohci->card.device, 780 ar_buffer_bus(ctx, i), 781 PAGE_SIZE, DMA_FROM_DEVICE); 782 i = ar_next_buffer_index(i); 783 } 784 if (end_buffer_offset > 0) 785 dma_sync_single_for_cpu(ctx->ohci->card.device, 786 ar_buffer_bus(ctx, i), 787 end_buffer_offset, DMA_FROM_DEVICE); 788 } 789 790 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) 791 #define cond_le32_to_cpu(v) \ 792 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v)) 793 #else 794 #define cond_le32_to_cpu(v) le32_to_cpu(v) 795 #endif 796 797 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) 798 { 799 struct fw_ohci *ohci = ctx->ohci; 800 struct fw_packet p; 801 u32 status, length, tcode; 802 int evt; 803 804 p.header[0] = cond_le32_to_cpu(buffer[0]); 805 p.header[1] = cond_le32_to_cpu(buffer[1]); 806 p.header[2] = cond_le32_to_cpu(buffer[2]); 807 808 tcode = (p.header[0] >> 4) & 0x0f; 809 switch (tcode) { 810 case TCODE_WRITE_QUADLET_REQUEST: 811 case TCODE_READ_QUADLET_RESPONSE: 812 p.header[3] = (__force __u32) buffer[3]; 813 p.header_length = 16; 814 p.payload_length = 0; 815 break; 816 817 case TCODE_READ_BLOCK_REQUEST : 818 p.header[3] = cond_le32_to_cpu(buffer[3]); 819 p.header_length = 16; 820 p.payload_length = 0; 821 break; 822 823 case TCODE_WRITE_BLOCK_REQUEST: 824 case TCODE_READ_BLOCK_RESPONSE: 825 case TCODE_LOCK_REQUEST: 826 case TCODE_LOCK_RESPONSE: 827 p.header[3] = cond_le32_to_cpu(buffer[3]); 828 p.header_length = 16; 829 p.payload_length = p.header[3] >> 16; 830 if (p.payload_length > MAX_ASYNC_PAYLOAD) { 831 ar_context_abort(ctx, "invalid packet length"); 832 return NULL; 833 } 834 break; 835 836 case TCODE_WRITE_RESPONSE: 837 case TCODE_READ_QUADLET_REQUEST: 838 case OHCI_TCODE_PHY_PACKET: 839 p.header_length = 12; 840 p.payload_length = 0; 841 break; 842 843 default: 844 ar_context_abort(ctx, "invalid tcode"); 845 return NULL; 846 } 847 848 p.payload = (void *) buffer + p.header_length; 849 850 /* FIXME: What to do about evt_* errors? */ 851 length = (p.header_length + p.payload_length + 3) / 4; 852 status = cond_le32_to_cpu(buffer[length]); 853 evt = (status >> 16) & 0x1f; 854 855 p.ack = evt - 16; 856 p.speed = (status >> 21) & 0x7; 857 p.timestamp = status & 0xffff; 858 p.generation = ohci->request_generation; 859 860 log_ar_at_event(ohci, 'R', p.speed, p.header, evt); 861 862 /* 863 * Several controllers, notably from NEC and VIA, forget to 864 * write ack_complete status at PHY packet reception. 865 */ 866 if (evt == OHCI1394_evt_no_status && 867 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4)) 868 p.ack = ACK_COMPLETE; 869 870 /* 871 * The OHCI bus reset handler synthesizes a PHY packet with 872 * the new generation number when a bus reset happens (see 873 * section 8.4.2.3). This helps us determine when a request 874 * was received and make sure we send the response in the same 875 * generation. We only need this for requests; for responses 876 * we use the unique tlabel for finding the matching 877 * request. 878 * 879 * Alas some chips sometimes emit bus reset packets with a 880 * wrong generation. We set the correct generation for these 881 * at a slightly incorrect time (in bus_reset_work). 882 */ 883 if (evt == OHCI1394_evt_bus_reset) { 884 if (!(ohci->quirks & QUIRK_RESET_PACKET)) 885 ohci->request_generation = (p.header[2] >> 16) & 0xff; 886 } else if (ctx == &ohci->ar_request_ctx) { 887 fw_core_handle_request(&ohci->card, &p); 888 } else { 889 fw_core_handle_response(&ohci->card, &p); 890 } 891 892 return buffer + length + 1; 893 } 894 895 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end) 896 { 897 void *next; 898 899 while (p < end) { 900 next = handle_ar_packet(ctx, p); 901 if (!next) 902 return p; 903 p = next; 904 } 905 906 return p; 907 } 908 909 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer) 910 { 911 unsigned int i; 912 913 i = ar_first_buffer_index(ctx); 914 while (i != end_buffer) { 915 dma_sync_single_for_device(ctx->ohci->card.device, 916 ar_buffer_bus(ctx, i), 917 PAGE_SIZE, DMA_FROM_DEVICE); 918 ar_context_link_page(ctx, i); 919 i = ar_next_buffer_index(i); 920 } 921 } 922 923 static void ar_context_tasklet(unsigned long data) 924 { 925 struct ar_context *ctx = (struct ar_context *)data; 926 unsigned int end_buffer_index, end_buffer_offset; 927 void *p, *end; 928 929 p = ctx->pointer; 930 if (!p) 931 return; 932 933 end_buffer_index = ar_search_last_active_buffer(ctx, 934 &end_buffer_offset); 935 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset); 936 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset; 937 938 if (end_buffer_index < ar_first_buffer_index(ctx)) { 939 /* 940 * The filled part of the overall buffer wraps around; handle 941 * all packets up to the buffer end here. If the last packet 942 * wraps around, its tail will be visible after the buffer end 943 * because the buffer start pages are mapped there again. 944 */ 945 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE; 946 p = handle_ar_packets(ctx, p, buffer_end); 947 if (p < buffer_end) 948 goto error; 949 /* adjust p to point back into the actual buffer */ 950 p -= AR_BUFFERS * PAGE_SIZE; 951 } 952 953 p = handle_ar_packets(ctx, p, end); 954 if (p != end) { 955 if (p > end) 956 ar_context_abort(ctx, "inconsistent descriptor"); 957 goto error; 958 } 959 960 ctx->pointer = p; 961 ar_recycle_buffers(ctx, end_buffer_index); 962 963 return; 964 965 error: 966 ctx->pointer = NULL; 967 } 968 969 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, 970 unsigned int descriptors_offset, u32 regs) 971 { 972 struct device *dev = ohci->card.device; 973 unsigned int i; 974 dma_addr_t dma_addr; 975 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES]; 976 struct descriptor *d; 977 978 ctx->regs = regs; 979 ctx->ohci = ohci; 980 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); 981 982 for (i = 0; i < AR_BUFFERS; i++) { 983 ctx->pages[i] = dma_alloc_pages(dev, PAGE_SIZE, &dma_addr, 984 DMA_FROM_DEVICE, GFP_KERNEL); 985 if (!ctx->pages[i]) 986 goto out_of_memory; 987 set_page_private(ctx->pages[i], dma_addr); 988 dma_sync_single_for_device(dev, dma_addr, PAGE_SIZE, 989 DMA_FROM_DEVICE); 990 } 991 992 for (i = 0; i < AR_BUFFERS; i++) 993 pages[i] = ctx->pages[i]; 994 for (i = 0; i < AR_WRAPAROUND_PAGES; i++) 995 pages[AR_BUFFERS + i] = ctx->pages[i]; 996 ctx->buffer = vmap(pages, ARRAY_SIZE(pages), VM_MAP, PAGE_KERNEL); 997 if (!ctx->buffer) 998 goto out_of_memory; 999 1000 ctx->descriptors = ohci->misc_buffer + descriptors_offset; 1001 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset; 1002 1003 for (i = 0; i < AR_BUFFERS; i++) { 1004 d = &ctx->descriptors[i]; 1005 d->req_count = cpu_to_le16(PAGE_SIZE); 1006 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 1007 DESCRIPTOR_STATUS | 1008 DESCRIPTOR_BRANCH_ALWAYS); 1009 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i)); 1010 d->branch_address = cpu_to_le32(ctx->descriptors_bus + 1011 ar_next_buffer_index(i) * sizeof(struct descriptor)); 1012 } 1013 1014 return 0; 1015 1016 out_of_memory: 1017 ar_context_release(ctx); 1018 1019 return -ENOMEM; 1020 } 1021 1022 static void ar_context_run(struct ar_context *ctx) 1023 { 1024 unsigned int i; 1025 1026 for (i = 0; i < AR_BUFFERS; i++) 1027 ar_context_link_page(ctx, i); 1028 1029 ctx->pointer = ctx->buffer; 1030 1031 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1); 1032 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); 1033 } 1034 1035 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z) 1036 { 1037 __le16 branch; 1038 1039 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS); 1040 1041 /* figure out which descriptor the branch address goes in */ 1042 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 1043 return d; 1044 else 1045 return d + z - 1; 1046 } 1047 1048 static void context_tasklet(unsigned long data) 1049 { 1050 struct context *ctx = (struct context *) data; 1051 struct descriptor *d, *last; 1052 u32 address; 1053 int z; 1054 struct descriptor_buffer *desc; 1055 1056 desc = list_entry(ctx->buffer_list.next, 1057 struct descriptor_buffer, list); 1058 last = ctx->last; 1059 while (last->branch_address != 0) { 1060 struct descriptor_buffer *old_desc = desc; 1061 address = le32_to_cpu(last->branch_address); 1062 z = address & 0xf; 1063 address &= ~0xf; 1064 ctx->current_bus = address; 1065 1066 /* If the branch address points to a buffer outside of the 1067 * current buffer, advance to the next buffer. */ 1068 if (address < desc->buffer_bus || 1069 address >= desc->buffer_bus + desc->used) 1070 desc = list_entry(desc->list.next, 1071 struct descriptor_buffer, list); 1072 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d); 1073 last = find_branch_descriptor(d, z); 1074 1075 if (!ctx->callback(ctx, d, last)) 1076 break; 1077 1078 if (old_desc != desc) { 1079 /* If we've advanced to the next buffer, move the 1080 * previous buffer to the free list. */ 1081 unsigned long flags; 1082 old_desc->used = 0; 1083 spin_lock_irqsave(&ctx->ohci->lock, flags); 1084 list_move_tail(&old_desc->list, &ctx->buffer_list); 1085 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1086 } 1087 ctx->last = last; 1088 } 1089 } 1090 1091 /* 1092 * Allocate a new buffer and add it to the list of free buffers for this 1093 * context. Must be called with ohci->lock held. 1094 */ 1095 static int context_add_buffer(struct context *ctx) 1096 { 1097 struct descriptor_buffer *desc; 1098 dma_addr_t bus_addr; 1099 int offset; 1100 1101 /* 1102 * 16MB of descriptors should be far more than enough for any DMA 1103 * program. This will catch run-away userspace or DoS attacks. 1104 */ 1105 if (ctx->total_allocation >= 16*1024*1024) 1106 return -ENOMEM; 1107 1108 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE, 1109 &bus_addr, GFP_ATOMIC); 1110 if (!desc) 1111 return -ENOMEM; 1112 1113 offset = (void *)&desc->buffer - (void *)desc; 1114 /* 1115 * Some controllers, like JMicron ones, always issue 0x20-byte DMA reads 1116 * for descriptors, even 0x10-byte ones. This can cause page faults when 1117 * an IOMMU is in use and the oversized read crosses a page boundary. 1118 * Work around this by always leaving at least 0x10 bytes of padding. 1119 */ 1120 desc->buffer_size = PAGE_SIZE - offset - 0x10; 1121 desc->buffer_bus = bus_addr + offset; 1122 desc->used = 0; 1123 1124 list_add_tail(&desc->list, &ctx->buffer_list); 1125 ctx->total_allocation += PAGE_SIZE; 1126 1127 return 0; 1128 } 1129 1130 static int context_init(struct context *ctx, struct fw_ohci *ohci, 1131 u32 regs, descriptor_callback_t callback) 1132 { 1133 ctx->ohci = ohci; 1134 ctx->regs = regs; 1135 ctx->total_allocation = 0; 1136 1137 INIT_LIST_HEAD(&ctx->buffer_list); 1138 if (context_add_buffer(ctx) < 0) 1139 return -ENOMEM; 1140 1141 ctx->buffer_tail = list_entry(ctx->buffer_list.next, 1142 struct descriptor_buffer, list); 1143 1144 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); 1145 ctx->callback = callback; 1146 1147 /* 1148 * We put a dummy descriptor in the buffer that has a NULL 1149 * branch address and looks like it's been sent. That way we 1150 * have a descriptor to append DMA programs to. 1151 */ 1152 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer)); 1153 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST); 1154 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011); 1155 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer); 1156 ctx->last = ctx->buffer_tail->buffer; 1157 ctx->prev = ctx->buffer_tail->buffer; 1158 ctx->prev_z = 1; 1159 1160 return 0; 1161 } 1162 1163 static void context_release(struct context *ctx) 1164 { 1165 struct fw_card *card = &ctx->ohci->card; 1166 struct descriptor_buffer *desc, *tmp; 1167 1168 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list) 1169 dma_free_coherent(card->device, PAGE_SIZE, desc, 1170 desc->buffer_bus - 1171 ((void *)&desc->buffer - (void *)desc)); 1172 } 1173 1174 /* Must be called with ohci->lock held */ 1175 static struct descriptor *context_get_descriptors(struct context *ctx, 1176 int z, dma_addr_t *d_bus) 1177 { 1178 struct descriptor *d = NULL; 1179 struct descriptor_buffer *desc = ctx->buffer_tail; 1180 1181 if (z * sizeof(*d) > desc->buffer_size) 1182 return NULL; 1183 1184 if (z * sizeof(*d) > desc->buffer_size - desc->used) { 1185 /* No room for the descriptor in this buffer, so advance to the 1186 * next one. */ 1187 1188 if (desc->list.next == &ctx->buffer_list) { 1189 /* If there is no free buffer next in the list, 1190 * allocate one. */ 1191 if (context_add_buffer(ctx) < 0) 1192 return NULL; 1193 } 1194 desc = list_entry(desc->list.next, 1195 struct descriptor_buffer, list); 1196 ctx->buffer_tail = desc; 1197 } 1198 1199 d = desc->buffer + desc->used / sizeof(*d); 1200 memset(d, 0, z * sizeof(*d)); 1201 *d_bus = desc->buffer_bus + desc->used; 1202 1203 return d; 1204 } 1205 1206 static void context_run(struct context *ctx, u32 extra) 1207 { 1208 struct fw_ohci *ohci = ctx->ohci; 1209 1210 reg_write(ohci, COMMAND_PTR(ctx->regs), 1211 le32_to_cpu(ctx->last->branch_address)); 1212 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); 1213 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); 1214 ctx->running = true; 1215 flush_writes(ohci); 1216 } 1217 1218 static void context_append(struct context *ctx, 1219 struct descriptor *d, int z, int extra) 1220 { 1221 dma_addr_t d_bus; 1222 struct descriptor_buffer *desc = ctx->buffer_tail; 1223 struct descriptor *d_branch; 1224 1225 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d); 1226 1227 desc->used += (z + extra) * sizeof(*d); 1228 1229 wmb(); /* finish init of new descriptors before branch_address update */ 1230 1231 d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z); 1232 d_branch->branch_address = cpu_to_le32(d_bus | z); 1233 1234 /* 1235 * VT6306 incorrectly checks only the single descriptor at the 1236 * CommandPtr when the wake bit is written, so if it's a 1237 * multi-descriptor block starting with an INPUT_MORE, put a copy of 1238 * the branch address in the first descriptor. 1239 * 1240 * Not doing this for transmit contexts since not sure how it interacts 1241 * with skip addresses. 1242 */ 1243 if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) && 1244 d_branch != ctx->prev && 1245 (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) == 1246 cpu_to_le16(DESCRIPTOR_INPUT_MORE)) { 1247 ctx->prev->branch_address = cpu_to_le32(d_bus | z); 1248 } 1249 1250 ctx->prev = d; 1251 ctx->prev_z = z; 1252 } 1253 1254 static void context_stop(struct context *ctx) 1255 { 1256 struct fw_ohci *ohci = ctx->ohci; 1257 u32 reg; 1258 int i; 1259 1260 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 1261 ctx->running = false; 1262 1263 for (i = 0; i < 1000; i++) { 1264 reg = reg_read(ohci, CONTROL_SET(ctx->regs)); 1265 if ((reg & CONTEXT_ACTIVE) == 0) 1266 return; 1267 1268 if (i) 1269 udelay(10); 1270 } 1271 ohci_err(ohci, "DMA context still active (0x%08x)\n", reg); 1272 } 1273 1274 struct driver_data { 1275 u8 inline_data[8]; 1276 struct fw_packet *packet; 1277 }; 1278 1279 /* 1280 * This function apppends a packet to the DMA queue for transmission. 1281 * Must always be called with the ochi->lock held to ensure proper 1282 * generation handling and locking around packet queue manipulation. 1283 */ 1284 static int at_context_queue_packet(struct context *ctx, 1285 struct fw_packet *packet) 1286 { 1287 struct fw_ohci *ohci = ctx->ohci; 1288 dma_addr_t d_bus, payload_bus; 1289 struct driver_data *driver_data; 1290 struct descriptor *d, *last; 1291 __le32 *header; 1292 int z, tcode; 1293 1294 d = context_get_descriptors(ctx, 4, &d_bus); 1295 if (d == NULL) { 1296 packet->ack = RCODE_SEND_ERROR; 1297 return -1; 1298 } 1299 1300 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 1301 d[0].res_count = cpu_to_le16(packet->timestamp); 1302 1303 /* 1304 * The DMA format for asynchronous link packets is different 1305 * from the IEEE1394 layout, so shift the fields around 1306 * accordingly. 1307 */ 1308 1309 tcode = (packet->header[0] >> 4) & 0x0f; 1310 header = (__le32 *) &d[1]; 1311 switch (tcode) { 1312 case TCODE_WRITE_QUADLET_REQUEST: 1313 case TCODE_WRITE_BLOCK_REQUEST: 1314 case TCODE_WRITE_RESPONSE: 1315 case TCODE_READ_QUADLET_REQUEST: 1316 case TCODE_READ_BLOCK_REQUEST: 1317 case TCODE_READ_QUADLET_RESPONSE: 1318 case TCODE_READ_BLOCK_RESPONSE: 1319 case TCODE_LOCK_REQUEST: 1320 case TCODE_LOCK_RESPONSE: 1321 header[0] = cpu_to_le32((packet->header[0] & 0xffff) | 1322 (packet->speed << 16)); 1323 header[1] = cpu_to_le32((packet->header[1] & 0xffff) | 1324 (packet->header[0] & 0xffff0000)); 1325 header[2] = cpu_to_le32(packet->header[2]); 1326 1327 if (TCODE_IS_BLOCK_PACKET(tcode)) 1328 header[3] = cpu_to_le32(packet->header[3]); 1329 else 1330 header[3] = (__force __le32) packet->header[3]; 1331 1332 d[0].req_count = cpu_to_le16(packet->header_length); 1333 break; 1334 1335 case TCODE_LINK_INTERNAL: 1336 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) | 1337 (packet->speed << 16)); 1338 header[1] = cpu_to_le32(packet->header[1]); 1339 header[2] = cpu_to_le32(packet->header[2]); 1340 d[0].req_count = cpu_to_le16(12); 1341 1342 if (is_ping_packet(&packet->header[1])) 1343 d[0].control |= cpu_to_le16(DESCRIPTOR_PING); 1344 break; 1345 1346 case TCODE_STREAM_DATA: 1347 header[0] = cpu_to_le32((packet->header[0] & 0xffff) | 1348 (packet->speed << 16)); 1349 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000); 1350 d[0].req_count = cpu_to_le16(8); 1351 break; 1352 1353 default: 1354 /* BUG(); */ 1355 packet->ack = RCODE_SEND_ERROR; 1356 return -1; 1357 } 1358 1359 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor)); 1360 driver_data = (struct driver_data *) &d[3]; 1361 driver_data->packet = packet; 1362 packet->driver_data = driver_data; 1363 1364 if (packet->payload_length > 0) { 1365 if (packet->payload_length > sizeof(driver_data->inline_data)) { 1366 payload_bus = dma_map_single(ohci->card.device, 1367 packet->payload, 1368 packet->payload_length, 1369 DMA_TO_DEVICE); 1370 if (dma_mapping_error(ohci->card.device, payload_bus)) { 1371 packet->ack = RCODE_SEND_ERROR; 1372 return -1; 1373 } 1374 packet->payload_bus = payload_bus; 1375 packet->payload_mapped = true; 1376 } else { 1377 memcpy(driver_data->inline_data, packet->payload, 1378 packet->payload_length); 1379 payload_bus = d_bus + 3 * sizeof(*d); 1380 } 1381 1382 d[2].req_count = cpu_to_le16(packet->payload_length); 1383 d[2].data_address = cpu_to_le32(payload_bus); 1384 last = &d[2]; 1385 z = 3; 1386 } else { 1387 last = &d[0]; 1388 z = 2; 1389 } 1390 1391 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 1392 DESCRIPTOR_IRQ_ALWAYS | 1393 DESCRIPTOR_BRANCH_ALWAYS); 1394 1395 /* FIXME: Document how the locking works. */ 1396 if (ohci->generation != packet->generation) { 1397 if (packet->payload_mapped) 1398 dma_unmap_single(ohci->card.device, payload_bus, 1399 packet->payload_length, DMA_TO_DEVICE); 1400 packet->ack = RCODE_GENERATION; 1401 return -1; 1402 } 1403 1404 context_append(ctx, d, z, 4 - z); 1405 1406 if (ctx->running) 1407 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 1408 else 1409 context_run(ctx, 0); 1410 1411 return 0; 1412 } 1413 1414 static void at_context_flush(struct context *ctx) 1415 { 1416 tasklet_disable(&ctx->tasklet); 1417 1418 ctx->flushing = true; 1419 context_tasklet((unsigned long)ctx); 1420 ctx->flushing = false; 1421 1422 tasklet_enable(&ctx->tasklet); 1423 } 1424 1425 static int handle_at_packet(struct context *context, 1426 struct descriptor *d, 1427 struct descriptor *last) 1428 { 1429 struct driver_data *driver_data; 1430 struct fw_packet *packet; 1431 struct fw_ohci *ohci = context->ohci; 1432 int evt; 1433 1434 if (last->transfer_status == 0 && !context->flushing) 1435 /* This descriptor isn't done yet, stop iteration. */ 1436 return 0; 1437 1438 driver_data = (struct driver_data *) &d[3]; 1439 packet = driver_data->packet; 1440 if (packet == NULL) 1441 /* This packet was cancelled, just continue. */ 1442 return 1; 1443 1444 if (packet->payload_mapped) 1445 dma_unmap_single(ohci->card.device, packet->payload_bus, 1446 packet->payload_length, DMA_TO_DEVICE); 1447 1448 evt = le16_to_cpu(last->transfer_status) & 0x1f; 1449 packet->timestamp = le16_to_cpu(last->res_count); 1450 1451 log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt); 1452 1453 switch (evt) { 1454 case OHCI1394_evt_timeout: 1455 /* Async response transmit timed out. */ 1456 packet->ack = RCODE_CANCELLED; 1457 break; 1458 1459 case OHCI1394_evt_flushed: 1460 /* 1461 * The packet was flushed should give same error as 1462 * when we try to use a stale generation count. 1463 */ 1464 packet->ack = RCODE_GENERATION; 1465 break; 1466 1467 case OHCI1394_evt_missing_ack: 1468 if (context->flushing) 1469 packet->ack = RCODE_GENERATION; 1470 else { 1471 /* 1472 * Using a valid (current) generation count, but the 1473 * node is not on the bus or not sending acks. 1474 */ 1475 packet->ack = RCODE_NO_ACK; 1476 } 1477 break; 1478 1479 case ACK_COMPLETE + 0x10: 1480 case ACK_PENDING + 0x10: 1481 case ACK_BUSY_X + 0x10: 1482 case ACK_BUSY_A + 0x10: 1483 case ACK_BUSY_B + 0x10: 1484 case ACK_DATA_ERROR + 0x10: 1485 case ACK_TYPE_ERROR + 0x10: 1486 packet->ack = evt - 0x10; 1487 break; 1488 1489 case OHCI1394_evt_no_status: 1490 if (context->flushing) { 1491 packet->ack = RCODE_GENERATION; 1492 break; 1493 } 1494 fallthrough; 1495 1496 default: 1497 packet->ack = RCODE_SEND_ERROR; 1498 break; 1499 } 1500 1501 packet->callback(packet, &ohci->card, packet->ack); 1502 1503 return 1; 1504 } 1505 1506 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff) 1507 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f) 1508 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff) 1509 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff) 1510 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff) 1511 1512 static void handle_local_rom(struct fw_ohci *ohci, 1513 struct fw_packet *packet, u32 csr) 1514 { 1515 struct fw_packet response; 1516 int tcode, length, i; 1517 1518 tcode = HEADER_GET_TCODE(packet->header[0]); 1519 if (TCODE_IS_BLOCK_PACKET(tcode)) 1520 length = HEADER_GET_DATA_LENGTH(packet->header[3]); 1521 else 1522 length = 4; 1523 1524 i = csr - CSR_CONFIG_ROM; 1525 if (i + length > CONFIG_ROM_SIZE) { 1526 fw_fill_response(&response, packet->header, 1527 RCODE_ADDRESS_ERROR, NULL, 0); 1528 } else if (!TCODE_IS_READ_REQUEST(tcode)) { 1529 fw_fill_response(&response, packet->header, 1530 RCODE_TYPE_ERROR, NULL, 0); 1531 } else { 1532 fw_fill_response(&response, packet->header, RCODE_COMPLETE, 1533 (void *) ohci->config_rom + i, length); 1534 } 1535 1536 fw_core_handle_response(&ohci->card, &response); 1537 } 1538 1539 static void handle_local_lock(struct fw_ohci *ohci, 1540 struct fw_packet *packet, u32 csr) 1541 { 1542 struct fw_packet response; 1543 int tcode, length, ext_tcode, sel, try; 1544 __be32 *payload, lock_old; 1545 u32 lock_arg, lock_data; 1546 1547 tcode = HEADER_GET_TCODE(packet->header[0]); 1548 length = HEADER_GET_DATA_LENGTH(packet->header[3]); 1549 payload = packet->payload; 1550 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]); 1551 1552 if (tcode == TCODE_LOCK_REQUEST && 1553 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { 1554 lock_arg = be32_to_cpu(payload[0]); 1555 lock_data = be32_to_cpu(payload[1]); 1556 } else if (tcode == TCODE_READ_QUADLET_REQUEST) { 1557 lock_arg = 0; 1558 lock_data = 0; 1559 } else { 1560 fw_fill_response(&response, packet->header, 1561 RCODE_TYPE_ERROR, NULL, 0); 1562 goto out; 1563 } 1564 1565 sel = (csr - CSR_BUS_MANAGER_ID) / 4; 1566 reg_write(ohci, OHCI1394_CSRData, lock_data); 1567 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); 1568 reg_write(ohci, OHCI1394_CSRControl, sel); 1569 1570 for (try = 0; try < 20; try++) 1571 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) { 1572 lock_old = cpu_to_be32(reg_read(ohci, 1573 OHCI1394_CSRData)); 1574 fw_fill_response(&response, packet->header, 1575 RCODE_COMPLETE, 1576 &lock_old, sizeof(lock_old)); 1577 goto out; 1578 } 1579 1580 ohci_err(ohci, "swap not done (CSR lock timeout)\n"); 1581 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0); 1582 1583 out: 1584 fw_core_handle_response(&ohci->card, &response); 1585 } 1586 1587 static void handle_local_request(struct context *ctx, struct fw_packet *packet) 1588 { 1589 u64 offset, csr; 1590 1591 if (ctx == &ctx->ohci->at_request_ctx) { 1592 packet->ack = ACK_PENDING; 1593 packet->callback(packet, &ctx->ohci->card, packet->ack); 1594 } 1595 1596 offset = 1597 ((unsigned long long) 1598 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) | 1599 packet->header[2]; 1600 csr = offset - CSR_REGISTER_BASE; 1601 1602 /* Handle config rom reads. */ 1603 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) 1604 handle_local_rom(ctx->ohci, packet, csr); 1605 else switch (csr) { 1606 case CSR_BUS_MANAGER_ID: 1607 case CSR_BANDWIDTH_AVAILABLE: 1608 case CSR_CHANNELS_AVAILABLE_HI: 1609 case CSR_CHANNELS_AVAILABLE_LO: 1610 handle_local_lock(ctx->ohci, packet, csr); 1611 break; 1612 default: 1613 if (ctx == &ctx->ohci->at_request_ctx) 1614 fw_core_handle_request(&ctx->ohci->card, packet); 1615 else 1616 fw_core_handle_response(&ctx->ohci->card, packet); 1617 break; 1618 } 1619 1620 if (ctx == &ctx->ohci->at_response_ctx) { 1621 packet->ack = ACK_COMPLETE; 1622 packet->callback(packet, &ctx->ohci->card, packet->ack); 1623 } 1624 } 1625 1626 static void at_context_transmit(struct context *ctx, struct fw_packet *packet) 1627 { 1628 unsigned long flags; 1629 int ret; 1630 1631 spin_lock_irqsave(&ctx->ohci->lock, flags); 1632 1633 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id && 1634 ctx->ohci->generation == packet->generation) { 1635 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1636 handle_local_request(ctx, packet); 1637 return; 1638 } 1639 1640 ret = at_context_queue_packet(ctx, packet); 1641 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1642 1643 if (ret < 0) 1644 packet->callback(packet, &ctx->ohci->card, packet->ack); 1645 1646 } 1647 1648 static void detect_dead_context(struct fw_ohci *ohci, 1649 const char *name, unsigned int regs) 1650 { 1651 u32 ctl; 1652 1653 ctl = reg_read(ohci, CONTROL_SET(regs)); 1654 if (ctl & CONTEXT_DEAD) 1655 ohci_err(ohci, "DMA context %s has stopped, error code: %s\n", 1656 name, evts[ctl & 0x1f]); 1657 } 1658 1659 static void handle_dead_contexts(struct fw_ohci *ohci) 1660 { 1661 unsigned int i; 1662 char name[8]; 1663 1664 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase); 1665 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase); 1666 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase); 1667 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase); 1668 for (i = 0; i < 32; ++i) { 1669 if (!(ohci->it_context_support & (1 << i))) 1670 continue; 1671 sprintf(name, "IT%u", i); 1672 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i)); 1673 } 1674 for (i = 0; i < 32; ++i) { 1675 if (!(ohci->ir_context_support & (1 << i))) 1676 continue; 1677 sprintf(name, "IR%u", i); 1678 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i)); 1679 } 1680 /* TODO: maybe try to flush and restart the dead contexts */ 1681 } 1682 1683 static u32 cycle_timer_ticks(u32 cycle_timer) 1684 { 1685 u32 ticks; 1686 1687 ticks = cycle_timer & 0xfff; 1688 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff); 1689 ticks += (3072 * 8000) * (cycle_timer >> 25); 1690 1691 return ticks; 1692 } 1693 1694 /* 1695 * Some controllers exhibit one or more of the following bugs when updating the 1696 * iso cycle timer register: 1697 * - When the lowest six bits are wrapping around to zero, a read that happens 1698 * at the same time will return garbage in the lowest ten bits. 1699 * - When the cycleOffset field wraps around to zero, the cycleCount field is 1700 * not incremented for about 60 ns. 1701 * - Occasionally, the entire register reads zero. 1702 * 1703 * To catch these, we read the register three times and ensure that the 1704 * difference between each two consecutive reads is approximately the same, i.e. 1705 * less than twice the other. Furthermore, any negative difference indicates an 1706 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to 1707 * execute, so we have enough precision to compute the ratio of the differences.) 1708 */ 1709 static u32 get_cycle_time(struct fw_ohci *ohci) 1710 { 1711 u32 c0, c1, c2; 1712 u32 t0, t1, t2; 1713 s32 diff01, diff12; 1714 int i; 1715 1716 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1717 1718 if (ohci->quirks & QUIRK_CYCLE_TIMER) { 1719 i = 0; 1720 c1 = c2; 1721 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1722 do { 1723 c0 = c1; 1724 c1 = c2; 1725 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1726 t0 = cycle_timer_ticks(c0); 1727 t1 = cycle_timer_ticks(c1); 1728 t2 = cycle_timer_ticks(c2); 1729 diff01 = t1 - t0; 1730 diff12 = t2 - t1; 1731 } while ((diff01 <= 0 || diff12 <= 0 || 1732 diff01 / diff12 >= 2 || diff12 / diff01 >= 2) 1733 && i++ < 20); 1734 } 1735 1736 return c2; 1737 } 1738 1739 /* 1740 * This function has to be called at least every 64 seconds. The bus_time 1741 * field stores not only the upper 25 bits of the BUS_TIME register but also 1742 * the most significant bit of the cycle timer in bit 6 so that we can detect 1743 * changes in this bit. 1744 */ 1745 static u32 update_bus_time(struct fw_ohci *ohci) 1746 { 1747 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25; 1748 1749 if (unlikely(!ohci->bus_time_running)) { 1750 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds); 1751 ohci->bus_time = (lower_32_bits(ktime_get_seconds()) & ~0x7f) | 1752 (cycle_time_seconds & 0x40); 1753 ohci->bus_time_running = true; 1754 } 1755 1756 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40)) 1757 ohci->bus_time += 0x40; 1758 1759 return ohci->bus_time | cycle_time_seconds; 1760 } 1761 1762 static int get_status_for_port(struct fw_ohci *ohci, int port_index) 1763 { 1764 int reg; 1765 1766 mutex_lock(&ohci->phy_reg_mutex); 1767 reg = write_phy_reg(ohci, 7, port_index); 1768 if (reg >= 0) 1769 reg = read_phy_reg(ohci, 8); 1770 mutex_unlock(&ohci->phy_reg_mutex); 1771 if (reg < 0) 1772 return reg; 1773 1774 switch (reg & 0x0f) { 1775 case 0x06: 1776 return 2; /* is child node (connected to parent node) */ 1777 case 0x0e: 1778 return 3; /* is parent node (connected to child node) */ 1779 } 1780 return 1; /* not connected */ 1781 } 1782 1783 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id, 1784 int self_id_count) 1785 { 1786 int i; 1787 u32 entry; 1788 1789 for (i = 0; i < self_id_count; i++) { 1790 entry = ohci->self_id_buffer[i]; 1791 if ((self_id & 0xff000000) == (entry & 0xff000000)) 1792 return -1; 1793 if ((self_id & 0xff000000) < (entry & 0xff000000)) 1794 return i; 1795 } 1796 return i; 1797 } 1798 1799 static int initiated_reset(struct fw_ohci *ohci) 1800 { 1801 int reg; 1802 int ret = 0; 1803 1804 mutex_lock(&ohci->phy_reg_mutex); 1805 reg = write_phy_reg(ohci, 7, 0xe0); /* Select page 7 */ 1806 if (reg >= 0) { 1807 reg = read_phy_reg(ohci, 8); 1808 reg |= 0x40; 1809 reg = write_phy_reg(ohci, 8, reg); /* set PMODE bit */ 1810 if (reg >= 0) { 1811 reg = read_phy_reg(ohci, 12); /* read register 12 */ 1812 if (reg >= 0) { 1813 if ((reg & 0x08) == 0x08) { 1814 /* bit 3 indicates "initiated reset" */ 1815 ret = 0x2; 1816 } 1817 } 1818 } 1819 } 1820 mutex_unlock(&ohci->phy_reg_mutex); 1821 return ret; 1822 } 1823 1824 /* 1825 * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally 1826 * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059. 1827 * Construct the selfID from phy register contents. 1828 */ 1829 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count) 1830 { 1831 int reg, i, pos, status; 1832 /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */ 1833 u32 self_id = 0x8040c800; 1834 1835 reg = reg_read(ohci, OHCI1394_NodeID); 1836 if (!(reg & OHCI1394_NodeID_idValid)) { 1837 ohci_notice(ohci, 1838 "node ID not valid, new bus reset in progress\n"); 1839 return -EBUSY; 1840 } 1841 self_id |= ((reg & 0x3f) << 24); /* phy ID */ 1842 1843 reg = ohci_read_phy_reg(&ohci->card, 4); 1844 if (reg < 0) 1845 return reg; 1846 self_id |= ((reg & 0x07) << 8); /* power class */ 1847 1848 reg = ohci_read_phy_reg(&ohci->card, 1); 1849 if (reg < 0) 1850 return reg; 1851 self_id |= ((reg & 0x3f) << 16); /* gap count */ 1852 1853 for (i = 0; i < 3; i++) { 1854 status = get_status_for_port(ohci, i); 1855 if (status < 0) 1856 return status; 1857 self_id |= ((status & 0x3) << (6 - (i * 2))); 1858 } 1859 1860 self_id |= initiated_reset(ohci); 1861 1862 pos = get_self_id_pos(ohci, self_id, self_id_count); 1863 if (pos >= 0) { 1864 memmove(&(ohci->self_id_buffer[pos+1]), 1865 &(ohci->self_id_buffer[pos]), 1866 (self_id_count - pos) * sizeof(*ohci->self_id_buffer)); 1867 ohci->self_id_buffer[pos] = self_id; 1868 self_id_count++; 1869 } 1870 return self_id_count; 1871 } 1872 1873 static void bus_reset_work(struct work_struct *work) 1874 { 1875 struct fw_ohci *ohci = 1876 container_of(work, struct fw_ohci, bus_reset_work); 1877 int self_id_count, generation, new_generation, i, j; 1878 u32 reg; 1879 void *free_rom = NULL; 1880 dma_addr_t free_rom_bus = 0; 1881 bool is_new_root; 1882 1883 reg = reg_read(ohci, OHCI1394_NodeID); 1884 if (!(reg & OHCI1394_NodeID_idValid)) { 1885 ohci_notice(ohci, 1886 "node ID not valid, new bus reset in progress\n"); 1887 return; 1888 } 1889 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { 1890 ohci_notice(ohci, "malconfigured bus\n"); 1891 return; 1892 } 1893 ohci->node_id = reg & (OHCI1394_NodeID_busNumber | 1894 OHCI1394_NodeID_nodeNumber); 1895 1896 is_new_root = (reg & OHCI1394_NodeID_root) != 0; 1897 if (!(ohci->is_root && is_new_root)) 1898 reg_write(ohci, OHCI1394_LinkControlSet, 1899 OHCI1394_LinkControl_cycleMaster); 1900 ohci->is_root = is_new_root; 1901 1902 reg = reg_read(ohci, OHCI1394_SelfIDCount); 1903 if (reg & OHCI1394_SelfIDCount_selfIDError) { 1904 ohci_notice(ohci, "self ID receive error\n"); 1905 return; 1906 } 1907 /* 1908 * The count in the SelfIDCount register is the number of 1909 * bytes in the self ID receive buffer. Since we also receive 1910 * the inverted quadlets and a header quadlet, we shift one 1911 * bit extra to get the actual number of self IDs. 1912 */ 1913 self_id_count = (reg >> 3) & 0xff; 1914 1915 if (self_id_count > 252) { 1916 ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg); 1917 return; 1918 } 1919 1920 generation = (cond_le32_to_cpu(ohci->self_id[0]) >> 16) & 0xff; 1921 rmb(); 1922 1923 for (i = 1, j = 0; j < self_id_count; i += 2, j++) { 1924 u32 id = cond_le32_to_cpu(ohci->self_id[i]); 1925 u32 id2 = cond_le32_to_cpu(ohci->self_id[i + 1]); 1926 1927 if (id != ~id2) { 1928 /* 1929 * If the invalid data looks like a cycle start packet, 1930 * it's likely to be the result of the cycle master 1931 * having a wrong gap count. In this case, the self IDs 1932 * so far are valid and should be processed so that the 1933 * bus manager can then correct the gap count. 1934 */ 1935 if (id == 0xffff008f) { 1936 ohci_notice(ohci, "ignoring spurious self IDs\n"); 1937 self_id_count = j; 1938 break; 1939 } 1940 1941 ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n", 1942 j, self_id_count, id, id2); 1943 return; 1944 } 1945 ohci->self_id_buffer[j] = id; 1946 } 1947 1948 if (ohci->quirks & QUIRK_TI_SLLZ059) { 1949 self_id_count = find_and_insert_self_id(ohci, self_id_count); 1950 if (self_id_count < 0) { 1951 ohci_notice(ohci, 1952 "could not construct local self ID\n"); 1953 return; 1954 } 1955 } 1956 1957 if (self_id_count == 0) { 1958 ohci_notice(ohci, "no self IDs\n"); 1959 return; 1960 } 1961 rmb(); 1962 1963 /* 1964 * Check the consistency of the self IDs we just read. The 1965 * problem we face is that a new bus reset can start while we 1966 * read out the self IDs from the DMA buffer. If this happens, 1967 * the DMA buffer will be overwritten with new self IDs and we 1968 * will read out inconsistent data. The OHCI specification 1969 * (section 11.2) recommends a technique similar to 1970 * linux/seqlock.h, where we remember the generation of the 1971 * self IDs in the buffer before reading them out and compare 1972 * it to the current generation after reading them out. If 1973 * the two generations match we know we have a consistent set 1974 * of self IDs. 1975 */ 1976 1977 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; 1978 if (new_generation != generation) { 1979 ohci_notice(ohci, "new bus reset, discarding self ids\n"); 1980 return; 1981 } 1982 1983 /* FIXME: Document how the locking works. */ 1984 spin_lock_irq(&ohci->lock); 1985 1986 ohci->generation = -1; /* prevent AT packet queueing */ 1987 context_stop(&ohci->at_request_ctx); 1988 context_stop(&ohci->at_response_ctx); 1989 1990 spin_unlock_irq(&ohci->lock); 1991 1992 /* 1993 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent 1994 * packets in the AT queues and software needs to drain them. 1995 * Some OHCI 1.1 controllers (JMicron) apparently require this too. 1996 */ 1997 at_context_flush(&ohci->at_request_ctx); 1998 at_context_flush(&ohci->at_response_ctx); 1999 2000 spin_lock_irq(&ohci->lock); 2001 2002 ohci->generation = generation; 2003 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); 2004 2005 if (ohci->quirks & QUIRK_RESET_PACKET) 2006 ohci->request_generation = generation; 2007 2008 /* 2009 * This next bit is unrelated to the AT context stuff but we 2010 * have to do it under the spinlock also. If a new config rom 2011 * was set up before this reset, the old one is now no longer 2012 * in use and we can free it. Update the config rom pointers 2013 * to point to the current config rom and clear the 2014 * next_config_rom pointer so a new update can take place. 2015 */ 2016 2017 if (ohci->next_config_rom != NULL) { 2018 if (ohci->next_config_rom != ohci->config_rom) { 2019 free_rom = ohci->config_rom; 2020 free_rom_bus = ohci->config_rom_bus; 2021 } 2022 ohci->config_rom = ohci->next_config_rom; 2023 ohci->config_rom_bus = ohci->next_config_rom_bus; 2024 ohci->next_config_rom = NULL; 2025 2026 /* 2027 * Restore config_rom image and manually update 2028 * config_rom registers. Writing the header quadlet 2029 * will indicate that the config rom is ready, so we 2030 * do that last. 2031 */ 2032 reg_write(ohci, OHCI1394_BusOptions, 2033 be32_to_cpu(ohci->config_rom[2])); 2034 ohci->config_rom[0] = ohci->next_header; 2035 reg_write(ohci, OHCI1394_ConfigROMhdr, 2036 be32_to_cpu(ohci->next_header)); 2037 } 2038 2039 if (param_remote_dma) { 2040 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0); 2041 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0); 2042 } 2043 2044 spin_unlock_irq(&ohci->lock); 2045 2046 if (free_rom) 2047 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2048 free_rom, free_rom_bus); 2049 2050 log_selfids(ohci, generation, self_id_count); 2051 2052 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, 2053 self_id_count, ohci->self_id_buffer, 2054 ohci->csr_state_setclear_abdicate); 2055 ohci->csr_state_setclear_abdicate = false; 2056 } 2057 2058 static irqreturn_t irq_handler(int irq, void *data) 2059 { 2060 struct fw_ohci *ohci = data; 2061 u32 event, iso_event; 2062 int i; 2063 2064 event = reg_read(ohci, OHCI1394_IntEventClear); 2065 2066 if (!event || !~event) 2067 return IRQ_NONE; 2068 2069 /* 2070 * busReset and postedWriteErr must not be cleared yet 2071 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1) 2072 */ 2073 reg_write(ohci, OHCI1394_IntEventClear, 2074 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr)); 2075 log_irqs(ohci, event); 2076 2077 if (event & OHCI1394_selfIDComplete) 2078 queue_work(selfid_workqueue, &ohci->bus_reset_work); 2079 2080 if (event & OHCI1394_RQPkt) 2081 tasklet_schedule(&ohci->ar_request_ctx.tasklet); 2082 2083 if (event & OHCI1394_RSPkt) 2084 tasklet_schedule(&ohci->ar_response_ctx.tasklet); 2085 2086 if (event & OHCI1394_reqTxComplete) 2087 tasklet_schedule(&ohci->at_request_ctx.tasklet); 2088 2089 if (event & OHCI1394_respTxComplete) 2090 tasklet_schedule(&ohci->at_response_ctx.tasklet); 2091 2092 if (event & OHCI1394_isochRx) { 2093 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); 2094 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); 2095 2096 while (iso_event) { 2097 i = ffs(iso_event) - 1; 2098 tasklet_schedule( 2099 &ohci->ir_context_list[i].context.tasklet); 2100 iso_event &= ~(1 << i); 2101 } 2102 } 2103 2104 if (event & OHCI1394_isochTx) { 2105 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); 2106 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); 2107 2108 while (iso_event) { 2109 i = ffs(iso_event) - 1; 2110 tasklet_schedule( 2111 &ohci->it_context_list[i].context.tasklet); 2112 iso_event &= ~(1 << i); 2113 } 2114 } 2115 2116 if (unlikely(event & OHCI1394_regAccessFail)) 2117 ohci_err(ohci, "register access failure\n"); 2118 2119 if (unlikely(event & OHCI1394_postedWriteErr)) { 2120 reg_read(ohci, OHCI1394_PostedWriteAddressHi); 2121 reg_read(ohci, OHCI1394_PostedWriteAddressLo); 2122 reg_write(ohci, OHCI1394_IntEventClear, 2123 OHCI1394_postedWriteErr); 2124 if (printk_ratelimit()) 2125 ohci_err(ohci, "PCI posted write error\n"); 2126 } 2127 2128 if (unlikely(event & OHCI1394_cycleTooLong)) { 2129 if (printk_ratelimit()) 2130 ohci_notice(ohci, "isochronous cycle too long\n"); 2131 reg_write(ohci, OHCI1394_LinkControlSet, 2132 OHCI1394_LinkControl_cycleMaster); 2133 } 2134 2135 if (unlikely(event & OHCI1394_cycleInconsistent)) { 2136 /* 2137 * We need to clear this event bit in order to make 2138 * cycleMatch isochronous I/O work. In theory we should 2139 * stop active cycleMatch iso contexts now and restart 2140 * them at least two cycles later. (FIXME?) 2141 */ 2142 if (printk_ratelimit()) 2143 ohci_notice(ohci, "isochronous cycle inconsistent\n"); 2144 } 2145 2146 if (unlikely(event & OHCI1394_unrecoverableError)) 2147 handle_dead_contexts(ohci); 2148 2149 if (event & OHCI1394_cycle64Seconds) { 2150 spin_lock(&ohci->lock); 2151 update_bus_time(ohci); 2152 spin_unlock(&ohci->lock); 2153 } else 2154 flush_writes(ohci); 2155 2156 return IRQ_HANDLED; 2157 } 2158 2159 static int software_reset(struct fw_ohci *ohci) 2160 { 2161 u32 val; 2162 int i; 2163 2164 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); 2165 for (i = 0; i < 500; i++) { 2166 val = reg_read(ohci, OHCI1394_HCControlSet); 2167 if (!~val) 2168 return -ENODEV; /* Card was ejected. */ 2169 2170 if (!(val & OHCI1394_HCControl_softReset)) 2171 return 0; 2172 2173 msleep(1); 2174 } 2175 2176 return -EBUSY; 2177 } 2178 2179 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length) 2180 { 2181 size_t size = length * 4; 2182 2183 memcpy(dest, src, size); 2184 if (size < CONFIG_ROM_SIZE) 2185 memset(&dest[length], 0, CONFIG_ROM_SIZE - size); 2186 } 2187 2188 static int configure_1394a_enhancements(struct fw_ohci *ohci) 2189 { 2190 bool enable_1394a; 2191 int ret, clear, set, offset; 2192 2193 /* Check if the driver should configure link and PHY. */ 2194 if (!(reg_read(ohci, OHCI1394_HCControlSet) & 2195 OHCI1394_HCControl_programPhyEnable)) 2196 return 0; 2197 2198 /* Paranoia: check whether the PHY supports 1394a, too. */ 2199 enable_1394a = false; 2200 ret = read_phy_reg(ohci, 2); 2201 if (ret < 0) 2202 return ret; 2203 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) { 2204 ret = read_paged_phy_reg(ohci, 1, 8); 2205 if (ret < 0) 2206 return ret; 2207 if (ret >= 1) 2208 enable_1394a = true; 2209 } 2210 2211 if (ohci->quirks & QUIRK_NO_1394A) 2212 enable_1394a = false; 2213 2214 /* Configure PHY and link consistently. */ 2215 if (enable_1394a) { 2216 clear = 0; 2217 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2218 } else { 2219 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2220 set = 0; 2221 } 2222 ret = update_phy_reg(ohci, 5, clear, set); 2223 if (ret < 0) 2224 return ret; 2225 2226 if (enable_1394a) 2227 offset = OHCI1394_HCControlSet; 2228 else 2229 offset = OHCI1394_HCControlClear; 2230 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable); 2231 2232 /* Clean up: configuration has been taken care of. */ 2233 reg_write(ohci, OHCI1394_HCControlClear, 2234 OHCI1394_HCControl_programPhyEnable); 2235 2236 return 0; 2237 } 2238 2239 static int probe_tsb41ba3d(struct fw_ohci *ohci) 2240 { 2241 /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */ 2242 static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, }; 2243 int reg, i; 2244 2245 reg = read_phy_reg(ohci, 2); 2246 if (reg < 0) 2247 return reg; 2248 if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS) 2249 return 0; 2250 2251 for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) { 2252 reg = read_paged_phy_reg(ohci, 1, i + 10); 2253 if (reg < 0) 2254 return reg; 2255 if (reg != id[i]) 2256 return 0; 2257 } 2258 return 1; 2259 } 2260 2261 static int ohci_enable(struct fw_card *card, 2262 const __be32 *config_rom, size_t length) 2263 { 2264 struct fw_ohci *ohci = fw_ohci(card); 2265 u32 lps, version, irqs; 2266 int i, ret; 2267 2268 ret = software_reset(ohci); 2269 if (ret < 0) { 2270 ohci_err(ohci, "failed to reset ohci card\n"); 2271 return ret; 2272 } 2273 2274 /* 2275 * Now enable LPS, which we need in order to start accessing 2276 * most of the registers. In fact, on some cards (ALI M5251), 2277 * accessing registers in the SClk domain without LPS enabled 2278 * will lock up the machine. Wait 50msec to make sure we have 2279 * full link enabled. However, with some cards (well, at least 2280 * a JMicron PCIe card), we have to try again sometimes. 2281 * 2282 * TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but 2283 * cannot actually use the phy at that time. These need tens of 2284 * millisecods pause between LPS write and first phy access too. 2285 */ 2286 2287 reg_write(ohci, OHCI1394_HCControlSet, 2288 OHCI1394_HCControl_LPS | 2289 OHCI1394_HCControl_postedWriteEnable); 2290 flush_writes(ohci); 2291 2292 for (lps = 0, i = 0; !lps && i < 3; i++) { 2293 msleep(50); 2294 lps = reg_read(ohci, OHCI1394_HCControlSet) & 2295 OHCI1394_HCControl_LPS; 2296 } 2297 2298 if (!lps) { 2299 ohci_err(ohci, "failed to set Link Power Status\n"); 2300 return -EIO; 2301 } 2302 2303 if (ohci->quirks & QUIRK_TI_SLLZ059) { 2304 ret = probe_tsb41ba3d(ohci); 2305 if (ret < 0) 2306 return ret; 2307 if (ret) 2308 ohci_notice(ohci, "local TSB41BA3D phy\n"); 2309 else 2310 ohci->quirks &= ~QUIRK_TI_SLLZ059; 2311 } 2312 2313 reg_write(ohci, OHCI1394_HCControlClear, 2314 OHCI1394_HCControl_noByteSwapData); 2315 2316 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); 2317 reg_write(ohci, OHCI1394_LinkControlSet, 2318 OHCI1394_LinkControl_cycleTimerEnable | 2319 OHCI1394_LinkControl_cycleMaster); 2320 2321 reg_write(ohci, OHCI1394_ATRetries, 2322 OHCI1394_MAX_AT_REQ_RETRIES | 2323 (OHCI1394_MAX_AT_RESP_RETRIES << 4) | 2324 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) | 2325 (200 << 16)); 2326 2327 ohci->bus_time_running = false; 2328 2329 for (i = 0; i < 32; i++) 2330 if (ohci->ir_context_support & (1 << i)) 2331 reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i), 2332 IR_CONTEXT_MULTI_CHANNEL_MODE); 2333 2334 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 2335 if (version >= OHCI_VERSION_1_1) { 2336 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi, 2337 0xfffffffe); 2338 card->broadcast_channel_auto_allocated = true; 2339 } 2340 2341 /* Get implemented bits of the priority arbitration request counter. */ 2342 reg_write(ohci, OHCI1394_FairnessControl, 0x3f); 2343 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f; 2344 reg_write(ohci, OHCI1394_FairnessControl, 0); 2345 card->priority_budget_implemented = ohci->pri_req_max != 0; 2346 2347 reg_write(ohci, OHCI1394_PhyUpperBound, FW_MAX_PHYSICAL_RANGE >> 16); 2348 reg_write(ohci, OHCI1394_IntEventClear, ~0); 2349 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 2350 2351 ret = configure_1394a_enhancements(ohci); 2352 if (ret < 0) 2353 return ret; 2354 2355 /* Activate link_on bit and contender bit in our self ID packets.*/ 2356 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER); 2357 if (ret < 0) 2358 return ret; 2359 2360 /* 2361 * When the link is not yet enabled, the atomic config rom 2362 * update mechanism described below in ohci_set_config_rom() 2363 * is not active. We have to update ConfigRomHeader and 2364 * BusOptions manually, and the write to ConfigROMmap takes 2365 * effect immediately. We tie this to the enabling of the 2366 * link, so we have a valid config rom before enabling - the 2367 * OHCI requires that ConfigROMhdr and BusOptions have valid 2368 * values before enabling. 2369 * 2370 * However, when the ConfigROMmap is written, some controllers 2371 * always read back quadlets 0 and 2 from the config rom to 2372 * the ConfigRomHeader and BusOptions registers on bus reset. 2373 * They shouldn't do that in this initial case where the link 2374 * isn't enabled. This means we have to use the same 2375 * workaround here, setting the bus header to 0 and then write 2376 * the right values in the bus reset tasklet. 2377 */ 2378 2379 if (config_rom) { 2380 ohci->next_config_rom = 2381 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2382 &ohci->next_config_rom_bus, 2383 GFP_KERNEL); 2384 if (ohci->next_config_rom == NULL) 2385 return -ENOMEM; 2386 2387 copy_config_rom(ohci->next_config_rom, config_rom, length); 2388 } else { 2389 /* 2390 * In the suspend case, config_rom is NULL, which 2391 * means that we just reuse the old config rom. 2392 */ 2393 ohci->next_config_rom = ohci->config_rom; 2394 ohci->next_config_rom_bus = ohci->config_rom_bus; 2395 } 2396 2397 ohci->next_header = ohci->next_config_rom[0]; 2398 ohci->next_config_rom[0] = 0; 2399 reg_write(ohci, OHCI1394_ConfigROMhdr, 0); 2400 reg_write(ohci, OHCI1394_BusOptions, 2401 be32_to_cpu(ohci->next_config_rom[2])); 2402 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2403 2404 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); 2405 2406 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete | 2407 OHCI1394_RQPkt | OHCI1394_RSPkt | 2408 OHCI1394_isochTx | OHCI1394_isochRx | 2409 OHCI1394_postedWriteErr | 2410 OHCI1394_selfIDComplete | 2411 OHCI1394_regAccessFail | 2412 OHCI1394_cycleInconsistent | 2413 OHCI1394_unrecoverableError | 2414 OHCI1394_cycleTooLong | 2415 OHCI1394_masterIntEnable; 2416 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS) 2417 irqs |= OHCI1394_busReset; 2418 reg_write(ohci, OHCI1394_IntMaskSet, irqs); 2419 2420 reg_write(ohci, OHCI1394_HCControlSet, 2421 OHCI1394_HCControl_linkEnable | 2422 OHCI1394_HCControl_BIBimageValid); 2423 2424 reg_write(ohci, OHCI1394_LinkControlSet, 2425 OHCI1394_LinkControl_rcvSelfID | 2426 OHCI1394_LinkControl_rcvPhyPkt); 2427 2428 ar_context_run(&ohci->ar_request_ctx); 2429 ar_context_run(&ohci->ar_response_ctx); 2430 2431 flush_writes(ohci); 2432 2433 /* We are ready to go, reset bus to finish initialization. */ 2434 fw_schedule_bus_reset(&ohci->card, false, true); 2435 2436 return 0; 2437 } 2438 2439 static int ohci_set_config_rom(struct fw_card *card, 2440 const __be32 *config_rom, size_t length) 2441 { 2442 struct fw_ohci *ohci; 2443 __be32 *next_config_rom; 2444 dma_addr_t next_config_rom_bus; 2445 2446 ohci = fw_ohci(card); 2447 2448 /* 2449 * When the OHCI controller is enabled, the config rom update 2450 * mechanism is a bit tricky, but easy enough to use. See 2451 * section 5.5.6 in the OHCI specification. 2452 * 2453 * The OHCI controller caches the new config rom address in a 2454 * shadow register (ConfigROMmapNext) and needs a bus reset 2455 * for the changes to take place. When the bus reset is 2456 * detected, the controller loads the new values for the 2457 * ConfigRomHeader and BusOptions registers from the specified 2458 * config rom and loads ConfigROMmap from the ConfigROMmapNext 2459 * shadow register. All automatically and atomically. 2460 * 2461 * Now, there's a twist to this story. The automatic load of 2462 * ConfigRomHeader and BusOptions doesn't honor the 2463 * noByteSwapData bit, so with a be32 config rom, the 2464 * controller will load be32 values in to these registers 2465 * during the atomic update, even on litte endian 2466 * architectures. The workaround we use is to put a 0 in the 2467 * header quadlet; 0 is endian agnostic and means that the 2468 * config rom isn't ready yet. In the bus reset tasklet we 2469 * then set up the real values for the two registers. 2470 * 2471 * We use ohci->lock to avoid racing with the code that sets 2472 * ohci->next_config_rom to NULL (see bus_reset_work). 2473 */ 2474 2475 next_config_rom = 2476 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2477 &next_config_rom_bus, GFP_KERNEL); 2478 if (next_config_rom == NULL) 2479 return -ENOMEM; 2480 2481 spin_lock_irq(&ohci->lock); 2482 2483 /* 2484 * If there is not an already pending config_rom update, 2485 * push our new allocation into the ohci->next_config_rom 2486 * and then mark the local variable as null so that we 2487 * won't deallocate the new buffer. 2488 * 2489 * OTOH, if there is a pending config_rom update, just 2490 * use that buffer with the new config_rom data, and 2491 * let this routine free the unused DMA allocation. 2492 */ 2493 2494 if (ohci->next_config_rom == NULL) { 2495 ohci->next_config_rom = next_config_rom; 2496 ohci->next_config_rom_bus = next_config_rom_bus; 2497 next_config_rom = NULL; 2498 } 2499 2500 copy_config_rom(ohci->next_config_rom, config_rom, length); 2501 2502 ohci->next_header = config_rom[0]; 2503 ohci->next_config_rom[0] = 0; 2504 2505 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2506 2507 spin_unlock_irq(&ohci->lock); 2508 2509 /* If we didn't use the DMA allocation, delete it. */ 2510 if (next_config_rom != NULL) 2511 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2512 next_config_rom, next_config_rom_bus); 2513 2514 /* 2515 * Now initiate a bus reset to have the changes take 2516 * effect. We clean up the old config rom memory and DMA 2517 * mappings in the bus reset tasklet, since the OHCI 2518 * controller could need to access it before the bus reset 2519 * takes effect. 2520 */ 2521 2522 fw_schedule_bus_reset(&ohci->card, true, true); 2523 2524 return 0; 2525 } 2526 2527 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) 2528 { 2529 struct fw_ohci *ohci = fw_ohci(card); 2530 2531 at_context_transmit(&ohci->at_request_ctx, packet); 2532 } 2533 2534 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) 2535 { 2536 struct fw_ohci *ohci = fw_ohci(card); 2537 2538 at_context_transmit(&ohci->at_response_ctx, packet); 2539 } 2540 2541 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) 2542 { 2543 struct fw_ohci *ohci = fw_ohci(card); 2544 struct context *ctx = &ohci->at_request_ctx; 2545 struct driver_data *driver_data = packet->driver_data; 2546 int ret = -ENOENT; 2547 2548 tasklet_disable_in_atomic(&ctx->tasklet); 2549 2550 if (packet->ack != 0) 2551 goto out; 2552 2553 if (packet->payload_mapped) 2554 dma_unmap_single(ohci->card.device, packet->payload_bus, 2555 packet->payload_length, DMA_TO_DEVICE); 2556 2557 log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20); 2558 driver_data->packet = NULL; 2559 packet->ack = RCODE_CANCELLED; 2560 packet->callback(packet, &ohci->card, packet->ack); 2561 ret = 0; 2562 out: 2563 tasklet_enable(&ctx->tasklet); 2564 2565 return ret; 2566 } 2567 2568 static int ohci_enable_phys_dma(struct fw_card *card, 2569 int node_id, int generation) 2570 { 2571 struct fw_ohci *ohci = fw_ohci(card); 2572 unsigned long flags; 2573 int n, ret = 0; 2574 2575 if (param_remote_dma) 2576 return 0; 2577 2578 /* 2579 * FIXME: Make sure this bitmask is cleared when we clear the busReset 2580 * interrupt bit. Clear physReqResourceAllBuses on bus reset. 2581 */ 2582 2583 spin_lock_irqsave(&ohci->lock, flags); 2584 2585 if (ohci->generation != generation) { 2586 ret = -ESTALE; 2587 goto out; 2588 } 2589 2590 /* 2591 * Note, if the node ID contains a non-local bus ID, physical DMA is 2592 * enabled for _all_ nodes on remote buses. 2593 */ 2594 2595 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; 2596 if (n < 32) 2597 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); 2598 else 2599 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); 2600 2601 flush_writes(ohci); 2602 out: 2603 spin_unlock_irqrestore(&ohci->lock, flags); 2604 2605 return ret; 2606 } 2607 2608 static u32 ohci_read_csr(struct fw_card *card, int csr_offset) 2609 { 2610 struct fw_ohci *ohci = fw_ohci(card); 2611 unsigned long flags; 2612 u32 value; 2613 2614 switch (csr_offset) { 2615 case CSR_STATE_CLEAR: 2616 case CSR_STATE_SET: 2617 if (ohci->is_root && 2618 (reg_read(ohci, OHCI1394_LinkControlSet) & 2619 OHCI1394_LinkControl_cycleMaster)) 2620 value = CSR_STATE_BIT_CMSTR; 2621 else 2622 value = 0; 2623 if (ohci->csr_state_setclear_abdicate) 2624 value |= CSR_STATE_BIT_ABDICATE; 2625 2626 return value; 2627 2628 case CSR_NODE_IDS: 2629 return reg_read(ohci, OHCI1394_NodeID) << 16; 2630 2631 case CSR_CYCLE_TIME: 2632 return get_cycle_time(ohci); 2633 2634 case CSR_BUS_TIME: 2635 /* 2636 * We might be called just after the cycle timer has wrapped 2637 * around but just before the cycle64Seconds handler, so we 2638 * better check here, too, if the bus time needs to be updated. 2639 */ 2640 spin_lock_irqsave(&ohci->lock, flags); 2641 value = update_bus_time(ohci); 2642 spin_unlock_irqrestore(&ohci->lock, flags); 2643 return value; 2644 2645 case CSR_BUSY_TIMEOUT: 2646 value = reg_read(ohci, OHCI1394_ATRetries); 2647 return (value >> 4) & 0x0ffff00f; 2648 2649 case CSR_PRIORITY_BUDGET: 2650 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) | 2651 (ohci->pri_req_max << 8); 2652 2653 default: 2654 WARN_ON(1); 2655 return 0; 2656 } 2657 } 2658 2659 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value) 2660 { 2661 struct fw_ohci *ohci = fw_ohci(card); 2662 unsigned long flags; 2663 2664 switch (csr_offset) { 2665 case CSR_STATE_CLEAR: 2666 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2667 reg_write(ohci, OHCI1394_LinkControlClear, 2668 OHCI1394_LinkControl_cycleMaster); 2669 flush_writes(ohci); 2670 } 2671 if (value & CSR_STATE_BIT_ABDICATE) 2672 ohci->csr_state_setclear_abdicate = false; 2673 break; 2674 2675 case CSR_STATE_SET: 2676 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2677 reg_write(ohci, OHCI1394_LinkControlSet, 2678 OHCI1394_LinkControl_cycleMaster); 2679 flush_writes(ohci); 2680 } 2681 if (value & CSR_STATE_BIT_ABDICATE) 2682 ohci->csr_state_setclear_abdicate = true; 2683 break; 2684 2685 case CSR_NODE_IDS: 2686 reg_write(ohci, OHCI1394_NodeID, value >> 16); 2687 flush_writes(ohci); 2688 break; 2689 2690 case CSR_CYCLE_TIME: 2691 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value); 2692 reg_write(ohci, OHCI1394_IntEventSet, 2693 OHCI1394_cycleInconsistent); 2694 flush_writes(ohci); 2695 break; 2696 2697 case CSR_BUS_TIME: 2698 spin_lock_irqsave(&ohci->lock, flags); 2699 ohci->bus_time = (update_bus_time(ohci) & 0x40) | 2700 (value & ~0x7f); 2701 spin_unlock_irqrestore(&ohci->lock, flags); 2702 break; 2703 2704 case CSR_BUSY_TIMEOUT: 2705 value = (value & 0xf) | ((value & 0xf) << 4) | 2706 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4); 2707 reg_write(ohci, OHCI1394_ATRetries, value); 2708 flush_writes(ohci); 2709 break; 2710 2711 case CSR_PRIORITY_BUDGET: 2712 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f); 2713 flush_writes(ohci); 2714 break; 2715 2716 default: 2717 WARN_ON(1); 2718 break; 2719 } 2720 } 2721 2722 static void flush_iso_completions(struct iso_context *ctx) 2723 { 2724 ctx->base.callback.sc(&ctx->base, ctx->last_timestamp, 2725 ctx->header_length, ctx->header, 2726 ctx->base.callback_data); 2727 ctx->header_length = 0; 2728 } 2729 2730 static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr) 2731 { 2732 u32 *ctx_hdr; 2733 2734 if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) { 2735 if (ctx->base.drop_overflow_headers) 2736 return; 2737 flush_iso_completions(ctx); 2738 } 2739 2740 ctx_hdr = ctx->header + ctx->header_length; 2741 ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]); 2742 2743 /* 2744 * The two iso header quadlets are byteswapped to little 2745 * endian by the controller, but we want to present them 2746 * as big endian for consistency with the bus endianness. 2747 */ 2748 if (ctx->base.header_size > 0) 2749 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */ 2750 if (ctx->base.header_size > 4) 2751 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */ 2752 if (ctx->base.header_size > 8) 2753 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8); 2754 ctx->header_length += ctx->base.header_size; 2755 } 2756 2757 static int handle_ir_packet_per_buffer(struct context *context, 2758 struct descriptor *d, 2759 struct descriptor *last) 2760 { 2761 struct iso_context *ctx = 2762 container_of(context, struct iso_context, context); 2763 struct descriptor *pd; 2764 u32 buffer_dma; 2765 2766 for (pd = d; pd <= last; pd++) 2767 if (pd->transfer_status) 2768 break; 2769 if (pd > last) 2770 /* Descriptor(s) not done yet, stop iteration */ 2771 return 0; 2772 2773 while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) { 2774 d++; 2775 buffer_dma = le32_to_cpu(d->data_address); 2776 dma_sync_single_range_for_cpu(context->ohci->card.device, 2777 buffer_dma & PAGE_MASK, 2778 buffer_dma & ~PAGE_MASK, 2779 le16_to_cpu(d->req_count), 2780 DMA_FROM_DEVICE); 2781 } 2782 2783 copy_iso_headers(ctx, (u32 *) (last + 1)); 2784 2785 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) 2786 flush_iso_completions(ctx); 2787 2788 return 1; 2789 } 2790 2791 /* d == last because each descriptor block is only a single descriptor. */ 2792 static int handle_ir_buffer_fill(struct context *context, 2793 struct descriptor *d, 2794 struct descriptor *last) 2795 { 2796 struct iso_context *ctx = 2797 container_of(context, struct iso_context, context); 2798 unsigned int req_count, res_count, completed; 2799 u32 buffer_dma; 2800 2801 req_count = le16_to_cpu(last->req_count); 2802 res_count = le16_to_cpu(READ_ONCE(last->res_count)); 2803 completed = req_count - res_count; 2804 buffer_dma = le32_to_cpu(last->data_address); 2805 2806 if (completed > 0) { 2807 ctx->mc_buffer_bus = buffer_dma; 2808 ctx->mc_completed = completed; 2809 } 2810 2811 if (res_count != 0) 2812 /* Descriptor(s) not done yet, stop iteration */ 2813 return 0; 2814 2815 dma_sync_single_range_for_cpu(context->ohci->card.device, 2816 buffer_dma & PAGE_MASK, 2817 buffer_dma & ~PAGE_MASK, 2818 completed, DMA_FROM_DEVICE); 2819 2820 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) { 2821 ctx->base.callback.mc(&ctx->base, 2822 buffer_dma + completed, 2823 ctx->base.callback_data); 2824 ctx->mc_completed = 0; 2825 } 2826 2827 return 1; 2828 } 2829 2830 static void flush_ir_buffer_fill(struct iso_context *ctx) 2831 { 2832 dma_sync_single_range_for_cpu(ctx->context.ohci->card.device, 2833 ctx->mc_buffer_bus & PAGE_MASK, 2834 ctx->mc_buffer_bus & ~PAGE_MASK, 2835 ctx->mc_completed, DMA_FROM_DEVICE); 2836 2837 ctx->base.callback.mc(&ctx->base, 2838 ctx->mc_buffer_bus + ctx->mc_completed, 2839 ctx->base.callback_data); 2840 ctx->mc_completed = 0; 2841 } 2842 2843 static inline void sync_it_packet_for_cpu(struct context *context, 2844 struct descriptor *pd) 2845 { 2846 __le16 control; 2847 u32 buffer_dma; 2848 2849 /* only packets beginning with OUTPUT_MORE* have data buffers */ 2850 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 2851 return; 2852 2853 /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */ 2854 pd += 2; 2855 2856 /* 2857 * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's 2858 * data buffer is in the context program's coherent page and must not 2859 * be synced. 2860 */ 2861 if ((le32_to_cpu(pd->data_address) & PAGE_MASK) == 2862 (context->current_bus & PAGE_MASK)) { 2863 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 2864 return; 2865 pd++; 2866 } 2867 2868 do { 2869 buffer_dma = le32_to_cpu(pd->data_address); 2870 dma_sync_single_range_for_cpu(context->ohci->card.device, 2871 buffer_dma & PAGE_MASK, 2872 buffer_dma & ~PAGE_MASK, 2873 le16_to_cpu(pd->req_count), 2874 DMA_TO_DEVICE); 2875 control = pd->control; 2876 pd++; 2877 } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))); 2878 } 2879 2880 static int handle_it_packet(struct context *context, 2881 struct descriptor *d, 2882 struct descriptor *last) 2883 { 2884 struct iso_context *ctx = 2885 container_of(context, struct iso_context, context); 2886 struct descriptor *pd; 2887 __be32 *ctx_hdr; 2888 2889 for (pd = d; pd <= last; pd++) 2890 if (pd->transfer_status) 2891 break; 2892 if (pd > last) 2893 /* Descriptor(s) not done yet, stop iteration */ 2894 return 0; 2895 2896 sync_it_packet_for_cpu(context, d); 2897 2898 if (ctx->header_length + 4 > PAGE_SIZE) { 2899 if (ctx->base.drop_overflow_headers) 2900 return 1; 2901 flush_iso_completions(ctx); 2902 } 2903 2904 ctx_hdr = ctx->header + ctx->header_length; 2905 ctx->last_timestamp = le16_to_cpu(last->res_count); 2906 /* Present this value as big-endian to match the receive code */ 2907 *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) | 2908 le16_to_cpu(pd->res_count)); 2909 ctx->header_length += 4; 2910 2911 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) 2912 flush_iso_completions(ctx); 2913 2914 return 1; 2915 } 2916 2917 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels) 2918 { 2919 u32 hi = channels >> 32, lo = channels; 2920 2921 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi); 2922 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo); 2923 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi); 2924 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo); 2925 ohci->mc_channels = channels; 2926 } 2927 2928 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card, 2929 int type, int channel, size_t header_size) 2930 { 2931 struct fw_ohci *ohci = fw_ohci(card); 2932 struct iso_context *ctx; 2933 descriptor_callback_t callback; 2934 u64 *channels; 2935 u32 *mask, regs; 2936 int index, ret = -EBUSY; 2937 2938 spin_lock_irq(&ohci->lock); 2939 2940 switch (type) { 2941 case FW_ISO_CONTEXT_TRANSMIT: 2942 mask = &ohci->it_context_mask; 2943 callback = handle_it_packet; 2944 index = ffs(*mask) - 1; 2945 if (index >= 0) { 2946 *mask &= ~(1 << index); 2947 regs = OHCI1394_IsoXmitContextBase(index); 2948 ctx = &ohci->it_context_list[index]; 2949 } 2950 break; 2951 2952 case FW_ISO_CONTEXT_RECEIVE: 2953 channels = &ohci->ir_context_channels; 2954 mask = &ohci->ir_context_mask; 2955 callback = handle_ir_packet_per_buffer; 2956 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1; 2957 if (index >= 0) { 2958 *channels &= ~(1ULL << channel); 2959 *mask &= ~(1 << index); 2960 regs = OHCI1394_IsoRcvContextBase(index); 2961 ctx = &ohci->ir_context_list[index]; 2962 } 2963 break; 2964 2965 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 2966 mask = &ohci->ir_context_mask; 2967 callback = handle_ir_buffer_fill; 2968 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1; 2969 if (index >= 0) { 2970 ohci->mc_allocated = true; 2971 *mask &= ~(1 << index); 2972 regs = OHCI1394_IsoRcvContextBase(index); 2973 ctx = &ohci->ir_context_list[index]; 2974 } 2975 break; 2976 2977 default: 2978 index = -1; 2979 ret = -ENOSYS; 2980 } 2981 2982 spin_unlock_irq(&ohci->lock); 2983 2984 if (index < 0) 2985 return ERR_PTR(ret); 2986 2987 memset(ctx, 0, sizeof(*ctx)); 2988 ctx->header_length = 0; 2989 ctx->header = (void *) __get_free_page(GFP_KERNEL); 2990 if (ctx->header == NULL) { 2991 ret = -ENOMEM; 2992 goto out; 2993 } 2994 ret = context_init(&ctx->context, ohci, regs, callback); 2995 if (ret < 0) 2996 goto out_with_header; 2997 2998 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) { 2999 set_multichannel_mask(ohci, 0); 3000 ctx->mc_completed = 0; 3001 } 3002 3003 return &ctx->base; 3004 3005 out_with_header: 3006 free_page((unsigned long)ctx->header); 3007 out: 3008 spin_lock_irq(&ohci->lock); 3009 3010 switch (type) { 3011 case FW_ISO_CONTEXT_RECEIVE: 3012 *channels |= 1ULL << channel; 3013 break; 3014 3015 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3016 ohci->mc_allocated = false; 3017 break; 3018 } 3019 *mask |= 1 << index; 3020 3021 spin_unlock_irq(&ohci->lock); 3022 3023 return ERR_PTR(ret); 3024 } 3025 3026 static int ohci_start_iso(struct fw_iso_context *base, 3027 s32 cycle, u32 sync, u32 tags) 3028 { 3029 struct iso_context *ctx = container_of(base, struct iso_context, base); 3030 struct fw_ohci *ohci = ctx->context.ohci; 3031 u32 control = IR_CONTEXT_ISOCH_HEADER, match; 3032 int index; 3033 3034 /* the controller cannot start without any queued packets */ 3035 if (ctx->context.last->branch_address == 0) 3036 return -ENODATA; 3037 3038 switch (ctx->base.type) { 3039 case FW_ISO_CONTEXT_TRANSMIT: 3040 index = ctx - ohci->it_context_list; 3041 match = 0; 3042 if (cycle >= 0) 3043 match = IT_CONTEXT_CYCLE_MATCH_ENABLE | 3044 (cycle & 0x7fff) << 16; 3045 3046 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); 3047 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); 3048 context_run(&ctx->context, match); 3049 break; 3050 3051 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3052 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE; 3053 fallthrough; 3054 case FW_ISO_CONTEXT_RECEIVE: 3055 index = ctx - ohci->ir_context_list; 3056 match = (tags << 28) | (sync << 8) | ctx->base.channel; 3057 if (cycle >= 0) { 3058 match |= (cycle & 0x07fff) << 12; 3059 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE; 3060 } 3061 3062 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); 3063 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); 3064 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match); 3065 context_run(&ctx->context, control); 3066 3067 ctx->sync = sync; 3068 ctx->tags = tags; 3069 3070 break; 3071 } 3072 3073 return 0; 3074 } 3075 3076 static int ohci_stop_iso(struct fw_iso_context *base) 3077 { 3078 struct fw_ohci *ohci = fw_ohci(base->card); 3079 struct iso_context *ctx = container_of(base, struct iso_context, base); 3080 int index; 3081 3082 switch (ctx->base.type) { 3083 case FW_ISO_CONTEXT_TRANSMIT: 3084 index = ctx - ohci->it_context_list; 3085 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); 3086 break; 3087 3088 case FW_ISO_CONTEXT_RECEIVE: 3089 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3090 index = ctx - ohci->ir_context_list; 3091 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); 3092 break; 3093 } 3094 flush_writes(ohci); 3095 context_stop(&ctx->context); 3096 tasklet_kill(&ctx->context.tasklet); 3097 3098 return 0; 3099 } 3100 3101 static void ohci_free_iso_context(struct fw_iso_context *base) 3102 { 3103 struct fw_ohci *ohci = fw_ohci(base->card); 3104 struct iso_context *ctx = container_of(base, struct iso_context, base); 3105 unsigned long flags; 3106 int index; 3107 3108 ohci_stop_iso(base); 3109 context_release(&ctx->context); 3110 free_page((unsigned long)ctx->header); 3111 3112 spin_lock_irqsave(&ohci->lock, flags); 3113 3114 switch (base->type) { 3115 case FW_ISO_CONTEXT_TRANSMIT: 3116 index = ctx - ohci->it_context_list; 3117 ohci->it_context_mask |= 1 << index; 3118 break; 3119 3120 case FW_ISO_CONTEXT_RECEIVE: 3121 index = ctx - ohci->ir_context_list; 3122 ohci->ir_context_mask |= 1 << index; 3123 ohci->ir_context_channels |= 1ULL << base->channel; 3124 break; 3125 3126 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3127 index = ctx - ohci->ir_context_list; 3128 ohci->ir_context_mask |= 1 << index; 3129 ohci->ir_context_channels |= ohci->mc_channels; 3130 ohci->mc_channels = 0; 3131 ohci->mc_allocated = false; 3132 break; 3133 } 3134 3135 spin_unlock_irqrestore(&ohci->lock, flags); 3136 } 3137 3138 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels) 3139 { 3140 struct fw_ohci *ohci = fw_ohci(base->card); 3141 unsigned long flags; 3142 int ret; 3143 3144 switch (base->type) { 3145 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3146 3147 spin_lock_irqsave(&ohci->lock, flags); 3148 3149 /* Don't allow multichannel to grab other contexts' channels. */ 3150 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) { 3151 *channels = ohci->ir_context_channels; 3152 ret = -EBUSY; 3153 } else { 3154 set_multichannel_mask(ohci, *channels); 3155 ret = 0; 3156 } 3157 3158 spin_unlock_irqrestore(&ohci->lock, flags); 3159 3160 break; 3161 default: 3162 ret = -EINVAL; 3163 } 3164 3165 return ret; 3166 } 3167 3168 #ifdef CONFIG_PM 3169 static void ohci_resume_iso_dma(struct fw_ohci *ohci) 3170 { 3171 int i; 3172 struct iso_context *ctx; 3173 3174 for (i = 0 ; i < ohci->n_ir ; i++) { 3175 ctx = &ohci->ir_context_list[i]; 3176 if (ctx->context.running) 3177 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 3178 } 3179 3180 for (i = 0 ; i < ohci->n_it ; i++) { 3181 ctx = &ohci->it_context_list[i]; 3182 if (ctx->context.running) 3183 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 3184 } 3185 } 3186 #endif 3187 3188 static int queue_iso_transmit(struct iso_context *ctx, 3189 struct fw_iso_packet *packet, 3190 struct fw_iso_buffer *buffer, 3191 unsigned long payload) 3192 { 3193 struct descriptor *d, *last, *pd; 3194 struct fw_iso_packet *p; 3195 __le32 *header; 3196 dma_addr_t d_bus, page_bus; 3197 u32 z, header_z, payload_z, irq; 3198 u32 payload_index, payload_end_index, next_page_index; 3199 int page, end_page, i, length, offset; 3200 3201 p = packet; 3202 payload_index = payload; 3203 3204 if (p->skip) 3205 z = 1; 3206 else 3207 z = 2; 3208 if (p->header_length > 0) 3209 z++; 3210 3211 /* Determine the first page the payload isn't contained in. */ 3212 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; 3213 if (p->payload_length > 0) 3214 payload_z = end_page - (payload_index >> PAGE_SHIFT); 3215 else 3216 payload_z = 0; 3217 3218 z += payload_z; 3219 3220 /* Get header size in number of descriptors. */ 3221 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d)); 3222 3223 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); 3224 if (d == NULL) 3225 return -ENOMEM; 3226 3227 if (!p->skip) { 3228 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 3229 d[0].req_count = cpu_to_le16(8); 3230 /* 3231 * Link the skip address to this descriptor itself. This causes 3232 * a context to skip a cycle whenever lost cycles or FIFO 3233 * overruns occur, without dropping the data. The application 3234 * should then decide whether this is an error condition or not. 3235 * FIXME: Make the context's cycle-lost behaviour configurable? 3236 */ 3237 d[0].branch_address = cpu_to_le32(d_bus | z); 3238 3239 header = (__le32 *) &d[1]; 3240 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) | 3241 IT_HEADER_TAG(p->tag) | 3242 IT_HEADER_TCODE(TCODE_STREAM_DATA) | 3243 IT_HEADER_CHANNEL(ctx->base.channel) | 3244 IT_HEADER_SPEED(ctx->base.speed)); 3245 header[1] = 3246 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length + 3247 p->payload_length)); 3248 } 3249 3250 if (p->header_length > 0) { 3251 d[2].req_count = cpu_to_le16(p->header_length); 3252 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d)); 3253 memcpy(&d[z], p->header, p->header_length); 3254 } 3255 3256 pd = d + z - payload_z; 3257 payload_end_index = payload_index + p->payload_length; 3258 for (i = 0; i < payload_z; i++) { 3259 page = payload_index >> PAGE_SHIFT; 3260 offset = payload_index & ~PAGE_MASK; 3261 next_page_index = (page + 1) << PAGE_SHIFT; 3262 length = 3263 min(next_page_index, payload_end_index) - payload_index; 3264 pd[i].req_count = cpu_to_le16(length); 3265 3266 page_bus = page_private(buffer->pages[page]); 3267 pd[i].data_address = cpu_to_le32(page_bus + offset); 3268 3269 dma_sync_single_range_for_device(ctx->context.ohci->card.device, 3270 page_bus, offset, length, 3271 DMA_TO_DEVICE); 3272 3273 payload_index += length; 3274 } 3275 3276 if (p->interrupt) 3277 irq = DESCRIPTOR_IRQ_ALWAYS; 3278 else 3279 irq = DESCRIPTOR_NO_IRQ; 3280 3281 last = z == 2 ? d : d + z - 1; 3282 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 3283 DESCRIPTOR_STATUS | 3284 DESCRIPTOR_BRANCH_ALWAYS | 3285 irq); 3286 3287 context_append(&ctx->context, d, z, header_z); 3288 3289 return 0; 3290 } 3291 3292 static int queue_iso_packet_per_buffer(struct iso_context *ctx, 3293 struct fw_iso_packet *packet, 3294 struct fw_iso_buffer *buffer, 3295 unsigned long payload) 3296 { 3297 struct device *device = ctx->context.ohci->card.device; 3298 struct descriptor *d, *pd; 3299 dma_addr_t d_bus, page_bus; 3300 u32 z, header_z, rest; 3301 int i, j, length; 3302 int page, offset, packet_count, header_size, payload_per_buffer; 3303 3304 /* 3305 * The OHCI controller puts the isochronous header and trailer in the 3306 * buffer, so we need at least 8 bytes. 3307 */ 3308 packet_count = packet->header_length / ctx->base.header_size; 3309 header_size = max(ctx->base.header_size, (size_t)8); 3310 3311 /* Get header size in number of descriptors. */ 3312 header_z = DIV_ROUND_UP(header_size, sizeof(*d)); 3313 page = payload >> PAGE_SHIFT; 3314 offset = payload & ~PAGE_MASK; 3315 payload_per_buffer = packet->payload_length / packet_count; 3316 3317 for (i = 0; i < packet_count; i++) { 3318 /* d points to the header descriptor */ 3319 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1; 3320 d = context_get_descriptors(&ctx->context, 3321 z + header_z, &d_bus); 3322 if (d == NULL) 3323 return -ENOMEM; 3324 3325 d->control = cpu_to_le16(DESCRIPTOR_STATUS | 3326 DESCRIPTOR_INPUT_MORE); 3327 if (packet->skip && i == 0) 3328 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3329 d->req_count = cpu_to_le16(header_size); 3330 d->res_count = d->req_count; 3331 d->transfer_status = 0; 3332 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d))); 3333 3334 rest = payload_per_buffer; 3335 pd = d; 3336 for (j = 1; j < z; j++) { 3337 pd++; 3338 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3339 DESCRIPTOR_INPUT_MORE); 3340 3341 if (offset + rest < PAGE_SIZE) 3342 length = rest; 3343 else 3344 length = PAGE_SIZE - offset; 3345 pd->req_count = cpu_to_le16(length); 3346 pd->res_count = pd->req_count; 3347 pd->transfer_status = 0; 3348 3349 page_bus = page_private(buffer->pages[page]); 3350 pd->data_address = cpu_to_le32(page_bus + offset); 3351 3352 dma_sync_single_range_for_device(device, page_bus, 3353 offset, length, 3354 DMA_FROM_DEVICE); 3355 3356 offset = (offset + length) & ~PAGE_MASK; 3357 rest -= length; 3358 if (offset == 0) 3359 page++; 3360 } 3361 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3362 DESCRIPTOR_INPUT_LAST | 3363 DESCRIPTOR_BRANCH_ALWAYS); 3364 if (packet->interrupt && i == packet_count - 1) 3365 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3366 3367 context_append(&ctx->context, d, z, header_z); 3368 } 3369 3370 return 0; 3371 } 3372 3373 static int queue_iso_buffer_fill(struct iso_context *ctx, 3374 struct fw_iso_packet *packet, 3375 struct fw_iso_buffer *buffer, 3376 unsigned long payload) 3377 { 3378 struct descriptor *d; 3379 dma_addr_t d_bus, page_bus; 3380 int page, offset, rest, z, i, length; 3381 3382 page = payload >> PAGE_SHIFT; 3383 offset = payload & ~PAGE_MASK; 3384 rest = packet->payload_length; 3385 3386 /* We need one descriptor for each page in the buffer. */ 3387 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE); 3388 3389 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count)) 3390 return -EFAULT; 3391 3392 for (i = 0; i < z; i++) { 3393 d = context_get_descriptors(&ctx->context, 1, &d_bus); 3394 if (d == NULL) 3395 return -ENOMEM; 3396 3397 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 3398 DESCRIPTOR_BRANCH_ALWAYS); 3399 if (packet->skip && i == 0) 3400 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3401 if (packet->interrupt && i == z - 1) 3402 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3403 3404 if (offset + rest < PAGE_SIZE) 3405 length = rest; 3406 else 3407 length = PAGE_SIZE - offset; 3408 d->req_count = cpu_to_le16(length); 3409 d->res_count = d->req_count; 3410 d->transfer_status = 0; 3411 3412 page_bus = page_private(buffer->pages[page]); 3413 d->data_address = cpu_to_le32(page_bus + offset); 3414 3415 dma_sync_single_range_for_device(ctx->context.ohci->card.device, 3416 page_bus, offset, length, 3417 DMA_FROM_DEVICE); 3418 3419 rest -= length; 3420 offset = 0; 3421 page++; 3422 3423 context_append(&ctx->context, d, 1, 0); 3424 } 3425 3426 return 0; 3427 } 3428 3429 static int ohci_queue_iso(struct fw_iso_context *base, 3430 struct fw_iso_packet *packet, 3431 struct fw_iso_buffer *buffer, 3432 unsigned long payload) 3433 { 3434 struct iso_context *ctx = container_of(base, struct iso_context, base); 3435 unsigned long flags; 3436 int ret = -ENOSYS; 3437 3438 spin_lock_irqsave(&ctx->context.ohci->lock, flags); 3439 switch (base->type) { 3440 case FW_ISO_CONTEXT_TRANSMIT: 3441 ret = queue_iso_transmit(ctx, packet, buffer, payload); 3442 break; 3443 case FW_ISO_CONTEXT_RECEIVE: 3444 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload); 3445 break; 3446 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3447 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload); 3448 break; 3449 } 3450 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags); 3451 3452 return ret; 3453 } 3454 3455 static void ohci_flush_queue_iso(struct fw_iso_context *base) 3456 { 3457 struct context *ctx = 3458 &container_of(base, struct iso_context, base)->context; 3459 3460 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 3461 } 3462 3463 static int ohci_flush_iso_completions(struct fw_iso_context *base) 3464 { 3465 struct iso_context *ctx = container_of(base, struct iso_context, base); 3466 int ret = 0; 3467 3468 tasklet_disable_in_atomic(&ctx->context.tasklet); 3469 3470 if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) { 3471 context_tasklet((unsigned long)&ctx->context); 3472 3473 switch (base->type) { 3474 case FW_ISO_CONTEXT_TRANSMIT: 3475 case FW_ISO_CONTEXT_RECEIVE: 3476 if (ctx->header_length != 0) 3477 flush_iso_completions(ctx); 3478 break; 3479 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3480 if (ctx->mc_completed != 0) 3481 flush_ir_buffer_fill(ctx); 3482 break; 3483 default: 3484 ret = -ENOSYS; 3485 } 3486 3487 clear_bit_unlock(0, &ctx->flushing_completions); 3488 smp_mb__after_atomic(); 3489 } 3490 3491 tasklet_enable(&ctx->context.tasklet); 3492 3493 return ret; 3494 } 3495 3496 static const struct fw_card_driver ohci_driver = { 3497 .enable = ohci_enable, 3498 .read_phy_reg = ohci_read_phy_reg, 3499 .update_phy_reg = ohci_update_phy_reg, 3500 .set_config_rom = ohci_set_config_rom, 3501 .send_request = ohci_send_request, 3502 .send_response = ohci_send_response, 3503 .cancel_packet = ohci_cancel_packet, 3504 .enable_phys_dma = ohci_enable_phys_dma, 3505 .read_csr = ohci_read_csr, 3506 .write_csr = ohci_write_csr, 3507 3508 .allocate_iso_context = ohci_allocate_iso_context, 3509 .free_iso_context = ohci_free_iso_context, 3510 .set_iso_channels = ohci_set_iso_channels, 3511 .queue_iso = ohci_queue_iso, 3512 .flush_queue_iso = ohci_flush_queue_iso, 3513 .flush_iso_completions = ohci_flush_iso_completions, 3514 .start_iso = ohci_start_iso, 3515 .stop_iso = ohci_stop_iso, 3516 }; 3517 3518 #ifdef CONFIG_PPC_PMAC 3519 static void pmac_ohci_on(struct pci_dev *dev) 3520 { 3521 if (machine_is(powermac)) { 3522 struct device_node *ofn = pci_device_to_OF_node(dev); 3523 3524 if (ofn) { 3525 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1); 3526 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1); 3527 } 3528 } 3529 } 3530 3531 static void pmac_ohci_off(struct pci_dev *dev) 3532 { 3533 if (machine_is(powermac)) { 3534 struct device_node *ofn = pci_device_to_OF_node(dev); 3535 3536 if (ofn) { 3537 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0); 3538 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0); 3539 } 3540 } 3541 } 3542 #else 3543 static inline void pmac_ohci_on(struct pci_dev *dev) {} 3544 static inline void pmac_ohci_off(struct pci_dev *dev) {} 3545 #endif /* CONFIG_PPC_PMAC */ 3546 3547 static int pci_probe(struct pci_dev *dev, 3548 const struct pci_device_id *ent) 3549 { 3550 struct fw_ohci *ohci; 3551 u32 bus_options, max_receive, link_speed, version; 3552 u64 guid; 3553 int i, err; 3554 size_t size; 3555 3556 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) { 3557 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n"); 3558 return -ENOSYS; 3559 } 3560 3561 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL); 3562 if (ohci == NULL) { 3563 err = -ENOMEM; 3564 goto fail; 3565 } 3566 3567 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); 3568 3569 pmac_ohci_on(dev); 3570 3571 err = pci_enable_device(dev); 3572 if (err) { 3573 dev_err(&dev->dev, "failed to enable OHCI hardware\n"); 3574 goto fail_free; 3575 } 3576 3577 pci_set_master(dev); 3578 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); 3579 pci_set_drvdata(dev, ohci); 3580 3581 spin_lock_init(&ohci->lock); 3582 mutex_init(&ohci->phy_reg_mutex); 3583 3584 INIT_WORK(&ohci->bus_reset_work, bus_reset_work); 3585 3586 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) || 3587 pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) { 3588 ohci_err(ohci, "invalid MMIO resource\n"); 3589 err = -ENXIO; 3590 goto fail_disable; 3591 } 3592 3593 err = pci_request_region(dev, 0, ohci_driver_name); 3594 if (err) { 3595 ohci_err(ohci, "MMIO resource unavailable\n"); 3596 goto fail_disable; 3597 } 3598 3599 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE); 3600 if (ohci->registers == NULL) { 3601 ohci_err(ohci, "failed to remap registers\n"); 3602 err = -ENXIO; 3603 goto fail_iomem; 3604 } 3605 3606 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++) 3607 if ((ohci_quirks[i].vendor == dev->vendor) && 3608 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID || 3609 ohci_quirks[i].device == dev->device) && 3610 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID || 3611 ohci_quirks[i].revision >= dev->revision)) { 3612 ohci->quirks = ohci_quirks[i].flags; 3613 break; 3614 } 3615 if (param_quirks) 3616 ohci->quirks = param_quirks; 3617 3618 /* 3619 * Because dma_alloc_coherent() allocates at least one page, 3620 * we save space by using a common buffer for the AR request/ 3621 * response descriptors and the self IDs buffer. 3622 */ 3623 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4); 3624 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2); 3625 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device, 3626 PAGE_SIZE, 3627 &ohci->misc_buffer_bus, 3628 GFP_KERNEL); 3629 if (!ohci->misc_buffer) { 3630 err = -ENOMEM; 3631 goto fail_iounmap; 3632 } 3633 3634 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0, 3635 OHCI1394_AsReqRcvContextControlSet); 3636 if (err < 0) 3637 goto fail_misc_buf; 3638 3639 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4, 3640 OHCI1394_AsRspRcvContextControlSet); 3641 if (err < 0) 3642 goto fail_arreq_ctx; 3643 3644 err = context_init(&ohci->at_request_ctx, ohci, 3645 OHCI1394_AsReqTrContextControlSet, handle_at_packet); 3646 if (err < 0) 3647 goto fail_arrsp_ctx; 3648 3649 err = context_init(&ohci->at_response_ctx, ohci, 3650 OHCI1394_AsRspTrContextControlSet, handle_at_packet); 3651 if (err < 0) 3652 goto fail_atreq_ctx; 3653 3654 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); 3655 ohci->ir_context_channels = ~0ULL; 3656 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); 3657 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); 3658 ohci->ir_context_mask = ohci->ir_context_support; 3659 ohci->n_ir = hweight32(ohci->ir_context_mask); 3660 size = sizeof(struct iso_context) * ohci->n_ir; 3661 ohci->ir_context_list = kzalloc(size, GFP_KERNEL); 3662 3663 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); 3664 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); 3665 /* JMicron JMB38x often shows 0 at first read, just ignore it */ 3666 if (!ohci->it_context_support) { 3667 ohci_notice(ohci, "overriding IsoXmitIntMask\n"); 3668 ohci->it_context_support = 0xf; 3669 } 3670 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); 3671 ohci->it_context_mask = ohci->it_context_support; 3672 ohci->n_it = hweight32(ohci->it_context_mask); 3673 size = sizeof(struct iso_context) * ohci->n_it; 3674 ohci->it_context_list = kzalloc(size, GFP_KERNEL); 3675 3676 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) { 3677 err = -ENOMEM; 3678 goto fail_contexts; 3679 } 3680 3681 ohci->self_id = ohci->misc_buffer + PAGE_SIZE/2; 3682 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2; 3683 3684 bus_options = reg_read(ohci, OHCI1394_BusOptions); 3685 max_receive = (bus_options >> 12) & 0xf; 3686 link_speed = bus_options & 0x7; 3687 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | 3688 reg_read(ohci, OHCI1394_GUIDLo); 3689 3690 if (!(ohci->quirks & QUIRK_NO_MSI)) 3691 pci_enable_msi(dev); 3692 if (request_irq(dev->irq, irq_handler, 3693 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED, 3694 ohci_driver_name, ohci)) { 3695 ohci_err(ohci, "failed to allocate interrupt %d\n", dev->irq); 3696 err = -EIO; 3697 goto fail_msi; 3698 } 3699 3700 err = fw_card_add(&ohci->card, max_receive, link_speed, guid); 3701 if (err) 3702 goto fail_irq; 3703 3704 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 3705 ohci_notice(ohci, 3706 "added OHCI v%x.%x device as card %d, " 3707 "%d IR + %d IT contexts, quirks 0x%x%s\n", 3708 version >> 16, version & 0xff, ohci->card.index, 3709 ohci->n_ir, ohci->n_it, ohci->quirks, 3710 reg_read(ohci, OHCI1394_PhyUpperBound) ? 3711 ", physUB" : ""); 3712 3713 return 0; 3714 3715 fail_irq: 3716 free_irq(dev->irq, ohci); 3717 fail_msi: 3718 pci_disable_msi(dev); 3719 fail_contexts: 3720 kfree(ohci->ir_context_list); 3721 kfree(ohci->it_context_list); 3722 context_release(&ohci->at_response_ctx); 3723 fail_atreq_ctx: 3724 context_release(&ohci->at_request_ctx); 3725 fail_arrsp_ctx: 3726 ar_context_release(&ohci->ar_response_ctx); 3727 fail_arreq_ctx: 3728 ar_context_release(&ohci->ar_request_ctx); 3729 fail_misc_buf: 3730 dma_free_coherent(ohci->card.device, PAGE_SIZE, 3731 ohci->misc_buffer, ohci->misc_buffer_bus); 3732 fail_iounmap: 3733 pci_iounmap(dev, ohci->registers); 3734 fail_iomem: 3735 pci_release_region(dev, 0); 3736 fail_disable: 3737 pci_disable_device(dev); 3738 fail_free: 3739 kfree(ohci); 3740 pmac_ohci_off(dev); 3741 fail: 3742 return err; 3743 } 3744 3745 static void pci_remove(struct pci_dev *dev) 3746 { 3747 struct fw_ohci *ohci = pci_get_drvdata(dev); 3748 3749 /* 3750 * If the removal is happening from the suspend state, LPS won't be 3751 * enabled and host registers (eg., IntMaskClear) won't be accessible. 3752 */ 3753 if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) { 3754 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 3755 flush_writes(ohci); 3756 } 3757 cancel_work_sync(&ohci->bus_reset_work); 3758 fw_core_remove_card(&ohci->card); 3759 3760 /* 3761 * FIXME: Fail all pending packets here, now that the upper 3762 * layers can't queue any more. 3763 */ 3764 3765 software_reset(ohci); 3766 free_irq(dev->irq, ohci); 3767 3768 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom) 3769 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 3770 ohci->next_config_rom, ohci->next_config_rom_bus); 3771 if (ohci->config_rom) 3772 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 3773 ohci->config_rom, ohci->config_rom_bus); 3774 ar_context_release(&ohci->ar_request_ctx); 3775 ar_context_release(&ohci->ar_response_ctx); 3776 dma_free_coherent(ohci->card.device, PAGE_SIZE, 3777 ohci->misc_buffer, ohci->misc_buffer_bus); 3778 context_release(&ohci->at_request_ctx); 3779 context_release(&ohci->at_response_ctx); 3780 kfree(ohci->it_context_list); 3781 kfree(ohci->ir_context_list); 3782 pci_disable_msi(dev); 3783 pci_iounmap(dev, ohci->registers); 3784 pci_release_region(dev, 0); 3785 pci_disable_device(dev); 3786 kfree(ohci); 3787 pmac_ohci_off(dev); 3788 3789 dev_notice(&dev->dev, "removed fw-ohci device\n"); 3790 } 3791 3792 #ifdef CONFIG_PM 3793 static int pci_suspend(struct pci_dev *dev, pm_message_t state) 3794 { 3795 struct fw_ohci *ohci = pci_get_drvdata(dev); 3796 int err; 3797 3798 software_reset(ohci); 3799 err = pci_save_state(dev); 3800 if (err) { 3801 ohci_err(ohci, "pci_save_state failed\n"); 3802 return err; 3803 } 3804 err = pci_set_power_state(dev, pci_choose_state(dev, state)); 3805 if (err) 3806 ohci_err(ohci, "pci_set_power_state failed with %d\n", err); 3807 pmac_ohci_off(dev); 3808 3809 return 0; 3810 } 3811 3812 static int pci_resume(struct pci_dev *dev) 3813 { 3814 struct fw_ohci *ohci = pci_get_drvdata(dev); 3815 int err; 3816 3817 pmac_ohci_on(dev); 3818 pci_set_power_state(dev, PCI_D0); 3819 pci_restore_state(dev); 3820 err = pci_enable_device(dev); 3821 if (err) { 3822 ohci_err(ohci, "pci_enable_device failed\n"); 3823 return err; 3824 } 3825 3826 /* Some systems don't setup GUID register on resume from ram */ 3827 if (!reg_read(ohci, OHCI1394_GUIDLo) && 3828 !reg_read(ohci, OHCI1394_GUIDHi)) { 3829 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid); 3830 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32)); 3831 } 3832 3833 err = ohci_enable(&ohci->card, NULL, 0); 3834 if (err) 3835 return err; 3836 3837 ohci_resume_iso_dma(ohci); 3838 3839 return 0; 3840 } 3841 #endif 3842 3843 static const struct pci_device_id pci_table[] = { 3844 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, 3845 { } 3846 }; 3847 3848 MODULE_DEVICE_TABLE(pci, pci_table); 3849 3850 static struct pci_driver fw_ohci_pci_driver = { 3851 .name = ohci_driver_name, 3852 .id_table = pci_table, 3853 .probe = pci_probe, 3854 .remove = pci_remove, 3855 #ifdef CONFIG_PM 3856 .resume = pci_resume, 3857 .suspend = pci_suspend, 3858 #endif 3859 }; 3860 3861 static int __init fw_ohci_init(void) 3862 { 3863 selfid_workqueue = alloc_workqueue(KBUILD_MODNAME, WQ_MEM_RECLAIM, 0); 3864 if (!selfid_workqueue) 3865 return -ENOMEM; 3866 3867 return pci_register_driver(&fw_ohci_pci_driver); 3868 } 3869 3870 static void __exit fw_ohci_cleanup(void) 3871 { 3872 pci_unregister_driver(&fw_ohci_pci_driver); 3873 destroy_workqueue(selfid_workqueue); 3874 } 3875 3876 module_init(fw_ohci_init); 3877 module_exit(fw_ohci_cleanup); 3878 3879 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); 3880 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); 3881 MODULE_LICENSE("GPL"); 3882 3883 /* Provide a module alias so root-on-sbp2 initrds don't break. */ 3884 MODULE_ALIAS("ohci1394"); 3885