1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for OHCI 1394 controllers 4 * 5 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/bug.h> 10 #include <linux/compiler.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/firewire.h> 15 #include <linux/firewire-constants.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/mm.h> 22 #include <linux/module.h> 23 #include <linux/moduleparam.h> 24 #include <linux/mutex.h> 25 #include <linux/pci.h> 26 #include <linux/pci_ids.h> 27 #include <linux/slab.h> 28 #include <linux/spinlock.h> 29 #include <linux/string.h> 30 #include <linux/time.h> 31 #include <linux/vmalloc.h> 32 #include <linux/workqueue.h> 33 34 #include <asm/byteorder.h> 35 #include <asm/page.h> 36 37 #ifdef CONFIG_PPC_PMAC 38 #include <asm/pmac_feature.h> 39 #endif 40 41 #include "core.h" 42 #include "ohci.h" 43 44 #define ohci_info(ohci, f, args...) dev_info(ohci->card.device, f, ##args) 45 #define ohci_notice(ohci, f, args...) dev_notice(ohci->card.device, f, ##args) 46 #define ohci_err(ohci, f, args...) dev_err(ohci->card.device, f, ##args) 47 48 #define DESCRIPTOR_OUTPUT_MORE 0 49 #define DESCRIPTOR_OUTPUT_LAST (1 << 12) 50 #define DESCRIPTOR_INPUT_MORE (2 << 12) 51 #define DESCRIPTOR_INPUT_LAST (3 << 12) 52 #define DESCRIPTOR_STATUS (1 << 11) 53 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8) 54 #define DESCRIPTOR_PING (1 << 7) 55 #define DESCRIPTOR_YY (1 << 6) 56 #define DESCRIPTOR_NO_IRQ (0 << 4) 57 #define DESCRIPTOR_IRQ_ERROR (1 << 4) 58 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4) 59 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2) 60 #define DESCRIPTOR_WAIT (3 << 0) 61 62 #define DESCRIPTOR_CMD (0xf << 12) 63 64 struct descriptor { 65 __le16 req_count; 66 __le16 control; 67 __le32 data_address; 68 __le32 branch_address; 69 __le16 res_count; 70 __le16 transfer_status; 71 } __attribute__((aligned(16))); 72 73 #define CONTROL_SET(regs) (regs) 74 #define CONTROL_CLEAR(regs) ((regs) + 4) 75 #define COMMAND_PTR(regs) ((regs) + 12) 76 #define CONTEXT_MATCH(regs) ((regs) + 16) 77 78 #define AR_BUFFER_SIZE (32*1024) 79 #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE) 80 /* we need at least two pages for proper list management */ 81 #define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2) 82 83 #define MAX_ASYNC_PAYLOAD 4096 84 #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4) 85 #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE) 86 87 struct ar_context { 88 struct fw_ohci *ohci; 89 struct page *pages[AR_BUFFERS]; 90 void *buffer; 91 struct descriptor *descriptors; 92 dma_addr_t descriptors_bus; 93 void *pointer; 94 unsigned int last_buffer_index; 95 u32 regs; 96 struct tasklet_struct tasklet; 97 }; 98 99 struct context; 100 101 typedef int (*descriptor_callback_t)(struct context *ctx, 102 struct descriptor *d, 103 struct descriptor *last); 104 105 /* 106 * A buffer that contains a block of DMA-able coherent memory used for 107 * storing a portion of a DMA descriptor program. 108 */ 109 struct descriptor_buffer { 110 struct list_head list; 111 dma_addr_t buffer_bus; 112 size_t buffer_size; 113 size_t used; 114 struct descriptor buffer[]; 115 }; 116 117 struct context { 118 struct fw_ohci *ohci; 119 u32 regs; 120 int total_allocation; 121 u32 current_bus; 122 bool running; 123 bool flushing; 124 125 /* 126 * List of page-sized buffers for storing DMA descriptors. 127 * Head of list contains buffers in use and tail of list contains 128 * free buffers. 129 */ 130 struct list_head buffer_list; 131 132 /* 133 * Pointer to a buffer inside buffer_list that contains the tail 134 * end of the current DMA program. 135 */ 136 struct descriptor_buffer *buffer_tail; 137 138 /* 139 * The descriptor containing the branch address of the first 140 * descriptor that has not yet been filled by the device. 141 */ 142 struct descriptor *last; 143 144 /* 145 * The last descriptor block in the DMA program. It contains the branch 146 * address that must be updated upon appending a new descriptor. 147 */ 148 struct descriptor *prev; 149 int prev_z; 150 151 descriptor_callback_t callback; 152 153 struct tasklet_struct tasklet; 154 }; 155 156 #define IT_HEADER_SY(v) ((v) << 0) 157 #define IT_HEADER_TCODE(v) ((v) << 4) 158 #define IT_HEADER_CHANNEL(v) ((v) << 8) 159 #define IT_HEADER_TAG(v) ((v) << 14) 160 #define IT_HEADER_SPEED(v) ((v) << 16) 161 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16) 162 163 struct iso_context { 164 struct fw_iso_context base; 165 struct context context; 166 void *header; 167 size_t header_length; 168 unsigned long flushing_completions; 169 u32 mc_buffer_bus; 170 u16 mc_completed; 171 u16 last_timestamp; 172 u8 sync; 173 u8 tags; 174 }; 175 176 #define CONFIG_ROM_SIZE 1024 177 178 struct fw_ohci { 179 struct fw_card card; 180 181 __iomem char *registers; 182 int node_id; 183 int generation; 184 int request_generation; /* for timestamping incoming requests */ 185 unsigned quirks; 186 unsigned int pri_req_max; 187 u32 bus_time; 188 bool bus_time_running; 189 bool is_root; 190 bool csr_state_setclear_abdicate; 191 int n_ir; 192 int n_it; 193 /* 194 * Spinlock for accessing fw_ohci data. Never call out of 195 * this driver with this lock held. 196 */ 197 spinlock_t lock; 198 199 struct mutex phy_reg_mutex; 200 201 void *misc_buffer; 202 dma_addr_t misc_buffer_bus; 203 204 struct ar_context ar_request_ctx; 205 struct ar_context ar_response_ctx; 206 struct context at_request_ctx; 207 struct context at_response_ctx; 208 209 u32 it_context_support; 210 u32 it_context_mask; /* unoccupied IT contexts */ 211 struct iso_context *it_context_list; 212 u64 ir_context_channels; /* unoccupied channels */ 213 u32 ir_context_support; 214 u32 ir_context_mask; /* unoccupied IR contexts */ 215 struct iso_context *ir_context_list; 216 u64 mc_channels; /* channels in use by the multichannel IR context */ 217 bool mc_allocated; 218 219 __be32 *config_rom; 220 dma_addr_t config_rom_bus; 221 __be32 *next_config_rom; 222 dma_addr_t next_config_rom_bus; 223 __be32 next_header; 224 225 __le32 *self_id; 226 dma_addr_t self_id_bus; 227 struct work_struct bus_reset_work; 228 229 u32 self_id_buffer[512]; 230 }; 231 232 static struct workqueue_struct *selfid_workqueue; 233 fw_ohci(struct fw_card * card)234 static inline struct fw_ohci *fw_ohci(struct fw_card *card) 235 { 236 return container_of(card, struct fw_ohci, card); 237 } 238 239 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 240 #define IR_CONTEXT_BUFFER_FILL 0x80000000 241 #define IR_CONTEXT_ISOCH_HEADER 0x40000000 242 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 243 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 244 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 245 246 #define CONTEXT_RUN 0x8000 247 #define CONTEXT_WAKE 0x1000 248 #define CONTEXT_DEAD 0x0800 249 #define CONTEXT_ACTIVE 0x0400 250 251 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf 252 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 253 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 254 255 #define OHCI1394_REGISTER_SIZE 0x800 256 #define OHCI1394_PCI_HCI_Control 0x40 257 #define SELF_ID_BUF_SIZE 0x800 258 #define OHCI_TCODE_PHY_PACKET 0x0e 259 #define OHCI_VERSION_1_1 0x010010 260 261 static char ohci_driver_name[] = KBUILD_MODNAME; 262 263 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd 264 #define PCI_DEVICE_ID_AGERE_FW643 0x5901 265 #define PCI_DEVICE_ID_CREATIVE_SB1394 0x4001 266 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380 267 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009 268 #define PCI_DEVICE_ID_TI_TSB12LV26 0x8020 269 #define PCI_DEVICE_ID_TI_TSB82AA2 0x8025 270 #define PCI_DEVICE_ID_VIA_VT630X 0x3044 271 #define PCI_REV_ID_VIA_VT6306 0x46 272 #define PCI_DEVICE_ID_VIA_VT6315 0x3403 273 274 #define QUIRK_CYCLE_TIMER 0x1 275 #define QUIRK_RESET_PACKET 0x2 276 #define QUIRK_BE_HEADERS 0x4 277 #define QUIRK_NO_1394A 0x8 278 #define QUIRK_NO_MSI 0x10 279 #define QUIRK_TI_SLLZ059 0x20 280 #define QUIRK_IR_WAKE 0x40 281 282 // On PCI Express Root Complex in any type of AMD Ryzen machine, VIA VT6306/6307/6308 with Asmedia 283 // ASM1083/1085 brings an inconvenience that the read accesses to 'Isochronous Cycle Timer' register 284 // (at offset 0xf0 in PCI I/O space) often causes unexpected system reboot. The mechanism is not 285 // clear, since the read access to the other registers is enough safe; e.g. 'Node ID' register, 286 // while it is probable due to detection of any type of PCIe error. 287 #define QUIRK_REBOOT_BY_CYCLE_TIMER_READ 0x80000000 288 289 #if IS_ENABLED(CONFIG_X86) 290 has_reboot_by_cycle_timer_read_quirk(const struct fw_ohci * ohci)291 static bool has_reboot_by_cycle_timer_read_quirk(const struct fw_ohci *ohci) 292 { 293 return !!(ohci->quirks & QUIRK_REBOOT_BY_CYCLE_TIMER_READ); 294 } 295 296 #define PCI_DEVICE_ID_ASMEDIA_ASM108X 0x1080 297 detect_vt630x_with_asm1083_on_amd_ryzen_machine(const struct pci_dev * pdev)298 static bool detect_vt630x_with_asm1083_on_amd_ryzen_machine(const struct pci_dev *pdev) 299 { 300 const struct pci_dev *pcie_to_pci_bridge; 301 302 // Detect any type of AMD Ryzen machine. 303 if (!static_cpu_has(X86_FEATURE_ZEN)) 304 return false; 305 306 // Detect VIA VT6306/6307/6308. 307 if (pdev->vendor != PCI_VENDOR_ID_VIA) 308 return false; 309 if (pdev->device != PCI_DEVICE_ID_VIA_VT630X) 310 return false; 311 312 // Detect Asmedia ASM1083/1085. 313 pcie_to_pci_bridge = pdev->bus->self; 314 if (pcie_to_pci_bridge->vendor != PCI_VENDOR_ID_ASMEDIA) 315 return false; 316 if (pcie_to_pci_bridge->device != PCI_DEVICE_ID_ASMEDIA_ASM108X) 317 return false; 318 319 return true; 320 } 321 322 #else 323 #define has_reboot_by_cycle_timer_read_quirk(ohci) false 324 #define detect_vt630x_with_asm1083_on_amd_ryzen_machine(pdev) false 325 #endif 326 327 /* In case of multiple matches in ohci_quirks[], only the first one is used. */ 328 static const struct { 329 unsigned short vendor, device, revision, flags; 330 } ohci_quirks[] = { 331 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID, 332 QUIRK_CYCLE_TIMER}, 333 334 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID, 335 QUIRK_BE_HEADERS}, 336 337 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6, 338 QUIRK_NO_MSI}, 339 340 {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID, 341 QUIRK_RESET_PACKET}, 342 343 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID, 344 QUIRK_NO_MSI}, 345 346 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID, 347 QUIRK_CYCLE_TIMER}, 348 349 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID, 350 QUIRK_NO_MSI}, 351 352 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID, 353 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, 354 355 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID, 356 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A}, 357 358 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID, 359 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059}, 360 361 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID, 362 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059}, 363 364 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID, 365 QUIRK_RESET_PACKET}, 366 367 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306, 368 QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE}, 369 370 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, 0, 371 QUIRK_CYCLE_TIMER /* FIXME: necessary? */ | QUIRK_NO_MSI}, 372 373 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, PCI_ANY_ID, 374 QUIRK_NO_MSI}, 375 376 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID, 377 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, 378 }; 379 380 /* This overrides anything that was found in ohci_quirks[]. */ 381 static int param_quirks; 382 module_param_named(quirks, param_quirks, int, 0644); 383 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0" 384 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER) 385 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET) 386 ", AR/selfID endianness = " __stringify(QUIRK_BE_HEADERS) 387 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A) 388 ", disable MSI = " __stringify(QUIRK_NO_MSI) 389 ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059) 390 ", IR wake unreliable = " __stringify(QUIRK_IR_WAKE) 391 ")"); 392 393 #define OHCI_PARAM_DEBUG_AT_AR 1 394 #define OHCI_PARAM_DEBUG_SELFIDS 2 395 #define OHCI_PARAM_DEBUG_IRQS 4 396 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */ 397 398 static int param_debug; 399 module_param_named(debug, param_debug, int, 0644); 400 MODULE_PARM_DESC(debug, "Verbose logging (default = 0" 401 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR) 402 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS) 403 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS) 404 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS) 405 ", or a combination, or all = -1)"); 406 407 static bool param_remote_dma; 408 module_param_named(remote_dma, param_remote_dma, bool, 0444); 409 MODULE_PARM_DESC(remote_dma, "Enable unfiltered remote DMA (default = N)"); 410 log_irqs(struct fw_ohci * ohci,u32 evt)411 static void log_irqs(struct fw_ohci *ohci, u32 evt) 412 { 413 if (likely(!(param_debug & 414 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS)))) 415 return; 416 417 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) && 418 !(evt & OHCI1394_busReset)) 419 return; 420 421 ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt, 422 evt & OHCI1394_selfIDComplete ? " selfID" : "", 423 evt & OHCI1394_RQPkt ? " AR_req" : "", 424 evt & OHCI1394_RSPkt ? " AR_resp" : "", 425 evt & OHCI1394_reqTxComplete ? " AT_req" : "", 426 evt & OHCI1394_respTxComplete ? " AT_resp" : "", 427 evt & OHCI1394_isochRx ? " IR" : "", 428 evt & OHCI1394_isochTx ? " IT" : "", 429 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", 430 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", 431 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "", 432 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "", 433 evt & OHCI1394_regAccessFail ? " regAccessFail" : "", 434 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "", 435 evt & OHCI1394_busReset ? " busReset" : "", 436 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | 437 OHCI1394_RSPkt | OHCI1394_reqTxComplete | 438 OHCI1394_respTxComplete | OHCI1394_isochRx | 439 OHCI1394_isochTx | OHCI1394_postedWriteErr | 440 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds | 441 OHCI1394_cycleInconsistent | 442 OHCI1394_regAccessFail | OHCI1394_busReset) 443 ? " ?" : ""); 444 } 445 446 static const char *speed[] = { 447 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta", 448 }; 449 static const char *power[] = { 450 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W", 451 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W", 452 }; 453 static const char port[] = { '.', '-', 'p', 'c', }; 454 _p(u32 * s,int shift)455 static char _p(u32 *s, int shift) 456 { 457 return port[*s >> shift & 3]; 458 } 459 log_selfids(struct fw_ohci * ohci,int generation,int self_id_count)460 static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count) 461 { 462 u32 *s; 463 464 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) 465 return; 466 467 ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n", 468 self_id_count, generation, ohci->node_id); 469 470 for (s = ohci->self_id_buffer; self_id_count--; ++s) 471 if ((*s & 1 << 23) == 0) 472 ohci_notice(ohci, 473 "selfID 0: %08x, phy %d [%c%c%c] %s gc=%d %s %s%s%s\n", 474 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2), 475 speed[*s >> 14 & 3], *s >> 16 & 63, 476 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", 477 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); 478 else 479 ohci_notice(ohci, 480 "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n", 481 *s, *s >> 24 & 63, 482 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10), 483 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2)); 484 } 485 486 static const char *evts[] = { 487 [0x00] = "evt_no_status", [0x01] = "-reserved-", 488 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack", 489 [0x04] = "evt_underrun", [0x05] = "evt_overrun", 490 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read", 491 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset", 492 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err", 493 [0x0c] = "-reserved-", [0x0d] = "-reserved-", 494 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed", 495 [0x10] = "-reserved-", [0x11] = "ack_complete", 496 [0x12] = "ack_pending ", [0x13] = "-reserved-", 497 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A", 498 [0x16] = "ack_busy_B", [0x17] = "-reserved-", 499 [0x18] = "-reserved-", [0x19] = "-reserved-", 500 [0x1a] = "-reserved-", [0x1b] = "ack_tardy", 501 [0x1c] = "-reserved-", [0x1d] = "ack_data_error", 502 [0x1e] = "ack_type_error", [0x1f] = "-reserved-", 503 [0x20] = "pending/cancelled", 504 }; 505 static const char *tcodes[] = { 506 [0x0] = "QW req", [0x1] = "BW req", 507 [0x2] = "W resp", [0x3] = "-reserved-", 508 [0x4] = "QR req", [0x5] = "BR req", 509 [0x6] = "QR resp", [0x7] = "BR resp", 510 [0x8] = "cycle start", [0x9] = "Lk req", 511 [0xa] = "async stream packet", [0xb] = "Lk resp", 512 [0xc] = "-reserved-", [0xd] = "-reserved-", 513 [0xe] = "link internal", [0xf] = "-reserved-", 514 }; 515 log_ar_at_event(struct fw_ohci * ohci,char dir,int speed,u32 * header,int evt)516 static void log_ar_at_event(struct fw_ohci *ohci, 517 char dir, int speed, u32 *header, int evt) 518 { 519 int tcode = header[0] >> 4 & 0xf; 520 char specific[12]; 521 522 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR))) 523 return; 524 525 if (unlikely(evt >= ARRAY_SIZE(evts))) 526 evt = 0x1f; 527 528 if (evt == OHCI1394_evt_bus_reset) { 529 ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n", 530 dir, (header[2] >> 16) & 0xff); 531 return; 532 } 533 534 switch (tcode) { 535 case 0x0: case 0x6: case 0x8: 536 snprintf(specific, sizeof(specific), " = %08x", 537 be32_to_cpu((__force __be32)header[3])); 538 break; 539 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb: 540 snprintf(specific, sizeof(specific), " %x,%x", 541 header[3] >> 16, header[3] & 0xffff); 542 break; 543 default: 544 specific[0] = '\0'; 545 } 546 547 switch (tcode) { 548 case 0xa: 549 ohci_notice(ohci, "A%c %s, %s\n", 550 dir, evts[evt], tcodes[tcode]); 551 break; 552 case 0xe: 553 ohci_notice(ohci, "A%c %s, PHY %08x %08x\n", 554 dir, evts[evt], header[1], header[2]); 555 break; 556 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9: 557 ohci_notice(ohci, 558 "A%c spd %x tl %02x, %04x -> %04x, %s, %s, %04x%08x%s\n", 559 dir, speed, header[0] >> 10 & 0x3f, 560 header[1] >> 16, header[0] >> 16, evts[evt], 561 tcodes[tcode], header[1] & 0xffff, header[2], specific); 562 break; 563 default: 564 ohci_notice(ohci, 565 "A%c spd %x tl %02x, %04x -> %04x, %s, %s%s\n", 566 dir, speed, header[0] >> 10 & 0x3f, 567 header[1] >> 16, header[0] >> 16, evts[evt], 568 tcodes[tcode], specific); 569 } 570 } 571 reg_write(const struct fw_ohci * ohci,int offset,u32 data)572 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) 573 { 574 writel(data, ohci->registers + offset); 575 } 576 reg_read(const struct fw_ohci * ohci,int offset)577 static inline u32 reg_read(const struct fw_ohci *ohci, int offset) 578 { 579 return readl(ohci->registers + offset); 580 } 581 flush_writes(const struct fw_ohci * ohci)582 static inline void flush_writes(const struct fw_ohci *ohci) 583 { 584 /* Do a dummy read to flush writes. */ 585 reg_read(ohci, OHCI1394_Version); 586 } 587 588 /* 589 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and 590 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex. 591 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg() 592 * directly. Exceptions are intrinsically serialized contexts like pci_probe. 593 */ read_phy_reg(struct fw_ohci * ohci,int addr)594 static int read_phy_reg(struct fw_ohci *ohci, int addr) 595 { 596 u32 val; 597 int i; 598 599 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); 600 for (i = 0; i < 3 + 100; i++) { 601 val = reg_read(ohci, OHCI1394_PhyControl); 602 if (!~val) 603 return -ENODEV; /* Card was ejected. */ 604 605 if (val & OHCI1394_PhyControl_ReadDone) 606 return OHCI1394_PhyControl_ReadData(val); 607 608 /* 609 * Try a few times without waiting. Sleeping is necessary 610 * only when the link/PHY interface is busy. 611 */ 612 if (i >= 3) 613 msleep(1); 614 } 615 ohci_err(ohci, "failed to read phy reg %d\n", addr); 616 dump_stack(); 617 618 return -EBUSY; 619 } 620 write_phy_reg(const struct fw_ohci * ohci,int addr,u32 val)621 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val) 622 { 623 int i; 624 625 reg_write(ohci, OHCI1394_PhyControl, 626 OHCI1394_PhyControl_Write(addr, val)); 627 for (i = 0; i < 3 + 100; i++) { 628 val = reg_read(ohci, OHCI1394_PhyControl); 629 if (!~val) 630 return -ENODEV; /* Card was ejected. */ 631 632 if (!(val & OHCI1394_PhyControl_WritePending)) 633 return 0; 634 635 if (i >= 3) 636 msleep(1); 637 } 638 ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val); 639 dump_stack(); 640 641 return -EBUSY; 642 } 643 update_phy_reg(struct fw_ohci * ohci,int addr,int clear_bits,int set_bits)644 static int update_phy_reg(struct fw_ohci *ohci, int addr, 645 int clear_bits, int set_bits) 646 { 647 int ret = read_phy_reg(ohci, addr); 648 if (ret < 0) 649 return ret; 650 651 /* 652 * The interrupt status bits are cleared by writing a one bit. 653 * Avoid clearing them unless explicitly requested in set_bits. 654 */ 655 if (addr == 5) 656 clear_bits |= PHY_INT_STATUS_BITS; 657 658 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits); 659 } 660 read_paged_phy_reg(struct fw_ohci * ohci,int page,int addr)661 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr) 662 { 663 int ret; 664 665 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5); 666 if (ret < 0) 667 return ret; 668 669 return read_phy_reg(ohci, addr); 670 } 671 ohci_read_phy_reg(struct fw_card * card,int addr)672 static int ohci_read_phy_reg(struct fw_card *card, int addr) 673 { 674 struct fw_ohci *ohci = fw_ohci(card); 675 int ret; 676 677 mutex_lock(&ohci->phy_reg_mutex); 678 ret = read_phy_reg(ohci, addr); 679 mutex_unlock(&ohci->phy_reg_mutex); 680 681 return ret; 682 } 683 ohci_update_phy_reg(struct fw_card * card,int addr,int clear_bits,int set_bits)684 static int ohci_update_phy_reg(struct fw_card *card, int addr, 685 int clear_bits, int set_bits) 686 { 687 struct fw_ohci *ohci = fw_ohci(card); 688 int ret; 689 690 mutex_lock(&ohci->phy_reg_mutex); 691 ret = update_phy_reg(ohci, addr, clear_bits, set_bits); 692 mutex_unlock(&ohci->phy_reg_mutex); 693 694 return ret; 695 } 696 ar_buffer_bus(struct ar_context * ctx,unsigned int i)697 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i) 698 { 699 return page_private(ctx->pages[i]); 700 } 701 ar_context_link_page(struct ar_context * ctx,unsigned int index)702 static void ar_context_link_page(struct ar_context *ctx, unsigned int index) 703 { 704 struct descriptor *d; 705 706 d = &ctx->descriptors[index]; 707 d->branch_address &= cpu_to_le32(~0xf); 708 d->res_count = cpu_to_le16(PAGE_SIZE); 709 d->transfer_status = 0; 710 711 wmb(); /* finish init of new descriptors before branch_address update */ 712 d = &ctx->descriptors[ctx->last_buffer_index]; 713 d->branch_address |= cpu_to_le32(1); 714 715 ctx->last_buffer_index = index; 716 717 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 718 } 719 ar_context_release(struct ar_context * ctx)720 static void ar_context_release(struct ar_context *ctx) 721 { 722 struct device *dev = ctx->ohci->card.device; 723 unsigned int i; 724 725 if (!ctx->buffer) 726 return; 727 728 vunmap(ctx->buffer); 729 730 for (i = 0; i < AR_BUFFERS; i++) { 731 if (ctx->pages[i]) 732 dma_free_pages(dev, PAGE_SIZE, ctx->pages[i], 733 ar_buffer_bus(ctx, i), DMA_FROM_DEVICE); 734 } 735 } 736 ar_context_abort(struct ar_context * ctx,const char * error_msg)737 static void ar_context_abort(struct ar_context *ctx, const char *error_msg) 738 { 739 struct fw_ohci *ohci = ctx->ohci; 740 741 if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) { 742 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 743 flush_writes(ohci); 744 745 ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg); 746 } 747 /* FIXME: restart? */ 748 } 749 ar_next_buffer_index(unsigned int index)750 static inline unsigned int ar_next_buffer_index(unsigned int index) 751 { 752 return (index + 1) % AR_BUFFERS; 753 } 754 ar_first_buffer_index(struct ar_context * ctx)755 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx) 756 { 757 return ar_next_buffer_index(ctx->last_buffer_index); 758 } 759 760 /* 761 * We search for the buffer that contains the last AR packet DMA data written 762 * by the controller. 763 */ ar_search_last_active_buffer(struct ar_context * ctx,unsigned int * buffer_offset)764 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx, 765 unsigned int *buffer_offset) 766 { 767 unsigned int i, next_i, last = ctx->last_buffer_index; 768 __le16 res_count, next_res_count; 769 770 i = ar_first_buffer_index(ctx); 771 res_count = READ_ONCE(ctx->descriptors[i].res_count); 772 773 /* A buffer that is not yet completely filled must be the last one. */ 774 while (i != last && res_count == 0) { 775 776 /* Peek at the next descriptor. */ 777 next_i = ar_next_buffer_index(i); 778 rmb(); /* read descriptors in order */ 779 next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count); 780 /* 781 * If the next descriptor is still empty, we must stop at this 782 * descriptor. 783 */ 784 if (next_res_count == cpu_to_le16(PAGE_SIZE)) { 785 /* 786 * The exception is when the DMA data for one packet is 787 * split over three buffers; in this case, the middle 788 * buffer's descriptor might be never updated by the 789 * controller and look still empty, and we have to peek 790 * at the third one. 791 */ 792 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) { 793 next_i = ar_next_buffer_index(next_i); 794 rmb(); 795 next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count); 796 if (next_res_count != cpu_to_le16(PAGE_SIZE)) 797 goto next_buffer_is_active; 798 } 799 800 break; 801 } 802 803 next_buffer_is_active: 804 i = next_i; 805 res_count = next_res_count; 806 } 807 808 rmb(); /* read res_count before the DMA data */ 809 810 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count); 811 if (*buffer_offset > PAGE_SIZE) { 812 *buffer_offset = 0; 813 ar_context_abort(ctx, "corrupted descriptor"); 814 } 815 816 return i; 817 } 818 ar_sync_buffers_for_cpu(struct ar_context * ctx,unsigned int end_buffer_index,unsigned int end_buffer_offset)819 static void ar_sync_buffers_for_cpu(struct ar_context *ctx, 820 unsigned int end_buffer_index, 821 unsigned int end_buffer_offset) 822 { 823 unsigned int i; 824 825 i = ar_first_buffer_index(ctx); 826 while (i != end_buffer_index) { 827 dma_sync_single_for_cpu(ctx->ohci->card.device, 828 ar_buffer_bus(ctx, i), 829 PAGE_SIZE, DMA_FROM_DEVICE); 830 i = ar_next_buffer_index(i); 831 } 832 if (end_buffer_offset > 0) 833 dma_sync_single_for_cpu(ctx->ohci->card.device, 834 ar_buffer_bus(ctx, i), 835 end_buffer_offset, DMA_FROM_DEVICE); 836 } 837 838 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) 839 #define cond_le32_to_cpu(v) \ 840 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v)) 841 #else 842 #define cond_le32_to_cpu(v) le32_to_cpu(v) 843 #endif 844 handle_ar_packet(struct ar_context * ctx,__le32 * buffer)845 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) 846 { 847 struct fw_ohci *ohci = ctx->ohci; 848 struct fw_packet p; 849 u32 status, length, tcode; 850 int evt; 851 852 p.header[0] = cond_le32_to_cpu(buffer[0]); 853 p.header[1] = cond_le32_to_cpu(buffer[1]); 854 p.header[2] = cond_le32_to_cpu(buffer[2]); 855 856 tcode = (p.header[0] >> 4) & 0x0f; 857 switch (tcode) { 858 case TCODE_WRITE_QUADLET_REQUEST: 859 case TCODE_READ_QUADLET_RESPONSE: 860 p.header[3] = (__force __u32) buffer[3]; 861 p.header_length = 16; 862 p.payload_length = 0; 863 break; 864 865 case TCODE_READ_BLOCK_REQUEST : 866 p.header[3] = cond_le32_to_cpu(buffer[3]); 867 p.header_length = 16; 868 p.payload_length = 0; 869 break; 870 871 case TCODE_WRITE_BLOCK_REQUEST: 872 case TCODE_READ_BLOCK_RESPONSE: 873 case TCODE_LOCK_REQUEST: 874 case TCODE_LOCK_RESPONSE: 875 p.header[3] = cond_le32_to_cpu(buffer[3]); 876 p.header_length = 16; 877 p.payload_length = p.header[3] >> 16; 878 if (p.payload_length > MAX_ASYNC_PAYLOAD) { 879 ar_context_abort(ctx, "invalid packet length"); 880 return NULL; 881 } 882 break; 883 884 case TCODE_WRITE_RESPONSE: 885 case TCODE_READ_QUADLET_REQUEST: 886 case OHCI_TCODE_PHY_PACKET: 887 p.header_length = 12; 888 p.payload_length = 0; 889 break; 890 891 default: 892 ar_context_abort(ctx, "invalid tcode"); 893 return NULL; 894 } 895 896 p.payload = (void *) buffer + p.header_length; 897 898 /* FIXME: What to do about evt_* errors? */ 899 length = (p.header_length + p.payload_length + 3) / 4; 900 status = cond_le32_to_cpu(buffer[length]); 901 evt = (status >> 16) & 0x1f; 902 903 p.ack = evt - 16; 904 p.speed = (status >> 21) & 0x7; 905 p.timestamp = status & 0xffff; 906 p.generation = ohci->request_generation; 907 908 log_ar_at_event(ohci, 'R', p.speed, p.header, evt); 909 910 /* 911 * Several controllers, notably from NEC and VIA, forget to 912 * write ack_complete status at PHY packet reception. 913 */ 914 if (evt == OHCI1394_evt_no_status && 915 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4)) 916 p.ack = ACK_COMPLETE; 917 918 /* 919 * The OHCI bus reset handler synthesizes a PHY packet with 920 * the new generation number when a bus reset happens (see 921 * section 8.4.2.3). This helps us determine when a request 922 * was received and make sure we send the response in the same 923 * generation. We only need this for requests; for responses 924 * we use the unique tlabel for finding the matching 925 * request. 926 * 927 * Alas some chips sometimes emit bus reset packets with a 928 * wrong generation. We set the correct generation for these 929 * at a slightly incorrect time (in bus_reset_work). 930 */ 931 if (evt == OHCI1394_evt_bus_reset) { 932 if (!(ohci->quirks & QUIRK_RESET_PACKET)) 933 ohci->request_generation = (p.header[2] >> 16) & 0xff; 934 } else if (ctx == &ohci->ar_request_ctx) { 935 fw_core_handle_request(&ohci->card, &p); 936 } else { 937 fw_core_handle_response(&ohci->card, &p); 938 } 939 940 return buffer + length + 1; 941 } 942 handle_ar_packets(struct ar_context * ctx,void * p,void * end)943 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end) 944 { 945 void *next; 946 947 while (p < end) { 948 next = handle_ar_packet(ctx, p); 949 if (!next) 950 return p; 951 p = next; 952 } 953 954 return p; 955 } 956 ar_recycle_buffers(struct ar_context * ctx,unsigned int end_buffer)957 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer) 958 { 959 unsigned int i; 960 961 i = ar_first_buffer_index(ctx); 962 while (i != end_buffer) { 963 dma_sync_single_for_device(ctx->ohci->card.device, 964 ar_buffer_bus(ctx, i), 965 PAGE_SIZE, DMA_FROM_DEVICE); 966 ar_context_link_page(ctx, i); 967 i = ar_next_buffer_index(i); 968 } 969 } 970 ar_context_tasklet(unsigned long data)971 static void ar_context_tasklet(unsigned long data) 972 { 973 struct ar_context *ctx = (struct ar_context *)data; 974 unsigned int end_buffer_index, end_buffer_offset; 975 void *p, *end; 976 977 p = ctx->pointer; 978 if (!p) 979 return; 980 981 end_buffer_index = ar_search_last_active_buffer(ctx, 982 &end_buffer_offset); 983 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset); 984 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset; 985 986 if (end_buffer_index < ar_first_buffer_index(ctx)) { 987 /* 988 * The filled part of the overall buffer wraps around; handle 989 * all packets up to the buffer end here. If the last packet 990 * wraps around, its tail will be visible after the buffer end 991 * because the buffer start pages are mapped there again. 992 */ 993 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE; 994 p = handle_ar_packets(ctx, p, buffer_end); 995 if (p < buffer_end) 996 goto error; 997 /* adjust p to point back into the actual buffer */ 998 p -= AR_BUFFERS * PAGE_SIZE; 999 } 1000 1001 p = handle_ar_packets(ctx, p, end); 1002 if (p != end) { 1003 if (p > end) 1004 ar_context_abort(ctx, "inconsistent descriptor"); 1005 goto error; 1006 } 1007 1008 ctx->pointer = p; 1009 ar_recycle_buffers(ctx, end_buffer_index); 1010 1011 return; 1012 1013 error: 1014 ctx->pointer = NULL; 1015 } 1016 ar_context_init(struct ar_context * ctx,struct fw_ohci * ohci,unsigned int descriptors_offset,u32 regs)1017 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, 1018 unsigned int descriptors_offset, u32 regs) 1019 { 1020 struct device *dev = ohci->card.device; 1021 unsigned int i; 1022 dma_addr_t dma_addr; 1023 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES]; 1024 struct descriptor *d; 1025 1026 ctx->regs = regs; 1027 ctx->ohci = ohci; 1028 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); 1029 1030 for (i = 0; i < AR_BUFFERS; i++) { 1031 ctx->pages[i] = dma_alloc_pages(dev, PAGE_SIZE, &dma_addr, 1032 DMA_FROM_DEVICE, GFP_KERNEL); 1033 if (!ctx->pages[i]) 1034 goto out_of_memory; 1035 set_page_private(ctx->pages[i], dma_addr); 1036 dma_sync_single_for_device(dev, dma_addr, PAGE_SIZE, 1037 DMA_FROM_DEVICE); 1038 } 1039 1040 for (i = 0; i < AR_BUFFERS; i++) 1041 pages[i] = ctx->pages[i]; 1042 for (i = 0; i < AR_WRAPAROUND_PAGES; i++) 1043 pages[AR_BUFFERS + i] = ctx->pages[i]; 1044 ctx->buffer = vmap(pages, ARRAY_SIZE(pages), VM_MAP, PAGE_KERNEL); 1045 if (!ctx->buffer) 1046 goto out_of_memory; 1047 1048 ctx->descriptors = ohci->misc_buffer + descriptors_offset; 1049 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset; 1050 1051 for (i = 0; i < AR_BUFFERS; i++) { 1052 d = &ctx->descriptors[i]; 1053 d->req_count = cpu_to_le16(PAGE_SIZE); 1054 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 1055 DESCRIPTOR_STATUS | 1056 DESCRIPTOR_BRANCH_ALWAYS); 1057 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i)); 1058 d->branch_address = cpu_to_le32(ctx->descriptors_bus + 1059 ar_next_buffer_index(i) * sizeof(struct descriptor)); 1060 } 1061 1062 return 0; 1063 1064 out_of_memory: 1065 ar_context_release(ctx); 1066 1067 return -ENOMEM; 1068 } 1069 ar_context_run(struct ar_context * ctx)1070 static void ar_context_run(struct ar_context *ctx) 1071 { 1072 unsigned int i; 1073 1074 for (i = 0; i < AR_BUFFERS; i++) 1075 ar_context_link_page(ctx, i); 1076 1077 ctx->pointer = ctx->buffer; 1078 1079 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1); 1080 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); 1081 } 1082 find_branch_descriptor(struct descriptor * d,int z)1083 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z) 1084 { 1085 __le16 branch; 1086 1087 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS); 1088 1089 /* figure out which descriptor the branch address goes in */ 1090 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 1091 return d; 1092 else 1093 return d + z - 1; 1094 } 1095 context_tasklet(unsigned long data)1096 static void context_tasklet(unsigned long data) 1097 { 1098 struct context *ctx = (struct context *) data; 1099 struct descriptor *d, *last; 1100 u32 address; 1101 int z; 1102 struct descriptor_buffer *desc; 1103 1104 desc = list_entry(ctx->buffer_list.next, 1105 struct descriptor_buffer, list); 1106 last = ctx->last; 1107 while (last->branch_address != 0) { 1108 struct descriptor_buffer *old_desc = desc; 1109 address = le32_to_cpu(last->branch_address); 1110 z = address & 0xf; 1111 address &= ~0xf; 1112 ctx->current_bus = address; 1113 1114 /* If the branch address points to a buffer outside of the 1115 * current buffer, advance to the next buffer. */ 1116 if (address < desc->buffer_bus || 1117 address >= desc->buffer_bus + desc->used) 1118 desc = list_entry(desc->list.next, 1119 struct descriptor_buffer, list); 1120 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d); 1121 last = find_branch_descriptor(d, z); 1122 1123 if (!ctx->callback(ctx, d, last)) 1124 break; 1125 1126 if (old_desc != desc) { 1127 /* If we've advanced to the next buffer, move the 1128 * previous buffer to the free list. */ 1129 unsigned long flags; 1130 old_desc->used = 0; 1131 spin_lock_irqsave(&ctx->ohci->lock, flags); 1132 list_move_tail(&old_desc->list, &ctx->buffer_list); 1133 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1134 } 1135 ctx->last = last; 1136 } 1137 } 1138 1139 /* 1140 * Allocate a new buffer and add it to the list of free buffers for this 1141 * context. Must be called with ohci->lock held. 1142 */ context_add_buffer(struct context * ctx)1143 static int context_add_buffer(struct context *ctx) 1144 { 1145 struct descriptor_buffer *desc; 1146 dma_addr_t bus_addr; 1147 int offset; 1148 1149 /* 1150 * 16MB of descriptors should be far more than enough for any DMA 1151 * program. This will catch run-away userspace or DoS attacks. 1152 */ 1153 if (ctx->total_allocation >= 16*1024*1024) 1154 return -ENOMEM; 1155 1156 desc = dmam_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE, &bus_addr, GFP_ATOMIC); 1157 if (!desc) 1158 return -ENOMEM; 1159 1160 offset = (void *)&desc->buffer - (void *)desc; 1161 /* 1162 * Some controllers, like JMicron ones, always issue 0x20-byte DMA reads 1163 * for descriptors, even 0x10-byte ones. This can cause page faults when 1164 * an IOMMU is in use and the oversized read crosses a page boundary. 1165 * Work around this by always leaving at least 0x10 bytes of padding. 1166 */ 1167 desc->buffer_size = PAGE_SIZE - offset - 0x10; 1168 desc->buffer_bus = bus_addr + offset; 1169 desc->used = 0; 1170 1171 list_add_tail(&desc->list, &ctx->buffer_list); 1172 ctx->total_allocation += PAGE_SIZE; 1173 1174 return 0; 1175 } 1176 context_init(struct context * ctx,struct fw_ohci * ohci,u32 regs,descriptor_callback_t callback)1177 static int context_init(struct context *ctx, struct fw_ohci *ohci, 1178 u32 regs, descriptor_callback_t callback) 1179 { 1180 ctx->ohci = ohci; 1181 ctx->regs = regs; 1182 ctx->total_allocation = 0; 1183 1184 INIT_LIST_HEAD(&ctx->buffer_list); 1185 if (context_add_buffer(ctx) < 0) 1186 return -ENOMEM; 1187 1188 ctx->buffer_tail = list_entry(ctx->buffer_list.next, 1189 struct descriptor_buffer, list); 1190 1191 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); 1192 ctx->callback = callback; 1193 1194 /* 1195 * We put a dummy descriptor in the buffer that has a NULL 1196 * branch address and looks like it's been sent. That way we 1197 * have a descriptor to append DMA programs to. 1198 */ 1199 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer)); 1200 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST); 1201 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011); 1202 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer); 1203 ctx->last = ctx->buffer_tail->buffer; 1204 ctx->prev = ctx->buffer_tail->buffer; 1205 ctx->prev_z = 1; 1206 1207 return 0; 1208 } 1209 context_release(struct context * ctx)1210 static void context_release(struct context *ctx) 1211 { 1212 struct fw_card *card = &ctx->ohci->card; 1213 struct descriptor_buffer *desc, *tmp; 1214 1215 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list) { 1216 dmam_free_coherent(card->device, PAGE_SIZE, desc, 1217 desc->buffer_bus - ((void *)&desc->buffer - (void *)desc)); 1218 } 1219 } 1220 1221 /* Must be called with ohci->lock held */ context_get_descriptors(struct context * ctx,int z,dma_addr_t * d_bus)1222 static struct descriptor *context_get_descriptors(struct context *ctx, 1223 int z, dma_addr_t *d_bus) 1224 { 1225 struct descriptor *d = NULL; 1226 struct descriptor_buffer *desc = ctx->buffer_tail; 1227 1228 if (z * sizeof(*d) > desc->buffer_size) 1229 return NULL; 1230 1231 if (z * sizeof(*d) > desc->buffer_size - desc->used) { 1232 /* No room for the descriptor in this buffer, so advance to the 1233 * next one. */ 1234 1235 if (desc->list.next == &ctx->buffer_list) { 1236 /* If there is no free buffer next in the list, 1237 * allocate one. */ 1238 if (context_add_buffer(ctx) < 0) 1239 return NULL; 1240 } 1241 desc = list_entry(desc->list.next, 1242 struct descriptor_buffer, list); 1243 ctx->buffer_tail = desc; 1244 } 1245 1246 d = desc->buffer + desc->used / sizeof(*d); 1247 memset(d, 0, z * sizeof(*d)); 1248 *d_bus = desc->buffer_bus + desc->used; 1249 1250 return d; 1251 } 1252 context_run(struct context * ctx,u32 extra)1253 static void context_run(struct context *ctx, u32 extra) 1254 { 1255 struct fw_ohci *ohci = ctx->ohci; 1256 1257 reg_write(ohci, COMMAND_PTR(ctx->regs), 1258 le32_to_cpu(ctx->last->branch_address)); 1259 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); 1260 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); 1261 ctx->running = true; 1262 flush_writes(ohci); 1263 } 1264 context_append(struct context * ctx,struct descriptor * d,int z,int extra)1265 static void context_append(struct context *ctx, 1266 struct descriptor *d, int z, int extra) 1267 { 1268 dma_addr_t d_bus; 1269 struct descriptor_buffer *desc = ctx->buffer_tail; 1270 struct descriptor *d_branch; 1271 1272 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d); 1273 1274 desc->used += (z + extra) * sizeof(*d); 1275 1276 wmb(); /* finish init of new descriptors before branch_address update */ 1277 1278 d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z); 1279 d_branch->branch_address = cpu_to_le32(d_bus | z); 1280 1281 /* 1282 * VT6306 incorrectly checks only the single descriptor at the 1283 * CommandPtr when the wake bit is written, so if it's a 1284 * multi-descriptor block starting with an INPUT_MORE, put a copy of 1285 * the branch address in the first descriptor. 1286 * 1287 * Not doing this for transmit contexts since not sure how it interacts 1288 * with skip addresses. 1289 */ 1290 if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) && 1291 d_branch != ctx->prev && 1292 (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) == 1293 cpu_to_le16(DESCRIPTOR_INPUT_MORE)) { 1294 ctx->prev->branch_address = cpu_to_le32(d_bus | z); 1295 } 1296 1297 ctx->prev = d; 1298 ctx->prev_z = z; 1299 } 1300 context_stop(struct context * ctx)1301 static void context_stop(struct context *ctx) 1302 { 1303 struct fw_ohci *ohci = ctx->ohci; 1304 u32 reg; 1305 int i; 1306 1307 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 1308 ctx->running = false; 1309 1310 for (i = 0; i < 1000; i++) { 1311 reg = reg_read(ohci, CONTROL_SET(ctx->regs)); 1312 if ((reg & CONTEXT_ACTIVE) == 0) 1313 return; 1314 1315 if (i) 1316 udelay(10); 1317 } 1318 ohci_err(ohci, "DMA context still active (0x%08x)\n", reg); 1319 } 1320 1321 struct driver_data { 1322 u8 inline_data[8]; 1323 struct fw_packet *packet; 1324 }; 1325 1326 /* 1327 * This function apppends a packet to the DMA queue for transmission. 1328 * Must always be called with the ochi->lock held to ensure proper 1329 * generation handling and locking around packet queue manipulation. 1330 */ at_context_queue_packet(struct context * ctx,struct fw_packet * packet)1331 static int at_context_queue_packet(struct context *ctx, 1332 struct fw_packet *packet) 1333 { 1334 struct fw_ohci *ohci = ctx->ohci; 1335 dma_addr_t d_bus, payload_bus; 1336 struct driver_data *driver_data; 1337 struct descriptor *d, *last; 1338 __le32 *header; 1339 int z, tcode; 1340 1341 d = context_get_descriptors(ctx, 4, &d_bus); 1342 if (d == NULL) { 1343 packet->ack = RCODE_SEND_ERROR; 1344 return -1; 1345 } 1346 1347 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 1348 d[0].res_count = cpu_to_le16(packet->timestamp); 1349 1350 /* 1351 * The DMA format for asynchronous link packets is different 1352 * from the IEEE1394 layout, so shift the fields around 1353 * accordingly. 1354 */ 1355 1356 tcode = (packet->header[0] >> 4) & 0x0f; 1357 header = (__le32 *) &d[1]; 1358 switch (tcode) { 1359 case TCODE_WRITE_QUADLET_REQUEST: 1360 case TCODE_WRITE_BLOCK_REQUEST: 1361 case TCODE_WRITE_RESPONSE: 1362 case TCODE_READ_QUADLET_REQUEST: 1363 case TCODE_READ_BLOCK_REQUEST: 1364 case TCODE_READ_QUADLET_RESPONSE: 1365 case TCODE_READ_BLOCK_RESPONSE: 1366 case TCODE_LOCK_REQUEST: 1367 case TCODE_LOCK_RESPONSE: 1368 header[0] = cpu_to_le32((packet->header[0] & 0xffff) | 1369 (packet->speed << 16)); 1370 header[1] = cpu_to_le32((packet->header[1] & 0xffff) | 1371 (packet->header[0] & 0xffff0000)); 1372 header[2] = cpu_to_le32(packet->header[2]); 1373 1374 if (TCODE_IS_BLOCK_PACKET(tcode)) 1375 header[3] = cpu_to_le32(packet->header[3]); 1376 else 1377 header[3] = (__force __le32) packet->header[3]; 1378 1379 d[0].req_count = cpu_to_le16(packet->header_length); 1380 break; 1381 1382 case TCODE_LINK_INTERNAL: 1383 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) | 1384 (packet->speed << 16)); 1385 header[1] = cpu_to_le32(packet->header[1]); 1386 header[2] = cpu_to_le32(packet->header[2]); 1387 d[0].req_count = cpu_to_le16(12); 1388 1389 if (is_ping_packet(&packet->header[1])) 1390 d[0].control |= cpu_to_le16(DESCRIPTOR_PING); 1391 break; 1392 1393 case TCODE_STREAM_DATA: 1394 header[0] = cpu_to_le32((packet->header[0] & 0xffff) | 1395 (packet->speed << 16)); 1396 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000); 1397 d[0].req_count = cpu_to_le16(8); 1398 break; 1399 1400 default: 1401 /* BUG(); */ 1402 packet->ack = RCODE_SEND_ERROR; 1403 return -1; 1404 } 1405 1406 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor)); 1407 driver_data = (struct driver_data *) &d[3]; 1408 driver_data->packet = packet; 1409 packet->driver_data = driver_data; 1410 1411 if (packet->payload_length > 0) { 1412 if (packet->payload_length > sizeof(driver_data->inline_data)) { 1413 payload_bus = dma_map_single(ohci->card.device, 1414 packet->payload, 1415 packet->payload_length, 1416 DMA_TO_DEVICE); 1417 if (dma_mapping_error(ohci->card.device, payload_bus)) { 1418 packet->ack = RCODE_SEND_ERROR; 1419 return -1; 1420 } 1421 packet->payload_bus = payload_bus; 1422 packet->payload_mapped = true; 1423 } else { 1424 memcpy(driver_data->inline_data, packet->payload, 1425 packet->payload_length); 1426 payload_bus = d_bus + 3 * sizeof(*d); 1427 } 1428 1429 d[2].req_count = cpu_to_le16(packet->payload_length); 1430 d[2].data_address = cpu_to_le32(payload_bus); 1431 last = &d[2]; 1432 z = 3; 1433 } else { 1434 last = &d[0]; 1435 z = 2; 1436 } 1437 1438 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 1439 DESCRIPTOR_IRQ_ALWAYS | 1440 DESCRIPTOR_BRANCH_ALWAYS); 1441 1442 /* FIXME: Document how the locking works. */ 1443 if (ohci->generation != packet->generation) { 1444 if (packet->payload_mapped) 1445 dma_unmap_single(ohci->card.device, payload_bus, 1446 packet->payload_length, DMA_TO_DEVICE); 1447 packet->ack = RCODE_GENERATION; 1448 return -1; 1449 } 1450 1451 context_append(ctx, d, z, 4 - z); 1452 1453 if (ctx->running) 1454 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 1455 else 1456 context_run(ctx, 0); 1457 1458 return 0; 1459 } 1460 at_context_flush(struct context * ctx)1461 static void at_context_flush(struct context *ctx) 1462 { 1463 tasklet_disable(&ctx->tasklet); 1464 1465 ctx->flushing = true; 1466 context_tasklet((unsigned long)ctx); 1467 ctx->flushing = false; 1468 1469 tasklet_enable(&ctx->tasklet); 1470 } 1471 handle_at_packet(struct context * context,struct descriptor * d,struct descriptor * last)1472 static int handle_at_packet(struct context *context, 1473 struct descriptor *d, 1474 struct descriptor *last) 1475 { 1476 struct driver_data *driver_data; 1477 struct fw_packet *packet; 1478 struct fw_ohci *ohci = context->ohci; 1479 int evt; 1480 1481 if (last->transfer_status == 0 && !context->flushing) 1482 /* This descriptor isn't done yet, stop iteration. */ 1483 return 0; 1484 1485 driver_data = (struct driver_data *) &d[3]; 1486 packet = driver_data->packet; 1487 if (packet == NULL) 1488 /* This packet was cancelled, just continue. */ 1489 return 1; 1490 1491 if (packet->payload_mapped) 1492 dma_unmap_single(ohci->card.device, packet->payload_bus, 1493 packet->payload_length, DMA_TO_DEVICE); 1494 1495 evt = le16_to_cpu(last->transfer_status) & 0x1f; 1496 packet->timestamp = le16_to_cpu(last->res_count); 1497 1498 log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt); 1499 1500 switch (evt) { 1501 case OHCI1394_evt_timeout: 1502 /* Async response transmit timed out. */ 1503 packet->ack = RCODE_CANCELLED; 1504 break; 1505 1506 case OHCI1394_evt_flushed: 1507 /* 1508 * The packet was flushed should give same error as 1509 * when we try to use a stale generation count. 1510 */ 1511 packet->ack = RCODE_GENERATION; 1512 break; 1513 1514 case OHCI1394_evt_missing_ack: 1515 if (context->flushing) 1516 packet->ack = RCODE_GENERATION; 1517 else { 1518 /* 1519 * Using a valid (current) generation count, but the 1520 * node is not on the bus or not sending acks. 1521 */ 1522 packet->ack = RCODE_NO_ACK; 1523 } 1524 break; 1525 1526 case ACK_COMPLETE + 0x10: 1527 case ACK_PENDING + 0x10: 1528 case ACK_BUSY_X + 0x10: 1529 case ACK_BUSY_A + 0x10: 1530 case ACK_BUSY_B + 0x10: 1531 case ACK_DATA_ERROR + 0x10: 1532 case ACK_TYPE_ERROR + 0x10: 1533 packet->ack = evt - 0x10; 1534 break; 1535 1536 case OHCI1394_evt_no_status: 1537 if (context->flushing) { 1538 packet->ack = RCODE_GENERATION; 1539 break; 1540 } 1541 fallthrough; 1542 1543 default: 1544 packet->ack = RCODE_SEND_ERROR; 1545 break; 1546 } 1547 1548 packet->callback(packet, &ohci->card, packet->ack); 1549 1550 return 1; 1551 } 1552 1553 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff) 1554 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f) 1555 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff) 1556 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff) 1557 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff) 1558 1559 static u32 get_cycle_time(struct fw_ohci *ohci); 1560 handle_local_rom(struct fw_ohci * ohci,struct fw_packet * packet,u32 csr)1561 static void handle_local_rom(struct fw_ohci *ohci, 1562 struct fw_packet *packet, u32 csr) 1563 { 1564 struct fw_packet response; 1565 int tcode, length, i; 1566 1567 tcode = HEADER_GET_TCODE(packet->header[0]); 1568 if (TCODE_IS_BLOCK_PACKET(tcode)) 1569 length = HEADER_GET_DATA_LENGTH(packet->header[3]); 1570 else 1571 length = 4; 1572 1573 i = csr - CSR_CONFIG_ROM; 1574 if (i + length > CONFIG_ROM_SIZE) { 1575 fw_fill_response(&response, packet->header, 1576 RCODE_ADDRESS_ERROR, NULL, 0); 1577 } else if (!TCODE_IS_READ_REQUEST(tcode)) { 1578 fw_fill_response(&response, packet->header, 1579 RCODE_TYPE_ERROR, NULL, 0); 1580 } else { 1581 fw_fill_response(&response, packet->header, RCODE_COMPLETE, 1582 (void *) ohci->config_rom + i, length); 1583 } 1584 1585 // Timestamping on behalf of the hardware. 1586 response.timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); 1587 fw_core_handle_response(&ohci->card, &response); 1588 } 1589 handle_local_lock(struct fw_ohci * ohci,struct fw_packet * packet,u32 csr)1590 static void handle_local_lock(struct fw_ohci *ohci, 1591 struct fw_packet *packet, u32 csr) 1592 { 1593 struct fw_packet response; 1594 int tcode, length, ext_tcode, sel, try; 1595 __be32 *payload, lock_old; 1596 u32 lock_arg, lock_data; 1597 1598 tcode = HEADER_GET_TCODE(packet->header[0]); 1599 length = HEADER_GET_DATA_LENGTH(packet->header[3]); 1600 payload = packet->payload; 1601 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]); 1602 1603 if (tcode == TCODE_LOCK_REQUEST && 1604 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { 1605 lock_arg = be32_to_cpu(payload[0]); 1606 lock_data = be32_to_cpu(payload[1]); 1607 } else if (tcode == TCODE_READ_QUADLET_REQUEST) { 1608 lock_arg = 0; 1609 lock_data = 0; 1610 } else { 1611 fw_fill_response(&response, packet->header, 1612 RCODE_TYPE_ERROR, NULL, 0); 1613 goto out; 1614 } 1615 1616 sel = (csr - CSR_BUS_MANAGER_ID) / 4; 1617 reg_write(ohci, OHCI1394_CSRData, lock_data); 1618 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); 1619 reg_write(ohci, OHCI1394_CSRControl, sel); 1620 1621 for (try = 0; try < 20; try++) 1622 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) { 1623 lock_old = cpu_to_be32(reg_read(ohci, 1624 OHCI1394_CSRData)); 1625 fw_fill_response(&response, packet->header, 1626 RCODE_COMPLETE, 1627 &lock_old, sizeof(lock_old)); 1628 goto out; 1629 } 1630 1631 ohci_err(ohci, "swap not done (CSR lock timeout)\n"); 1632 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0); 1633 1634 out: 1635 // Timestamping on behalf of the hardware. 1636 response.timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); 1637 fw_core_handle_response(&ohci->card, &response); 1638 } 1639 handle_local_request(struct context * ctx,struct fw_packet * packet)1640 static void handle_local_request(struct context *ctx, struct fw_packet *packet) 1641 { 1642 u64 offset, csr; 1643 1644 if (ctx == &ctx->ohci->at_request_ctx) { 1645 packet->ack = ACK_PENDING; 1646 packet->callback(packet, &ctx->ohci->card, packet->ack); 1647 } 1648 1649 offset = 1650 ((unsigned long long) 1651 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) | 1652 packet->header[2]; 1653 csr = offset - CSR_REGISTER_BASE; 1654 1655 /* Handle config rom reads. */ 1656 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) 1657 handle_local_rom(ctx->ohci, packet, csr); 1658 else switch (csr) { 1659 case CSR_BUS_MANAGER_ID: 1660 case CSR_BANDWIDTH_AVAILABLE: 1661 case CSR_CHANNELS_AVAILABLE_HI: 1662 case CSR_CHANNELS_AVAILABLE_LO: 1663 handle_local_lock(ctx->ohci, packet, csr); 1664 break; 1665 default: 1666 if (ctx == &ctx->ohci->at_request_ctx) 1667 fw_core_handle_request(&ctx->ohci->card, packet); 1668 else 1669 fw_core_handle_response(&ctx->ohci->card, packet); 1670 break; 1671 } 1672 1673 if (ctx == &ctx->ohci->at_response_ctx) { 1674 packet->ack = ACK_COMPLETE; 1675 packet->callback(packet, &ctx->ohci->card, packet->ack); 1676 } 1677 } 1678 at_context_transmit(struct context * ctx,struct fw_packet * packet)1679 static void at_context_transmit(struct context *ctx, struct fw_packet *packet) 1680 { 1681 unsigned long flags; 1682 int ret; 1683 1684 spin_lock_irqsave(&ctx->ohci->lock, flags); 1685 1686 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id && 1687 ctx->ohci->generation == packet->generation) { 1688 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1689 1690 // Timestamping on behalf of the hardware. 1691 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ctx->ohci)); 1692 1693 handle_local_request(ctx, packet); 1694 return; 1695 } 1696 1697 ret = at_context_queue_packet(ctx, packet); 1698 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1699 1700 if (ret < 0) { 1701 // Timestamping on behalf of the hardware. 1702 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ctx->ohci)); 1703 1704 packet->callback(packet, &ctx->ohci->card, packet->ack); 1705 } 1706 } 1707 detect_dead_context(struct fw_ohci * ohci,const char * name,unsigned int regs)1708 static void detect_dead_context(struct fw_ohci *ohci, 1709 const char *name, unsigned int regs) 1710 { 1711 u32 ctl; 1712 1713 ctl = reg_read(ohci, CONTROL_SET(regs)); 1714 if (ctl & CONTEXT_DEAD) 1715 ohci_err(ohci, "DMA context %s has stopped, error code: %s\n", 1716 name, evts[ctl & 0x1f]); 1717 } 1718 handle_dead_contexts(struct fw_ohci * ohci)1719 static void handle_dead_contexts(struct fw_ohci *ohci) 1720 { 1721 unsigned int i; 1722 char name[8]; 1723 1724 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase); 1725 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase); 1726 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase); 1727 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase); 1728 for (i = 0; i < 32; ++i) { 1729 if (!(ohci->it_context_support & (1 << i))) 1730 continue; 1731 sprintf(name, "IT%u", i); 1732 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i)); 1733 } 1734 for (i = 0; i < 32; ++i) { 1735 if (!(ohci->ir_context_support & (1 << i))) 1736 continue; 1737 sprintf(name, "IR%u", i); 1738 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i)); 1739 } 1740 /* TODO: maybe try to flush and restart the dead contexts */ 1741 } 1742 cycle_timer_ticks(u32 cycle_timer)1743 static u32 cycle_timer_ticks(u32 cycle_timer) 1744 { 1745 u32 ticks; 1746 1747 ticks = cycle_timer & 0xfff; 1748 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff); 1749 ticks += (3072 * 8000) * (cycle_timer >> 25); 1750 1751 return ticks; 1752 } 1753 1754 /* 1755 * Some controllers exhibit one or more of the following bugs when updating the 1756 * iso cycle timer register: 1757 * - When the lowest six bits are wrapping around to zero, a read that happens 1758 * at the same time will return garbage in the lowest ten bits. 1759 * - When the cycleOffset field wraps around to zero, the cycleCount field is 1760 * not incremented for about 60 ns. 1761 * - Occasionally, the entire register reads zero. 1762 * 1763 * To catch these, we read the register three times and ensure that the 1764 * difference between each two consecutive reads is approximately the same, i.e. 1765 * less than twice the other. Furthermore, any negative difference indicates an 1766 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to 1767 * execute, so we have enough precision to compute the ratio of the differences.) 1768 */ get_cycle_time(struct fw_ohci * ohci)1769 static u32 get_cycle_time(struct fw_ohci *ohci) 1770 { 1771 u32 c0, c1, c2; 1772 u32 t0, t1, t2; 1773 s32 diff01, diff12; 1774 int i; 1775 1776 if (has_reboot_by_cycle_timer_read_quirk(ohci)) 1777 return 0; 1778 1779 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1780 1781 if (ohci->quirks & QUIRK_CYCLE_TIMER) { 1782 i = 0; 1783 c1 = c2; 1784 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1785 do { 1786 c0 = c1; 1787 c1 = c2; 1788 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1789 t0 = cycle_timer_ticks(c0); 1790 t1 = cycle_timer_ticks(c1); 1791 t2 = cycle_timer_ticks(c2); 1792 diff01 = t1 - t0; 1793 diff12 = t2 - t1; 1794 } while ((diff01 <= 0 || diff12 <= 0 || 1795 diff01 / diff12 >= 2 || diff12 / diff01 >= 2) 1796 && i++ < 20); 1797 } 1798 1799 return c2; 1800 } 1801 1802 /* 1803 * This function has to be called at least every 64 seconds. The bus_time 1804 * field stores not only the upper 25 bits of the BUS_TIME register but also 1805 * the most significant bit of the cycle timer in bit 6 so that we can detect 1806 * changes in this bit. 1807 */ update_bus_time(struct fw_ohci * ohci)1808 static u32 update_bus_time(struct fw_ohci *ohci) 1809 { 1810 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25; 1811 1812 if (unlikely(!ohci->bus_time_running)) { 1813 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds); 1814 ohci->bus_time = (lower_32_bits(ktime_get_seconds()) & ~0x7f) | 1815 (cycle_time_seconds & 0x40); 1816 ohci->bus_time_running = true; 1817 } 1818 1819 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40)) 1820 ohci->bus_time += 0x40; 1821 1822 return ohci->bus_time | cycle_time_seconds; 1823 } 1824 get_status_for_port(struct fw_ohci * ohci,int port_index)1825 static int get_status_for_port(struct fw_ohci *ohci, int port_index) 1826 { 1827 int reg; 1828 1829 mutex_lock(&ohci->phy_reg_mutex); 1830 reg = write_phy_reg(ohci, 7, port_index); 1831 if (reg >= 0) 1832 reg = read_phy_reg(ohci, 8); 1833 mutex_unlock(&ohci->phy_reg_mutex); 1834 if (reg < 0) 1835 return reg; 1836 1837 switch (reg & 0x0f) { 1838 case 0x06: 1839 return 2; /* is child node (connected to parent node) */ 1840 case 0x0e: 1841 return 3; /* is parent node (connected to child node) */ 1842 } 1843 return 1; /* not connected */ 1844 } 1845 get_self_id_pos(struct fw_ohci * ohci,u32 self_id,int self_id_count)1846 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id, 1847 int self_id_count) 1848 { 1849 int i; 1850 u32 entry; 1851 1852 for (i = 0; i < self_id_count; i++) { 1853 entry = ohci->self_id_buffer[i]; 1854 if ((self_id & 0xff000000) == (entry & 0xff000000)) 1855 return -1; 1856 if ((self_id & 0xff000000) < (entry & 0xff000000)) 1857 return i; 1858 } 1859 return i; 1860 } 1861 initiated_reset(struct fw_ohci * ohci)1862 static int initiated_reset(struct fw_ohci *ohci) 1863 { 1864 int reg; 1865 int ret = 0; 1866 1867 mutex_lock(&ohci->phy_reg_mutex); 1868 reg = write_phy_reg(ohci, 7, 0xe0); /* Select page 7 */ 1869 if (reg >= 0) { 1870 reg = read_phy_reg(ohci, 8); 1871 reg |= 0x40; 1872 reg = write_phy_reg(ohci, 8, reg); /* set PMODE bit */ 1873 if (reg >= 0) { 1874 reg = read_phy_reg(ohci, 12); /* read register 12 */ 1875 if (reg >= 0) { 1876 if ((reg & 0x08) == 0x08) { 1877 /* bit 3 indicates "initiated reset" */ 1878 ret = 0x2; 1879 } 1880 } 1881 } 1882 } 1883 mutex_unlock(&ohci->phy_reg_mutex); 1884 return ret; 1885 } 1886 1887 /* 1888 * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally 1889 * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059. 1890 * Construct the selfID from phy register contents. 1891 */ find_and_insert_self_id(struct fw_ohci * ohci,int self_id_count)1892 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count) 1893 { 1894 int reg, i, pos, status; 1895 /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */ 1896 u32 self_id = 0x8040c800; 1897 1898 reg = reg_read(ohci, OHCI1394_NodeID); 1899 if (!(reg & OHCI1394_NodeID_idValid)) { 1900 ohci_notice(ohci, 1901 "node ID not valid, new bus reset in progress\n"); 1902 return -EBUSY; 1903 } 1904 self_id |= ((reg & 0x3f) << 24); /* phy ID */ 1905 1906 reg = ohci_read_phy_reg(&ohci->card, 4); 1907 if (reg < 0) 1908 return reg; 1909 self_id |= ((reg & 0x07) << 8); /* power class */ 1910 1911 reg = ohci_read_phy_reg(&ohci->card, 1); 1912 if (reg < 0) 1913 return reg; 1914 self_id |= ((reg & 0x3f) << 16); /* gap count */ 1915 1916 for (i = 0; i < 3; i++) { 1917 status = get_status_for_port(ohci, i); 1918 if (status < 0) 1919 return status; 1920 self_id |= ((status & 0x3) << (6 - (i * 2))); 1921 } 1922 1923 self_id |= initiated_reset(ohci); 1924 1925 pos = get_self_id_pos(ohci, self_id, self_id_count); 1926 if (pos >= 0) { 1927 memmove(&(ohci->self_id_buffer[pos+1]), 1928 &(ohci->self_id_buffer[pos]), 1929 (self_id_count - pos) * sizeof(*ohci->self_id_buffer)); 1930 ohci->self_id_buffer[pos] = self_id; 1931 self_id_count++; 1932 } 1933 return self_id_count; 1934 } 1935 bus_reset_work(struct work_struct * work)1936 static void bus_reset_work(struct work_struct *work) 1937 { 1938 struct fw_ohci *ohci = 1939 container_of(work, struct fw_ohci, bus_reset_work); 1940 int self_id_count, generation, new_generation, i, j; 1941 u32 reg; 1942 void *free_rom = NULL; 1943 dma_addr_t free_rom_bus = 0; 1944 bool is_new_root; 1945 1946 reg = reg_read(ohci, OHCI1394_NodeID); 1947 if (!(reg & OHCI1394_NodeID_idValid)) { 1948 ohci_notice(ohci, 1949 "node ID not valid, new bus reset in progress\n"); 1950 return; 1951 } 1952 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { 1953 ohci_notice(ohci, "malconfigured bus\n"); 1954 return; 1955 } 1956 ohci->node_id = reg & (OHCI1394_NodeID_busNumber | 1957 OHCI1394_NodeID_nodeNumber); 1958 1959 is_new_root = (reg & OHCI1394_NodeID_root) != 0; 1960 if (!(ohci->is_root && is_new_root)) 1961 reg_write(ohci, OHCI1394_LinkControlSet, 1962 OHCI1394_LinkControl_cycleMaster); 1963 ohci->is_root = is_new_root; 1964 1965 reg = reg_read(ohci, OHCI1394_SelfIDCount); 1966 if (reg & OHCI1394_SelfIDCount_selfIDError) { 1967 ohci_notice(ohci, "self ID receive error\n"); 1968 return; 1969 } 1970 /* 1971 * The count in the SelfIDCount register is the number of 1972 * bytes in the self ID receive buffer. Since we also receive 1973 * the inverted quadlets and a header quadlet, we shift one 1974 * bit extra to get the actual number of self IDs. 1975 */ 1976 self_id_count = (reg >> 3) & 0xff; 1977 1978 if (self_id_count > 252) { 1979 ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg); 1980 return; 1981 } 1982 1983 generation = (cond_le32_to_cpu(ohci->self_id[0]) >> 16) & 0xff; 1984 rmb(); 1985 1986 for (i = 1, j = 0; j < self_id_count; i += 2, j++) { 1987 u32 id = cond_le32_to_cpu(ohci->self_id[i]); 1988 u32 id2 = cond_le32_to_cpu(ohci->self_id[i + 1]); 1989 1990 if (id != ~id2) { 1991 /* 1992 * If the invalid data looks like a cycle start packet, 1993 * it's likely to be the result of the cycle master 1994 * having a wrong gap count. In this case, the self IDs 1995 * so far are valid and should be processed so that the 1996 * bus manager can then correct the gap count. 1997 */ 1998 if (id == 0xffff008f) { 1999 ohci_notice(ohci, "ignoring spurious self IDs\n"); 2000 self_id_count = j; 2001 break; 2002 } 2003 2004 ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n", 2005 j, self_id_count, id, id2); 2006 return; 2007 } 2008 ohci->self_id_buffer[j] = id; 2009 } 2010 2011 if (ohci->quirks & QUIRK_TI_SLLZ059) { 2012 self_id_count = find_and_insert_self_id(ohci, self_id_count); 2013 if (self_id_count < 0) { 2014 ohci_notice(ohci, 2015 "could not construct local self ID\n"); 2016 return; 2017 } 2018 } 2019 2020 if (self_id_count == 0) { 2021 ohci_notice(ohci, "no self IDs\n"); 2022 return; 2023 } 2024 rmb(); 2025 2026 /* 2027 * Check the consistency of the self IDs we just read. The 2028 * problem we face is that a new bus reset can start while we 2029 * read out the self IDs from the DMA buffer. If this happens, 2030 * the DMA buffer will be overwritten with new self IDs and we 2031 * will read out inconsistent data. The OHCI specification 2032 * (section 11.2) recommends a technique similar to 2033 * linux/seqlock.h, where we remember the generation of the 2034 * self IDs in the buffer before reading them out and compare 2035 * it to the current generation after reading them out. If 2036 * the two generations match we know we have a consistent set 2037 * of self IDs. 2038 */ 2039 2040 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; 2041 if (new_generation != generation) { 2042 ohci_notice(ohci, "new bus reset, discarding self ids\n"); 2043 return; 2044 } 2045 2046 /* FIXME: Document how the locking works. */ 2047 spin_lock_irq(&ohci->lock); 2048 2049 ohci->generation = -1; /* prevent AT packet queueing */ 2050 context_stop(&ohci->at_request_ctx); 2051 context_stop(&ohci->at_response_ctx); 2052 2053 spin_unlock_irq(&ohci->lock); 2054 2055 /* 2056 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent 2057 * packets in the AT queues and software needs to drain them. 2058 * Some OHCI 1.1 controllers (JMicron) apparently require this too. 2059 */ 2060 at_context_flush(&ohci->at_request_ctx); 2061 at_context_flush(&ohci->at_response_ctx); 2062 2063 spin_lock_irq(&ohci->lock); 2064 2065 ohci->generation = generation; 2066 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); 2067 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS) 2068 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset); 2069 2070 if (ohci->quirks & QUIRK_RESET_PACKET) 2071 ohci->request_generation = generation; 2072 2073 /* 2074 * This next bit is unrelated to the AT context stuff but we 2075 * have to do it under the spinlock also. If a new config rom 2076 * was set up before this reset, the old one is now no longer 2077 * in use and we can free it. Update the config rom pointers 2078 * to point to the current config rom and clear the 2079 * next_config_rom pointer so a new update can take place. 2080 */ 2081 2082 if (ohci->next_config_rom != NULL) { 2083 if (ohci->next_config_rom != ohci->config_rom) { 2084 free_rom = ohci->config_rom; 2085 free_rom_bus = ohci->config_rom_bus; 2086 } 2087 ohci->config_rom = ohci->next_config_rom; 2088 ohci->config_rom_bus = ohci->next_config_rom_bus; 2089 ohci->next_config_rom = NULL; 2090 2091 /* 2092 * Restore config_rom image and manually update 2093 * config_rom registers. Writing the header quadlet 2094 * will indicate that the config rom is ready, so we 2095 * do that last. 2096 */ 2097 reg_write(ohci, OHCI1394_BusOptions, 2098 be32_to_cpu(ohci->config_rom[2])); 2099 ohci->config_rom[0] = ohci->next_header; 2100 reg_write(ohci, OHCI1394_ConfigROMhdr, 2101 be32_to_cpu(ohci->next_header)); 2102 } 2103 2104 if (param_remote_dma) { 2105 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0); 2106 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0); 2107 } 2108 2109 spin_unlock_irq(&ohci->lock); 2110 2111 if (free_rom) 2112 dmam_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, free_rom, free_rom_bus); 2113 2114 log_selfids(ohci, generation, self_id_count); 2115 2116 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, 2117 self_id_count, ohci->self_id_buffer, 2118 ohci->csr_state_setclear_abdicate); 2119 ohci->csr_state_setclear_abdicate = false; 2120 } 2121 irq_handler(int irq,void * data)2122 static irqreturn_t irq_handler(int irq, void *data) 2123 { 2124 struct fw_ohci *ohci = data; 2125 u32 event, iso_event; 2126 int i; 2127 2128 event = reg_read(ohci, OHCI1394_IntEventClear); 2129 2130 if (!event || !~event) 2131 return IRQ_NONE; 2132 2133 /* 2134 * busReset and postedWriteErr events must not be cleared yet 2135 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1) 2136 */ 2137 reg_write(ohci, OHCI1394_IntEventClear, 2138 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr)); 2139 log_irqs(ohci, event); 2140 if (event & OHCI1394_busReset) 2141 reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_busReset); 2142 2143 if (event & OHCI1394_selfIDComplete) 2144 queue_work(selfid_workqueue, &ohci->bus_reset_work); 2145 2146 if (event & OHCI1394_RQPkt) 2147 tasklet_schedule(&ohci->ar_request_ctx.tasklet); 2148 2149 if (event & OHCI1394_RSPkt) 2150 tasklet_schedule(&ohci->ar_response_ctx.tasklet); 2151 2152 if (event & OHCI1394_reqTxComplete) 2153 tasklet_schedule(&ohci->at_request_ctx.tasklet); 2154 2155 if (event & OHCI1394_respTxComplete) 2156 tasklet_schedule(&ohci->at_response_ctx.tasklet); 2157 2158 if (event & OHCI1394_isochRx) { 2159 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); 2160 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); 2161 2162 while (iso_event) { 2163 i = ffs(iso_event) - 1; 2164 tasklet_schedule( 2165 &ohci->ir_context_list[i].context.tasklet); 2166 iso_event &= ~(1 << i); 2167 } 2168 } 2169 2170 if (event & OHCI1394_isochTx) { 2171 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); 2172 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); 2173 2174 while (iso_event) { 2175 i = ffs(iso_event) - 1; 2176 tasklet_schedule( 2177 &ohci->it_context_list[i].context.tasklet); 2178 iso_event &= ~(1 << i); 2179 } 2180 } 2181 2182 if (unlikely(event & OHCI1394_regAccessFail)) 2183 ohci_err(ohci, "register access failure\n"); 2184 2185 if (unlikely(event & OHCI1394_postedWriteErr)) { 2186 reg_read(ohci, OHCI1394_PostedWriteAddressHi); 2187 reg_read(ohci, OHCI1394_PostedWriteAddressLo); 2188 reg_write(ohci, OHCI1394_IntEventClear, 2189 OHCI1394_postedWriteErr); 2190 if (printk_ratelimit()) 2191 ohci_err(ohci, "PCI posted write error\n"); 2192 } 2193 2194 if (unlikely(event & OHCI1394_cycleTooLong)) { 2195 if (printk_ratelimit()) 2196 ohci_notice(ohci, "isochronous cycle too long\n"); 2197 reg_write(ohci, OHCI1394_LinkControlSet, 2198 OHCI1394_LinkControl_cycleMaster); 2199 } 2200 2201 if (unlikely(event & OHCI1394_cycleInconsistent)) { 2202 /* 2203 * We need to clear this event bit in order to make 2204 * cycleMatch isochronous I/O work. In theory we should 2205 * stop active cycleMatch iso contexts now and restart 2206 * them at least two cycles later. (FIXME?) 2207 */ 2208 if (printk_ratelimit()) 2209 ohci_notice(ohci, "isochronous cycle inconsistent\n"); 2210 } 2211 2212 if (unlikely(event & OHCI1394_unrecoverableError)) 2213 handle_dead_contexts(ohci); 2214 2215 if (event & OHCI1394_cycle64Seconds) { 2216 spin_lock(&ohci->lock); 2217 update_bus_time(ohci); 2218 spin_unlock(&ohci->lock); 2219 } else 2220 flush_writes(ohci); 2221 2222 return IRQ_HANDLED; 2223 } 2224 software_reset(struct fw_ohci * ohci)2225 static int software_reset(struct fw_ohci *ohci) 2226 { 2227 u32 val; 2228 int i; 2229 2230 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); 2231 for (i = 0; i < 500; i++) { 2232 val = reg_read(ohci, OHCI1394_HCControlSet); 2233 if (!~val) 2234 return -ENODEV; /* Card was ejected. */ 2235 2236 if (!(val & OHCI1394_HCControl_softReset)) 2237 return 0; 2238 2239 msleep(1); 2240 } 2241 2242 return -EBUSY; 2243 } 2244 copy_config_rom(__be32 * dest,const __be32 * src,size_t length)2245 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length) 2246 { 2247 size_t size = length * 4; 2248 2249 memcpy(dest, src, size); 2250 if (size < CONFIG_ROM_SIZE) 2251 memset(&dest[length], 0, CONFIG_ROM_SIZE - size); 2252 } 2253 configure_1394a_enhancements(struct fw_ohci * ohci)2254 static int configure_1394a_enhancements(struct fw_ohci *ohci) 2255 { 2256 bool enable_1394a; 2257 int ret, clear, set, offset; 2258 2259 /* Check if the driver should configure link and PHY. */ 2260 if (!(reg_read(ohci, OHCI1394_HCControlSet) & 2261 OHCI1394_HCControl_programPhyEnable)) 2262 return 0; 2263 2264 /* Paranoia: check whether the PHY supports 1394a, too. */ 2265 enable_1394a = false; 2266 ret = read_phy_reg(ohci, 2); 2267 if (ret < 0) 2268 return ret; 2269 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) { 2270 ret = read_paged_phy_reg(ohci, 1, 8); 2271 if (ret < 0) 2272 return ret; 2273 if (ret >= 1) 2274 enable_1394a = true; 2275 } 2276 2277 if (ohci->quirks & QUIRK_NO_1394A) 2278 enable_1394a = false; 2279 2280 /* Configure PHY and link consistently. */ 2281 if (enable_1394a) { 2282 clear = 0; 2283 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2284 } else { 2285 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2286 set = 0; 2287 } 2288 ret = update_phy_reg(ohci, 5, clear, set); 2289 if (ret < 0) 2290 return ret; 2291 2292 if (enable_1394a) 2293 offset = OHCI1394_HCControlSet; 2294 else 2295 offset = OHCI1394_HCControlClear; 2296 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable); 2297 2298 /* Clean up: configuration has been taken care of. */ 2299 reg_write(ohci, OHCI1394_HCControlClear, 2300 OHCI1394_HCControl_programPhyEnable); 2301 2302 return 0; 2303 } 2304 probe_tsb41ba3d(struct fw_ohci * ohci)2305 static int probe_tsb41ba3d(struct fw_ohci *ohci) 2306 { 2307 /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */ 2308 static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, }; 2309 int reg, i; 2310 2311 reg = read_phy_reg(ohci, 2); 2312 if (reg < 0) 2313 return reg; 2314 if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS) 2315 return 0; 2316 2317 for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) { 2318 reg = read_paged_phy_reg(ohci, 1, i + 10); 2319 if (reg < 0) 2320 return reg; 2321 if (reg != id[i]) 2322 return 0; 2323 } 2324 return 1; 2325 } 2326 ohci_enable(struct fw_card * card,const __be32 * config_rom,size_t length)2327 static int ohci_enable(struct fw_card *card, 2328 const __be32 *config_rom, size_t length) 2329 { 2330 struct fw_ohci *ohci = fw_ohci(card); 2331 u32 lps, version, irqs; 2332 int i, ret; 2333 2334 ret = software_reset(ohci); 2335 if (ret < 0) { 2336 ohci_err(ohci, "failed to reset ohci card\n"); 2337 return ret; 2338 } 2339 2340 /* 2341 * Now enable LPS, which we need in order to start accessing 2342 * most of the registers. In fact, on some cards (ALI M5251), 2343 * accessing registers in the SClk domain without LPS enabled 2344 * will lock up the machine. Wait 50msec to make sure we have 2345 * full link enabled. However, with some cards (well, at least 2346 * a JMicron PCIe card), we have to try again sometimes. 2347 * 2348 * TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but 2349 * cannot actually use the phy at that time. These need tens of 2350 * millisecods pause between LPS write and first phy access too. 2351 */ 2352 2353 reg_write(ohci, OHCI1394_HCControlSet, 2354 OHCI1394_HCControl_LPS | 2355 OHCI1394_HCControl_postedWriteEnable); 2356 flush_writes(ohci); 2357 2358 for (lps = 0, i = 0; !lps && i < 3; i++) { 2359 msleep(50); 2360 lps = reg_read(ohci, OHCI1394_HCControlSet) & 2361 OHCI1394_HCControl_LPS; 2362 } 2363 2364 if (!lps) { 2365 ohci_err(ohci, "failed to set Link Power Status\n"); 2366 return -EIO; 2367 } 2368 2369 if (ohci->quirks & QUIRK_TI_SLLZ059) { 2370 ret = probe_tsb41ba3d(ohci); 2371 if (ret < 0) 2372 return ret; 2373 if (ret) 2374 ohci_notice(ohci, "local TSB41BA3D phy\n"); 2375 else 2376 ohci->quirks &= ~QUIRK_TI_SLLZ059; 2377 } 2378 2379 reg_write(ohci, OHCI1394_HCControlClear, 2380 OHCI1394_HCControl_noByteSwapData); 2381 2382 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); 2383 reg_write(ohci, OHCI1394_LinkControlSet, 2384 OHCI1394_LinkControl_cycleTimerEnable | 2385 OHCI1394_LinkControl_cycleMaster); 2386 2387 reg_write(ohci, OHCI1394_ATRetries, 2388 OHCI1394_MAX_AT_REQ_RETRIES | 2389 (OHCI1394_MAX_AT_RESP_RETRIES << 4) | 2390 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) | 2391 (200 << 16)); 2392 2393 ohci->bus_time_running = false; 2394 2395 for (i = 0; i < 32; i++) 2396 if (ohci->ir_context_support & (1 << i)) 2397 reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i), 2398 IR_CONTEXT_MULTI_CHANNEL_MODE); 2399 2400 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 2401 if (version >= OHCI_VERSION_1_1) { 2402 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi, 2403 0xfffffffe); 2404 card->broadcast_channel_auto_allocated = true; 2405 } 2406 2407 /* Get implemented bits of the priority arbitration request counter. */ 2408 reg_write(ohci, OHCI1394_FairnessControl, 0x3f); 2409 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f; 2410 reg_write(ohci, OHCI1394_FairnessControl, 0); 2411 card->priority_budget_implemented = ohci->pri_req_max != 0; 2412 2413 reg_write(ohci, OHCI1394_PhyUpperBound, FW_MAX_PHYSICAL_RANGE >> 16); 2414 reg_write(ohci, OHCI1394_IntEventClear, ~0); 2415 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 2416 2417 ret = configure_1394a_enhancements(ohci); 2418 if (ret < 0) 2419 return ret; 2420 2421 /* Activate link_on bit and contender bit in our self ID packets.*/ 2422 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER); 2423 if (ret < 0) 2424 return ret; 2425 2426 /* 2427 * When the link is not yet enabled, the atomic config rom 2428 * update mechanism described below in ohci_set_config_rom() 2429 * is not active. We have to update ConfigRomHeader and 2430 * BusOptions manually, and the write to ConfigROMmap takes 2431 * effect immediately. We tie this to the enabling of the 2432 * link, so we have a valid config rom before enabling - the 2433 * OHCI requires that ConfigROMhdr and BusOptions have valid 2434 * values before enabling. 2435 * 2436 * However, when the ConfigROMmap is written, some controllers 2437 * always read back quadlets 0 and 2 from the config rom to 2438 * the ConfigRomHeader and BusOptions registers on bus reset. 2439 * They shouldn't do that in this initial case where the link 2440 * isn't enabled. This means we have to use the same 2441 * workaround here, setting the bus header to 0 and then write 2442 * the right values in the bus reset tasklet. 2443 */ 2444 2445 if (config_rom) { 2446 ohci->next_config_rom = dmam_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2447 &ohci->next_config_rom_bus, GFP_KERNEL); 2448 if (ohci->next_config_rom == NULL) 2449 return -ENOMEM; 2450 2451 copy_config_rom(ohci->next_config_rom, config_rom, length); 2452 } else { 2453 /* 2454 * In the suspend case, config_rom is NULL, which 2455 * means that we just reuse the old config rom. 2456 */ 2457 ohci->next_config_rom = ohci->config_rom; 2458 ohci->next_config_rom_bus = ohci->config_rom_bus; 2459 } 2460 2461 ohci->next_header = ohci->next_config_rom[0]; 2462 ohci->next_config_rom[0] = 0; 2463 reg_write(ohci, OHCI1394_ConfigROMhdr, 0); 2464 reg_write(ohci, OHCI1394_BusOptions, 2465 be32_to_cpu(ohci->next_config_rom[2])); 2466 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2467 2468 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); 2469 2470 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete | 2471 OHCI1394_RQPkt | OHCI1394_RSPkt | 2472 OHCI1394_isochTx | OHCI1394_isochRx | 2473 OHCI1394_postedWriteErr | 2474 OHCI1394_selfIDComplete | 2475 OHCI1394_regAccessFail | 2476 OHCI1394_cycleInconsistent | 2477 OHCI1394_unrecoverableError | 2478 OHCI1394_cycleTooLong | 2479 OHCI1394_masterIntEnable; 2480 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS) 2481 irqs |= OHCI1394_busReset; 2482 reg_write(ohci, OHCI1394_IntMaskSet, irqs); 2483 2484 reg_write(ohci, OHCI1394_HCControlSet, 2485 OHCI1394_HCControl_linkEnable | 2486 OHCI1394_HCControl_BIBimageValid); 2487 2488 reg_write(ohci, OHCI1394_LinkControlSet, 2489 OHCI1394_LinkControl_rcvSelfID | 2490 OHCI1394_LinkControl_rcvPhyPkt); 2491 2492 ar_context_run(&ohci->ar_request_ctx); 2493 ar_context_run(&ohci->ar_response_ctx); 2494 2495 flush_writes(ohci); 2496 2497 /* We are ready to go, reset bus to finish initialization. */ 2498 fw_schedule_bus_reset(&ohci->card, false, true); 2499 2500 return 0; 2501 } 2502 ohci_set_config_rom(struct fw_card * card,const __be32 * config_rom,size_t length)2503 static int ohci_set_config_rom(struct fw_card *card, 2504 const __be32 *config_rom, size_t length) 2505 { 2506 struct fw_ohci *ohci; 2507 __be32 *next_config_rom; 2508 dma_addr_t next_config_rom_bus; 2509 2510 ohci = fw_ohci(card); 2511 2512 /* 2513 * When the OHCI controller is enabled, the config rom update 2514 * mechanism is a bit tricky, but easy enough to use. See 2515 * section 5.5.6 in the OHCI specification. 2516 * 2517 * The OHCI controller caches the new config rom address in a 2518 * shadow register (ConfigROMmapNext) and needs a bus reset 2519 * for the changes to take place. When the bus reset is 2520 * detected, the controller loads the new values for the 2521 * ConfigRomHeader and BusOptions registers from the specified 2522 * config rom and loads ConfigROMmap from the ConfigROMmapNext 2523 * shadow register. All automatically and atomically. 2524 * 2525 * Now, there's a twist to this story. The automatic load of 2526 * ConfigRomHeader and BusOptions doesn't honor the 2527 * noByteSwapData bit, so with a be32 config rom, the 2528 * controller will load be32 values in to these registers 2529 * during the atomic update, even on litte endian 2530 * architectures. The workaround we use is to put a 0 in the 2531 * header quadlet; 0 is endian agnostic and means that the 2532 * config rom isn't ready yet. In the bus reset tasklet we 2533 * then set up the real values for the two registers. 2534 * 2535 * We use ohci->lock to avoid racing with the code that sets 2536 * ohci->next_config_rom to NULL (see bus_reset_work). 2537 */ 2538 2539 next_config_rom = dmam_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2540 &next_config_rom_bus, GFP_KERNEL); 2541 if (next_config_rom == NULL) 2542 return -ENOMEM; 2543 2544 spin_lock_irq(&ohci->lock); 2545 2546 /* 2547 * If there is not an already pending config_rom update, 2548 * push our new allocation into the ohci->next_config_rom 2549 * and then mark the local variable as null so that we 2550 * won't deallocate the new buffer. 2551 * 2552 * OTOH, if there is a pending config_rom update, just 2553 * use that buffer with the new config_rom data, and 2554 * let this routine free the unused DMA allocation. 2555 */ 2556 2557 if (ohci->next_config_rom == NULL) { 2558 ohci->next_config_rom = next_config_rom; 2559 ohci->next_config_rom_bus = next_config_rom_bus; 2560 next_config_rom = NULL; 2561 } 2562 2563 copy_config_rom(ohci->next_config_rom, config_rom, length); 2564 2565 ohci->next_header = config_rom[0]; 2566 ohci->next_config_rom[0] = 0; 2567 2568 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2569 2570 spin_unlock_irq(&ohci->lock); 2571 2572 /* If we didn't use the DMA allocation, delete it. */ 2573 if (next_config_rom != NULL) { 2574 dmam_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, next_config_rom, 2575 next_config_rom_bus); 2576 } 2577 2578 /* 2579 * Now initiate a bus reset to have the changes take 2580 * effect. We clean up the old config rom memory and DMA 2581 * mappings in the bus reset tasklet, since the OHCI 2582 * controller could need to access it before the bus reset 2583 * takes effect. 2584 */ 2585 2586 fw_schedule_bus_reset(&ohci->card, true, true); 2587 2588 return 0; 2589 } 2590 ohci_send_request(struct fw_card * card,struct fw_packet * packet)2591 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) 2592 { 2593 struct fw_ohci *ohci = fw_ohci(card); 2594 2595 at_context_transmit(&ohci->at_request_ctx, packet); 2596 } 2597 ohci_send_response(struct fw_card * card,struct fw_packet * packet)2598 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) 2599 { 2600 struct fw_ohci *ohci = fw_ohci(card); 2601 2602 at_context_transmit(&ohci->at_response_ctx, packet); 2603 } 2604 ohci_cancel_packet(struct fw_card * card,struct fw_packet * packet)2605 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) 2606 { 2607 struct fw_ohci *ohci = fw_ohci(card); 2608 struct context *ctx = &ohci->at_request_ctx; 2609 struct driver_data *driver_data = packet->driver_data; 2610 int ret = -ENOENT; 2611 2612 tasklet_disable_in_atomic(&ctx->tasklet); 2613 2614 if (packet->ack != 0) 2615 goto out; 2616 2617 if (packet->payload_mapped) 2618 dma_unmap_single(ohci->card.device, packet->payload_bus, 2619 packet->payload_length, DMA_TO_DEVICE); 2620 2621 log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20); 2622 driver_data->packet = NULL; 2623 packet->ack = RCODE_CANCELLED; 2624 2625 // Timestamping on behalf of the hardware. 2626 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); 2627 2628 packet->callback(packet, &ohci->card, packet->ack); 2629 ret = 0; 2630 out: 2631 tasklet_enable(&ctx->tasklet); 2632 2633 return ret; 2634 } 2635 ohci_enable_phys_dma(struct fw_card * card,int node_id,int generation)2636 static int ohci_enable_phys_dma(struct fw_card *card, 2637 int node_id, int generation) 2638 { 2639 struct fw_ohci *ohci = fw_ohci(card); 2640 unsigned long flags; 2641 int n, ret = 0; 2642 2643 if (param_remote_dma) 2644 return 0; 2645 2646 /* 2647 * FIXME: Make sure this bitmask is cleared when we clear the busReset 2648 * interrupt bit. Clear physReqResourceAllBuses on bus reset. 2649 */ 2650 2651 spin_lock_irqsave(&ohci->lock, flags); 2652 2653 if (ohci->generation != generation) { 2654 ret = -ESTALE; 2655 goto out; 2656 } 2657 2658 /* 2659 * Note, if the node ID contains a non-local bus ID, physical DMA is 2660 * enabled for _all_ nodes on remote buses. 2661 */ 2662 2663 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; 2664 if (n < 32) 2665 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); 2666 else 2667 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); 2668 2669 flush_writes(ohci); 2670 out: 2671 spin_unlock_irqrestore(&ohci->lock, flags); 2672 2673 return ret; 2674 } 2675 ohci_read_csr(struct fw_card * card,int csr_offset)2676 static u32 ohci_read_csr(struct fw_card *card, int csr_offset) 2677 { 2678 struct fw_ohci *ohci = fw_ohci(card); 2679 unsigned long flags; 2680 u32 value; 2681 2682 switch (csr_offset) { 2683 case CSR_STATE_CLEAR: 2684 case CSR_STATE_SET: 2685 if (ohci->is_root && 2686 (reg_read(ohci, OHCI1394_LinkControlSet) & 2687 OHCI1394_LinkControl_cycleMaster)) 2688 value = CSR_STATE_BIT_CMSTR; 2689 else 2690 value = 0; 2691 if (ohci->csr_state_setclear_abdicate) 2692 value |= CSR_STATE_BIT_ABDICATE; 2693 2694 return value; 2695 2696 case CSR_NODE_IDS: 2697 return reg_read(ohci, OHCI1394_NodeID) << 16; 2698 2699 case CSR_CYCLE_TIME: 2700 return get_cycle_time(ohci); 2701 2702 case CSR_BUS_TIME: 2703 /* 2704 * We might be called just after the cycle timer has wrapped 2705 * around but just before the cycle64Seconds handler, so we 2706 * better check here, too, if the bus time needs to be updated. 2707 */ 2708 spin_lock_irqsave(&ohci->lock, flags); 2709 value = update_bus_time(ohci); 2710 spin_unlock_irqrestore(&ohci->lock, flags); 2711 return value; 2712 2713 case CSR_BUSY_TIMEOUT: 2714 value = reg_read(ohci, OHCI1394_ATRetries); 2715 return (value >> 4) & 0x0ffff00f; 2716 2717 case CSR_PRIORITY_BUDGET: 2718 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) | 2719 (ohci->pri_req_max << 8); 2720 2721 default: 2722 WARN_ON(1); 2723 return 0; 2724 } 2725 } 2726 ohci_write_csr(struct fw_card * card,int csr_offset,u32 value)2727 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value) 2728 { 2729 struct fw_ohci *ohci = fw_ohci(card); 2730 unsigned long flags; 2731 2732 switch (csr_offset) { 2733 case CSR_STATE_CLEAR: 2734 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2735 reg_write(ohci, OHCI1394_LinkControlClear, 2736 OHCI1394_LinkControl_cycleMaster); 2737 flush_writes(ohci); 2738 } 2739 if (value & CSR_STATE_BIT_ABDICATE) 2740 ohci->csr_state_setclear_abdicate = false; 2741 break; 2742 2743 case CSR_STATE_SET: 2744 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2745 reg_write(ohci, OHCI1394_LinkControlSet, 2746 OHCI1394_LinkControl_cycleMaster); 2747 flush_writes(ohci); 2748 } 2749 if (value & CSR_STATE_BIT_ABDICATE) 2750 ohci->csr_state_setclear_abdicate = true; 2751 break; 2752 2753 case CSR_NODE_IDS: 2754 reg_write(ohci, OHCI1394_NodeID, value >> 16); 2755 flush_writes(ohci); 2756 break; 2757 2758 case CSR_CYCLE_TIME: 2759 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value); 2760 reg_write(ohci, OHCI1394_IntEventSet, 2761 OHCI1394_cycleInconsistent); 2762 flush_writes(ohci); 2763 break; 2764 2765 case CSR_BUS_TIME: 2766 spin_lock_irqsave(&ohci->lock, flags); 2767 ohci->bus_time = (update_bus_time(ohci) & 0x40) | 2768 (value & ~0x7f); 2769 spin_unlock_irqrestore(&ohci->lock, flags); 2770 break; 2771 2772 case CSR_BUSY_TIMEOUT: 2773 value = (value & 0xf) | ((value & 0xf) << 4) | 2774 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4); 2775 reg_write(ohci, OHCI1394_ATRetries, value); 2776 flush_writes(ohci); 2777 break; 2778 2779 case CSR_PRIORITY_BUDGET: 2780 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f); 2781 flush_writes(ohci); 2782 break; 2783 2784 default: 2785 WARN_ON(1); 2786 break; 2787 } 2788 } 2789 flush_iso_completions(struct iso_context * ctx)2790 static void flush_iso_completions(struct iso_context *ctx) 2791 { 2792 ctx->base.callback.sc(&ctx->base, ctx->last_timestamp, 2793 ctx->header_length, ctx->header, 2794 ctx->base.callback_data); 2795 ctx->header_length = 0; 2796 } 2797 copy_iso_headers(struct iso_context * ctx,const u32 * dma_hdr)2798 static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr) 2799 { 2800 u32 *ctx_hdr; 2801 2802 if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) { 2803 if (ctx->base.drop_overflow_headers) 2804 return; 2805 flush_iso_completions(ctx); 2806 } 2807 2808 ctx_hdr = ctx->header + ctx->header_length; 2809 ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]); 2810 2811 /* 2812 * The two iso header quadlets are byteswapped to little 2813 * endian by the controller, but we want to present them 2814 * as big endian for consistency with the bus endianness. 2815 */ 2816 if (ctx->base.header_size > 0) 2817 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */ 2818 if (ctx->base.header_size > 4) 2819 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */ 2820 if (ctx->base.header_size > 8) 2821 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8); 2822 ctx->header_length += ctx->base.header_size; 2823 } 2824 handle_ir_packet_per_buffer(struct context * context,struct descriptor * d,struct descriptor * last)2825 static int handle_ir_packet_per_buffer(struct context *context, 2826 struct descriptor *d, 2827 struct descriptor *last) 2828 { 2829 struct iso_context *ctx = 2830 container_of(context, struct iso_context, context); 2831 struct descriptor *pd; 2832 u32 buffer_dma; 2833 2834 for (pd = d; pd <= last; pd++) 2835 if (pd->transfer_status) 2836 break; 2837 if (pd > last) 2838 /* Descriptor(s) not done yet, stop iteration */ 2839 return 0; 2840 2841 while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) { 2842 d++; 2843 buffer_dma = le32_to_cpu(d->data_address); 2844 dma_sync_single_range_for_cpu(context->ohci->card.device, 2845 buffer_dma & PAGE_MASK, 2846 buffer_dma & ~PAGE_MASK, 2847 le16_to_cpu(d->req_count), 2848 DMA_FROM_DEVICE); 2849 } 2850 2851 copy_iso_headers(ctx, (u32 *) (last + 1)); 2852 2853 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) 2854 flush_iso_completions(ctx); 2855 2856 return 1; 2857 } 2858 2859 /* d == last because each descriptor block is only a single descriptor. */ handle_ir_buffer_fill(struct context * context,struct descriptor * d,struct descriptor * last)2860 static int handle_ir_buffer_fill(struct context *context, 2861 struct descriptor *d, 2862 struct descriptor *last) 2863 { 2864 struct iso_context *ctx = 2865 container_of(context, struct iso_context, context); 2866 unsigned int req_count, res_count, completed; 2867 u32 buffer_dma; 2868 2869 req_count = le16_to_cpu(last->req_count); 2870 res_count = le16_to_cpu(READ_ONCE(last->res_count)); 2871 completed = req_count - res_count; 2872 buffer_dma = le32_to_cpu(last->data_address); 2873 2874 if (completed > 0) { 2875 ctx->mc_buffer_bus = buffer_dma; 2876 ctx->mc_completed = completed; 2877 } 2878 2879 if (res_count != 0) 2880 /* Descriptor(s) not done yet, stop iteration */ 2881 return 0; 2882 2883 dma_sync_single_range_for_cpu(context->ohci->card.device, 2884 buffer_dma & PAGE_MASK, 2885 buffer_dma & ~PAGE_MASK, 2886 completed, DMA_FROM_DEVICE); 2887 2888 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) { 2889 ctx->base.callback.mc(&ctx->base, 2890 buffer_dma + completed, 2891 ctx->base.callback_data); 2892 ctx->mc_completed = 0; 2893 } 2894 2895 return 1; 2896 } 2897 flush_ir_buffer_fill(struct iso_context * ctx)2898 static void flush_ir_buffer_fill(struct iso_context *ctx) 2899 { 2900 dma_sync_single_range_for_cpu(ctx->context.ohci->card.device, 2901 ctx->mc_buffer_bus & PAGE_MASK, 2902 ctx->mc_buffer_bus & ~PAGE_MASK, 2903 ctx->mc_completed, DMA_FROM_DEVICE); 2904 2905 ctx->base.callback.mc(&ctx->base, 2906 ctx->mc_buffer_bus + ctx->mc_completed, 2907 ctx->base.callback_data); 2908 ctx->mc_completed = 0; 2909 } 2910 sync_it_packet_for_cpu(struct context * context,struct descriptor * pd)2911 static inline void sync_it_packet_for_cpu(struct context *context, 2912 struct descriptor *pd) 2913 { 2914 __le16 control; 2915 u32 buffer_dma; 2916 2917 /* only packets beginning with OUTPUT_MORE* have data buffers */ 2918 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 2919 return; 2920 2921 /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */ 2922 pd += 2; 2923 2924 /* 2925 * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's 2926 * data buffer is in the context program's coherent page and must not 2927 * be synced. 2928 */ 2929 if ((le32_to_cpu(pd->data_address) & PAGE_MASK) == 2930 (context->current_bus & PAGE_MASK)) { 2931 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 2932 return; 2933 pd++; 2934 } 2935 2936 do { 2937 buffer_dma = le32_to_cpu(pd->data_address); 2938 dma_sync_single_range_for_cpu(context->ohci->card.device, 2939 buffer_dma & PAGE_MASK, 2940 buffer_dma & ~PAGE_MASK, 2941 le16_to_cpu(pd->req_count), 2942 DMA_TO_DEVICE); 2943 control = pd->control; 2944 pd++; 2945 } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))); 2946 } 2947 handle_it_packet(struct context * context,struct descriptor * d,struct descriptor * last)2948 static int handle_it_packet(struct context *context, 2949 struct descriptor *d, 2950 struct descriptor *last) 2951 { 2952 struct iso_context *ctx = 2953 container_of(context, struct iso_context, context); 2954 struct descriptor *pd; 2955 __be32 *ctx_hdr; 2956 2957 for (pd = d; pd <= last; pd++) 2958 if (pd->transfer_status) 2959 break; 2960 if (pd > last) 2961 /* Descriptor(s) not done yet, stop iteration */ 2962 return 0; 2963 2964 sync_it_packet_for_cpu(context, d); 2965 2966 if (ctx->header_length + 4 > PAGE_SIZE) { 2967 if (ctx->base.drop_overflow_headers) 2968 return 1; 2969 flush_iso_completions(ctx); 2970 } 2971 2972 ctx_hdr = ctx->header + ctx->header_length; 2973 ctx->last_timestamp = le16_to_cpu(last->res_count); 2974 /* Present this value as big-endian to match the receive code */ 2975 *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) | 2976 le16_to_cpu(pd->res_count)); 2977 ctx->header_length += 4; 2978 2979 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) 2980 flush_iso_completions(ctx); 2981 2982 return 1; 2983 } 2984 set_multichannel_mask(struct fw_ohci * ohci,u64 channels)2985 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels) 2986 { 2987 u32 hi = channels >> 32, lo = channels; 2988 2989 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi); 2990 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo); 2991 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi); 2992 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo); 2993 ohci->mc_channels = channels; 2994 } 2995 ohci_allocate_iso_context(struct fw_card * card,int type,int channel,size_t header_size)2996 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card, 2997 int type, int channel, size_t header_size) 2998 { 2999 struct fw_ohci *ohci = fw_ohci(card); 3000 struct iso_context *ctx; 3001 descriptor_callback_t callback; 3002 u64 *channels; 3003 u32 *mask, regs; 3004 int index, ret = -EBUSY; 3005 3006 spin_lock_irq(&ohci->lock); 3007 3008 switch (type) { 3009 case FW_ISO_CONTEXT_TRANSMIT: 3010 mask = &ohci->it_context_mask; 3011 callback = handle_it_packet; 3012 index = ffs(*mask) - 1; 3013 if (index >= 0) { 3014 *mask &= ~(1 << index); 3015 regs = OHCI1394_IsoXmitContextBase(index); 3016 ctx = &ohci->it_context_list[index]; 3017 } 3018 break; 3019 3020 case FW_ISO_CONTEXT_RECEIVE: 3021 channels = &ohci->ir_context_channels; 3022 mask = &ohci->ir_context_mask; 3023 callback = handle_ir_packet_per_buffer; 3024 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1; 3025 if (index >= 0) { 3026 *channels &= ~(1ULL << channel); 3027 *mask &= ~(1 << index); 3028 regs = OHCI1394_IsoRcvContextBase(index); 3029 ctx = &ohci->ir_context_list[index]; 3030 } 3031 break; 3032 3033 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3034 mask = &ohci->ir_context_mask; 3035 callback = handle_ir_buffer_fill; 3036 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1; 3037 if (index >= 0) { 3038 ohci->mc_allocated = true; 3039 *mask &= ~(1 << index); 3040 regs = OHCI1394_IsoRcvContextBase(index); 3041 ctx = &ohci->ir_context_list[index]; 3042 } 3043 break; 3044 3045 default: 3046 index = -1; 3047 ret = -ENOSYS; 3048 } 3049 3050 spin_unlock_irq(&ohci->lock); 3051 3052 if (index < 0) 3053 return ERR_PTR(ret); 3054 3055 memset(ctx, 0, sizeof(*ctx)); 3056 ctx->header_length = 0; 3057 ctx->header = (void *) __get_free_page(GFP_KERNEL); 3058 if (ctx->header == NULL) { 3059 ret = -ENOMEM; 3060 goto out; 3061 } 3062 ret = context_init(&ctx->context, ohci, regs, callback); 3063 if (ret < 0) 3064 goto out_with_header; 3065 3066 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) { 3067 set_multichannel_mask(ohci, 0); 3068 ctx->mc_completed = 0; 3069 } 3070 3071 return &ctx->base; 3072 3073 out_with_header: 3074 free_page((unsigned long)ctx->header); 3075 out: 3076 spin_lock_irq(&ohci->lock); 3077 3078 switch (type) { 3079 case FW_ISO_CONTEXT_RECEIVE: 3080 *channels |= 1ULL << channel; 3081 break; 3082 3083 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3084 ohci->mc_allocated = false; 3085 break; 3086 } 3087 *mask |= 1 << index; 3088 3089 spin_unlock_irq(&ohci->lock); 3090 3091 return ERR_PTR(ret); 3092 } 3093 ohci_start_iso(struct fw_iso_context * base,s32 cycle,u32 sync,u32 tags)3094 static int ohci_start_iso(struct fw_iso_context *base, 3095 s32 cycle, u32 sync, u32 tags) 3096 { 3097 struct iso_context *ctx = container_of(base, struct iso_context, base); 3098 struct fw_ohci *ohci = ctx->context.ohci; 3099 u32 control = IR_CONTEXT_ISOCH_HEADER, match; 3100 int index; 3101 3102 /* the controller cannot start without any queued packets */ 3103 if (ctx->context.last->branch_address == 0) 3104 return -ENODATA; 3105 3106 switch (ctx->base.type) { 3107 case FW_ISO_CONTEXT_TRANSMIT: 3108 index = ctx - ohci->it_context_list; 3109 match = 0; 3110 if (cycle >= 0) 3111 match = IT_CONTEXT_CYCLE_MATCH_ENABLE | 3112 (cycle & 0x7fff) << 16; 3113 3114 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); 3115 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); 3116 context_run(&ctx->context, match); 3117 break; 3118 3119 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3120 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE; 3121 fallthrough; 3122 case FW_ISO_CONTEXT_RECEIVE: 3123 index = ctx - ohci->ir_context_list; 3124 match = (tags << 28) | (sync << 8) | ctx->base.channel; 3125 if (cycle >= 0) { 3126 match |= (cycle & 0x07fff) << 12; 3127 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE; 3128 } 3129 3130 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); 3131 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); 3132 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match); 3133 context_run(&ctx->context, control); 3134 3135 ctx->sync = sync; 3136 ctx->tags = tags; 3137 3138 break; 3139 } 3140 3141 return 0; 3142 } 3143 ohci_stop_iso(struct fw_iso_context * base)3144 static int ohci_stop_iso(struct fw_iso_context *base) 3145 { 3146 struct fw_ohci *ohci = fw_ohci(base->card); 3147 struct iso_context *ctx = container_of(base, struct iso_context, base); 3148 int index; 3149 3150 switch (ctx->base.type) { 3151 case FW_ISO_CONTEXT_TRANSMIT: 3152 index = ctx - ohci->it_context_list; 3153 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); 3154 break; 3155 3156 case FW_ISO_CONTEXT_RECEIVE: 3157 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3158 index = ctx - ohci->ir_context_list; 3159 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); 3160 break; 3161 } 3162 flush_writes(ohci); 3163 context_stop(&ctx->context); 3164 tasklet_kill(&ctx->context.tasklet); 3165 3166 return 0; 3167 } 3168 ohci_free_iso_context(struct fw_iso_context * base)3169 static void ohci_free_iso_context(struct fw_iso_context *base) 3170 { 3171 struct fw_ohci *ohci = fw_ohci(base->card); 3172 struct iso_context *ctx = container_of(base, struct iso_context, base); 3173 unsigned long flags; 3174 int index; 3175 3176 ohci_stop_iso(base); 3177 context_release(&ctx->context); 3178 free_page((unsigned long)ctx->header); 3179 3180 spin_lock_irqsave(&ohci->lock, flags); 3181 3182 switch (base->type) { 3183 case FW_ISO_CONTEXT_TRANSMIT: 3184 index = ctx - ohci->it_context_list; 3185 ohci->it_context_mask |= 1 << index; 3186 break; 3187 3188 case FW_ISO_CONTEXT_RECEIVE: 3189 index = ctx - ohci->ir_context_list; 3190 ohci->ir_context_mask |= 1 << index; 3191 ohci->ir_context_channels |= 1ULL << base->channel; 3192 break; 3193 3194 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3195 index = ctx - ohci->ir_context_list; 3196 ohci->ir_context_mask |= 1 << index; 3197 ohci->ir_context_channels |= ohci->mc_channels; 3198 ohci->mc_channels = 0; 3199 ohci->mc_allocated = false; 3200 break; 3201 } 3202 3203 spin_unlock_irqrestore(&ohci->lock, flags); 3204 } 3205 ohci_set_iso_channels(struct fw_iso_context * base,u64 * channels)3206 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels) 3207 { 3208 struct fw_ohci *ohci = fw_ohci(base->card); 3209 unsigned long flags; 3210 int ret; 3211 3212 switch (base->type) { 3213 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3214 3215 spin_lock_irqsave(&ohci->lock, flags); 3216 3217 /* Don't allow multichannel to grab other contexts' channels. */ 3218 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) { 3219 *channels = ohci->ir_context_channels; 3220 ret = -EBUSY; 3221 } else { 3222 set_multichannel_mask(ohci, *channels); 3223 ret = 0; 3224 } 3225 3226 spin_unlock_irqrestore(&ohci->lock, flags); 3227 3228 break; 3229 default: 3230 ret = -EINVAL; 3231 } 3232 3233 return ret; 3234 } 3235 3236 #ifdef CONFIG_PM ohci_resume_iso_dma(struct fw_ohci * ohci)3237 static void ohci_resume_iso_dma(struct fw_ohci *ohci) 3238 { 3239 int i; 3240 struct iso_context *ctx; 3241 3242 for (i = 0 ; i < ohci->n_ir ; i++) { 3243 ctx = &ohci->ir_context_list[i]; 3244 if (ctx->context.running) 3245 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 3246 } 3247 3248 for (i = 0 ; i < ohci->n_it ; i++) { 3249 ctx = &ohci->it_context_list[i]; 3250 if (ctx->context.running) 3251 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 3252 } 3253 } 3254 #endif 3255 queue_iso_transmit(struct iso_context * ctx,struct fw_iso_packet * packet,struct fw_iso_buffer * buffer,unsigned long payload)3256 static int queue_iso_transmit(struct iso_context *ctx, 3257 struct fw_iso_packet *packet, 3258 struct fw_iso_buffer *buffer, 3259 unsigned long payload) 3260 { 3261 struct descriptor *d, *last, *pd; 3262 struct fw_iso_packet *p; 3263 __le32 *header; 3264 dma_addr_t d_bus, page_bus; 3265 u32 z, header_z, payload_z, irq; 3266 u32 payload_index, payload_end_index, next_page_index; 3267 int page, end_page, i, length, offset; 3268 3269 p = packet; 3270 payload_index = payload; 3271 3272 if (p->skip) 3273 z = 1; 3274 else 3275 z = 2; 3276 if (p->header_length > 0) 3277 z++; 3278 3279 /* Determine the first page the payload isn't contained in. */ 3280 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; 3281 if (p->payload_length > 0) 3282 payload_z = end_page - (payload_index >> PAGE_SHIFT); 3283 else 3284 payload_z = 0; 3285 3286 z += payload_z; 3287 3288 /* Get header size in number of descriptors. */ 3289 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d)); 3290 3291 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); 3292 if (d == NULL) 3293 return -ENOMEM; 3294 3295 if (!p->skip) { 3296 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 3297 d[0].req_count = cpu_to_le16(8); 3298 /* 3299 * Link the skip address to this descriptor itself. This causes 3300 * a context to skip a cycle whenever lost cycles or FIFO 3301 * overruns occur, without dropping the data. The application 3302 * should then decide whether this is an error condition or not. 3303 * FIXME: Make the context's cycle-lost behaviour configurable? 3304 */ 3305 d[0].branch_address = cpu_to_le32(d_bus | z); 3306 3307 header = (__le32 *) &d[1]; 3308 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) | 3309 IT_HEADER_TAG(p->tag) | 3310 IT_HEADER_TCODE(TCODE_STREAM_DATA) | 3311 IT_HEADER_CHANNEL(ctx->base.channel) | 3312 IT_HEADER_SPEED(ctx->base.speed)); 3313 header[1] = 3314 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length + 3315 p->payload_length)); 3316 } 3317 3318 if (p->header_length > 0) { 3319 d[2].req_count = cpu_to_le16(p->header_length); 3320 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d)); 3321 memcpy(&d[z], p->header, p->header_length); 3322 } 3323 3324 pd = d + z - payload_z; 3325 payload_end_index = payload_index + p->payload_length; 3326 for (i = 0; i < payload_z; i++) { 3327 page = payload_index >> PAGE_SHIFT; 3328 offset = payload_index & ~PAGE_MASK; 3329 next_page_index = (page + 1) << PAGE_SHIFT; 3330 length = 3331 min(next_page_index, payload_end_index) - payload_index; 3332 pd[i].req_count = cpu_to_le16(length); 3333 3334 page_bus = page_private(buffer->pages[page]); 3335 pd[i].data_address = cpu_to_le32(page_bus + offset); 3336 3337 dma_sync_single_range_for_device(ctx->context.ohci->card.device, 3338 page_bus, offset, length, 3339 DMA_TO_DEVICE); 3340 3341 payload_index += length; 3342 } 3343 3344 if (p->interrupt) 3345 irq = DESCRIPTOR_IRQ_ALWAYS; 3346 else 3347 irq = DESCRIPTOR_NO_IRQ; 3348 3349 last = z == 2 ? d : d + z - 1; 3350 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 3351 DESCRIPTOR_STATUS | 3352 DESCRIPTOR_BRANCH_ALWAYS | 3353 irq); 3354 3355 context_append(&ctx->context, d, z, header_z); 3356 3357 return 0; 3358 } 3359 queue_iso_packet_per_buffer(struct iso_context * ctx,struct fw_iso_packet * packet,struct fw_iso_buffer * buffer,unsigned long payload)3360 static int queue_iso_packet_per_buffer(struct iso_context *ctx, 3361 struct fw_iso_packet *packet, 3362 struct fw_iso_buffer *buffer, 3363 unsigned long payload) 3364 { 3365 struct device *device = ctx->context.ohci->card.device; 3366 struct descriptor *d, *pd; 3367 dma_addr_t d_bus, page_bus; 3368 u32 z, header_z, rest; 3369 int i, j, length; 3370 int page, offset, packet_count, header_size, payload_per_buffer; 3371 3372 /* 3373 * The OHCI controller puts the isochronous header and trailer in the 3374 * buffer, so we need at least 8 bytes. 3375 */ 3376 packet_count = packet->header_length / ctx->base.header_size; 3377 header_size = max(ctx->base.header_size, (size_t)8); 3378 3379 /* Get header size in number of descriptors. */ 3380 header_z = DIV_ROUND_UP(header_size, sizeof(*d)); 3381 page = payload >> PAGE_SHIFT; 3382 offset = payload & ~PAGE_MASK; 3383 payload_per_buffer = packet->payload_length / packet_count; 3384 3385 for (i = 0; i < packet_count; i++) { 3386 /* d points to the header descriptor */ 3387 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1; 3388 d = context_get_descriptors(&ctx->context, 3389 z + header_z, &d_bus); 3390 if (d == NULL) 3391 return -ENOMEM; 3392 3393 d->control = cpu_to_le16(DESCRIPTOR_STATUS | 3394 DESCRIPTOR_INPUT_MORE); 3395 if (packet->skip && i == 0) 3396 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3397 d->req_count = cpu_to_le16(header_size); 3398 d->res_count = d->req_count; 3399 d->transfer_status = 0; 3400 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d))); 3401 3402 rest = payload_per_buffer; 3403 pd = d; 3404 for (j = 1; j < z; j++) { 3405 pd++; 3406 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3407 DESCRIPTOR_INPUT_MORE); 3408 3409 if (offset + rest < PAGE_SIZE) 3410 length = rest; 3411 else 3412 length = PAGE_SIZE - offset; 3413 pd->req_count = cpu_to_le16(length); 3414 pd->res_count = pd->req_count; 3415 pd->transfer_status = 0; 3416 3417 page_bus = page_private(buffer->pages[page]); 3418 pd->data_address = cpu_to_le32(page_bus + offset); 3419 3420 dma_sync_single_range_for_device(device, page_bus, 3421 offset, length, 3422 DMA_FROM_DEVICE); 3423 3424 offset = (offset + length) & ~PAGE_MASK; 3425 rest -= length; 3426 if (offset == 0) 3427 page++; 3428 } 3429 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3430 DESCRIPTOR_INPUT_LAST | 3431 DESCRIPTOR_BRANCH_ALWAYS); 3432 if (packet->interrupt && i == packet_count - 1) 3433 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3434 3435 context_append(&ctx->context, d, z, header_z); 3436 } 3437 3438 return 0; 3439 } 3440 queue_iso_buffer_fill(struct iso_context * ctx,struct fw_iso_packet * packet,struct fw_iso_buffer * buffer,unsigned long payload)3441 static int queue_iso_buffer_fill(struct iso_context *ctx, 3442 struct fw_iso_packet *packet, 3443 struct fw_iso_buffer *buffer, 3444 unsigned long payload) 3445 { 3446 struct descriptor *d; 3447 dma_addr_t d_bus, page_bus; 3448 int page, offset, rest, z, i, length; 3449 3450 page = payload >> PAGE_SHIFT; 3451 offset = payload & ~PAGE_MASK; 3452 rest = packet->payload_length; 3453 3454 /* We need one descriptor for each page in the buffer. */ 3455 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE); 3456 3457 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count)) 3458 return -EFAULT; 3459 3460 for (i = 0; i < z; i++) { 3461 d = context_get_descriptors(&ctx->context, 1, &d_bus); 3462 if (d == NULL) 3463 return -ENOMEM; 3464 3465 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 3466 DESCRIPTOR_BRANCH_ALWAYS); 3467 if (packet->skip && i == 0) 3468 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3469 if (packet->interrupt && i == z - 1) 3470 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3471 3472 if (offset + rest < PAGE_SIZE) 3473 length = rest; 3474 else 3475 length = PAGE_SIZE - offset; 3476 d->req_count = cpu_to_le16(length); 3477 d->res_count = d->req_count; 3478 d->transfer_status = 0; 3479 3480 page_bus = page_private(buffer->pages[page]); 3481 d->data_address = cpu_to_le32(page_bus + offset); 3482 3483 dma_sync_single_range_for_device(ctx->context.ohci->card.device, 3484 page_bus, offset, length, 3485 DMA_FROM_DEVICE); 3486 3487 rest -= length; 3488 offset = 0; 3489 page++; 3490 3491 context_append(&ctx->context, d, 1, 0); 3492 } 3493 3494 return 0; 3495 } 3496 ohci_queue_iso(struct fw_iso_context * base,struct fw_iso_packet * packet,struct fw_iso_buffer * buffer,unsigned long payload)3497 static int ohci_queue_iso(struct fw_iso_context *base, 3498 struct fw_iso_packet *packet, 3499 struct fw_iso_buffer *buffer, 3500 unsigned long payload) 3501 { 3502 struct iso_context *ctx = container_of(base, struct iso_context, base); 3503 unsigned long flags; 3504 int ret = -ENOSYS; 3505 3506 spin_lock_irqsave(&ctx->context.ohci->lock, flags); 3507 switch (base->type) { 3508 case FW_ISO_CONTEXT_TRANSMIT: 3509 ret = queue_iso_transmit(ctx, packet, buffer, payload); 3510 break; 3511 case FW_ISO_CONTEXT_RECEIVE: 3512 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload); 3513 break; 3514 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3515 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload); 3516 break; 3517 } 3518 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags); 3519 3520 return ret; 3521 } 3522 ohci_flush_queue_iso(struct fw_iso_context * base)3523 static void ohci_flush_queue_iso(struct fw_iso_context *base) 3524 { 3525 struct context *ctx = 3526 &container_of(base, struct iso_context, base)->context; 3527 3528 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 3529 } 3530 ohci_flush_iso_completions(struct fw_iso_context * base)3531 static int ohci_flush_iso_completions(struct fw_iso_context *base) 3532 { 3533 struct iso_context *ctx = container_of(base, struct iso_context, base); 3534 int ret = 0; 3535 3536 tasklet_disable_in_atomic(&ctx->context.tasklet); 3537 3538 if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) { 3539 context_tasklet((unsigned long)&ctx->context); 3540 3541 switch (base->type) { 3542 case FW_ISO_CONTEXT_TRANSMIT: 3543 case FW_ISO_CONTEXT_RECEIVE: 3544 if (ctx->header_length != 0) 3545 flush_iso_completions(ctx); 3546 break; 3547 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3548 if (ctx->mc_completed != 0) 3549 flush_ir_buffer_fill(ctx); 3550 break; 3551 default: 3552 ret = -ENOSYS; 3553 } 3554 3555 clear_bit_unlock(0, &ctx->flushing_completions); 3556 smp_mb__after_atomic(); 3557 } 3558 3559 tasklet_enable(&ctx->context.tasklet); 3560 3561 return ret; 3562 } 3563 3564 static const struct fw_card_driver ohci_driver = { 3565 .enable = ohci_enable, 3566 .read_phy_reg = ohci_read_phy_reg, 3567 .update_phy_reg = ohci_update_phy_reg, 3568 .set_config_rom = ohci_set_config_rom, 3569 .send_request = ohci_send_request, 3570 .send_response = ohci_send_response, 3571 .cancel_packet = ohci_cancel_packet, 3572 .enable_phys_dma = ohci_enable_phys_dma, 3573 .read_csr = ohci_read_csr, 3574 .write_csr = ohci_write_csr, 3575 3576 .allocate_iso_context = ohci_allocate_iso_context, 3577 .free_iso_context = ohci_free_iso_context, 3578 .set_iso_channels = ohci_set_iso_channels, 3579 .queue_iso = ohci_queue_iso, 3580 .flush_queue_iso = ohci_flush_queue_iso, 3581 .flush_iso_completions = ohci_flush_iso_completions, 3582 .start_iso = ohci_start_iso, 3583 .stop_iso = ohci_stop_iso, 3584 }; 3585 3586 #ifdef CONFIG_PPC_PMAC pmac_ohci_on(struct pci_dev * dev)3587 static void pmac_ohci_on(struct pci_dev *dev) 3588 { 3589 if (machine_is(powermac)) { 3590 struct device_node *ofn = pci_device_to_OF_node(dev); 3591 3592 if (ofn) { 3593 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1); 3594 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1); 3595 } 3596 } 3597 } 3598 pmac_ohci_off(struct pci_dev * dev)3599 static void pmac_ohci_off(struct pci_dev *dev) 3600 { 3601 if (machine_is(powermac)) { 3602 struct device_node *ofn = pci_device_to_OF_node(dev); 3603 3604 if (ofn) { 3605 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0); 3606 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0); 3607 } 3608 } 3609 } 3610 #else pmac_ohci_on(struct pci_dev * dev)3611 static inline void pmac_ohci_on(struct pci_dev *dev) {} pmac_ohci_off(struct pci_dev * dev)3612 static inline void pmac_ohci_off(struct pci_dev *dev) {} 3613 #endif /* CONFIG_PPC_PMAC */ 3614 release_ohci(struct device * dev,void * data)3615 static void release_ohci(struct device *dev, void *data) 3616 { 3617 struct pci_dev *pdev = to_pci_dev(dev); 3618 struct fw_ohci *ohci = pci_get_drvdata(pdev); 3619 3620 pmac_ohci_off(pdev); 3621 3622 ar_context_release(&ohci->ar_response_ctx); 3623 ar_context_release(&ohci->ar_request_ctx); 3624 3625 dev_notice(dev, "removed fw-ohci device\n"); 3626 } 3627 pci_probe(struct pci_dev * dev,const struct pci_device_id * ent)3628 static int pci_probe(struct pci_dev *dev, 3629 const struct pci_device_id *ent) 3630 { 3631 struct fw_ohci *ohci; 3632 u32 bus_options, max_receive, link_speed, version; 3633 u64 guid; 3634 int i, err; 3635 size_t size; 3636 3637 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) { 3638 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n"); 3639 return -ENOSYS; 3640 } 3641 3642 ohci = devres_alloc(release_ohci, sizeof(*ohci), GFP_KERNEL); 3643 if (ohci == NULL) 3644 return -ENOMEM; 3645 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); 3646 pci_set_drvdata(dev, ohci); 3647 pmac_ohci_on(dev); 3648 devres_add(&dev->dev, ohci); 3649 3650 err = pcim_enable_device(dev); 3651 if (err) { 3652 dev_err(&dev->dev, "failed to enable OHCI hardware\n"); 3653 return err; 3654 } 3655 3656 pci_set_master(dev); 3657 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); 3658 3659 spin_lock_init(&ohci->lock); 3660 mutex_init(&ohci->phy_reg_mutex); 3661 3662 INIT_WORK(&ohci->bus_reset_work, bus_reset_work); 3663 3664 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) || 3665 pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) { 3666 ohci_err(ohci, "invalid MMIO resource\n"); 3667 return -ENXIO; 3668 } 3669 3670 err = pcim_iomap_regions(dev, 1 << 0, ohci_driver_name); 3671 if (err) { 3672 ohci_err(ohci, "request and map MMIO resource unavailable\n"); 3673 return -ENXIO; 3674 } 3675 ohci->registers = pcim_iomap_table(dev)[0]; 3676 3677 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++) 3678 if ((ohci_quirks[i].vendor == dev->vendor) && 3679 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID || 3680 ohci_quirks[i].device == dev->device) && 3681 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID || 3682 ohci_quirks[i].revision >= dev->revision)) { 3683 ohci->quirks = ohci_quirks[i].flags; 3684 break; 3685 } 3686 if (param_quirks) 3687 ohci->quirks = param_quirks; 3688 3689 if (detect_vt630x_with_asm1083_on_amd_ryzen_machine(dev)) 3690 ohci->quirks |= QUIRK_REBOOT_BY_CYCLE_TIMER_READ; 3691 3692 /* 3693 * Because dma_alloc_coherent() allocates at least one page, 3694 * we save space by using a common buffer for the AR request/ 3695 * response descriptors and the self IDs buffer. 3696 */ 3697 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4); 3698 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2); 3699 ohci->misc_buffer = dmam_alloc_coherent(&dev->dev, PAGE_SIZE, &ohci->misc_buffer_bus, 3700 GFP_KERNEL); 3701 if (!ohci->misc_buffer) 3702 return -ENOMEM; 3703 3704 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0, 3705 OHCI1394_AsReqRcvContextControlSet); 3706 if (err < 0) 3707 return err; 3708 3709 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4, 3710 OHCI1394_AsRspRcvContextControlSet); 3711 if (err < 0) 3712 return err; 3713 3714 err = context_init(&ohci->at_request_ctx, ohci, 3715 OHCI1394_AsReqTrContextControlSet, handle_at_packet); 3716 if (err < 0) 3717 return err; 3718 3719 err = context_init(&ohci->at_response_ctx, ohci, 3720 OHCI1394_AsRspTrContextControlSet, handle_at_packet); 3721 if (err < 0) 3722 return err; 3723 3724 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); 3725 ohci->ir_context_channels = ~0ULL; 3726 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); 3727 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); 3728 ohci->ir_context_mask = ohci->ir_context_support; 3729 ohci->n_ir = hweight32(ohci->ir_context_mask); 3730 size = sizeof(struct iso_context) * ohci->n_ir; 3731 ohci->ir_context_list = devm_kzalloc(&dev->dev, size, GFP_KERNEL); 3732 if (!ohci->ir_context_list) 3733 return -ENOMEM; 3734 3735 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); 3736 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); 3737 /* JMicron JMB38x often shows 0 at first read, just ignore it */ 3738 if (!ohci->it_context_support) { 3739 ohci_notice(ohci, "overriding IsoXmitIntMask\n"); 3740 ohci->it_context_support = 0xf; 3741 } 3742 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); 3743 ohci->it_context_mask = ohci->it_context_support; 3744 ohci->n_it = hweight32(ohci->it_context_mask); 3745 size = sizeof(struct iso_context) * ohci->n_it; 3746 ohci->it_context_list = devm_kzalloc(&dev->dev, size, GFP_KERNEL); 3747 if (!ohci->it_context_list) 3748 return -ENOMEM; 3749 3750 ohci->self_id = ohci->misc_buffer + PAGE_SIZE/2; 3751 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2; 3752 3753 bus_options = reg_read(ohci, OHCI1394_BusOptions); 3754 max_receive = (bus_options >> 12) & 0xf; 3755 link_speed = bus_options & 0x7; 3756 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | 3757 reg_read(ohci, OHCI1394_GUIDLo); 3758 3759 if (!(ohci->quirks & QUIRK_NO_MSI)) 3760 pci_enable_msi(dev); 3761 err = devm_request_irq(&dev->dev, dev->irq, irq_handler, 3762 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED, ohci_driver_name, ohci); 3763 if (err < 0) { 3764 ohci_err(ohci, "failed to allocate interrupt %d\n", dev->irq); 3765 goto fail_msi; 3766 } 3767 3768 err = fw_card_add(&ohci->card, max_receive, link_speed, guid); 3769 if (err) 3770 goto fail_msi; 3771 3772 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 3773 ohci_notice(ohci, 3774 "added OHCI v%x.%x device as card %d, " 3775 "%d IR + %d IT contexts, quirks 0x%x%s\n", 3776 version >> 16, version & 0xff, ohci->card.index, 3777 ohci->n_ir, ohci->n_it, ohci->quirks, 3778 reg_read(ohci, OHCI1394_PhyUpperBound) ? 3779 ", physUB" : ""); 3780 3781 return 0; 3782 3783 fail_msi: 3784 devm_free_irq(&dev->dev, dev->irq, ohci); 3785 pci_disable_msi(dev); 3786 3787 return err; 3788 } 3789 pci_remove(struct pci_dev * dev)3790 static void pci_remove(struct pci_dev *dev) 3791 { 3792 struct fw_ohci *ohci = pci_get_drvdata(dev); 3793 3794 /* 3795 * If the removal is happening from the suspend state, LPS won't be 3796 * enabled and host registers (eg., IntMaskClear) won't be accessible. 3797 */ 3798 if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) { 3799 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 3800 flush_writes(ohci); 3801 } 3802 cancel_work_sync(&ohci->bus_reset_work); 3803 fw_core_remove_card(&ohci->card); 3804 3805 /* 3806 * FIXME: Fail all pending packets here, now that the upper 3807 * layers can't queue any more. 3808 */ 3809 3810 software_reset(ohci); 3811 3812 devm_free_irq(&dev->dev, dev->irq, ohci); 3813 pci_disable_msi(dev); 3814 3815 dev_notice(&dev->dev, "removing fw-ohci device\n"); 3816 } 3817 3818 #ifdef CONFIG_PM pci_suspend(struct pci_dev * dev,pm_message_t state)3819 static int pci_suspend(struct pci_dev *dev, pm_message_t state) 3820 { 3821 struct fw_ohci *ohci = pci_get_drvdata(dev); 3822 int err; 3823 3824 software_reset(ohci); 3825 err = pci_save_state(dev); 3826 if (err) { 3827 ohci_err(ohci, "pci_save_state failed\n"); 3828 return err; 3829 } 3830 err = pci_set_power_state(dev, pci_choose_state(dev, state)); 3831 if (err) 3832 ohci_err(ohci, "pci_set_power_state failed with %d\n", err); 3833 pmac_ohci_off(dev); 3834 3835 return 0; 3836 } 3837 pci_resume(struct pci_dev * dev)3838 static int pci_resume(struct pci_dev *dev) 3839 { 3840 struct fw_ohci *ohci = pci_get_drvdata(dev); 3841 int err; 3842 3843 pmac_ohci_on(dev); 3844 pci_set_power_state(dev, PCI_D0); 3845 pci_restore_state(dev); 3846 err = pci_enable_device(dev); 3847 if (err) { 3848 ohci_err(ohci, "pci_enable_device failed\n"); 3849 return err; 3850 } 3851 3852 /* Some systems don't setup GUID register on resume from ram */ 3853 if (!reg_read(ohci, OHCI1394_GUIDLo) && 3854 !reg_read(ohci, OHCI1394_GUIDHi)) { 3855 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid); 3856 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32)); 3857 } 3858 3859 err = ohci_enable(&ohci->card, NULL, 0); 3860 if (err) 3861 return err; 3862 3863 ohci_resume_iso_dma(ohci); 3864 3865 return 0; 3866 } 3867 #endif 3868 3869 static const struct pci_device_id pci_table[] = { 3870 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, 3871 { } 3872 }; 3873 3874 MODULE_DEVICE_TABLE(pci, pci_table); 3875 3876 static struct pci_driver fw_ohci_pci_driver = { 3877 .name = ohci_driver_name, 3878 .id_table = pci_table, 3879 .probe = pci_probe, 3880 .remove = pci_remove, 3881 #ifdef CONFIG_PM 3882 .resume = pci_resume, 3883 .suspend = pci_suspend, 3884 #endif 3885 }; 3886 fw_ohci_init(void)3887 static int __init fw_ohci_init(void) 3888 { 3889 selfid_workqueue = alloc_workqueue(KBUILD_MODNAME, WQ_MEM_RECLAIM, 0); 3890 if (!selfid_workqueue) 3891 return -ENOMEM; 3892 3893 return pci_register_driver(&fw_ohci_pci_driver); 3894 } 3895 fw_ohci_cleanup(void)3896 static void __exit fw_ohci_cleanup(void) 3897 { 3898 pci_unregister_driver(&fw_ohci_pci_driver); 3899 destroy_workqueue(selfid_workqueue); 3900 } 3901 3902 module_init(fw_ohci_init); 3903 module_exit(fw_ohci_cleanup); 3904 3905 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); 3906 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); 3907 MODULE_LICENSE("GPL"); 3908 3909 /* Provide a module alias so root-on-sbp2 initrds don't break. */ 3910 MODULE_ALIAS("ohci1394"); 3911