1 /* 2 * Extcon charger detection driver for Intel Cherrytrail Whiskey Cove PMIC 3 * Copyright (C) 2017 Hans de Goede <hdegoede@redhat.com> 4 * 5 * Based on various non upstream patches to support the CHT Whiskey Cove PMIC: 6 * Copyright (C) 2013-2015 Intel Corporation. All rights reserved. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 */ 17 18 #include <linux/extcon.h> 19 #include <linux/interrupt.h> 20 #include <linux/kernel.h> 21 #include <linux/mfd/intel_soc_pmic.h> 22 #include <linux/module.h> 23 #include <linux/platform_device.h> 24 #include <linux/regmap.h> 25 #include <linux/slab.h> 26 27 #define CHT_WC_PHYCTRL 0x5e07 28 29 #define CHT_WC_CHGRCTRL0 0x5e16 30 #define CHT_WC_CHGRCTRL0_CHGRRESET BIT(0) 31 #define CHT_WC_CHGRCTRL0_EMRGCHREN BIT(1) 32 #define CHT_WC_CHGRCTRL0_EXTCHRDIS BIT(2) 33 #define CHT_WC_CHGRCTRL0_SWCONTROL BIT(3) 34 #define CHT_WC_CHGRCTRL0_TTLCK_MASK BIT(4) 35 #define CHT_WC_CHGRCTRL0_CCSM_OFF_MASK BIT(5) 36 #define CHT_WC_CHGRCTRL0_DBPOFF_MASK BIT(6) 37 #define CHT_WC_CHGRCTRL0_WDT_NOKICK BIT(7) 38 39 #define CHT_WC_CHGRCTRL1 0x5e17 40 41 #define CHT_WC_USBSRC 0x5e29 42 #define CHT_WC_USBSRC_STS_MASK GENMASK(1, 0) 43 #define CHT_WC_USBSRC_STS_SUCCESS 2 44 #define CHT_WC_USBSRC_STS_FAIL 3 45 #define CHT_WC_USBSRC_TYPE_SHIFT 2 46 #define CHT_WC_USBSRC_TYPE_MASK GENMASK(5, 2) 47 #define CHT_WC_USBSRC_TYPE_NONE 0 48 #define CHT_WC_USBSRC_TYPE_SDP 1 49 #define CHT_WC_USBSRC_TYPE_DCP 2 50 #define CHT_WC_USBSRC_TYPE_CDP 3 51 #define CHT_WC_USBSRC_TYPE_ACA 4 52 #define CHT_WC_USBSRC_TYPE_SE1 5 53 #define CHT_WC_USBSRC_TYPE_MHL 6 54 #define CHT_WC_USBSRC_TYPE_FLOAT_DP_DN 7 55 #define CHT_WC_USBSRC_TYPE_OTHER 8 56 #define CHT_WC_USBSRC_TYPE_DCP_EXTPHY 9 57 58 #define CHT_WC_PWRSRC_IRQ 0x6e03 59 #define CHT_WC_PWRSRC_IRQ_MASK 0x6e0f 60 #define CHT_WC_PWRSRC_STS 0x6e1e 61 #define CHT_WC_PWRSRC_VBUS BIT(0) 62 #define CHT_WC_PWRSRC_DC BIT(1) 63 #define CHT_WC_PWRSRC_BAT BIT(2) 64 #define CHT_WC_PWRSRC_ID_GND BIT(3) 65 #define CHT_WC_PWRSRC_ID_FLOAT BIT(4) 66 67 #define CHT_WC_VBUS_GPIO_CTLO 0x6e2d 68 #define CHT_WC_VBUS_GPIO_CTLO_OUTPUT BIT(0) 69 70 enum cht_wc_usb_id { 71 USB_ID_OTG, 72 USB_ID_GND, 73 USB_ID_FLOAT, 74 USB_RID_A, 75 USB_RID_B, 76 USB_RID_C, 77 }; 78 79 enum cht_wc_mux_select { 80 MUX_SEL_PMIC = 0, 81 MUX_SEL_SOC, 82 }; 83 84 static const unsigned int cht_wc_extcon_cables[] = { 85 EXTCON_USB, 86 EXTCON_USB_HOST, 87 EXTCON_CHG_USB_SDP, 88 EXTCON_CHG_USB_CDP, 89 EXTCON_CHG_USB_DCP, 90 EXTCON_CHG_USB_ACA, 91 EXTCON_NONE, 92 }; 93 94 struct cht_wc_extcon_data { 95 struct device *dev; 96 struct regmap *regmap; 97 struct extcon_dev *edev; 98 unsigned int previous_cable; 99 bool usb_host; 100 }; 101 102 static int cht_wc_extcon_get_id(struct cht_wc_extcon_data *ext, int pwrsrc_sts) 103 { 104 if (pwrsrc_sts & CHT_WC_PWRSRC_ID_GND) 105 return USB_ID_GND; 106 if (pwrsrc_sts & CHT_WC_PWRSRC_ID_FLOAT) 107 return USB_ID_FLOAT; 108 109 /* 110 * Once we have iio support for the gpadc we should read the USBID 111 * gpadc channel here and determine ACA role based on that. 112 */ 113 return USB_ID_FLOAT; 114 } 115 116 static int cht_wc_extcon_get_charger(struct cht_wc_extcon_data *ext, 117 bool ignore_errors) 118 { 119 int ret, usbsrc, status; 120 unsigned long timeout; 121 122 /* Charger detection can take upto 600ms, wait 800ms max. */ 123 timeout = jiffies + msecs_to_jiffies(800); 124 do { 125 ret = regmap_read(ext->regmap, CHT_WC_USBSRC, &usbsrc); 126 if (ret) { 127 dev_err(ext->dev, "Error reading usbsrc: %d\n", ret); 128 return ret; 129 } 130 131 status = usbsrc & CHT_WC_USBSRC_STS_MASK; 132 if (status == CHT_WC_USBSRC_STS_SUCCESS || 133 status == CHT_WC_USBSRC_STS_FAIL) 134 break; 135 136 msleep(50); /* Wait a bit before retrying */ 137 } while (time_before(jiffies, timeout)); 138 139 if (status != CHT_WC_USBSRC_STS_SUCCESS) { 140 if (ignore_errors) 141 return EXTCON_CHG_USB_SDP; /* Save fallback */ 142 143 if (status == CHT_WC_USBSRC_STS_FAIL) 144 dev_warn(ext->dev, "Could not detect charger type\n"); 145 else 146 dev_warn(ext->dev, "Timeout detecting charger type\n"); 147 return EXTCON_CHG_USB_SDP; /* Save fallback */ 148 } 149 150 usbsrc = (usbsrc & CHT_WC_USBSRC_TYPE_MASK) >> CHT_WC_USBSRC_TYPE_SHIFT; 151 switch (usbsrc) { 152 default: 153 dev_warn(ext->dev, 154 "Unhandled charger type %d, defaulting to SDP\n", 155 ret); 156 /* Fall through, treat as SDP */ 157 case CHT_WC_USBSRC_TYPE_SDP: 158 case CHT_WC_USBSRC_TYPE_FLOAT_DP_DN: 159 case CHT_WC_USBSRC_TYPE_OTHER: 160 return EXTCON_CHG_USB_SDP; 161 case CHT_WC_USBSRC_TYPE_CDP: 162 return EXTCON_CHG_USB_CDP; 163 case CHT_WC_USBSRC_TYPE_DCP: 164 case CHT_WC_USBSRC_TYPE_DCP_EXTPHY: 165 case CHT_WC_USBSRC_TYPE_MHL: /* MHL2+ delivers upto 2A, treat as DCP */ 166 return EXTCON_CHG_USB_DCP; 167 case CHT_WC_USBSRC_TYPE_ACA: 168 return EXTCON_CHG_USB_ACA; 169 } 170 } 171 172 static void cht_wc_extcon_set_phymux(struct cht_wc_extcon_data *ext, u8 state) 173 { 174 int ret; 175 176 ret = regmap_write(ext->regmap, CHT_WC_PHYCTRL, state); 177 if (ret) 178 dev_err(ext->dev, "Error writing phyctrl: %d\n", ret); 179 } 180 181 static void cht_wc_extcon_set_5v_boost(struct cht_wc_extcon_data *ext, 182 bool enable) 183 { 184 int ret, val; 185 186 val = enable ? CHT_WC_VBUS_GPIO_CTLO_OUTPUT : 0; 187 188 /* 189 * The 5V boost converter is enabled through a gpio on the PMIC, since 190 * there currently is no gpio driver we access the gpio reg directly. 191 */ 192 ret = regmap_update_bits(ext->regmap, CHT_WC_VBUS_GPIO_CTLO, 193 CHT_WC_VBUS_GPIO_CTLO_OUTPUT, val); 194 if (ret) 195 dev_err(ext->dev, "Error writing Vbus GPIO CTLO: %d\n", ret); 196 } 197 198 /* Small helper to sync EXTCON_CHG_USB_SDP and EXTCON_USB state */ 199 static void cht_wc_extcon_set_state(struct cht_wc_extcon_data *ext, 200 unsigned int cable, bool state) 201 { 202 extcon_set_state_sync(ext->edev, cable, state); 203 if (cable == EXTCON_CHG_USB_SDP) 204 extcon_set_state_sync(ext->edev, EXTCON_USB, state); 205 } 206 207 static void cht_wc_extcon_pwrsrc_event(struct cht_wc_extcon_data *ext) 208 { 209 int ret, pwrsrc_sts, id; 210 unsigned int cable = EXTCON_NONE; 211 /* Ignore errors in host mode, as the 5v boost converter is on then */ 212 bool ignore_get_charger_errors = ext->usb_host; 213 214 ret = regmap_read(ext->regmap, CHT_WC_PWRSRC_STS, &pwrsrc_sts); 215 if (ret) { 216 dev_err(ext->dev, "Error reading pwrsrc status: %d\n", ret); 217 return; 218 } 219 220 id = cht_wc_extcon_get_id(ext, pwrsrc_sts); 221 if (id == USB_ID_GND) { 222 /* The 5v boost causes a false VBUS / SDP detect, skip */ 223 goto charger_det_done; 224 } 225 226 /* Plugged into a host/charger or not connected? */ 227 if (!(pwrsrc_sts & CHT_WC_PWRSRC_VBUS)) { 228 /* Route D+ and D- to PMIC for future charger detection */ 229 cht_wc_extcon_set_phymux(ext, MUX_SEL_PMIC); 230 goto set_state; 231 } 232 233 ret = cht_wc_extcon_get_charger(ext, ignore_get_charger_errors); 234 if (ret >= 0) 235 cable = ret; 236 237 charger_det_done: 238 /* Route D+ and D- to SoC for the host or gadget controller */ 239 cht_wc_extcon_set_phymux(ext, MUX_SEL_SOC); 240 241 set_state: 242 if (cable != ext->previous_cable) { 243 cht_wc_extcon_set_state(ext, cable, true); 244 cht_wc_extcon_set_state(ext, ext->previous_cable, false); 245 ext->previous_cable = cable; 246 } 247 248 ext->usb_host = ((id == USB_ID_GND) || (id == USB_RID_A)); 249 extcon_set_state_sync(ext->edev, EXTCON_USB_HOST, ext->usb_host); 250 } 251 252 static irqreturn_t cht_wc_extcon_isr(int irq, void *data) 253 { 254 struct cht_wc_extcon_data *ext = data; 255 int ret, irqs; 256 257 ret = regmap_read(ext->regmap, CHT_WC_PWRSRC_IRQ, &irqs); 258 if (ret) { 259 dev_err(ext->dev, "Error reading irqs: %d\n", ret); 260 return IRQ_NONE; 261 } 262 263 cht_wc_extcon_pwrsrc_event(ext); 264 265 ret = regmap_write(ext->regmap, CHT_WC_PWRSRC_IRQ, irqs); 266 if (ret) { 267 dev_err(ext->dev, "Error writing irqs: %d\n", ret); 268 return IRQ_NONE; 269 } 270 271 return IRQ_HANDLED; 272 } 273 274 static int cht_wc_extcon_sw_control(struct cht_wc_extcon_data *ext, bool enable) 275 { 276 int ret, mask, val; 277 278 mask = CHT_WC_CHGRCTRL0_SWCONTROL | CHT_WC_CHGRCTRL0_CCSM_OFF_MASK; 279 val = enable ? mask : 0; 280 ret = regmap_update_bits(ext->regmap, CHT_WC_CHGRCTRL0, mask, val); 281 if (ret) 282 dev_err(ext->dev, "Error setting sw control: %d\n", ret); 283 284 return ret; 285 } 286 287 static int cht_wc_extcon_probe(struct platform_device *pdev) 288 { 289 struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent); 290 struct cht_wc_extcon_data *ext; 291 int irq, ret; 292 293 irq = platform_get_irq(pdev, 0); 294 if (irq < 0) 295 return irq; 296 297 ext = devm_kzalloc(&pdev->dev, sizeof(*ext), GFP_KERNEL); 298 if (!ext) 299 return -ENOMEM; 300 301 ext->dev = &pdev->dev; 302 ext->regmap = pmic->regmap; 303 ext->previous_cable = EXTCON_NONE; 304 305 /* Initialize extcon device */ 306 ext->edev = devm_extcon_dev_allocate(ext->dev, cht_wc_extcon_cables); 307 if (IS_ERR(ext->edev)) 308 return PTR_ERR(ext->edev); 309 310 /* 311 * When a host-cable is detected the BIOS enables an external 5v boost 312 * converter to power connected devices there are 2 problems with this: 313 * 1) This gets seen by the external battery charger as a valid Vbus 314 * supply and it then tries to feed Vsys from this creating a 315 * feedback loop which causes aprox. 300 mA extra battery drain 316 * (and unless we drive the external-charger-disable pin high it 317 * also tries to charge the battery causing even more feedback). 318 * 2) This gets seen by the pwrsrc block as a SDP USB Vbus supply 319 * Since the external battery charger has its own 5v boost converter 320 * which does not have these issues, we simply turn the separate 321 * external 5v boost converter off and leave it off entirely. 322 */ 323 cht_wc_extcon_set_5v_boost(ext, false); 324 325 /* Enable sw control */ 326 ret = cht_wc_extcon_sw_control(ext, true); 327 if (ret) 328 return ret; 329 330 /* Register extcon device */ 331 ret = devm_extcon_dev_register(ext->dev, ext->edev); 332 if (ret) { 333 dev_err(ext->dev, "Error registering extcon device: %d\n", ret); 334 goto disable_sw_control; 335 } 336 337 /* Route D+ and D- to PMIC for initial charger detection */ 338 cht_wc_extcon_set_phymux(ext, MUX_SEL_PMIC); 339 340 /* Get initial state */ 341 cht_wc_extcon_pwrsrc_event(ext); 342 343 ret = devm_request_threaded_irq(ext->dev, irq, NULL, cht_wc_extcon_isr, 344 IRQF_ONESHOT, pdev->name, ext); 345 if (ret) { 346 dev_err(ext->dev, "Error requesting interrupt: %d\n", ret); 347 goto disable_sw_control; 348 } 349 350 /* Unmask irqs */ 351 ret = regmap_write(ext->regmap, CHT_WC_PWRSRC_IRQ_MASK, 352 (int)~(CHT_WC_PWRSRC_VBUS | CHT_WC_PWRSRC_ID_GND | 353 CHT_WC_PWRSRC_ID_FLOAT)); 354 if (ret) { 355 dev_err(ext->dev, "Error writing irq-mask: %d\n", ret); 356 goto disable_sw_control; 357 } 358 359 platform_set_drvdata(pdev, ext); 360 361 return 0; 362 363 disable_sw_control: 364 cht_wc_extcon_sw_control(ext, false); 365 return ret; 366 } 367 368 static int cht_wc_extcon_remove(struct platform_device *pdev) 369 { 370 struct cht_wc_extcon_data *ext = platform_get_drvdata(pdev); 371 372 cht_wc_extcon_sw_control(ext, false); 373 374 return 0; 375 } 376 377 static const struct platform_device_id cht_wc_extcon_table[] = { 378 { .name = "cht_wcove_pwrsrc" }, 379 {}, 380 }; 381 MODULE_DEVICE_TABLE(platform, cht_wc_extcon_table); 382 383 static struct platform_driver cht_wc_extcon_driver = { 384 .probe = cht_wc_extcon_probe, 385 .remove = cht_wc_extcon_remove, 386 .id_table = cht_wc_extcon_table, 387 .driver = { 388 .name = "cht_wcove_pwrsrc", 389 }, 390 }; 391 module_platform_driver(cht_wc_extcon_driver); 392 393 MODULE_DESCRIPTION("Intel Cherrytrail Whiskey Cove PMIC extcon driver"); 394 MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>"); 395 MODULE_LICENSE("GPL v2"); 396