1 /* 2 * Synopsys DDR ECC Driver 3 * This driver is based on ppc4xx_edac.c drivers 4 * 5 * Copyright (C) 2012 - 2014 Xilinx, Inc. 6 * 7 * This program is free software: you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation, either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * This file is subject to the terms and conditions of the GNU General Public 18 * License. See the file "COPYING" in the main directory of this archive 19 * for more details 20 */ 21 22 #include <linux/edac.h> 23 #include <linux/module.h> 24 #include <linux/platform_device.h> 25 #include <linux/interrupt.h> 26 #include <linux/of.h> 27 #include <linux/of_device.h> 28 29 #include "edac_module.h" 30 31 /* Number of cs_rows needed per memory controller */ 32 #define SYNPS_EDAC_NR_CSROWS 1 33 34 /* Number of channels per memory controller */ 35 #define SYNPS_EDAC_NR_CHANS 1 36 37 /* Granularity of reported error in bytes */ 38 #define SYNPS_EDAC_ERR_GRAIN 1 39 40 #define SYNPS_EDAC_MSG_SIZE 256 41 42 #define SYNPS_EDAC_MOD_STRING "synps_edac" 43 #define SYNPS_EDAC_MOD_VER "1" 44 45 /* Synopsys DDR memory controller registers that are relevant to ECC */ 46 #define CTRL_OFST 0x0 47 #define T_ZQ_OFST 0xA4 48 49 /* ECC control register */ 50 #define ECC_CTRL_OFST 0xC4 51 /* ECC log register */ 52 #define CE_LOG_OFST 0xC8 53 /* ECC address register */ 54 #define CE_ADDR_OFST 0xCC 55 /* ECC data[31:0] register */ 56 #define CE_DATA_31_0_OFST 0xD0 57 58 /* Uncorrectable error info registers */ 59 #define UE_LOG_OFST 0xDC 60 #define UE_ADDR_OFST 0xE0 61 #define UE_DATA_31_0_OFST 0xE4 62 63 #define STAT_OFST 0xF0 64 #define SCRUB_OFST 0xF4 65 66 /* Control register bit field definitions */ 67 #define CTRL_BW_MASK 0xC 68 #define CTRL_BW_SHIFT 2 69 70 #define DDRCTL_WDTH_16 1 71 #define DDRCTL_WDTH_32 0 72 73 /* ZQ register bit field definitions */ 74 #define T_ZQ_DDRMODE_MASK 0x2 75 76 /* ECC control register bit field definitions */ 77 #define ECC_CTRL_CLR_CE_ERR 0x2 78 #define ECC_CTRL_CLR_UE_ERR 0x1 79 80 /* ECC correctable/uncorrectable error log register definitions */ 81 #define LOG_VALID 0x1 82 #define CE_LOG_BITPOS_MASK 0xFE 83 #define CE_LOG_BITPOS_SHIFT 1 84 85 /* ECC correctable/uncorrectable error address register definitions */ 86 #define ADDR_COL_MASK 0xFFF 87 #define ADDR_ROW_MASK 0xFFFF000 88 #define ADDR_ROW_SHIFT 12 89 #define ADDR_BANK_MASK 0x70000000 90 #define ADDR_BANK_SHIFT 28 91 92 /* ECC statistic register definitions */ 93 #define STAT_UECNT_MASK 0xFF 94 #define STAT_CECNT_MASK 0xFF00 95 #define STAT_CECNT_SHIFT 8 96 97 /* ECC scrub register definitions */ 98 #define SCRUB_MODE_MASK 0x7 99 #define SCRUB_MODE_SECDED 0x4 100 101 /* DDR ECC Quirks */ 102 #define DDR_ECC_INTR_SUPPORT BIT(0) 103 #define DDR_ECC_DATA_POISON_SUPPORT BIT(1) 104 105 /* ZynqMP Enhanced DDR memory controller registers that are relevant to ECC */ 106 /* ECC Configuration Registers */ 107 #define ECC_CFG0_OFST 0x70 108 #define ECC_CFG1_OFST 0x74 109 110 /* ECC Status Register */ 111 #define ECC_STAT_OFST 0x78 112 113 /* ECC Clear Register */ 114 #define ECC_CLR_OFST 0x7C 115 116 /* ECC Error count Register */ 117 #define ECC_ERRCNT_OFST 0x80 118 119 /* ECC Corrected Error Address Register */ 120 #define ECC_CEADDR0_OFST 0x84 121 #define ECC_CEADDR1_OFST 0x88 122 123 /* ECC Syndrome Registers */ 124 #define ECC_CSYND0_OFST 0x8C 125 #define ECC_CSYND1_OFST 0x90 126 #define ECC_CSYND2_OFST 0x94 127 128 /* ECC Bit Mask0 Address Register */ 129 #define ECC_BITMASK0_OFST 0x98 130 #define ECC_BITMASK1_OFST 0x9C 131 #define ECC_BITMASK2_OFST 0xA0 132 133 /* ECC UnCorrected Error Address Register */ 134 #define ECC_UEADDR0_OFST 0xA4 135 #define ECC_UEADDR1_OFST 0xA8 136 137 /* ECC Syndrome Registers */ 138 #define ECC_UESYND0_OFST 0xAC 139 #define ECC_UESYND1_OFST 0xB0 140 #define ECC_UESYND2_OFST 0xB4 141 142 /* ECC Poison Address Reg */ 143 #define ECC_POISON0_OFST 0xB8 144 #define ECC_POISON1_OFST 0xBC 145 146 #define ECC_ADDRMAP0_OFFSET 0x200 147 148 /* Control register bitfield definitions */ 149 #define ECC_CTRL_BUSWIDTH_MASK 0x3000 150 #define ECC_CTRL_BUSWIDTH_SHIFT 12 151 #define ECC_CTRL_CLR_CE_ERRCNT BIT(2) 152 #define ECC_CTRL_CLR_UE_ERRCNT BIT(3) 153 154 /* DDR Control Register width definitions */ 155 #define DDRCTL_EWDTH_16 2 156 #define DDRCTL_EWDTH_32 1 157 #define DDRCTL_EWDTH_64 0 158 159 /* ECC status register definitions */ 160 #define ECC_STAT_UECNT_MASK 0xF0000 161 #define ECC_STAT_UECNT_SHIFT 16 162 #define ECC_STAT_CECNT_MASK 0xF00 163 #define ECC_STAT_CECNT_SHIFT 8 164 #define ECC_STAT_BITNUM_MASK 0x7F 165 166 /* DDR QOS Interrupt register definitions */ 167 #define DDR_QOS_IRQ_STAT_OFST 0x20200 168 #define DDR_QOSUE_MASK 0x4 169 #define DDR_QOSCE_MASK 0x2 170 #define ECC_CE_UE_INTR_MASK 0x6 171 #define DDR_QOS_IRQ_EN_OFST 0x20208 172 #define DDR_QOS_IRQ_DB_OFST 0x2020C 173 174 /* ECC Corrected Error Register Mask and Shifts*/ 175 #define ECC_CEADDR0_RW_MASK 0x3FFFF 176 #define ECC_CEADDR0_RNK_MASK BIT(24) 177 #define ECC_CEADDR1_BNKGRP_MASK 0x3000000 178 #define ECC_CEADDR1_BNKNR_MASK 0x70000 179 #define ECC_CEADDR1_BLKNR_MASK 0xFFF 180 #define ECC_CEADDR1_BNKGRP_SHIFT 24 181 #define ECC_CEADDR1_BNKNR_SHIFT 16 182 183 /* ECC Poison register shifts */ 184 #define ECC_POISON0_RANK_SHIFT 24 185 #define ECC_POISON0_RANK_MASK BIT(24) 186 #define ECC_POISON0_COLUMN_SHIFT 0 187 #define ECC_POISON0_COLUMN_MASK 0xFFF 188 #define ECC_POISON1_BG_SHIFT 28 189 #define ECC_POISON1_BG_MASK 0x30000000 190 #define ECC_POISON1_BANKNR_SHIFT 24 191 #define ECC_POISON1_BANKNR_MASK 0x7000000 192 #define ECC_POISON1_ROW_SHIFT 0 193 #define ECC_POISON1_ROW_MASK 0x3FFFF 194 195 /* DDR Memory type defines */ 196 #define MEM_TYPE_DDR3 0x1 197 #define MEM_TYPE_LPDDR3 0x8 198 #define MEM_TYPE_DDR2 0x4 199 #define MEM_TYPE_DDR4 0x10 200 #define MEM_TYPE_LPDDR4 0x20 201 202 /* DDRC Software control register */ 203 #define DDRC_SWCTL 0x320 204 205 /* DDRC ECC CE & UE poison mask */ 206 #define ECC_CEPOISON_MASK 0x3 207 #define ECC_UEPOISON_MASK 0x1 208 209 /* DDRC Device config masks */ 210 #define DDRC_MSTR_CFG_MASK 0xC0000000 211 #define DDRC_MSTR_CFG_SHIFT 30 212 #define DDRC_MSTR_CFG_X4_MASK 0x0 213 #define DDRC_MSTR_CFG_X8_MASK 0x1 214 #define DDRC_MSTR_CFG_X16_MASK 0x2 215 #define DDRC_MSTR_CFG_X32_MASK 0x3 216 217 #define DDR_MAX_ROW_SHIFT 18 218 #define DDR_MAX_COL_SHIFT 14 219 #define DDR_MAX_BANK_SHIFT 3 220 #define DDR_MAX_BANKGRP_SHIFT 2 221 222 #define ROW_MAX_VAL_MASK 0xF 223 #define COL_MAX_VAL_MASK 0xF 224 #define BANK_MAX_VAL_MASK 0x1F 225 #define BANKGRP_MAX_VAL_MASK 0x1F 226 #define RANK_MAX_VAL_MASK 0x1F 227 228 #define ROW_B0_BASE 6 229 #define ROW_B1_BASE 7 230 #define ROW_B2_BASE 8 231 #define ROW_B3_BASE 9 232 #define ROW_B4_BASE 10 233 #define ROW_B5_BASE 11 234 #define ROW_B6_BASE 12 235 #define ROW_B7_BASE 13 236 #define ROW_B8_BASE 14 237 #define ROW_B9_BASE 15 238 #define ROW_B10_BASE 16 239 #define ROW_B11_BASE 17 240 #define ROW_B12_BASE 18 241 #define ROW_B13_BASE 19 242 #define ROW_B14_BASE 20 243 #define ROW_B15_BASE 21 244 #define ROW_B16_BASE 22 245 #define ROW_B17_BASE 23 246 247 #define COL_B2_BASE 2 248 #define COL_B3_BASE 3 249 #define COL_B4_BASE 4 250 #define COL_B5_BASE 5 251 #define COL_B6_BASE 6 252 #define COL_B7_BASE 7 253 #define COL_B8_BASE 8 254 #define COL_B9_BASE 9 255 #define COL_B10_BASE 10 256 #define COL_B11_BASE 11 257 #define COL_B12_BASE 12 258 #define COL_B13_BASE 13 259 260 #define BANK_B0_BASE 2 261 #define BANK_B1_BASE 3 262 #define BANK_B2_BASE 4 263 264 #define BANKGRP_B0_BASE 2 265 #define BANKGRP_B1_BASE 3 266 267 #define RANK_B0_BASE 6 268 269 /** 270 * struct ecc_error_info - ECC error log information. 271 * @row: Row number. 272 * @col: Column number. 273 * @bank: Bank number. 274 * @bitpos: Bit position. 275 * @data: Data causing the error. 276 * @bankgrpnr: Bank group number. 277 * @blknr: Block number. 278 */ 279 struct ecc_error_info { 280 u32 row; 281 u32 col; 282 u32 bank; 283 u32 bitpos; 284 u32 data; 285 u32 bankgrpnr; 286 u32 blknr; 287 }; 288 289 /** 290 * struct synps_ecc_status - ECC status information to report. 291 * @ce_cnt: Correctable error count. 292 * @ue_cnt: Uncorrectable error count. 293 * @ceinfo: Correctable error log information. 294 * @ueinfo: Uncorrectable error log information. 295 */ 296 struct synps_ecc_status { 297 u32 ce_cnt; 298 u32 ue_cnt; 299 struct ecc_error_info ceinfo; 300 struct ecc_error_info ueinfo; 301 }; 302 303 /** 304 * struct synps_edac_priv - DDR memory controller private instance data. 305 * @baseaddr: Base address of the DDR controller. 306 * @message: Buffer for framing the event specific info. 307 * @stat: ECC status information. 308 * @p_data: Platform data. 309 * @ce_cnt: Correctable Error count. 310 * @ue_cnt: Uncorrectable Error count. 311 * @poison_addr: Data poison address. 312 * @row_shift: Bit shifts for row bit. 313 * @col_shift: Bit shifts for column bit. 314 * @bank_shift: Bit shifts for bank bit. 315 * @bankgrp_shift: Bit shifts for bank group bit. 316 * @rank_shift: Bit shifts for rank bit. 317 */ 318 struct synps_edac_priv { 319 void __iomem *baseaddr; 320 char message[SYNPS_EDAC_MSG_SIZE]; 321 struct synps_ecc_status stat; 322 const struct synps_platform_data *p_data; 323 u32 ce_cnt; 324 u32 ue_cnt; 325 #ifdef CONFIG_EDAC_DEBUG 326 ulong poison_addr; 327 u32 row_shift[18]; 328 u32 col_shift[14]; 329 u32 bank_shift[3]; 330 u32 bankgrp_shift[2]; 331 u32 rank_shift[1]; 332 #endif 333 }; 334 335 /** 336 * struct synps_platform_data - synps platform data structure. 337 * @get_error_info: Get EDAC error info. 338 * @get_mtype: Get mtype. 339 * @get_dtype: Get dtype. 340 * @get_ecc_state: Get ECC state. 341 * @quirks: To differentiate IPs. 342 */ 343 struct synps_platform_data { 344 int (*get_error_info)(struct synps_edac_priv *priv); 345 enum mem_type (*get_mtype)(const void __iomem *base); 346 enum dev_type (*get_dtype)(const void __iomem *base); 347 bool (*get_ecc_state)(void __iomem *base); 348 int quirks; 349 }; 350 351 /** 352 * zynq_get_error_info - Get the current ECC error info. 353 * @priv: DDR memory controller private instance data. 354 * 355 * Return: one if there is no error, otherwise zero. 356 */ 357 static int zynq_get_error_info(struct synps_edac_priv *priv) 358 { 359 struct synps_ecc_status *p; 360 u32 regval, clearval = 0; 361 void __iomem *base; 362 363 base = priv->baseaddr; 364 p = &priv->stat; 365 366 regval = readl(base + STAT_OFST); 367 if (!regval) 368 return 1; 369 370 p->ce_cnt = (regval & STAT_CECNT_MASK) >> STAT_CECNT_SHIFT; 371 p->ue_cnt = regval & STAT_UECNT_MASK; 372 373 regval = readl(base + CE_LOG_OFST); 374 if (!(p->ce_cnt && (regval & LOG_VALID))) 375 goto ue_err; 376 377 p->ceinfo.bitpos = (regval & CE_LOG_BITPOS_MASK) >> CE_LOG_BITPOS_SHIFT; 378 regval = readl(base + CE_ADDR_OFST); 379 p->ceinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT; 380 p->ceinfo.col = regval & ADDR_COL_MASK; 381 p->ceinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; 382 p->ceinfo.data = readl(base + CE_DATA_31_0_OFST); 383 edac_dbg(3, "CE bit position: %d data: %d\n", p->ceinfo.bitpos, 384 p->ceinfo.data); 385 clearval = ECC_CTRL_CLR_CE_ERR; 386 387 ue_err: 388 regval = readl(base + UE_LOG_OFST); 389 if (!(p->ue_cnt && (regval & LOG_VALID))) 390 goto out; 391 392 regval = readl(base + UE_ADDR_OFST); 393 p->ueinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT; 394 p->ueinfo.col = regval & ADDR_COL_MASK; 395 p->ueinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; 396 p->ueinfo.data = readl(base + UE_DATA_31_0_OFST); 397 clearval |= ECC_CTRL_CLR_UE_ERR; 398 399 out: 400 writel(clearval, base + ECC_CTRL_OFST); 401 writel(0x0, base + ECC_CTRL_OFST); 402 403 return 0; 404 } 405 406 /** 407 * zynqmp_get_error_info - Get the current ECC error info. 408 * @priv: DDR memory controller private instance data. 409 * 410 * Return: one if there is no error otherwise returns zero. 411 */ 412 static int zynqmp_get_error_info(struct synps_edac_priv *priv) 413 { 414 struct synps_ecc_status *p; 415 u32 regval, clearval = 0; 416 void __iomem *base; 417 418 base = priv->baseaddr; 419 p = &priv->stat; 420 421 regval = readl(base + ECC_STAT_OFST); 422 if (!regval) 423 return 1; 424 425 p->ce_cnt = (regval & ECC_STAT_CECNT_MASK) >> ECC_STAT_CECNT_SHIFT; 426 p->ue_cnt = (regval & ECC_STAT_UECNT_MASK) >> ECC_STAT_UECNT_SHIFT; 427 if (!p->ce_cnt) 428 goto ue_err; 429 430 p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK); 431 432 regval = readl(base + ECC_CEADDR0_OFST); 433 p->ceinfo.row = (regval & ECC_CEADDR0_RW_MASK); 434 regval = readl(base + ECC_CEADDR1_OFST); 435 p->ceinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >> 436 ECC_CEADDR1_BNKNR_SHIFT; 437 p->ceinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >> 438 ECC_CEADDR1_BNKGRP_SHIFT; 439 p->ceinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK); 440 p->ceinfo.data = readl(base + ECC_CSYND0_OFST); 441 edac_dbg(2, "ECCCSYN0: 0x%08X ECCCSYN1: 0x%08X ECCCSYN2: 0x%08X\n", 442 readl(base + ECC_CSYND0_OFST), readl(base + ECC_CSYND1_OFST), 443 readl(base + ECC_CSYND2_OFST)); 444 ue_err: 445 if (!p->ue_cnt) 446 goto out; 447 448 regval = readl(base + ECC_UEADDR0_OFST); 449 p->ueinfo.row = (regval & ECC_CEADDR0_RW_MASK); 450 regval = readl(base + ECC_UEADDR1_OFST); 451 p->ueinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >> 452 ECC_CEADDR1_BNKGRP_SHIFT; 453 p->ueinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >> 454 ECC_CEADDR1_BNKNR_SHIFT; 455 p->ueinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK); 456 p->ueinfo.data = readl(base + ECC_UESYND0_OFST); 457 out: 458 clearval = ECC_CTRL_CLR_CE_ERR | ECC_CTRL_CLR_CE_ERRCNT; 459 clearval |= ECC_CTRL_CLR_UE_ERR | ECC_CTRL_CLR_UE_ERRCNT; 460 writel(clearval, base + ECC_CLR_OFST); 461 writel(0x0, base + ECC_CLR_OFST); 462 463 return 0; 464 } 465 466 /** 467 * handle_error - Handle Correctable and Uncorrectable errors. 468 * @mci: EDAC memory controller instance. 469 * @p: Synopsys ECC status structure. 470 * 471 * Handles ECC correctable and uncorrectable errors. 472 */ 473 static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p) 474 { 475 struct synps_edac_priv *priv = mci->pvt_info; 476 struct ecc_error_info *pinf; 477 478 if (p->ce_cnt) { 479 pinf = &p->ceinfo; 480 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { 481 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, 482 "DDR ECC error type:%s Row %d Bank %d BankGroup Number %d Block Number %d Bit Position: %d Data: 0x%08x", 483 "CE", pinf->row, pinf->bank, 484 pinf->bankgrpnr, pinf->blknr, 485 pinf->bitpos, pinf->data); 486 } else { 487 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, 488 "DDR ECC error type:%s Row %d Bank %d Col %d Bit Position: %d Data: 0x%08x", 489 "CE", pinf->row, pinf->bank, pinf->col, 490 pinf->bitpos, pinf->data); 491 } 492 493 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 494 p->ce_cnt, 0, 0, 0, 0, 0, -1, 495 priv->message, ""); 496 } 497 498 if (p->ue_cnt) { 499 pinf = &p->ueinfo; 500 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { 501 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, 502 "DDR ECC error type :%s Row %d Bank %d BankGroup Number %d Block Number %d", 503 "UE", pinf->row, pinf->bank, 504 pinf->bankgrpnr, pinf->blknr); 505 } else { 506 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, 507 "DDR ECC error type :%s Row %d Bank %d Col %d ", 508 "UE", pinf->row, pinf->bank, pinf->col); 509 } 510 511 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 512 p->ue_cnt, 0, 0, 0, 0, 0, -1, 513 priv->message, ""); 514 } 515 516 memset(p, 0, sizeof(*p)); 517 } 518 519 /** 520 * intr_handler - Interrupt Handler for ECC interrupts. 521 * @irq: IRQ number. 522 * @dev_id: Device ID. 523 * 524 * Return: IRQ_NONE, if interrupt not set or IRQ_HANDLED otherwise. 525 */ 526 static irqreturn_t intr_handler(int irq, void *dev_id) 527 { 528 const struct synps_platform_data *p_data; 529 struct mem_ctl_info *mci = dev_id; 530 struct synps_edac_priv *priv; 531 int status, regval; 532 533 priv = mci->pvt_info; 534 p_data = priv->p_data; 535 536 regval = readl(priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); 537 regval &= (DDR_QOSCE_MASK | DDR_QOSUE_MASK); 538 if (!(regval & ECC_CE_UE_INTR_MASK)) 539 return IRQ_NONE; 540 541 status = p_data->get_error_info(priv); 542 if (status) 543 return IRQ_NONE; 544 545 priv->ce_cnt += priv->stat.ce_cnt; 546 priv->ue_cnt += priv->stat.ue_cnt; 547 handle_error(mci, &priv->stat); 548 549 edac_dbg(3, "Total error count CE %d UE %d\n", 550 priv->ce_cnt, priv->ue_cnt); 551 writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); 552 return IRQ_HANDLED; 553 } 554 555 /** 556 * check_errors - Check controller for ECC errors. 557 * @mci: EDAC memory controller instance. 558 * 559 * Check and post ECC errors. Called by the polling thread. 560 */ 561 static void check_errors(struct mem_ctl_info *mci) 562 { 563 const struct synps_platform_data *p_data; 564 struct synps_edac_priv *priv; 565 int status; 566 567 priv = mci->pvt_info; 568 p_data = priv->p_data; 569 570 status = p_data->get_error_info(priv); 571 if (status) 572 return; 573 574 priv->ce_cnt += priv->stat.ce_cnt; 575 priv->ue_cnt += priv->stat.ue_cnt; 576 handle_error(mci, &priv->stat); 577 578 edac_dbg(3, "Total error count CE %d UE %d\n", 579 priv->ce_cnt, priv->ue_cnt); 580 } 581 582 /** 583 * zynq_get_dtype - Return the controller memory width. 584 * @base: DDR memory controller base address. 585 * 586 * Get the EDAC device type width appropriate for the current controller 587 * configuration. 588 * 589 * Return: a device type width enumeration. 590 */ 591 static enum dev_type zynq_get_dtype(const void __iomem *base) 592 { 593 enum dev_type dt; 594 u32 width; 595 596 width = readl(base + CTRL_OFST); 597 width = (width & CTRL_BW_MASK) >> CTRL_BW_SHIFT; 598 599 switch (width) { 600 case DDRCTL_WDTH_16: 601 dt = DEV_X2; 602 break; 603 case DDRCTL_WDTH_32: 604 dt = DEV_X4; 605 break; 606 default: 607 dt = DEV_UNKNOWN; 608 } 609 610 return dt; 611 } 612 613 /** 614 * zynqmp_get_dtype - Return the controller memory width. 615 * @base: DDR memory controller base address. 616 * 617 * Get the EDAC device type width appropriate for the current controller 618 * configuration. 619 * 620 * Return: a device type width enumeration. 621 */ 622 static enum dev_type zynqmp_get_dtype(const void __iomem *base) 623 { 624 enum dev_type dt; 625 u32 width; 626 627 width = readl(base + CTRL_OFST); 628 width = (width & ECC_CTRL_BUSWIDTH_MASK) >> ECC_CTRL_BUSWIDTH_SHIFT; 629 switch (width) { 630 case DDRCTL_EWDTH_16: 631 dt = DEV_X2; 632 break; 633 case DDRCTL_EWDTH_32: 634 dt = DEV_X4; 635 break; 636 case DDRCTL_EWDTH_64: 637 dt = DEV_X8; 638 break; 639 default: 640 dt = DEV_UNKNOWN; 641 } 642 643 return dt; 644 } 645 646 /** 647 * zynq_get_ecc_state - Return the controller ECC enable/disable status. 648 * @base: DDR memory controller base address. 649 * 650 * Get the ECC enable/disable status of the controller. 651 * 652 * Return: true if enabled, otherwise false. 653 */ 654 static bool zynq_get_ecc_state(void __iomem *base) 655 { 656 enum dev_type dt; 657 u32 ecctype; 658 659 dt = zynq_get_dtype(base); 660 if (dt == DEV_UNKNOWN) 661 return false; 662 663 ecctype = readl(base + SCRUB_OFST) & SCRUB_MODE_MASK; 664 if ((ecctype == SCRUB_MODE_SECDED) && (dt == DEV_X2)) 665 return true; 666 667 return false; 668 } 669 670 /** 671 * zynqmp_get_ecc_state - Return the controller ECC enable/disable status. 672 * @base: DDR memory controller base address. 673 * 674 * Get the ECC enable/disable status for the controller. 675 * 676 * Return: a ECC status boolean i.e true/false - enabled/disabled. 677 */ 678 static bool zynqmp_get_ecc_state(void __iomem *base) 679 { 680 enum dev_type dt; 681 u32 ecctype; 682 683 dt = zynqmp_get_dtype(base); 684 if (dt == DEV_UNKNOWN) 685 return false; 686 687 ecctype = readl(base + ECC_CFG0_OFST) & SCRUB_MODE_MASK; 688 if ((ecctype == SCRUB_MODE_SECDED) && 689 ((dt == DEV_X2) || (dt == DEV_X4) || (dt == DEV_X8))) 690 return true; 691 692 return false; 693 } 694 695 /** 696 * get_memsize - Read the size of the attached memory device. 697 * 698 * Return: the memory size in bytes. 699 */ 700 static u32 get_memsize(void) 701 { 702 struct sysinfo inf; 703 704 si_meminfo(&inf); 705 706 return inf.totalram * inf.mem_unit; 707 } 708 709 /** 710 * zynq_get_mtype - Return the controller memory type. 711 * @base: Synopsys ECC status structure. 712 * 713 * Get the EDAC memory type appropriate for the current controller 714 * configuration. 715 * 716 * Return: a memory type enumeration. 717 */ 718 static enum mem_type zynq_get_mtype(const void __iomem *base) 719 { 720 enum mem_type mt; 721 u32 memtype; 722 723 memtype = readl(base + T_ZQ_OFST); 724 725 if (memtype & T_ZQ_DDRMODE_MASK) 726 mt = MEM_DDR3; 727 else 728 mt = MEM_DDR2; 729 730 return mt; 731 } 732 733 /** 734 * zynqmp_get_mtype - Returns controller memory type. 735 * @base: Synopsys ECC status structure. 736 * 737 * Get the EDAC memory type appropriate for the current controller 738 * configuration. 739 * 740 * Return: a memory type enumeration. 741 */ 742 static enum mem_type zynqmp_get_mtype(const void __iomem *base) 743 { 744 enum mem_type mt; 745 u32 memtype; 746 747 memtype = readl(base + CTRL_OFST); 748 749 if ((memtype & MEM_TYPE_DDR3) || (memtype & MEM_TYPE_LPDDR3)) 750 mt = MEM_DDR3; 751 else if (memtype & MEM_TYPE_DDR2) 752 mt = MEM_RDDR2; 753 else if ((memtype & MEM_TYPE_LPDDR4) || (memtype & MEM_TYPE_DDR4)) 754 mt = MEM_DDR4; 755 else 756 mt = MEM_EMPTY; 757 758 return mt; 759 } 760 761 /** 762 * init_csrows - Initialize the csrow data. 763 * @mci: EDAC memory controller instance. 764 * 765 * Initialize the chip select rows associated with the EDAC memory 766 * controller instance. 767 */ 768 static void init_csrows(struct mem_ctl_info *mci) 769 { 770 struct synps_edac_priv *priv = mci->pvt_info; 771 const struct synps_platform_data *p_data; 772 struct csrow_info *csi; 773 struct dimm_info *dimm; 774 u32 size, row; 775 int j; 776 777 p_data = priv->p_data; 778 779 for (row = 0; row < mci->nr_csrows; row++) { 780 csi = mci->csrows[row]; 781 size = get_memsize(); 782 783 for (j = 0; j < csi->nr_channels; j++) { 784 dimm = csi->channels[j]->dimm; 785 dimm->edac_mode = EDAC_FLAG_SECDED; 786 dimm->mtype = p_data->get_mtype(priv->baseaddr); 787 dimm->nr_pages = (size >> PAGE_SHIFT) / csi->nr_channels; 788 dimm->grain = SYNPS_EDAC_ERR_GRAIN; 789 dimm->dtype = p_data->get_dtype(priv->baseaddr); 790 } 791 } 792 } 793 794 /** 795 * mc_init - Initialize one driver instance. 796 * @mci: EDAC memory controller instance. 797 * @pdev: platform device. 798 * 799 * Perform initialization of the EDAC memory controller instance and 800 * related driver-private data associated with the memory controller the 801 * instance is bound to. 802 */ 803 static void mc_init(struct mem_ctl_info *mci, struct platform_device *pdev) 804 { 805 struct synps_edac_priv *priv; 806 807 mci->pdev = &pdev->dev; 808 priv = mci->pvt_info; 809 platform_set_drvdata(pdev, mci); 810 811 /* Initialize controller capabilities and configuration */ 812 mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR2; 813 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; 814 mci->scrub_cap = SCRUB_HW_SRC; 815 mci->scrub_mode = SCRUB_NONE; 816 817 mci->edac_cap = EDAC_FLAG_SECDED; 818 mci->ctl_name = "synps_ddr_controller"; 819 mci->dev_name = SYNPS_EDAC_MOD_STRING; 820 mci->mod_name = SYNPS_EDAC_MOD_VER; 821 822 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { 823 edac_op_state = EDAC_OPSTATE_INT; 824 } else { 825 edac_op_state = EDAC_OPSTATE_POLL; 826 mci->edac_check = check_errors; 827 } 828 829 mci->ctl_page_to_phys = NULL; 830 831 init_csrows(mci); 832 } 833 834 static void enable_intr(struct synps_edac_priv *priv) 835 { 836 /* Enable UE/CE Interrupts */ 837 writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK, 838 priv->baseaddr + DDR_QOS_IRQ_EN_OFST); 839 } 840 841 static void disable_intr(struct synps_edac_priv *priv) 842 { 843 /* Disable UE/CE Interrupts */ 844 writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK, 845 priv->baseaddr + DDR_QOS_IRQ_DB_OFST); 846 } 847 848 static int setup_irq(struct mem_ctl_info *mci, 849 struct platform_device *pdev) 850 { 851 struct synps_edac_priv *priv = mci->pvt_info; 852 int ret, irq; 853 854 irq = platform_get_irq(pdev, 0); 855 if (irq < 0) { 856 edac_printk(KERN_ERR, EDAC_MC, 857 "No IRQ %d in DT\n", irq); 858 return irq; 859 } 860 861 ret = devm_request_irq(&pdev->dev, irq, intr_handler, 862 0, dev_name(&pdev->dev), mci); 863 if (ret < 0) { 864 edac_printk(KERN_ERR, EDAC_MC, "Failed to request IRQ\n"); 865 return ret; 866 } 867 868 enable_intr(priv); 869 870 return 0; 871 } 872 873 static const struct synps_platform_data zynq_edac_def = { 874 .get_error_info = zynq_get_error_info, 875 .get_mtype = zynq_get_mtype, 876 .get_dtype = zynq_get_dtype, 877 .get_ecc_state = zynq_get_ecc_state, 878 .quirks = 0, 879 }; 880 881 static const struct synps_platform_data zynqmp_edac_def = { 882 .get_error_info = zynqmp_get_error_info, 883 .get_mtype = zynqmp_get_mtype, 884 .get_dtype = zynqmp_get_dtype, 885 .get_ecc_state = zynqmp_get_ecc_state, 886 .quirks = (DDR_ECC_INTR_SUPPORT 887 #ifdef CONFIG_EDAC_DEBUG 888 | DDR_ECC_DATA_POISON_SUPPORT 889 #endif 890 ), 891 }; 892 893 static const struct of_device_id synps_edac_match[] = { 894 { 895 .compatible = "xlnx,zynq-ddrc-a05", 896 .data = (void *)&zynq_edac_def 897 }, 898 { 899 .compatible = "xlnx,zynqmp-ddrc-2.40a", 900 .data = (void *)&zynqmp_edac_def 901 }, 902 { 903 /* end of table */ 904 } 905 }; 906 907 MODULE_DEVICE_TABLE(of, synps_edac_match); 908 909 #ifdef CONFIG_EDAC_DEBUG 910 #define to_mci(k) container_of(k, struct mem_ctl_info, dev) 911 912 /** 913 * ddr_poison_setup - Update poison registers. 914 * @priv: DDR memory controller private instance data. 915 * 916 * Update poison registers as per DDR mapping. 917 * Return: none. 918 */ 919 static void ddr_poison_setup(struct synps_edac_priv *priv) 920 { 921 int col = 0, row = 0, bank = 0, bankgrp = 0, rank = 0, regval; 922 int index; 923 ulong hif_addr = 0; 924 925 hif_addr = priv->poison_addr >> 3; 926 927 for (index = 0; index < DDR_MAX_ROW_SHIFT; index++) { 928 if (priv->row_shift[index]) 929 row |= (((hif_addr >> priv->row_shift[index]) & 930 BIT(0)) << index); 931 else 932 break; 933 } 934 935 for (index = 0; index < DDR_MAX_COL_SHIFT; index++) { 936 if (priv->col_shift[index] || index < 3) 937 col |= (((hif_addr >> priv->col_shift[index]) & 938 BIT(0)) << index); 939 else 940 break; 941 } 942 943 for (index = 0; index < DDR_MAX_BANK_SHIFT; index++) { 944 if (priv->bank_shift[index]) 945 bank |= (((hif_addr >> priv->bank_shift[index]) & 946 BIT(0)) << index); 947 else 948 break; 949 } 950 951 for (index = 0; index < DDR_MAX_BANKGRP_SHIFT; index++) { 952 if (priv->bankgrp_shift[index]) 953 bankgrp |= (((hif_addr >> priv->bankgrp_shift[index]) 954 & BIT(0)) << index); 955 else 956 break; 957 } 958 959 if (priv->rank_shift[0]) 960 rank = (hif_addr >> priv->rank_shift[0]) & BIT(0); 961 962 regval = (rank << ECC_POISON0_RANK_SHIFT) & ECC_POISON0_RANK_MASK; 963 regval |= (col << ECC_POISON0_COLUMN_SHIFT) & ECC_POISON0_COLUMN_MASK; 964 writel(regval, priv->baseaddr + ECC_POISON0_OFST); 965 966 regval = (bankgrp << ECC_POISON1_BG_SHIFT) & ECC_POISON1_BG_MASK; 967 regval |= (bank << ECC_POISON1_BANKNR_SHIFT) & ECC_POISON1_BANKNR_MASK; 968 regval |= (row << ECC_POISON1_ROW_SHIFT) & ECC_POISON1_ROW_MASK; 969 writel(regval, priv->baseaddr + ECC_POISON1_OFST); 970 } 971 972 static ssize_t inject_data_error_show(struct device *dev, 973 struct device_attribute *mattr, 974 char *data) 975 { 976 struct mem_ctl_info *mci = to_mci(dev); 977 struct synps_edac_priv *priv = mci->pvt_info; 978 979 return sprintf(data, "Poison0 Addr: 0x%08x\n\rPoison1 Addr: 0x%08x\n\r" 980 "Error injection Address: 0x%lx\n\r", 981 readl(priv->baseaddr + ECC_POISON0_OFST), 982 readl(priv->baseaddr + ECC_POISON1_OFST), 983 priv->poison_addr); 984 } 985 986 static ssize_t inject_data_error_store(struct device *dev, 987 struct device_attribute *mattr, 988 const char *data, size_t count) 989 { 990 struct mem_ctl_info *mci = to_mci(dev); 991 struct synps_edac_priv *priv = mci->pvt_info; 992 993 if (kstrtoul(data, 0, &priv->poison_addr)) 994 return -EINVAL; 995 996 ddr_poison_setup(priv); 997 998 return count; 999 } 1000 1001 static ssize_t inject_data_poison_show(struct device *dev, 1002 struct device_attribute *mattr, 1003 char *data) 1004 { 1005 struct mem_ctl_info *mci = to_mci(dev); 1006 struct synps_edac_priv *priv = mci->pvt_info; 1007 1008 return sprintf(data, "Data Poisoning: %s\n\r", 1009 (((readl(priv->baseaddr + ECC_CFG1_OFST)) & 0x3) == 0x3) 1010 ? ("Correctable Error") : ("UnCorrectable Error")); 1011 } 1012 1013 static ssize_t inject_data_poison_store(struct device *dev, 1014 struct device_attribute *mattr, 1015 const char *data, size_t count) 1016 { 1017 struct mem_ctl_info *mci = to_mci(dev); 1018 struct synps_edac_priv *priv = mci->pvt_info; 1019 1020 writel(0, priv->baseaddr + DDRC_SWCTL); 1021 if (strncmp(data, "CE", 2) == 0) 1022 writel(ECC_CEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST); 1023 else 1024 writel(ECC_UEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST); 1025 writel(1, priv->baseaddr + DDRC_SWCTL); 1026 1027 return count; 1028 } 1029 1030 static DEVICE_ATTR_RW(inject_data_error); 1031 static DEVICE_ATTR_RW(inject_data_poison); 1032 1033 static int edac_create_sysfs_attributes(struct mem_ctl_info *mci) 1034 { 1035 int rc; 1036 1037 rc = device_create_file(&mci->dev, &dev_attr_inject_data_error); 1038 if (rc < 0) 1039 return rc; 1040 rc = device_create_file(&mci->dev, &dev_attr_inject_data_poison); 1041 if (rc < 0) 1042 return rc; 1043 return 0; 1044 } 1045 1046 static void edac_remove_sysfs_attributes(struct mem_ctl_info *mci) 1047 { 1048 device_remove_file(&mci->dev, &dev_attr_inject_data_error); 1049 device_remove_file(&mci->dev, &dev_attr_inject_data_poison); 1050 } 1051 1052 static void setup_row_address_map(struct synps_edac_priv *priv, u32 *addrmap) 1053 { 1054 u32 addrmap_row_b2_10; 1055 int index; 1056 1057 priv->row_shift[0] = (addrmap[5] & ROW_MAX_VAL_MASK) + ROW_B0_BASE; 1058 priv->row_shift[1] = ((addrmap[5] >> 8) & 1059 ROW_MAX_VAL_MASK) + ROW_B1_BASE; 1060 1061 addrmap_row_b2_10 = (addrmap[5] >> 16) & ROW_MAX_VAL_MASK; 1062 if (addrmap_row_b2_10 != ROW_MAX_VAL_MASK) { 1063 for (index = 2; index < 11; index++) 1064 priv->row_shift[index] = addrmap_row_b2_10 + 1065 index + ROW_B0_BASE; 1066 1067 } else { 1068 priv->row_shift[2] = (addrmap[9] & 1069 ROW_MAX_VAL_MASK) + ROW_B2_BASE; 1070 priv->row_shift[3] = ((addrmap[9] >> 8) & 1071 ROW_MAX_VAL_MASK) + ROW_B3_BASE; 1072 priv->row_shift[4] = ((addrmap[9] >> 16) & 1073 ROW_MAX_VAL_MASK) + ROW_B4_BASE; 1074 priv->row_shift[5] = ((addrmap[9] >> 24) & 1075 ROW_MAX_VAL_MASK) + ROW_B5_BASE; 1076 priv->row_shift[6] = (addrmap[10] & 1077 ROW_MAX_VAL_MASK) + ROW_B6_BASE; 1078 priv->row_shift[7] = ((addrmap[10] >> 8) & 1079 ROW_MAX_VAL_MASK) + ROW_B7_BASE; 1080 priv->row_shift[8] = ((addrmap[10] >> 16) & 1081 ROW_MAX_VAL_MASK) + ROW_B8_BASE; 1082 priv->row_shift[9] = ((addrmap[10] >> 24) & 1083 ROW_MAX_VAL_MASK) + ROW_B9_BASE; 1084 priv->row_shift[10] = (addrmap[11] & 1085 ROW_MAX_VAL_MASK) + ROW_B10_BASE; 1086 } 1087 1088 priv->row_shift[11] = (((addrmap[5] >> 24) & ROW_MAX_VAL_MASK) == 1089 ROW_MAX_VAL_MASK) ? 0 : (((addrmap[5] >> 24) & 1090 ROW_MAX_VAL_MASK) + ROW_B11_BASE); 1091 priv->row_shift[12] = ((addrmap[6] & ROW_MAX_VAL_MASK) == 1092 ROW_MAX_VAL_MASK) ? 0 : ((addrmap[6] & 1093 ROW_MAX_VAL_MASK) + ROW_B12_BASE); 1094 priv->row_shift[13] = (((addrmap[6] >> 8) & ROW_MAX_VAL_MASK) == 1095 ROW_MAX_VAL_MASK) ? 0 : (((addrmap[6] >> 8) & 1096 ROW_MAX_VAL_MASK) + ROW_B13_BASE); 1097 priv->row_shift[14] = (((addrmap[6] >> 16) & ROW_MAX_VAL_MASK) == 1098 ROW_MAX_VAL_MASK) ? 0 : (((addrmap[6] >> 16) & 1099 ROW_MAX_VAL_MASK) + ROW_B14_BASE); 1100 priv->row_shift[15] = (((addrmap[6] >> 24) & ROW_MAX_VAL_MASK) == 1101 ROW_MAX_VAL_MASK) ? 0 : (((addrmap[6] >> 24) & 1102 ROW_MAX_VAL_MASK) + ROW_B15_BASE); 1103 priv->row_shift[16] = ((addrmap[7] & ROW_MAX_VAL_MASK) == 1104 ROW_MAX_VAL_MASK) ? 0 : ((addrmap[7] & 1105 ROW_MAX_VAL_MASK) + ROW_B16_BASE); 1106 priv->row_shift[17] = (((addrmap[7] >> 8) & ROW_MAX_VAL_MASK) == 1107 ROW_MAX_VAL_MASK) ? 0 : (((addrmap[7] >> 8) & 1108 ROW_MAX_VAL_MASK) + ROW_B17_BASE); 1109 } 1110 1111 static void setup_column_address_map(struct synps_edac_priv *priv, u32 *addrmap) 1112 { 1113 u32 width, memtype; 1114 int index; 1115 1116 memtype = readl(priv->baseaddr + CTRL_OFST); 1117 width = (memtype & ECC_CTRL_BUSWIDTH_MASK) >> ECC_CTRL_BUSWIDTH_SHIFT; 1118 1119 priv->col_shift[0] = 0; 1120 priv->col_shift[1] = 1; 1121 priv->col_shift[2] = (addrmap[2] & COL_MAX_VAL_MASK) + COL_B2_BASE; 1122 priv->col_shift[3] = ((addrmap[2] >> 8) & 1123 COL_MAX_VAL_MASK) + COL_B3_BASE; 1124 priv->col_shift[4] = (((addrmap[2] >> 16) & COL_MAX_VAL_MASK) == 1125 COL_MAX_VAL_MASK) ? 0 : (((addrmap[2] >> 16) & 1126 COL_MAX_VAL_MASK) + COL_B4_BASE); 1127 priv->col_shift[5] = (((addrmap[2] >> 24) & COL_MAX_VAL_MASK) == 1128 COL_MAX_VAL_MASK) ? 0 : (((addrmap[2] >> 24) & 1129 COL_MAX_VAL_MASK) + COL_B5_BASE); 1130 priv->col_shift[6] = ((addrmap[3] & COL_MAX_VAL_MASK) == 1131 COL_MAX_VAL_MASK) ? 0 : ((addrmap[3] & 1132 COL_MAX_VAL_MASK) + COL_B6_BASE); 1133 priv->col_shift[7] = (((addrmap[3] >> 8) & COL_MAX_VAL_MASK) == 1134 COL_MAX_VAL_MASK) ? 0 : (((addrmap[3] >> 8) & 1135 COL_MAX_VAL_MASK) + COL_B7_BASE); 1136 priv->col_shift[8] = (((addrmap[3] >> 16) & COL_MAX_VAL_MASK) == 1137 COL_MAX_VAL_MASK) ? 0 : (((addrmap[3] >> 16) & 1138 COL_MAX_VAL_MASK) + COL_B8_BASE); 1139 priv->col_shift[9] = (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) == 1140 COL_MAX_VAL_MASK) ? 0 : (((addrmap[3] >> 24) & 1141 COL_MAX_VAL_MASK) + COL_B9_BASE); 1142 if (width == DDRCTL_EWDTH_64) { 1143 if (memtype & MEM_TYPE_LPDDR3) { 1144 priv->col_shift[10] = ((addrmap[4] & 1145 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 : 1146 ((addrmap[4] & COL_MAX_VAL_MASK) + 1147 COL_B10_BASE); 1148 priv->col_shift[11] = (((addrmap[4] >> 8) & 1149 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 : 1150 (((addrmap[4] >> 8) & COL_MAX_VAL_MASK) + 1151 COL_B11_BASE); 1152 } else { 1153 priv->col_shift[11] = ((addrmap[4] & 1154 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 : 1155 ((addrmap[4] & COL_MAX_VAL_MASK) + 1156 COL_B10_BASE); 1157 priv->col_shift[13] = (((addrmap[4] >> 8) & 1158 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 : 1159 (((addrmap[4] >> 8) & COL_MAX_VAL_MASK) + 1160 COL_B11_BASE); 1161 } 1162 } else if (width == DDRCTL_EWDTH_32) { 1163 if (memtype & MEM_TYPE_LPDDR3) { 1164 priv->col_shift[10] = (((addrmap[3] >> 24) & 1165 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 : 1166 (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) + 1167 COL_B9_BASE); 1168 priv->col_shift[11] = ((addrmap[4] & 1169 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 : 1170 ((addrmap[4] & COL_MAX_VAL_MASK) + 1171 COL_B10_BASE); 1172 } else { 1173 priv->col_shift[11] = (((addrmap[3] >> 24) & 1174 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 : 1175 (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) + 1176 COL_B9_BASE); 1177 priv->col_shift[13] = ((addrmap[4] & 1178 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 : 1179 ((addrmap[4] & COL_MAX_VAL_MASK) + 1180 COL_B10_BASE); 1181 } 1182 } else { 1183 if (memtype & MEM_TYPE_LPDDR3) { 1184 priv->col_shift[10] = (((addrmap[3] >> 16) & 1185 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 : 1186 (((addrmap[3] >> 16) & COL_MAX_VAL_MASK) + 1187 COL_B8_BASE); 1188 priv->col_shift[11] = (((addrmap[3] >> 24) & 1189 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 : 1190 (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) + 1191 COL_B9_BASE); 1192 priv->col_shift[13] = ((addrmap[4] & 1193 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 : 1194 ((addrmap[4] & COL_MAX_VAL_MASK) + 1195 COL_B10_BASE); 1196 } else { 1197 priv->col_shift[11] = (((addrmap[3] >> 16) & 1198 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 : 1199 (((addrmap[3] >> 16) & COL_MAX_VAL_MASK) + 1200 COL_B8_BASE); 1201 priv->col_shift[13] = (((addrmap[3] >> 24) & 1202 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 : 1203 (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) + 1204 COL_B9_BASE); 1205 } 1206 } 1207 1208 if (width) { 1209 for (index = 9; index > width; index--) { 1210 priv->col_shift[index] = priv->col_shift[index - width]; 1211 priv->col_shift[index - width] = 0; 1212 } 1213 } 1214 1215 } 1216 1217 static void setup_bank_address_map(struct synps_edac_priv *priv, u32 *addrmap) 1218 { 1219 priv->bank_shift[0] = (addrmap[1] & BANK_MAX_VAL_MASK) + BANK_B0_BASE; 1220 priv->bank_shift[1] = ((addrmap[1] >> 8) & 1221 BANK_MAX_VAL_MASK) + BANK_B1_BASE; 1222 priv->bank_shift[2] = (((addrmap[1] >> 16) & 1223 BANK_MAX_VAL_MASK) == BANK_MAX_VAL_MASK) ? 0 : 1224 (((addrmap[1] >> 16) & BANK_MAX_VAL_MASK) + 1225 BANK_B2_BASE); 1226 1227 } 1228 1229 static void setup_bg_address_map(struct synps_edac_priv *priv, u32 *addrmap) 1230 { 1231 priv->bankgrp_shift[0] = (addrmap[8] & 1232 BANKGRP_MAX_VAL_MASK) + BANKGRP_B0_BASE; 1233 priv->bankgrp_shift[1] = (((addrmap[8] >> 8) & BANKGRP_MAX_VAL_MASK) == 1234 BANKGRP_MAX_VAL_MASK) ? 0 : (((addrmap[8] >> 8) 1235 & BANKGRP_MAX_VAL_MASK) + BANKGRP_B1_BASE); 1236 1237 } 1238 1239 static void setup_rank_address_map(struct synps_edac_priv *priv, u32 *addrmap) 1240 { 1241 priv->rank_shift[0] = ((addrmap[0] & RANK_MAX_VAL_MASK) == 1242 RANK_MAX_VAL_MASK) ? 0 : ((addrmap[0] & 1243 RANK_MAX_VAL_MASK) + RANK_B0_BASE); 1244 } 1245 1246 /** 1247 * setup_address_map - Set Address Map by querying ADDRMAP registers. 1248 * @priv: DDR memory controller private instance data. 1249 * 1250 * Set Address Map by querying ADDRMAP registers. 1251 * 1252 * Return: none. 1253 */ 1254 static void setup_address_map(struct synps_edac_priv *priv) 1255 { 1256 u32 addrmap[12]; 1257 int index; 1258 1259 for (index = 0; index < 12; index++) { 1260 u32 addrmap_offset; 1261 1262 addrmap_offset = ECC_ADDRMAP0_OFFSET + (index * 4); 1263 addrmap[index] = readl(priv->baseaddr + addrmap_offset); 1264 } 1265 1266 setup_row_address_map(priv, addrmap); 1267 1268 setup_column_address_map(priv, addrmap); 1269 1270 setup_bank_address_map(priv, addrmap); 1271 1272 setup_bg_address_map(priv, addrmap); 1273 1274 setup_rank_address_map(priv, addrmap); 1275 } 1276 #endif /* CONFIG_EDAC_DEBUG */ 1277 1278 /** 1279 * mc_probe - Check controller and bind driver. 1280 * @pdev: platform device. 1281 * 1282 * Probe a specific controller instance for binding with the driver. 1283 * 1284 * Return: 0 if the controller instance was successfully bound to the 1285 * driver; otherwise, < 0 on error. 1286 */ 1287 static int mc_probe(struct platform_device *pdev) 1288 { 1289 const struct synps_platform_data *p_data; 1290 struct edac_mc_layer layers[2]; 1291 struct synps_edac_priv *priv; 1292 struct mem_ctl_info *mci; 1293 void __iomem *baseaddr; 1294 struct resource *res; 1295 int rc; 1296 1297 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1298 baseaddr = devm_ioremap_resource(&pdev->dev, res); 1299 if (IS_ERR(baseaddr)) 1300 return PTR_ERR(baseaddr); 1301 1302 p_data = of_device_get_match_data(&pdev->dev); 1303 if (!p_data) 1304 return -ENODEV; 1305 1306 if (!p_data->get_ecc_state(baseaddr)) { 1307 edac_printk(KERN_INFO, EDAC_MC, "ECC not enabled\n"); 1308 return -ENXIO; 1309 } 1310 1311 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 1312 layers[0].size = SYNPS_EDAC_NR_CSROWS; 1313 layers[0].is_virt_csrow = true; 1314 layers[1].type = EDAC_MC_LAYER_CHANNEL; 1315 layers[1].size = SYNPS_EDAC_NR_CHANS; 1316 layers[1].is_virt_csrow = false; 1317 1318 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 1319 sizeof(struct synps_edac_priv)); 1320 if (!mci) { 1321 edac_printk(KERN_ERR, EDAC_MC, 1322 "Failed memory allocation for mc instance\n"); 1323 return -ENOMEM; 1324 } 1325 1326 priv = mci->pvt_info; 1327 priv->baseaddr = baseaddr; 1328 priv->p_data = p_data; 1329 1330 mc_init(mci, pdev); 1331 1332 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { 1333 rc = setup_irq(mci, pdev); 1334 if (rc) 1335 goto free_edac_mc; 1336 } 1337 1338 rc = edac_mc_add_mc(mci); 1339 if (rc) { 1340 edac_printk(KERN_ERR, EDAC_MC, 1341 "Failed to register with EDAC core\n"); 1342 goto free_edac_mc; 1343 } 1344 1345 #ifdef CONFIG_EDAC_DEBUG 1346 if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT) { 1347 if (edac_create_sysfs_attributes(mci)) { 1348 edac_printk(KERN_ERR, EDAC_MC, 1349 "Failed to create sysfs entries\n"); 1350 goto free_edac_mc; 1351 } 1352 } 1353 1354 if (of_device_is_compatible(pdev->dev.of_node, 1355 "xlnx,zynqmp-ddrc-2.40a")) 1356 setup_address_map(priv); 1357 #endif 1358 1359 /* 1360 * Start capturing the correctable and uncorrectable errors. A write of 1361 * 0 starts the counters. 1362 */ 1363 if (!(priv->p_data->quirks & DDR_ECC_INTR_SUPPORT)) 1364 writel(0x0, baseaddr + ECC_CTRL_OFST); 1365 1366 return rc; 1367 1368 free_edac_mc: 1369 edac_mc_free(mci); 1370 1371 return rc; 1372 } 1373 1374 /** 1375 * mc_remove - Unbind driver from controller. 1376 * @pdev: Platform device. 1377 * 1378 * Return: Unconditionally 0 1379 */ 1380 static int mc_remove(struct platform_device *pdev) 1381 { 1382 struct mem_ctl_info *mci = platform_get_drvdata(pdev); 1383 struct synps_edac_priv *priv = mci->pvt_info; 1384 1385 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) 1386 disable_intr(priv); 1387 1388 #ifdef CONFIG_EDAC_DEBUG 1389 if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT) 1390 edac_remove_sysfs_attributes(mci); 1391 #endif 1392 1393 edac_mc_del_mc(&pdev->dev); 1394 edac_mc_free(mci); 1395 1396 return 0; 1397 } 1398 1399 static struct platform_driver synps_edac_mc_driver = { 1400 .driver = { 1401 .name = "synopsys-edac", 1402 .of_match_table = synps_edac_match, 1403 }, 1404 .probe = mc_probe, 1405 .remove = mc_remove, 1406 }; 1407 1408 module_platform_driver(synps_edac_mc_driver); 1409 1410 MODULE_AUTHOR("Xilinx Inc"); 1411 MODULE_DESCRIPTION("Synopsys DDR ECC driver"); 1412 MODULE_LICENSE("GPL v2"); 1413