1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * 4 * Shared code by both skx_edac and i10nm_edac. Originally split out 5 * from the skx_edac driver. 6 * 7 * This file is linked into both skx_edac and i10nm_edac drivers. In 8 * order to avoid link errors, this file must be like a pure library 9 * without including symbols and defines which would otherwise conflict, 10 * when linked once into a module and into a built-in object, at the 11 * same time. For example, __this_module symbol references when that 12 * file is being linked into a built-in object. 13 * 14 * Copyright (c) 2018, Intel Corporation. 15 */ 16 17 #include <linux/acpi.h> 18 #include <linux/dmi.h> 19 #include <linux/adxl.h> 20 #include <acpi/nfit.h> 21 #include <asm/mce.h> 22 #include "edac_module.h" 23 #include "skx_common.h" 24 25 static const char * const component_names[] = { 26 [INDEX_SOCKET] = "ProcessorSocketId", 27 [INDEX_MEMCTRL] = "MemoryControllerId", 28 [INDEX_CHANNEL] = "ChannelId", 29 [INDEX_DIMM] = "DimmSlotId", 30 [INDEX_CS] = "ChipSelect", 31 [INDEX_NM_MEMCTRL] = "NmMemoryControllerId", 32 [INDEX_NM_CHANNEL] = "NmChannelId", 33 [INDEX_NM_DIMM] = "NmDimmSlotId", 34 [INDEX_NM_CS] = "NmChipSelect", 35 }; 36 37 static int component_indices[ARRAY_SIZE(component_names)]; 38 static int adxl_component_count; 39 static const char * const *adxl_component_names; 40 static u64 *adxl_values; 41 static char *adxl_msg; 42 static unsigned long adxl_nm_bitmap; 43 44 static char skx_msg[MSG_SIZE]; 45 static skx_decode_f driver_decode; 46 static skx_show_retry_log_f skx_show_retry_rd_err_log; 47 static u64 skx_tolm, skx_tohm; 48 static LIST_HEAD(dev_edac_list); 49 static bool skx_mem_cfg_2lm; 50 static struct res_config *skx_res_cfg; 51 52 int skx_adxl_get(void) 53 { 54 const char * const *names; 55 int i, j; 56 57 names = adxl_get_component_names(); 58 if (!names) { 59 skx_printk(KERN_NOTICE, "No firmware support for address translation.\n"); 60 return -ENODEV; 61 } 62 63 for (i = 0; i < INDEX_MAX; i++) { 64 for (j = 0; names[j]; j++) { 65 if (!strcmp(component_names[i], names[j])) { 66 component_indices[i] = j; 67 68 if (i >= INDEX_NM_FIRST) 69 adxl_nm_bitmap |= 1 << i; 70 71 break; 72 } 73 } 74 75 if (!names[j] && i < INDEX_NM_FIRST) 76 goto err; 77 } 78 79 if (skx_mem_cfg_2lm) { 80 if (!adxl_nm_bitmap) 81 skx_printk(KERN_NOTICE, "Not enough ADXL components for 2-level memory.\n"); 82 else 83 edac_dbg(2, "adxl_nm_bitmap: 0x%lx\n", adxl_nm_bitmap); 84 } 85 86 adxl_component_names = names; 87 while (*names++) 88 adxl_component_count++; 89 90 adxl_values = kcalloc(adxl_component_count, sizeof(*adxl_values), 91 GFP_KERNEL); 92 if (!adxl_values) { 93 adxl_component_count = 0; 94 return -ENOMEM; 95 } 96 97 adxl_msg = kzalloc(MSG_SIZE, GFP_KERNEL); 98 if (!adxl_msg) { 99 adxl_component_count = 0; 100 kfree(adxl_values); 101 return -ENOMEM; 102 } 103 104 return 0; 105 err: 106 skx_printk(KERN_ERR, "'%s' is not matched from DSM parameters: ", 107 component_names[i]); 108 for (j = 0; names[j]; j++) 109 skx_printk(KERN_CONT, "%s ", names[j]); 110 skx_printk(KERN_CONT, "\n"); 111 112 return -ENODEV; 113 } 114 EXPORT_SYMBOL_GPL(skx_adxl_get); 115 116 void skx_adxl_put(void) 117 { 118 kfree(adxl_values); 119 kfree(adxl_msg); 120 } 121 EXPORT_SYMBOL_GPL(skx_adxl_put); 122 123 static bool skx_adxl_decode(struct decoded_addr *res, enum error_source err_src) 124 { 125 struct skx_dev *d; 126 int i, len = 0; 127 128 if (res->addr >= skx_tohm || (res->addr >= skx_tolm && 129 res->addr < BIT_ULL(32))) { 130 edac_dbg(0, "Address 0x%llx out of range\n", res->addr); 131 return false; 132 } 133 134 if (adxl_decode(res->addr, adxl_values)) { 135 edac_dbg(0, "Failed to decode 0x%llx\n", res->addr); 136 return false; 137 } 138 139 /* 140 * GNR with a Flat2LM memory configuration may mistakenly classify 141 * a near-memory error(DDR5) as a far-memory error(CXL), resulting 142 * in the incorrect selection of decoded ADXL components. 143 * To address this, prefetch the decoded far-memory controller ID 144 * and adjust the error source to near-memory if the far-memory 145 * controller ID is invalid. 146 */ 147 if (skx_res_cfg && skx_res_cfg->type == GNR && err_src == ERR_SRC_2LM_FM) { 148 res->imc = (int)adxl_values[component_indices[INDEX_MEMCTRL]]; 149 if (res->imc == -1) { 150 err_src = ERR_SRC_2LM_NM; 151 edac_dbg(0, "Adjust the error source to near-memory.\n"); 152 } 153 } 154 155 res->socket = (int)adxl_values[component_indices[INDEX_SOCKET]]; 156 if (err_src == ERR_SRC_2LM_NM) { 157 res->imc = (adxl_nm_bitmap & BIT_NM_MEMCTRL) ? 158 (int)adxl_values[component_indices[INDEX_NM_MEMCTRL]] : -1; 159 res->channel = (adxl_nm_bitmap & BIT_NM_CHANNEL) ? 160 (int)adxl_values[component_indices[INDEX_NM_CHANNEL]] : -1; 161 res->dimm = (adxl_nm_bitmap & BIT_NM_DIMM) ? 162 (int)adxl_values[component_indices[INDEX_NM_DIMM]] : -1; 163 res->cs = (adxl_nm_bitmap & BIT_NM_CS) ? 164 (int)adxl_values[component_indices[INDEX_NM_CS]] : -1; 165 } else { 166 res->imc = (int)adxl_values[component_indices[INDEX_MEMCTRL]]; 167 res->channel = (int)adxl_values[component_indices[INDEX_CHANNEL]]; 168 res->dimm = (int)adxl_values[component_indices[INDEX_DIMM]]; 169 res->cs = (int)adxl_values[component_indices[INDEX_CS]]; 170 } 171 172 if (res->imc > NUM_IMC - 1 || res->imc < 0) { 173 skx_printk(KERN_ERR, "Bad imc %d\n", res->imc); 174 return false; 175 } 176 177 list_for_each_entry(d, &dev_edac_list, list) { 178 if (d->imc[0].src_id == res->socket) { 179 res->dev = d; 180 break; 181 } 182 } 183 184 if (!res->dev) { 185 skx_printk(KERN_ERR, "No device for src_id %d imc %d\n", 186 res->socket, res->imc); 187 return false; 188 } 189 190 for (i = 0; i < adxl_component_count; i++) { 191 if (adxl_values[i] == ~0x0ull) 192 continue; 193 194 len += snprintf(adxl_msg + len, MSG_SIZE - len, " %s:0x%llx", 195 adxl_component_names[i], adxl_values[i]); 196 if (MSG_SIZE - len <= 0) 197 break; 198 } 199 200 res->decoded_by_adxl = true; 201 202 return true; 203 } 204 205 void skx_set_mem_cfg(bool mem_cfg_2lm) 206 { 207 skx_mem_cfg_2lm = mem_cfg_2lm; 208 } 209 EXPORT_SYMBOL_GPL(skx_set_mem_cfg); 210 211 void skx_set_res_cfg(struct res_config *cfg) 212 { 213 skx_res_cfg = cfg; 214 } 215 EXPORT_SYMBOL_GPL(skx_set_res_cfg); 216 217 void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log) 218 { 219 driver_decode = decode; 220 skx_show_retry_rd_err_log = show_retry_log; 221 } 222 EXPORT_SYMBOL_GPL(skx_set_decode); 223 224 int skx_get_src_id(struct skx_dev *d, int off, u8 *id) 225 { 226 u32 reg; 227 228 if (pci_read_config_dword(d->util_all, off, ®)) { 229 skx_printk(KERN_ERR, "Failed to read src id\n"); 230 return -ENODEV; 231 } 232 233 *id = GET_BITFIELD(reg, 12, 14); 234 return 0; 235 } 236 EXPORT_SYMBOL_GPL(skx_get_src_id); 237 238 int skx_get_node_id(struct skx_dev *d, u8 *id) 239 { 240 u32 reg; 241 242 if (pci_read_config_dword(d->util_all, 0xf4, ®)) { 243 skx_printk(KERN_ERR, "Failed to read node id\n"); 244 return -ENODEV; 245 } 246 247 *id = GET_BITFIELD(reg, 0, 2); 248 return 0; 249 } 250 EXPORT_SYMBOL_GPL(skx_get_node_id); 251 252 static int get_width(u32 mtr) 253 { 254 switch (GET_BITFIELD(mtr, 8, 9)) { 255 case 0: 256 return DEV_X4; 257 case 1: 258 return DEV_X8; 259 case 2: 260 return DEV_X16; 261 } 262 return DEV_UNKNOWN; 263 } 264 265 /* 266 * We use the per-socket device @cfg->did to count how many sockets are present, 267 * and to detemine which PCI buses are associated with each socket. Allocate 268 * and build the full list of all the skx_dev structures that we need here. 269 */ 270 int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **list) 271 { 272 struct pci_dev *pdev, *prev; 273 struct skx_dev *d; 274 u32 reg; 275 int ndev = 0; 276 277 prev = NULL; 278 for (;;) { 279 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, cfg->decs_did, prev); 280 if (!pdev) 281 break; 282 ndev++; 283 d = kzalloc(sizeof(*d), GFP_KERNEL); 284 if (!d) { 285 pci_dev_put(pdev); 286 return -ENOMEM; 287 } 288 289 if (pci_read_config_dword(pdev, cfg->busno_cfg_offset, ®)) { 290 kfree(d); 291 pci_dev_put(pdev); 292 skx_printk(KERN_ERR, "Failed to read bus idx\n"); 293 return -ENODEV; 294 } 295 296 d->bus[0] = GET_BITFIELD(reg, 0, 7); 297 d->bus[1] = GET_BITFIELD(reg, 8, 15); 298 if (cfg->type == SKX) { 299 d->seg = pci_domain_nr(pdev->bus); 300 d->bus[2] = GET_BITFIELD(reg, 16, 23); 301 d->bus[3] = GET_BITFIELD(reg, 24, 31); 302 } else { 303 d->seg = GET_BITFIELD(reg, 16, 23); 304 } 305 306 edac_dbg(2, "busses: 0x%x, 0x%x, 0x%x, 0x%x\n", 307 d->bus[0], d->bus[1], d->bus[2], d->bus[3]); 308 list_add_tail(&d->list, &dev_edac_list); 309 prev = pdev; 310 } 311 312 if (list) 313 *list = &dev_edac_list; 314 return ndev; 315 } 316 EXPORT_SYMBOL_GPL(skx_get_all_bus_mappings); 317 318 int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm) 319 { 320 struct pci_dev *pdev; 321 u32 reg; 322 323 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, did, NULL); 324 if (!pdev) { 325 edac_dbg(2, "Can't get tolm/tohm\n"); 326 return -ENODEV; 327 } 328 329 if (pci_read_config_dword(pdev, off[0], ®)) { 330 skx_printk(KERN_ERR, "Failed to read tolm\n"); 331 goto fail; 332 } 333 skx_tolm = reg; 334 335 if (pci_read_config_dword(pdev, off[1], ®)) { 336 skx_printk(KERN_ERR, "Failed to read lower tohm\n"); 337 goto fail; 338 } 339 skx_tohm = reg; 340 341 if (pci_read_config_dword(pdev, off[2], ®)) { 342 skx_printk(KERN_ERR, "Failed to read upper tohm\n"); 343 goto fail; 344 } 345 skx_tohm |= (u64)reg << 32; 346 347 pci_dev_put(pdev); 348 *tolm = skx_tolm; 349 *tohm = skx_tohm; 350 edac_dbg(2, "tolm = 0x%llx tohm = 0x%llx\n", skx_tolm, skx_tohm); 351 return 0; 352 fail: 353 pci_dev_put(pdev); 354 return -ENODEV; 355 } 356 EXPORT_SYMBOL_GPL(skx_get_hi_lo); 357 358 static int skx_get_dimm_attr(u32 reg, int lobit, int hibit, int add, 359 int minval, int maxval, const char *name) 360 { 361 u32 val = GET_BITFIELD(reg, lobit, hibit); 362 363 if (val < minval || val > maxval) { 364 edac_dbg(2, "bad %s = %d (raw=0x%x)\n", name, val, reg); 365 return -EINVAL; 366 } 367 return val + add; 368 } 369 370 #define numrank(reg) skx_get_dimm_attr(reg, 12, 13, 0, 0, 2, "ranks") 371 #define numrow(reg) skx_get_dimm_attr(reg, 2, 4, 12, 1, 6, "rows") 372 #define numcol(reg) skx_get_dimm_attr(reg, 0, 1, 10, 0, 2, "cols") 373 374 int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm, 375 struct skx_imc *imc, int chan, int dimmno, 376 struct res_config *cfg) 377 { 378 int banks, ranks, rows, cols, npages; 379 enum mem_type mtype; 380 u64 size; 381 382 ranks = numrank(mtr); 383 rows = numrow(mtr); 384 cols = imc->hbm_mc ? 6 : numcol(mtr); 385 386 if (imc->hbm_mc) { 387 banks = 32; 388 mtype = MEM_HBM2; 389 } else if (cfg->support_ddr5 && (amap & 0x8)) { 390 banks = 32; 391 mtype = MEM_DDR5; 392 } else { 393 banks = 16; 394 mtype = MEM_DDR4; 395 } 396 397 /* 398 * Compute size in 8-byte (2^3) words, then shift to MiB (2^20) 399 */ 400 size = ((1ull << (rows + cols + ranks)) * banks) >> (20 - 3); 401 npages = MiB_TO_PAGES(size); 402 403 edac_dbg(0, "mc#%d: channel %d, dimm %d, %lld MiB (%d pages) bank: %d, rank: %d, row: 0x%x, col: 0x%x\n", 404 imc->mc, chan, dimmno, size, npages, 405 banks, 1 << ranks, rows, cols); 406 407 imc->chan[chan].dimms[dimmno].close_pg = GET_BITFIELD(mcmtr, 0, 0); 408 imc->chan[chan].dimms[dimmno].bank_xor_enable = GET_BITFIELD(mcmtr, 9, 9); 409 imc->chan[chan].dimms[dimmno].fine_grain_bank = GET_BITFIELD(amap, 0, 0); 410 imc->chan[chan].dimms[dimmno].rowbits = rows; 411 imc->chan[chan].dimms[dimmno].colbits = cols; 412 413 dimm->nr_pages = npages; 414 dimm->grain = 32; 415 dimm->dtype = get_width(mtr); 416 dimm->mtype = mtype; 417 dimm->edac_mode = EDAC_SECDED; /* likely better than this */ 418 419 if (imc->hbm_mc) 420 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_HBMC#%u_Chan#%u", 421 imc->src_id, imc->lmc, chan); 422 else 423 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u", 424 imc->src_id, imc->lmc, chan, dimmno); 425 426 return 1; 427 } 428 EXPORT_SYMBOL_GPL(skx_get_dimm_info); 429 430 int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc, 431 int chan, int dimmno, const char *mod_str) 432 { 433 int smbios_handle; 434 u32 dev_handle; 435 u16 flags; 436 u64 size = 0; 437 438 dev_handle = ACPI_NFIT_BUILD_DEVICE_HANDLE(dimmno, chan, imc->lmc, 439 imc->src_id, 0); 440 441 smbios_handle = nfit_get_smbios_id(dev_handle, &flags); 442 if (smbios_handle == -EOPNOTSUPP) { 443 pr_warn_once("%s: Can't find size of NVDIMM. Try enabling CONFIG_ACPI_NFIT\n", mod_str); 444 goto unknown_size; 445 } 446 447 if (smbios_handle < 0) { 448 skx_printk(KERN_ERR, "Can't find handle for NVDIMM ADR=0x%x\n", dev_handle); 449 goto unknown_size; 450 } 451 452 if (flags & ACPI_NFIT_MEM_MAP_FAILED) { 453 skx_printk(KERN_ERR, "NVDIMM ADR=0x%x is not mapped\n", dev_handle); 454 goto unknown_size; 455 } 456 457 size = dmi_memdev_size(smbios_handle); 458 if (size == ~0ull) 459 skx_printk(KERN_ERR, "Can't find size for NVDIMM ADR=0x%x/SMBIOS=0x%x\n", 460 dev_handle, smbios_handle); 461 462 unknown_size: 463 dimm->nr_pages = size >> PAGE_SHIFT; 464 dimm->grain = 32; 465 dimm->dtype = DEV_UNKNOWN; 466 dimm->mtype = MEM_NVDIMM; 467 dimm->edac_mode = EDAC_SECDED; /* likely better than this */ 468 469 edac_dbg(0, "mc#%d: channel %d, dimm %d, %llu MiB (%u pages)\n", 470 imc->mc, chan, dimmno, size >> 20, dimm->nr_pages); 471 472 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u", 473 imc->src_id, imc->lmc, chan, dimmno); 474 475 return (size == 0 || size == ~0ull) ? 0 : 1; 476 } 477 EXPORT_SYMBOL_GPL(skx_get_nvdimm_info); 478 479 int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev, 480 const char *ctl_name, const char *mod_str, 481 get_dimm_config_f get_dimm_config, 482 struct res_config *cfg) 483 { 484 struct mem_ctl_info *mci; 485 struct edac_mc_layer layers[2]; 486 struct skx_pvt *pvt; 487 int rc; 488 489 /* Allocate a new MC control structure */ 490 layers[0].type = EDAC_MC_LAYER_CHANNEL; 491 layers[0].size = NUM_CHANNELS; 492 layers[0].is_virt_csrow = false; 493 layers[1].type = EDAC_MC_LAYER_SLOT; 494 layers[1].size = NUM_DIMMS; 495 layers[1].is_virt_csrow = true; 496 mci = edac_mc_alloc(imc->mc, ARRAY_SIZE(layers), layers, 497 sizeof(struct skx_pvt)); 498 499 if (unlikely(!mci)) 500 return -ENOMEM; 501 502 edac_dbg(0, "MC#%d: mci = %p\n", imc->mc, mci); 503 504 /* Associate skx_dev and mci for future usage */ 505 imc->mci = mci; 506 pvt = mci->pvt_info; 507 pvt->imc = imc; 508 509 mci->ctl_name = kasprintf(GFP_KERNEL, "%s#%d IMC#%d", ctl_name, 510 imc->node_id, imc->lmc); 511 if (!mci->ctl_name) { 512 rc = -ENOMEM; 513 goto fail0; 514 } 515 516 mci->mtype_cap = MEM_FLAG_DDR4 | MEM_FLAG_NVDIMM; 517 if (cfg->support_ddr5) 518 mci->mtype_cap |= MEM_FLAG_DDR5; 519 mci->edac_ctl_cap = EDAC_FLAG_NONE; 520 mci->edac_cap = EDAC_FLAG_NONE; 521 mci->mod_name = mod_str; 522 mci->dev_name = pci_name(pdev); 523 mci->ctl_page_to_phys = NULL; 524 525 rc = get_dimm_config(mci, cfg); 526 if (rc < 0) 527 goto fail; 528 529 /* Record ptr to the generic device */ 530 mci->pdev = &pdev->dev; 531 532 /* Add this new MC control structure to EDAC's list of MCs */ 533 if (unlikely(edac_mc_add_mc(mci))) { 534 edac_dbg(0, "MC: failed edac_mc_add_mc()\n"); 535 rc = -EINVAL; 536 goto fail; 537 } 538 539 return 0; 540 541 fail: 542 kfree(mci->ctl_name); 543 fail0: 544 edac_mc_free(mci); 545 imc->mci = NULL; 546 return rc; 547 } 548 EXPORT_SYMBOL_GPL(skx_register_mci); 549 550 static void skx_unregister_mci(struct skx_imc *imc) 551 { 552 struct mem_ctl_info *mci = imc->mci; 553 554 if (!mci) 555 return; 556 557 edac_dbg(0, "MC%d: mci = %p\n", imc->mc, mci); 558 559 /* Remove MC sysfs nodes */ 560 edac_mc_del_mc(mci->pdev); 561 562 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name); 563 kfree(mci->ctl_name); 564 edac_mc_free(mci); 565 } 566 567 static void skx_mce_output_error(struct mem_ctl_info *mci, 568 const struct mce *m, 569 struct decoded_addr *res) 570 { 571 enum hw_event_mc_err_type tp_event; 572 char *optype; 573 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0); 574 bool overflow = GET_BITFIELD(m->status, 62, 62); 575 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61); 576 bool scrub_err = false; 577 bool recoverable; 578 int len; 579 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52); 580 u32 mscod = GET_BITFIELD(m->status, 16, 31); 581 u32 errcode = GET_BITFIELD(m->status, 0, 15); 582 u32 optypenum = GET_BITFIELD(m->status, 4, 6); 583 584 recoverable = GET_BITFIELD(m->status, 56, 56); 585 586 if (uncorrected_error) { 587 core_err_cnt = 1; 588 if (ripv) { 589 tp_event = HW_EVENT_ERR_UNCORRECTED; 590 } else { 591 tp_event = HW_EVENT_ERR_FATAL; 592 } 593 } else { 594 tp_event = HW_EVENT_ERR_CORRECTED; 595 } 596 597 switch (optypenum) { 598 case 0: 599 optype = "generic undef request error"; 600 break; 601 case 1: 602 optype = "memory read error"; 603 break; 604 case 2: 605 optype = "memory write error"; 606 break; 607 case 3: 608 optype = "addr/cmd error"; 609 break; 610 case 4: 611 optype = "memory scrubbing error"; 612 scrub_err = true; 613 break; 614 default: 615 optype = "reserved"; 616 break; 617 } 618 619 if (res->decoded_by_adxl) { 620 len = snprintf(skx_msg, MSG_SIZE, "%s%s err_code:0x%04x:0x%04x %s", 621 overflow ? " OVERFLOW" : "", 622 (uncorrected_error && recoverable) ? " recoverable" : "", 623 mscod, errcode, adxl_msg); 624 } else { 625 len = snprintf(skx_msg, MSG_SIZE, 626 "%s%s err_code:0x%04x:0x%04x ProcessorSocketId:0x%x MemoryControllerId:0x%x PhysicalRankId:0x%x Row:0x%x Column:0x%x Bank:0x%x BankGroup:0x%x", 627 overflow ? " OVERFLOW" : "", 628 (uncorrected_error && recoverable) ? " recoverable" : "", 629 mscod, errcode, 630 res->socket, res->imc, res->rank, 631 res->row, res->column, res->bank_address, res->bank_group); 632 } 633 634 if (skx_show_retry_rd_err_log) 635 skx_show_retry_rd_err_log(res, skx_msg + len, MSG_SIZE - len, scrub_err); 636 637 edac_dbg(0, "%s\n", skx_msg); 638 639 /* Call the helper to output message */ 640 edac_mc_handle_error(tp_event, mci, core_err_cnt, 641 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, 642 res->channel, res->dimm, -1, 643 optype, skx_msg); 644 } 645 646 static enum error_source skx_error_source(const struct mce *m) 647 { 648 u32 errcode = GET_BITFIELD(m->status, 0, 15) & MCACOD_MEM_ERR_MASK; 649 650 if (errcode != MCACOD_MEM_CTL_ERR && errcode != MCACOD_EXT_MEM_ERR) 651 return ERR_SRC_NOT_MEMORY; 652 653 if (!skx_mem_cfg_2lm) 654 return ERR_SRC_1LM; 655 656 if (errcode == MCACOD_EXT_MEM_ERR) 657 return ERR_SRC_2LM_NM; 658 659 return ERR_SRC_2LM_FM; 660 } 661 662 int skx_mce_check_error(struct notifier_block *nb, unsigned long val, 663 void *data) 664 { 665 struct mce *mce = (struct mce *)data; 666 enum error_source err_src; 667 struct decoded_addr res; 668 struct mem_ctl_info *mci; 669 char *type; 670 671 if (mce->kflags & MCE_HANDLED_CEC) 672 return NOTIFY_DONE; 673 674 err_src = skx_error_source(mce); 675 676 /* Ignore unless this is memory related with an address */ 677 if (err_src == ERR_SRC_NOT_MEMORY || !(mce->status & MCI_STATUS_ADDRV)) 678 return NOTIFY_DONE; 679 680 memset(&res, 0, sizeof(res)); 681 res.mce = mce; 682 res.addr = mce->addr & MCI_ADDR_PHYSADDR; 683 if (!pfn_to_online_page(res.addr >> PAGE_SHIFT) && !arch_is_platform_page(res.addr)) { 684 pr_err("Invalid address 0x%llx in IA32_MC%d_ADDR\n", mce->addr, mce->bank); 685 return NOTIFY_DONE; 686 } 687 688 /* Try driver decoder first */ 689 if (!(driver_decode && driver_decode(&res))) { 690 /* Then try firmware decoder (ACPI DSM methods) */ 691 if (!(adxl_component_count && skx_adxl_decode(&res, err_src))) 692 return NOTIFY_DONE; 693 } 694 695 mci = res.dev->imc[res.imc].mci; 696 697 if (!mci) 698 return NOTIFY_DONE; 699 700 if (mce->mcgstatus & MCG_STATUS_MCIP) 701 type = "Exception"; 702 else 703 type = "Event"; 704 705 skx_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n"); 706 707 skx_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: 0x%llx " 708 "Bank %d: 0x%llx\n", mce->extcpu, type, 709 mce->mcgstatus, mce->bank, mce->status); 710 skx_mc_printk(mci, KERN_DEBUG, "TSC 0x%llx ", mce->tsc); 711 skx_mc_printk(mci, KERN_DEBUG, "ADDR 0x%llx ", mce->addr); 712 skx_mc_printk(mci, KERN_DEBUG, "MISC 0x%llx ", mce->misc); 713 714 skx_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:0x%x TIME %llu SOCKET " 715 "%u APIC 0x%x\n", mce->cpuvendor, mce->cpuid, 716 mce->time, mce->socketid, mce->apicid); 717 718 skx_mce_output_error(mci, mce, &res); 719 720 mce->kflags |= MCE_HANDLED_EDAC; 721 return NOTIFY_DONE; 722 } 723 EXPORT_SYMBOL_GPL(skx_mce_check_error); 724 725 void skx_remove(void) 726 { 727 int i, j; 728 struct skx_dev *d, *tmp; 729 730 edac_dbg(0, "\n"); 731 732 list_for_each_entry_safe(d, tmp, &dev_edac_list, list) { 733 list_del(&d->list); 734 for (i = 0; i < NUM_IMC; i++) { 735 if (d->imc[i].mci) 736 skx_unregister_mci(&d->imc[i]); 737 738 if (d->imc[i].mdev) 739 pci_dev_put(d->imc[i].mdev); 740 741 if (d->imc[i].mbase) 742 iounmap(d->imc[i].mbase); 743 744 for (j = 0; j < NUM_CHANNELS; j++) { 745 if (d->imc[i].chan[j].cdev) 746 pci_dev_put(d->imc[i].chan[j].cdev); 747 } 748 } 749 if (d->util_all) 750 pci_dev_put(d->util_all); 751 if (d->pcu_cr3) 752 pci_dev_put(d->pcu_cr3); 753 if (d->sad_all) 754 pci_dev_put(d->sad_all); 755 if (d->uracu) 756 pci_dev_put(d->uracu); 757 758 kfree(d); 759 } 760 } 761 EXPORT_SYMBOL_GPL(skx_remove); 762 763 MODULE_LICENSE("GPL v2"); 764 MODULE_AUTHOR("Tony Luck"); 765 MODULE_DESCRIPTION("MC Driver for Intel server processors"); 766