1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Common codes for both the skx_edac driver and Intel 10nm server EDAC driver. 4 * Originally split out from the skx_edac driver. 5 * 6 * Copyright (c) 2018, Intel Corporation. 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/dmi.h> 11 #include <linux/adxl.h> 12 #include <acpi/nfit.h> 13 #include <asm/mce.h> 14 #include "edac_module.h" 15 #include "skx_common.h" 16 17 static const char * const component_names[] = { 18 [INDEX_SOCKET] = "ProcessorSocketId", 19 [INDEX_MEMCTRL] = "MemoryControllerId", 20 [INDEX_CHANNEL] = "ChannelId", 21 [INDEX_DIMM] = "DimmSlotId", 22 }; 23 24 static int component_indices[ARRAY_SIZE(component_names)]; 25 static int adxl_component_count; 26 static const char * const *adxl_component_names; 27 static u64 *adxl_values; 28 static char *adxl_msg; 29 30 static char skx_msg[MSG_SIZE]; 31 static skx_decode_f skx_decode; 32 static u64 skx_tolm, skx_tohm; 33 static LIST_HEAD(dev_edac_list); 34 35 int __init skx_adxl_get(void) 36 { 37 const char * const *names; 38 int i, j; 39 40 names = adxl_get_component_names(); 41 if (!names) { 42 skx_printk(KERN_NOTICE, "No firmware support for address translation.\n"); 43 return -ENODEV; 44 } 45 46 for (i = 0; i < INDEX_MAX; i++) { 47 for (j = 0; names[j]; j++) { 48 if (!strcmp(component_names[i], names[j])) { 49 component_indices[i] = j; 50 break; 51 } 52 } 53 54 if (!names[j]) 55 goto err; 56 } 57 58 adxl_component_names = names; 59 while (*names++) 60 adxl_component_count++; 61 62 adxl_values = kcalloc(adxl_component_count, sizeof(*adxl_values), 63 GFP_KERNEL); 64 if (!adxl_values) { 65 adxl_component_count = 0; 66 return -ENOMEM; 67 } 68 69 adxl_msg = kzalloc(MSG_SIZE, GFP_KERNEL); 70 if (!adxl_msg) { 71 adxl_component_count = 0; 72 kfree(adxl_values); 73 return -ENOMEM; 74 } 75 76 return 0; 77 err: 78 skx_printk(KERN_ERR, "'%s' is not matched from DSM parameters: ", 79 component_names[i]); 80 for (j = 0; names[j]; j++) 81 skx_printk(KERN_CONT, "%s ", names[j]); 82 skx_printk(KERN_CONT, "\n"); 83 84 return -ENODEV; 85 } 86 87 void __exit skx_adxl_put(void) 88 { 89 kfree(adxl_values); 90 kfree(adxl_msg); 91 } 92 93 static bool skx_adxl_decode(struct decoded_addr *res) 94 { 95 int i, len = 0; 96 97 if (res->addr >= skx_tohm || (res->addr >= skx_tolm && 98 res->addr < BIT_ULL(32))) { 99 edac_dbg(0, "Address 0x%llx out of range\n", res->addr); 100 return false; 101 } 102 103 if (adxl_decode(res->addr, adxl_values)) { 104 edac_dbg(0, "Failed to decode 0x%llx\n", res->addr); 105 return false; 106 } 107 108 res->socket = (int)adxl_values[component_indices[INDEX_SOCKET]]; 109 res->imc = (int)adxl_values[component_indices[INDEX_MEMCTRL]]; 110 res->channel = (int)adxl_values[component_indices[INDEX_CHANNEL]]; 111 res->dimm = (int)adxl_values[component_indices[INDEX_DIMM]]; 112 113 for (i = 0; i < adxl_component_count; i++) { 114 if (adxl_values[i] == ~0x0ull) 115 continue; 116 117 len += snprintf(adxl_msg + len, MSG_SIZE - len, " %s:0x%llx", 118 adxl_component_names[i], adxl_values[i]); 119 if (MSG_SIZE - len <= 0) 120 break; 121 } 122 123 return true; 124 } 125 126 void skx_set_decode(skx_decode_f decode) 127 { 128 skx_decode = decode; 129 } 130 131 int skx_get_src_id(struct skx_dev *d, u8 *id) 132 { 133 u32 reg; 134 135 if (pci_read_config_dword(d->util_all, 0xf0, ®)) { 136 skx_printk(KERN_ERR, "Failed to read src id\n"); 137 return -ENODEV; 138 } 139 140 *id = GET_BITFIELD(reg, 12, 14); 141 return 0; 142 } 143 144 int skx_get_node_id(struct skx_dev *d, u8 *id) 145 { 146 u32 reg; 147 148 if (pci_read_config_dword(d->util_all, 0xf4, ®)) { 149 skx_printk(KERN_ERR, "Failed to read node id\n"); 150 return -ENODEV; 151 } 152 153 *id = GET_BITFIELD(reg, 0, 2); 154 return 0; 155 } 156 157 static int get_width(u32 mtr) 158 { 159 switch (GET_BITFIELD(mtr, 8, 9)) { 160 case 0: 161 return DEV_X4; 162 case 1: 163 return DEV_X8; 164 case 2: 165 return DEV_X16; 166 } 167 return DEV_UNKNOWN; 168 } 169 170 /* 171 * We use the per-socket device @did to count how many sockets are present, 172 * and to detemine which PCI buses are associated with each socket. Allocate 173 * and build the full list of all the skx_dev structures that we need here. 174 */ 175 int skx_get_all_bus_mappings(unsigned int did, int off, enum type type, 176 struct list_head **list) 177 { 178 struct pci_dev *pdev, *prev; 179 struct skx_dev *d; 180 u32 reg; 181 int ndev = 0; 182 183 prev = NULL; 184 for (;;) { 185 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, did, prev); 186 if (!pdev) 187 break; 188 ndev++; 189 d = kzalloc(sizeof(*d), GFP_KERNEL); 190 if (!d) { 191 pci_dev_put(pdev); 192 return -ENOMEM; 193 } 194 195 if (pci_read_config_dword(pdev, off, ®)) { 196 kfree(d); 197 pci_dev_put(pdev); 198 skx_printk(KERN_ERR, "Failed to read bus idx\n"); 199 return -ENODEV; 200 } 201 202 d->bus[0] = GET_BITFIELD(reg, 0, 7); 203 d->bus[1] = GET_BITFIELD(reg, 8, 15); 204 if (type == SKX) { 205 d->seg = pci_domain_nr(pdev->bus); 206 d->bus[2] = GET_BITFIELD(reg, 16, 23); 207 d->bus[3] = GET_BITFIELD(reg, 24, 31); 208 } else { 209 d->seg = GET_BITFIELD(reg, 16, 23); 210 } 211 212 edac_dbg(2, "busses: 0x%x, 0x%x, 0x%x, 0x%x\n", 213 d->bus[0], d->bus[1], d->bus[2], d->bus[3]); 214 list_add_tail(&d->list, &dev_edac_list); 215 prev = pdev; 216 } 217 218 if (list) 219 *list = &dev_edac_list; 220 return ndev; 221 } 222 223 int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm) 224 { 225 struct pci_dev *pdev; 226 u32 reg; 227 228 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, did, NULL); 229 if (!pdev) { 230 skx_printk(KERN_ERR, "Can't get tolm/tohm\n"); 231 return -ENODEV; 232 } 233 234 if (pci_read_config_dword(pdev, off[0], ®)) { 235 skx_printk(KERN_ERR, "Failed to read tolm\n"); 236 goto fail; 237 } 238 skx_tolm = reg; 239 240 if (pci_read_config_dword(pdev, off[1], ®)) { 241 skx_printk(KERN_ERR, "Failed to read lower tohm\n"); 242 goto fail; 243 } 244 skx_tohm = reg; 245 246 if (pci_read_config_dword(pdev, off[2], ®)) { 247 skx_printk(KERN_ERR, "Failed to read upper tohm\n"); 248 goto fail; 249 } 250 skx_tohm |= (u64)reg << 32; 251 252 pci_dev_put(pdev); 253 *tolm = skx_tolm; 254 *tohm = skx_tohm; 255 edac_dbg(2, "tolm = 0x%llx tohm = 0x%llx\n", skx_tolm, skx_tohm); 256 return 0; 257 fail: 258 pci_dev_put(pdev); 259 return -ENODEV; 260 } 261 262 static int skx_get_dimm_attr(u32 reg, int lobit, int hibit, int add, 263 int minval, int maxval, const char *name) 264 { 265 u32 val = GET_BITFIELD(reg, lobit, hibit); 266 267 if (val < minval || val > maxval) { 268 edac_dbg(2, "bad %s = %d (raw=0x%x)\n", name, val, reg); 269 return -EINVAL; 270 } 271 return val + add; 272 } 273 274 #define numrank(reg) skx_get_dimm_attr(reg, 12, 13, 0, 0, 2, "ranks") 275 #define numrow(reg) skx_get_dimm_attr(reg, 2, 4, 12, 1, 6, "rows") 276 #define numcol(reg) skx_get_dimm_attr(reg, 0, 1, 10, 0, 2, "cols") 277 278 int skx_get_dimm_info(u32 mtr, u32 amap, struct dimm_info *dimm, 279 struct skx_imc *imc, int chan, int dimmno) 280 { 281 int banks = 16, ranks, rows, cols, npages; 282 u64 size; 283 284 ranks = numrank(mtr); 285 rows = numrow(mtr); 286 cols = numcol(mtr); 287 288 /* 289 * Compute size in 8-byte (2^3) words, then shift to MiB (2^20) 290 */ 291 size = ((1ull << (rows + cols + ranks)) * banks) >> (20 - 3); 292 npages = MiB_TO_PAGES(size); 293 294 edac_dbg(0, "mc#%d: channel %d, dimm %d, %lld MiB (%d pages) bank: %d, rank: %d, row: 0x%x, col: 0x%x\n", 295 imc->mc, chan, dimmno, size, npages, 296 banks, 1 << ranks, rows, cols); 297 298 imc->chan[chan].dimms[dimmno].close_pg = GET_BITFIELD(mtr, 0, 0); 299 imc->chan[chan].dimms[dimmno].bank_xor_enable = GET_BITFIELD(mtr, 9, 9); 300 imc->chan[chan].dimms[dimmno].fine_grain_bank = GET_BITFIELD(amap, 0, 0); 301 imc->chan[chan].dimms[dimmno].rowbits = rows; 302 imc->chan[chan].dimms[dimmno].colbits = cols; 303 304 dimm->nr_pages = npages; 305 dimm->grain = 32; 306 dimm->dtype = get_width(mtr); 307 dimm->mtype = MEM_DDR4; 308 dimm->edac_mode = EDAC_SECDED; /* likely better than this */ 309 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u", 310 imc->src_id, imc->lmc, chan, dimmno); 311 312 return 1; 313 } 314 315 int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc, 316 int chan, int dimmno, const char *mod_str) 317 { 318 int smbios_handle; 319 u32 dev_handle; 320 u16 flags; 321 u64 size = 0; 322 323 dev_handle = ACPI_NFIT_BUILD_DEVICE_HANDLE(dimmno, chan, imc->lmc, 324 imc->src_id, 0); 325 326 smbios_handle = nfit_get_smbios_id(dev_handle, &flags); 327 if (smbios_handle == -EOPNOTSUPP) { 328 pr_warn_once("%s: Can't find size of NVDIMM. Try enabling CONFIG_ACPI_NFIT\n", mod_str); 329 goto unknown_size; 330 } 331 332 if (smbios_handle < 0) { 333 skx_printk(KERN_ERR, "Can't find handle for NVDIMM ADR=0x%x\n", dev_handle); 334 goto unknown_size; 335 } 336 337 if (flags & ACPI_NFIT_MEM_MAP_FAILED) { 338 skx_printk(KERN_ERR, "NVDIMM ADR=0x%x is not mapped\n", dev_handle); 339 goto unknown_size; 340 } 341 342 size = dmi_memdev_size(smbios_handle); 343 if (size == ~0ull) 344 skx_printk(KERN_ERR, "Can't find size for NVDIMM ADR=0x%x/SMBIOS=0x%x\n", 345 dev_handle, smbios_handle); 346 347 unknown_size: 348 dimm->nr_pages = size >> PAGE_SHIFT; 349 dimm->grain = 32; 350 dimm->dtype = DEV_UNKNOWN; 351 dimm->mtype = MEM_NVDIMM; 352 dimm->edac_mode = EDAC_SECDED; /* likely better than this */ 353 354 edac_dbg(0, "mc#%d: channel %d, dimm %d, %llu MiB (%u pages)\n", 355 imc->mc, chan, dimmno, size >> 20, dimm->nr_pages); 356 357 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u", 358 imc->src_id, imc->lmc, chan, dimmno); 359 360 return (size == 0 || size == ~0ull) ? 0 : 1; 361 } 362 363 int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev, 364 const char *ctl_name, const char *mod_str, 365 get_dimm_config_f get_dimm_config) 366 { 367 struct mem_ctl_info *mci; 368 struct edac_mc_layer layers[2]; 369 struct skx_pvt *pvt; 370 int rc; 371 372 /* Allocate a new MC control structure */ 373 layers[0].type = EDAC_MC_LAYER_CHANNEL; 374 layers[0].size = NUM_CHANNELS; 375 layers[0].is_virt_csrow = false; 376 layers[1].type = EDAC_MC_LAYER_SLOT; 377 layers[1].size = NUM_DIMMS; 378 layers[1].is_virt_csrow = true; 379 mci = edac_mc_alloc(imc->mc, ARRAY_SIZE(layers), layers, 380 sizeof(struct skx_pvt)); 381 382 if (unlikely(!mci)) 383 return -ENOMEM; 384 385 edac_dbg(0, "MC#%d: mci = %p\n", imc->mc, mci); 386 387 /* Associate skx_dev and mci for future usage */ 388 imc->mci = mci; 389 pvt = mci->pvt_info; 390 pvt->imc = imc; 391 392 mci->ctl_name = kasprintf(GFP_KERNEL, "%s#%d IMC#%d", ctl_name, 393 imc->node_id, imc->lmc); 394 if (!mci->ctl_name) { 395 rc = -ENOMEM; 396 goto fail0; 397 } 398 399 mci->mtype_cap = MEM_FLAG_DDR4 | MEM_FLAG_NVDIMM; 400 mci->edac_ctl_cap = EDAC_FLAG_NONE; 401 mci->edac_cap = EDAC_FLAG_NONE; 402 mci->mod_name = mod_str; 403 mci->dev_name = pci_name(pdev); 404 mci->ctl_page_to_phys = NULL; 405 406 rc = get_dimm_config(mci); 407 if (rc < 0) 408 goto fail; 409 410 /* Record ptr to the generic device */ 411 mci->pdev = &pdev->dev; 412 413 /* Add this new MC control structure to EDAC's list of MCs */ 414 if (unlikely(edac_mc_add_mc(mci))) { 415 edac_dbg(0, "MC: failed edac_mc_add_mc()\n"); 416 rc = -EINVAL; 417 goto fail; 418 } 419 420 return 0; 421 422 fail: 423 kfree(mci->ctl_name); 424 fail0: 425 edac_mc_free(mci); 426 imc->mci = NULL; 427 return rc; 428 } 429 430 static void skx_unregister_mci(struct skx_imc *imc) 431 { 432 struct mem_ctl_info *mci = imc->mci; 433 434 if (!mci) 435 return; 436 437 edac_dbg(0, "MC%d: mci = %p\n", imc->mc, mci); 438 439 /* Remove MC sysfs nodes */ 440 edac_mc_del_mc(mci->pdev); 441 442 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name); 443 kfree(mci->ctl_name); 444 edac_mc_free(mci); 445 } 446 447 static struct mem_ctl_info *get_mci(int src_id, int lmc) 448 { 449 struct skx_dev *d; 450 451 if (lmc > NUM_IMC - 1) { 452 skx_printk(KERN_ERR, "Bad lmc %d\n", lmc); 453 return NULL; 454 } 455 456 list_for_each_entry(d, &dev_edac_list, list) { 457 if (d->imc[0].src_id == src_id) 458 return d->imc[lmc].mci; 459 } 460 461 skx_printk(KERN_ERR, "No mci for src_id %d lmc %d\n", src_id, lmc); 462 return NULL; 463 } 464 465 static void skx_mce_output_error(struct mem_ctl_info *mci, 466 const struct mce *m, 467 struct decoded_addr *res) 468 { 469 enum hw_event_mc_err_type tp_event; 470 char *type, *optype; 471 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0); 472 bool overflow = GET_BITFIELD(m->status, 62, 62); 473 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61); 474 bool recoverable; 475 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52); 476 u32 mscod = GET_BITFIELD(m->status, 16, 31); 477 u32 errcode = GET_BITFIELD(m->status, 0, 15); 478 u32 optypenum = GET_BITFIELD(m->status, 4, 6); 479 480 recoverable = GET_BITFIELD(m->status, 56, 56); 481 482 if (uncorrected_error) { 483 core_err_cnt = 1; 484 if (ripv) { 485 type = "FATAL"; 486 tp_event = HW_EVENT_ERR_FATAL; 487 } else { 488 type = "NON_FATAL"; 489 tp_event = HW_EVENT_ERR_UNCORRECTED; 490 } 491 } else { 492 type = "CORRECTED"; 493 tp_event = HW_EVENT_ERR_CORRECTED; 494 } 495 496 /* 497 * According to Intel Architecture spec vol 3B, 498 * Table 15-10 "IA32_MCi_Status [15:0] Compound Error Code Encoding" 499 * memory errors should fit one of these masks: 500 * 000f 0000 1mmm cccc (binary) 501 * 000f 0010 1mmm cccc (binary) [RAM used as cache] 502 * where: 503 * f = Correction Report Filtering Bit. If 1, subsequent errors 504 * won't be shown 505 * mmm = error type 506 * cccc = channel 507 * If the mask doesn't match, report an error to the parsing logic 508 */ 509 if (!((errcode & 0xef80) == 0x80 || (errcode & 0xef80) == 0x280)) { 510 optype = "Can't parse: it is not a mem"; 511 } else { 512 switch (optypenum) { 513 case 0: 514 optype = "generic undef request error"; 515 break; 516 case 1: 517 optype = "memory read error"; 518 break; 519 case 2: 520 optype = "memory write error"; 521 break; 522 case 3: 523 optype = "addr/cmd error"; 524 break; 525 case 4: 526 optype = "memory scrubbing error"; 527 break; 528 default: 529 optype = "reserved"; 530 break; 531 } 532 } 533 if (adxl_component_count) { 534 snprintf(skx_msg, MSG_SIZE, "%s%s err_code:0x%04x:0x%04x %s", 535 overflow ? " OVERFLOW" : "", 536 (uncorrected_error && recoverable) ? " recoverable" : "", 537 mscod, errcode, adxl_msg); 538 } else { 539 snprintf(skx_msg, MSG_SIZE, 540 "%s%s err_code:0x%04x:0x%04x socket:%d imc:%d rank:%d bg:%d ba:%d row:0x%x col:0x%x", 541 overflow ? " OVERFLOW" : "", 542 (uncorrected_error && recoverable) ? " recoverable" : "", 543 mscod, errcode, 544 res->socket, res->imc, res->rank, 545 res->bank_group, res->bank_address, res->row, res->column); 546 } 547 548 edac_dbg(0, "%s\n", skx_msg); 549 550 /* Call the helper to output message */ 551 edac_mc_handle_error(tp_event, mci, core_err_cnt, 552 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, 553 res->channel, res->dimm, -1, 554 optype, skx_msg); 555 } 556 557 int skx_mce_check_error(struct notifier_block *nb, unsigned long val, 558 void *data) 559 { 560 struct mce *mce = (struct mce *)data; 561 struct decoded_addr res; 562 struct mem_ctl_info *mci; 563 char *type; 564 565 if (edac_get_report_status() == EDAC_REPORTING_DISABLED) 566 return NOTIFY_DONE; 567 568 /* ignore unless this is memory related with an address */ 569 if ((mce->status & 0xefff) >> 7 != 1 || !(mce->status & MCI_STATUS_ADDRV)) 570 return NOTIFY_DONE; 571 572 memset(&res, 0, sizeof(res)); 573 res.addr = mce->addr; 574 575 if (adxl_component_count) { 576 if (!skx_adxl_decode(&res)) 577 return NOTIFY_DONE; 578 579 mci = get_mci(res.socket, res.imc); 580 } else { 581 if (!skx_decode || !skx_decode(&res)) 582 return NOTIFY_DONE; 583 584 mci = res.dev->imc[res.imc].mci; 585 } 586 587 if (!mci) 588 return NOTIFY_DONE; 589 590 if (mce->mcgstatus & MCG_STATUS_MCIP) 591 type = "Exception"; 592 else 593 type = "Event"; 594 595 skx_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n"); 596 597 skx_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: 0x%llx " 598 "Bank %d: 0x%llx\n", mce->extcpu, type, 599 mce->mcgstatus, mce->bank, mce->status); 600 skx_mc_printk(mci, KERN_DEBUG, "TSC 0x%llx ", mce->tsc); 601 skx_mc_printk(mci, KERN_DEBUG, "ADDR 0x%llx ", mce->addr); 602 skx_mc_printk(mci, KERN_DEBUG, "MISC 0x%llx ", mce->misc); 603 604 skx_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:0x%x TIME %llu SOCKET " 605 "%u APIC 0x%x\n", mce->cpuvendor, mce->cpuid, 606 mce->time, mce->socketid, mce->apicid); 607 608 skx_mce_output_error(mci, mce, &res); 609 610 return NOTIFY_DONE; 611 } 612 613 void skx_remove(void) 614 { 615 int i, j; 616 struct skx_dev *d, *tmp; 617 618 edac_dbg(0, "\n"); 619 620 list_for_each_entry_safe(d, tmp, &dev_edac_list, list) { 621 list_del(&d->list); 622 for (i = 0; i < NUM_IMC; i++) { 623 if (d->imc[i].mci) 624 skx_unregister_mci(&d->imc[i]); 625 626 if (d->imc[i].mdev) 627 pci_dev_put(d->imc[i].mdev); 628 629 if (d->imc[i].mbase) 630 iounmap(d->imc[i].mbase); 631 632 for (j = 0; j < NUM_CHANNELS; j++) { 633 if (d->imc[i].chan[j].cdev) 634 pci_dev_put(d->imc[i].chan[j].cdev); 635 } 636 } 637 if (d->util_all) 638 pci_dev_put(d->util_all); 639 if (d->sad_all) 640 pci_dev_put(d->sad_all); 641 if (d->uracu) 642 pci_dev_put(d->uracu); 643 644 kfree(d); 645 } 646 } 647 648 #ifdef CONFIG_EDAC_DEBUG 649 /* 650 * Debug feature. 651 * Exercise the address decode logic by writing an address to 652 * /sys/kernel/debug/edac/dirname/addr. 653 */ 654 static struct dentry *skx_test; 655 656 static int debugfs_u64_set(void *data, u64 val) 657 { 658 struct mce m; 659 660 pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val); 661 662 memset(&m, 0, sizeof(m)); 663 /* ADDRV + MemRd + Unknown channel */ 664 m.status = MCI_STATUS_ADDRV + 0x90; 665 /* One corrected error */ 666 m.status |= BIT_ULL(MCI_STATUS_CEC_SHIFT); 667 m.addr = val; 668 skx_mce_check_error(NULL, 0, &m); 669 670 return 0; 671 } 672 DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n"); 673 674 void setup_skx_debug(const char *dirname) 675 { 676 skx_test = edac_debugfs_create_dir(dirname); 677 if (!skx_test) 678 return; 679 680 if (!edac_debugfs_create_file("addr", 0200, skx_test, 681 NULL, &fops_u64_wo)) { 682 debugfs_remove(skx_test); 683 skx_test = NULL; 684 } 685 } 686 687 void teardown_skx_debug(void) 688 { 689 debugfs_remove_recursive(skx_test); 690 } 691 #endif /*CONFIG_EDAC_DEBUG*/ 692