1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * 4 * Shared code by both skx_edac and i10nm_edac. Originally split out 5 * from the skx_edac driver. 6 * 7 * This file is linked into both skx_edac and i10nm_edac drivers. In 8 * order to avoid link errors, this file must be like a pure library 9 * without including symbols and defines which would otherwise conflict, 10 * when linked once into a module and into a built-in object, at the 11 * same time. For example, __this_module symbol references when that 12 * file is being linked into a built-in object. 13 * 14 * Copyright (c) 2018, Intel Corporation. 15 */ 16 17 #include <linux/acpi.h> 18 #include <linux/dmi.h> 19 #include <linux/adxl.h> 20 #include <acpi/nfit.h> 21 #include <asm/mce.h> 22 #include "edac_module.h" 23 #include "skx_common.h" 24 25 static const char * const component_names[] = { 26 [INDEX_SOCKET] = "ProcessorSocketId", 27 [INDEX_MEMCTRL] = "MemoryControllerId", 28 [INDEX_CHANNEL] = "ChannelId", 29 [INDEX_DIMM] = "DimmSlotId", 30 [INDEX_CS] = "ChipSelect", 31 [INDEX_NM_MEMCTRL] = "NmMemoryControllerId", 32 [INDEX_NM_CHANNEL] = "NmChannelId", 33 [INDEX_NM_DIMM] = "NmDimmSlotId", 34 [INDEX_NM_CS] = "NmChipSelect", 35 }; 36 37 static int component_indices[ARRAY_SIZE(component_names)]; 38 static int adxl_component_count; 39 static const char * const *adxl_component_names; 40 static u64 *adxl_values; 41 static char *adxl_msg; 42 static unsigned long adxl_nm_bitmap; 43 44 static char skx_msg[MSG_SIZE]; 45 static skx_decode_f driver_decode; 46 static skx_show_retry_log_f skx_show_retry_rd_err_log; 47 static u64 skx_tolm, skx_tohm; 48 static LIST_HEAD(dev_edac_list); 49 static bool skx_mem_cfg_2lm; 50 static struct res_config *skx_res_cfg; 51 52 int skx_adxl_get(void) 53 { 54 const char * const *names; 55 int i, j; 56 57 names = adxl_get_component_names(); 58 if (!names) { 59 skx_printk(KERN_NOTICE, "No firmware support for address translation.\n"); 60 return -ENODEV; 61 } 62 63 for (i = 0; i < INDEX_MAX; i++) { 64 for (j = 0; names[j]; j++) { 65 if (!strcmp(component_names[i], names[j])) { 66 component_indices[i] = j; 67 68 if (i >= INDEX_NM_FIRST) 69 adxl_nm_bitmap |= 1 << i; 70 71 break; 72 } 73 } 74 75 if (!names[j] && i < INDEX_NM_FIRST) 76 goto err; 77 } 78 79 if (skx_mem_cfg_2lm) { 80 if (!adxl_nm_bitmap) 81 skx_printk(KERN_NOTICE, "Not enough ADXL components for 2-level memory.\n"); 82 else 83 edac_dbg(2, "adxl_nm_bitmap: 0x%lx\n", adxl_nm_bitmap); 84 } 85 86 adxl_component_names = names; 87 while (*names++) 88 adxl_component_count++; 89 90 adxl_values = kcalloc(adxl_component_count, sizeof(*adxl_values), 91 GFP_KERNEL); 92 if (!adxl_values) { 93 adxl_component_count = 0; 94 return -ENOMEM; 95 } 96 97 adxl_msg = kzalloc(MSG_SIZE, GFP_KERNEL); 98 if (!adxl_msg) { 99 adxl_component_count = 0; 100 kfree(adxl_values); 101 return -ENOMEM; 102 } 103 104 return 0; 105 err: 106 skx_printk(KERN_ERR, "'%s' is not matched from DSM parameters: ", 107 component_names[i]); 108 for (j = 0; names[j]; j++) 109 skx_printk(KERN_CONT, "%s ", names[j]); 110 skx_printk(KERN_CONT, "\n"); 111 112 return -ENODEV; 113 } 114 EXPORT_SYMBOL_GPL(skx_adxl_get); 115 116 void skx_adxl_put(void) 117 { 118 kfree(adxl_values); 119 kfree(adxl_msg); 120 } 121 EXPORT_SYMBOL_GPL(skx_adxl_put); 122 123 static void skx_init_mc_mapping(struct skx_dev *d) 124 { 125 /* 126 * By default, the BIOS presents all memory controllers within each 127 * socket to the EDAC driver. The physical indices are the same as 128 * the logical indices of the memory controllers enumerated by the 129 * EDAC driver. 130 */ 131 for (int i = 0; i < NUM_IMC; i++) 132 d->mc_mapping[i] = i; 133 } 134 135 void skx_set_mc_mapping(struct skx_dev *d, u8 pmc, u8 lmc) 136 { 137 edac_dbg(0, "Set the mapping of mc phy idx to logical idx: %02d -> %02d\n", 138 pmc, lmc); 139 140 d->mc_mapping[pmc] = lmc; 141 } 142 EXPORT_SYMBOL_GPL(skx_set_mc_mapping); 143 144 static u8 skx_get_mc_mapping(struct skx_dev *d, u8 pmc) 145 { 146 edac_dbg(0, "Get the mapping of mc phy idx to logical idx: %02d -> %02d\n", 147 pmc, d->mc_mapping[pmc]); 148 149 return d->mc_mapping[pmc]; 150 } 151 152 static bool skx_adxl_decode(struct decoded_addr *res, enum error_source err_src) 153 { 154 struct skx_dev *d; 155 int i, len = 0; 156 157 if (res->addr >= skx_tohm || (res->addr >= skx_tolm && 158 res->addr < BIT_ULL(32))) { 159 edac_dbg(0, "Address 0x%llx out of range\n", res->addr); 160 return false; 161 } 162 163 if (adxl_decode(res->addr, adxl_values)) { 164 edac_dbg(0, "Failed to decode 0x%llx\n", res->addr); 165 return false; 166 } 167 168 /* 169 * GNR with a Flat2LM memory configuration may mistakenly classify 170 * a near-memory error(DDR5) as a far-memory error(CXL), resulting 171 * in the incorrect selection of decoded ADXL components. 172 * To address this, prefetch the decoded far-memory controller ID 173 * and adjust the error source to near-memory if the far-memory 174 * controller ID is invalid. 175 */ 176 if (skx_res_cfg && skx_res_cfg->type == GNR && err_src == ERR_SRC_2LM_FM) { 177 res->imc = (int)adxl_values[component_indices[INDEX_MEMCTRL]]; 178 if (res->imc == -1) { 179 err_src = ERR_SRC_2LM_NM; 180 edac_dbg(0, "Adjust the error source to near-memory.\n"); 181 } 182 } 183 184 res->socket = (int)adxl_values[component_indices[INDEX_SOCKET]]; 185 if (err_src == ERR_SRC_2LM_NM) { 186 res->imc = (adxl_nm_bitmap & BIT_NM_MEMCTRL) ? 187 (int)adxl_values[component_indices[INDEX_NM_MEMCTRL]] : -1; 188 res->channel = (adxl_nm_bitmap & BIT_NM_CHANNEL) ? 189 (int)adxl_values[component_indices[INDEX_NM_CHANNEL]] : -1; 190 res->dimm = (adxl_nm_bitmap & BIT_NM_DIMM) ? 191 (int)adxl_values[component_indices[INDEX_NM_DIMM]] : -1; 192 res->cs = (adxl_nm_bitmap & BIT_NM_CS) ? 193 (int)adxl_values[component_indices[INDEX_NM_CS]] : -1; 194 } else { 195 res->imc = (int)adxl_values[component_indices[INDEX_MEMCTRL]]; 196 res->channel = (int)adxl_values[component_indices[INDEX_CHANNEL]]; 197 res->dimm = (int)adxl_values[component_indices[INDEX_DIMM]]; 198 res->cs = (int)adxl_values[component_indices[INDEX_CS]]; 199 } 200 201 if (res->imc > NUM_IMC - 1 || res->imc < 0) { 202 skx_printk(KERN_ERR, "Bad imc %d\n", res->imc); 203 return false; 204 } 205 206 list_for_each_entry(d, &dev_edac_list, list) { 207 if (d->imc[0].src_id == res->socket) { 208 res->dev = d; 209 break; 210 } 211 } 212 213 if (!res->dev) { 214 skx_printk(KERN_ERR, "No device for src_id %d imc %d\n", 215 res->socket, res->imc); 216 return false; 217 } 218 219 res->imc = skx_get_mc_mapping(d, res->imc); 220 221 for (i = 0; i < adxl_component_count; i++) { 222 if (adxl_values[i] == ~0x0ull) 223 continue; 224 225 len += snprintf(adxl_msg + len, MSG_SIZE - len, " %s:0x%llx", 226 adxl_component_names[i], adxl_values[i]); 227 if (MSG_SIZE - len <= 0) 228 break; 229 } 230 231 res->decoded_by_adxl = true; 232 233 return true; 234 } 235 236 void skx_set_mem_cfg(bool mem_cfg_2lm) 237 { 238 skx_mem_cfg_2lm = mem_cfg_2lm; 239 } 240 EXPORT_SYMBOL_GPL(skx_set_mem_cfg); 241 242 void skx_set_res_cfg(struct res_config *cfg) 243 { 244 skx_res_cfg = cfg; 245 } 246 EXPORT_SYMBOL_GPL(skx_set_res_cfg); 247 248 void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log) 249 { 250 driver_decode = decode; 251 skx_show_retry_rd_err_log = show_retry_log; 252 } 253 EXPORT_SYMBOL_GPL(skx_set_decode); 254 255 int skx_get_src_id(struct skx_dev *d, int off, u8 *id) 256 { 257 u32 reg; 258 259 if (pci_read_config_dword(d->util_all, off, ®)) { 260 skx_printk(KERN_ERR, "Failed to read src id\n"); 261 return -ENODEV; 262 } 263 264 *id = GET_BITFIELD(reg, 12, 14); 265 return 0; 266 } 267 EXPORT_SYMBOL_GPL(skx_get_src_id); 268 269 int skx_get_node_id(struct skx_dev *d, u8 *id) 270 { 271 u32 reg; 272 273 if (pci_read_config_dword(d->util_all, 0xf4, ®)) { 274 skx_printk(KERN_ERR, "Failed to read node id\n"); 275 return -ENODEV; 276 } 277 278 *id = GET_BITFIELD(reg, 0, 2); 279 return 0; 280 } 281 EXPORT_SYMBOL_GPL(skx_get_node_id); 282 283 static int get_width(u32 mtr) 284 { 285 switch (GET_BITFIELD(mtr, 8, 9)) { 286 case 0: 287 return DEV_X4; 288 case 1: 289 return DEV_X8; 290 case 2: 291 return DEV_X16; 292 } 293 return DEV_UNKNOWN; 294 } 295 296 /* 297 * We use the per-socket device @cfg->did to count how many sockets are present, 298 * and to detemine which PCI buses are associated with each socket. Allocate 299 * and build the full list of all the skx_dev structures that we need here. 300 */ 301 int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **list) 302 { 303 struct pci_dev *pdev, *prev; 304 struct skx_dev *d; 305 u32 reg; 306 int ndev = 0; 307 308 prev = NULL; 309 for (;;) { 310 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, cfg->decs_did, prev); 311 if (!pdev) 312 break; 313 ndev++; 314 d = kzalloc(sizeof(*d), GFP_KERNEL); 315 if (!d) { 316 pci_dev_put(pdev); 317 return -ENOMEM; 318 } 319 320 if (pci_read_config_dword(pdev, cfg->busno_cfg_offset, ®)) { 321 kfree(d); 322 pci_dev_put(pdev); 323 skx_printk(KERN_ERR, "Failed to read bus idx\n"); 324 return -ENODEV; 325 } 326 327 d->bus[0] = GET_BITFIELD(reg, 0, 7); 328 d->bus[1] = GET_BITFIELD(reg, 8, 15); 329 if (cfg->type == SKX) { 330 d->seg = pci_domain_nr(pdev->bus); 331 d->bus[2] = GET_BITFIELD(reg, 16, 23); 332 d->bus[3] = GET_BITFIELD(reg, 24, 31); 333 } else { 334 d->seg = GET_BITFIELD(reg, 16, 23); 335 } 336 337 edac_dbg(2, "busses: 0x%x, 0x%x, 0x%x, 0x%x\n", 338 d->bus[0], d->bus[1], d->bus[2], d->bus[3]); 339 list_add_tail(&d->list, &dev_edac_list); 340 prev = pdev; 341 342 skx_init_mc_mapping(d); 343 } 344 345 if (list) 346 *list = &dev_edac_list; 347 return ndev; 348 } 349 EXPORT_SYMBOL_GPL(skx_get_all_bus_mappings); 350 351 int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm) 352 { 353 struct pci_dev *pdev; 354 u32 reg; 355 356 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, did, NULL); 357 if (!pdev) { 358 edac_dbg(2, "Can't get tolm/tohm\n"); 359 return -ENODEV; 360 } 361 362 if (pci_read_config_dword(pdev, off[0], ®)) { 363 skx_printk(KERN_ERR, "Failed to read tolm\n"); 364 goto fail; 365 } 366 skx_tolm = reg; 367 368 if (pci_read_config_dword(pdev, off[1], ®)) { 369 skx_printk(KERN_ERR, "Failed to read lower tohm\n"); 370 goto fail; 371 } 372 skx_tohm = reg; 373 374 if (pci_read_config_dword(pdev, off[2], ®)) { 375 skx_printk(KERN_ERR, "Failed to read upper tohm\n"); 376 goto fail; 377 } 378 skx_tohm |= (u64)reg << 32; 379 380 pci_dev_put(pdev); 381 *tolm = skx_tolm; 382 *tohm = skx_tohm; 383 edac_dbg(2, "tolm = 0x%llx tohm = 0x%llx\n", skx_tolm, skx_tohm); 384 return 0; 385 fail: 386 pci_dev_put(pdev); 387 return -ENODEV; 388 } 389 EXPORT_SYMBOL_GPL(skx_get_hi_lo); 390 391 static int skx_get_dimm_attr(u32 reg, int lobit, int hibit, int add, 392 int minval, int maxval, const char *name) 393 { 394 u32 val = GET_BITFIELD(reg, lobit, hibit); 395 396 if (val < minval || val > maxval) { 397 edac_dbg(2, "bad %s = %d (raw=0x%x)\n", name, val, reg); 398 return -EINVAL; 399 } 400 return val + add; 401 } 402 403 #define numrank(reg) skx_get_dimm_attr(reg, 12, 13, 0, 0, 2, "ranks") 404 #define numrow(reg) skx_get_dimm_attr(reg, 2, 4, 12, 1, 6, "rows") 405 #define numcol(reg) skx_get_dimm_attr(reg, 0, 1, 10, 0, 2, "cols") 406 407 int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm, 408 struct skx_imc *imc, int chan, int dimmno, 409 struct res_config *cfg) 410 { 411 int banks, ranks, rows, cols, npages; 412 enum mem_type mtype; 413 u64 size; 414 415 ranks = numrank(mtr); 416 rows = numrow(mtr); 417 cols = imc->hbm_mc ? 6 : numcol(mtr); 418 419 if (imc->hbm_mc) { 420 banks = 32; 421 mtype = MEM_HBM2; 422 } else if (cfg->support_ddr5 && (amap & 0x8)) { 423 banks = 32; 424 mtype = MEM_DDR5; 425 } else { 426 banks = 16; 427 mtype = MEM_DDR4; 428 } 429 430 /* 431 * Compute size in 8-byte (2^3) words, then shift to MiB (2^20) 432 */ 433 size = ((1ull << (rows + cols + ranks)) * banks) >> (20 - 3); 434 npages = MiB_TO_PAGES(size); 435 436 edac_dbg(0, "mc#%d: channel %d, dimm %d, %lld MiB (%d pages) bank: %d, rank: %d, row: 0x%x, col: 0x%x\n", 437 imc->mc, chan, dimmno, size, npages, 438 banks, 1 << ranks, rows, cols); 439 440 imc->chan[chan].dimms[dimmno].close_pg = GET_BITFIELD(mcmtr, 0, 0); 441 imc->chan[chan].dimms[dimmno].bank_xor_enable = GET_BITFIELD(mcmtr, 9, 9); 442 imc->chan[chan].dimms[dimmno].fine_grain_bank = GET_BITFIELD(amap, 0, 0); 443 imc->chan[chan].dimms[dimmno].rowbits = rows; 444 imc->chan[chan].dimms[dimmno].colbits = cols; 445 446 dimm->nr_pages = npages; 447 dimm->grain = 32; 448 dimm->dtype = get_width(mtr); 449 dimm->mtype = mtype; 450 dimm->edac_mode = EDAC_SECDED; /* likely better than this */ 451 452 if (imc->hbm_mc) 453 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_HBMC#%u_Chan#%u", 454 imc->src_id, imc->lmc, chan); 455 else 456 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u", 457 imc->src_id, imc->lmc, chan, dimmno); 458 459 return 1; 460 } 461 EXPORT_SYMBOL_GPL(skx_get_dimm_info); 462 463 int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc, 464 int chan, int dimmno, const char *mod_str) 465 { 466 int smbios_handle; 467 u32 dev_handle; 468 u16 flags; 469 u64 size = 0; 470 471 dev_handle = ACPI_NFIT_BUILD_DEVICE_HANDLE(dimmno, chan, imc->lmc, 472 imc->src_id, 0); 473 474 smbios_handle = nfit_get_smbios_id(dev_handle, &flags); 475 if (smbios_handle == -EOPNOTSUPP) { 476 pr_warn_once("%s: Can't find size of NVDIMM. Try enabling CONFIG_ACPI_NFIT\n", mod_str); 477 goto unknown_size; 478 } 479 480 if (smbios_handle < 0) { 481 skx_printk(KERN_ERR, "Can't find handle for NVDIMM ADR=0x%x\n", dev_handle); 482 goto unknown_size; 483 } 484 485 if (flags & ACPI_NFIT_MEM_MAP_FAILED) { 486 skx_printk(KERN_ERR, "NVDIMM ADR=0x%x is not mapped\n", dev_handle); 487 goto unknown_size; 488 } 489 490 size = dmi_memdev_size(smbios_handle); 491 if (size == ~0ull) 492 skx_printk(KERN_ERR, "Can't find size for NVDIMM ADR=0x%x/SMBIOS=0x%x\n", 493 dev_handle, smbios_handle); 494 495 unknown_size: 496 dimm->nr_pages = size >> PAGE_SHIFT; 497 dimm->grain = 32; 498 dimm->dtype = DEV_UNKNOWN; 499 dimm->mtype = MEM_NVDIMM; 500 dimm->edac_mode = EDAC_SECDED; /* likely better than this */ 501 502 edac_dbg(0, "mc#%d: channel %d, dimm %d, %llu MiB (%u pages)\n", 503 imc->mc, chan, dimmno, size >> 20, dimm->nr_pages); 504 505 snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u", 506 imc->src_id, imc->lmc, chan, dimmno); 507 508 return (size == 0 || size == ~0ull) ? 0 : 1; 509 } 510 EXPORT_SYMBOL_GPL(skx_get_nvdimm_info); 511 512 int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev, 513 const char *ctl_name, const char *mod_str, 514 get_dimm_config_f get_dimm_config, 515 struct res_config *cfg) 516 { 517 struct mem_ctl_info *mci; 518 struct edac_mc_layer layers[2]; 519 struct skx_pvt *pvt; 520 int rc; 521 522 /* Allocate a new MC control structure */ 523 layers[0].type = EDAC_MC_LAYER_CHANNEL; 524 layers[0].size = NUM_CHANNELS; 525 layers[0].is_virt_csrow = false; 526 layers[1].type = EDAC_MC_LAYER_SLOT; 527 layers[1].size = NUM_DIMMS; 528 layers[1].is_virt_csrow = true; 529 mci = edac_mc_alloc(imc->mc, ARRAY_SIZE(layers), layers, 530 sizeof(struct skx_pvt)); 531 532 if (unlikely(!mci)) 533 return -ENOMEM; 534 535 edac_dbg(0, "MC#%d: mci = %p\n", imc->mc, mci); 536 537 /* Associate skx_dev and mci for future usage */ 538 imc->mci = mci; 539 pvt = mci->pvt_info; 540 pvt->imc = imc; 541 542 mci->ctl_name = kasprintf(GFP_KERNEL, "%s#%d IMC#%d", ctl_name, 543 imc->node_id, imc->lmc); 544 if (!mci->ctl_name) { 545 rc = -ENOMEM; 546 goto fail0; 547 } 548 549 mci->mtype_cap = MEM_FLAG_DDR4 | MEM_FLAG_NVDIMM; 550 if (cfg->support_ddr5) 551 mci->mtype_cap |= MEM_FLAG_DDR5; 552 mci->edac_ctl_cap = EDAC_FLAG_NONE; 553 mci->edac_cap = EDAC_FLAG_NONE; 554 mci->mod_name = mod_str; 555 mci->dev_name = pci_name(pdev); 556 mci->ctl_page_to_phys = NULL; 557 558 rc = get_dimm_config(mci, cfg); 559 if (rc < 0) 560 goto fail; 561 562 /* Record ptr to the generic device */ 563 mci->pdev = &pdev->dev; 564 565 /* Add this new MC control structure to EDAC's list of MCs */ 566 if (unlikely(edac_mc_add_mc(mci))) { 567 edac_dbg(0, "MC: failed edac_mc_add_mc()\n"); 568 rc = -EINVAL; 569 goto fail; 570 } 571 572 return 0; 573 574 fail: 575 kfree(mci->ctl_name); 576 fail0: 577 edac_mc_free(mci); 578 imc->mci = NULL; 579 return rc; 580 } 581 EXPORT_SYMBOL_GPL(skx_register_mci); 582 583 static void skx_unregister_mci(struct skx_imc *imc) 584 { 585 struct mem_ctl_info *mci = imc->mci; 586 587 if (!mci) 588 return; 589 590 edac_dbg(0, "MC%d: mci = %p\n", imc->mc, mci); 591 592 /* Remove MC sysfs nodes */ 593 edac_mc_del_mc(mci->pdev); 594 595 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name); 596 kfree(mci->ctl_name); 597 edac_mc_free(mci); 598 } 599 600 static void skx_mce_output_error(struct mem_ctl_info *mci, 601 const struct mce *m, 602 struct decoded_addr *res) 603 { 604 enum hw_event_mc_err_type tp_event; 605 char *optype; 606 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0); 607 bool overflow = GET_BITFIELD(m->status, 62, 62); 608 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61); 609 bool scrub_err = false; 610 bool recoverable; 611 int len; 612 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52); 613 u32 mscod = GET_BITFIELD(m->status, 16, 31); 614 u32 errcode = GET_BITFIELD(m->status, 0, 15); 615 u32 optypenum = GET_BITFIELD(m->status, 4, 6); 616 617 recoverable = GET_BITFIELD(m->status, 56, 56); 618 619 if (uncorrected_error) { 620 core_err_cnt = 1; 621 if (ripv) { 622 tp_event = HW_EVENT_ERR_UNCORRECTED; 623 } else { 624 tp_event = HW_EVENT_ERR_FATAL; 625 } 626 } else { 627 tp_event = HW_EVENT_ERR_CORRECTED; 628 } 629 630 switch (optypenum) { 631 case 0: 632 optype = "generic undef request error"; 633 break; 634 case 1: 635 optype = "memory read error"; 636 break; 637 case 2: 638 optype = "memory write error"; 639 break; 640 case 3: 641 optype = "addr/cmd error"; 642 break; 643 case 4: 644 optype = "memory scrubbing error"; 645 scrub_err = true; 646 break; 647 default: 648 optype = "reserved"; 649 break; 650 } 651 652 if (res->decoded_by_adxl) { 653 len = snprintf(skx_msg, MSG_SIZE, "%s%s err_code:0x%04x:0x%04x %s", 654 overflow ? " OVERFLOW" : "", 655 (uncorrected_error && recoverable) ? " recoverable" : "", 656 mscod, errcode, adxl_msg); 657 } else { 658 len = snprintf(skx_msg, MSG_SIZE, 659 "%s%s err_code:0x%04x:0x%04x ProcessorSocketId:0x%x MemoryControllerId:0x%x PhysicalRankId:0x%x Row:0x%x Column:0x%x Bank:0x%x BankGroup:0x%x", 660 overflow ? " OVERFLOW" : "", 661 (uncorrected_error && recoverable) ? " recoverable" : "", 662 mscod, errcode, 663 res->socket, res->imc, res->rank, 664 res->row, res->column, res->bank_address, res->bank_group); 665 } 666 667 if (skx_show_retry_rd_err_log) 668 skx_show_retry_rd_err_log(res, skx_msg + len, MSG_SIZE - len, scrub_err); 669 670 edac_dbg(0, "%s\n", skx_msg); 671 672 /* Call the helper to output message */ 673 edac_mc_handle_error(tp_event, mci, core_err_cnt, 674 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, 675 res->channel, res->dimm, -1, 676 optype, skx_msg); 677 } 678 679 static enum error_source skx_error_source(const struct mce *m) 680 { 681 u32 errcode = GET_BITFIELD(m->status, 0, 15) & MCACOD_MEM_ERR_MASK; 682 683 if (errcode != MCACOD_MEM_CTL_ERR && errcode != MCACOD_EXT_MEM_ERR) 684 return ERR_SRC_NOT_MEMORY; 685 686 if (!skx_mem_cfg_2lm) 687 return ERR_SRC_1LM; 688 689 if (errcode == MCACOD_EXT_MEM_ERR) 690 return ERR_SRC_2LM_NM; 691 692 return ERR_SRC_2LM_FM; 693 } 694 695 int skx_mce_check_error(struct notifier_block *nb, unsigned long val, 696 void *data) 697 { 698 struct mce *mce = (struct mce *)data; 699 enum error_source err_src; 700 struct decoded_addr res; 701 struct mem_ctl_info *mci; 702 char *type; 703 704 if (mce->kflags & MCE_HANDLED_CEC) 705 return NOTIFY_DONE; 706 707 err_src = skx_error_source(mce); 708 709 /* Ignore unless this is memory related with an address */ 710 if (err_src == ERR_SRC_NOT_MEMORY || !(mce->status & MCI_STATUS_ADDRV)) 711 return NOTIFY_DONE; 712 713 memset(&res, 0, sizeof(res)); 714 res.mce = mce; 715 res.addr = mce->addr & MCI_ADDR_PHYSADDR; 716 if (!pfn_to_online_page(res.addr >> PAGE_SHIFT) && !arch_is_platform_page(res.addr)) { 717 pr_err("Invalid address 0x%llx in IA32_MC%d_ADDR\n", mce->addr, mce->bank); 718 return NOTIFY_DONE; 719 } 720 721 /* Try driver decoder first */ 722 if (!(driver_decode && driver_decode(&res))) { 723 /* Then try firmware decoder (ACPI DSM methods) */ 724 if (!(adxl_component_count && skx_adxl_decode(&res, err_src))) 725 return NOTIFY_DONE; 726 } 727 728 mci = res.dev->imc[res.imc].mci; 729 730 if (!mci) 731 return NOTIFY_DONE; 732 733 if (mce->mcgstatus & MCG_STATUS_MCIP) 734 type = "Exception"; 735 else 736 type = "Event"; 737 738 skx_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n"); 739 740 skx_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: 0x%llx " 741 "Bank %d: 0x%llx\n", mce->extcpu, type, 742 mce->mcgstatus, mce->bank, mce->status); 743 skx_mc_printk(mci, KERN_DEBUG, "TSC 0x%llx ", mce->tsc); 744 skx_mc_printk(mci, KERN_DEBUG, "ADDR 0x%llx ", mce->addr); 745 skx_mc_printk(mci, KERN_DEBUG, "MISC 0x%llx ", mce->misc); 746 747 skx_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:0x%x TIME %llu SOCKET " 748 "%u APIC 0x%x\n", mce->cpuvendor, mce->cpuid, 749 mce->time, mce->socketid, mce->apicid); 750 751 skx_mce_output_error(mci, mce, &res); 752 753 mce->kflags |= MCE_HANDLED_EDAC; 754 return NOTIFY_DONE; 755 } 756 EXPORT_SYMBOL_GPL(skx_mce_check_error); 757 758 void skx_remove(void) 759 { 760 int i, j; 761 struct skx_dev *d, *tmp; 762 763 edac_dbg(0, "\n"); 764 765 list_for_each_entry_safe(d, tmp, &dev_edac_list, list) { 766 list_del(&d->list); 767 for (i = 0; i < NUM_IMC; i++) { 768 if (d->imc[i].mci) 769 skx_unregister_mci(&d->imc[i]); 770 771 if (d->imc[i].mdev) 772 pci_dev_put(d->imc[i].mdev); 773 774 if (d->imc[i].mbase) 775 iounmap(d->imc[i].mbase); 776 777 for (j = 0; j < NUM_CHANNELS; j++) { 778 if (d->imc[i].chan[j].cdev) 779 pci_dev_put(d->imc[i].chan[j].cdev); 780 } 781 } 782 if (d->util_all) 783 pci_dev_put(d->util_all); 784 if (d->pcu_cr3) 785 pci_dev_put(d->pcu_cr3); 786 if (d->sad_all) 787 pci_dev_put(d->sad_all); 788 if (d->uracu) 789 pci_dev_put(d->uracu); 790 791 kfree(d); 792 } 793 } 794 EXPORT_SYMBOL_GPL(skx_remove); 795 796 MODULE_LICENSE("GPL v2"); 797 MODULE_AUTHOR("Tony Luck"); 798 MODULE_DESCRIPTION("MC Driver for Intel server processors"); 799