1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * EDAC driver for Intel(R) Xeon(R) Skylake processors 4 * Copyright (c) 2016, Intel Corporation. 5 */ 6 7 #include <linux/kernel.h> 8 #include <linux/processor.h> 9 #include <asm/cpu_device_id.h> 10 #include <asm/intel-family.h> 11 #include <asm/mce.h> 12 13 #include "edac_module.h" 14 #include "skx_common.h" 15 16 #define EDAC_MOD_STR "skx_edac" 17 18 /* 19 * Debug macros 20 */ 21 #define skx_printk(level, fmt, arg...) \ 22 edac_printk(level, "skx", fmt, ##arg) 23 24 #define skx_mc_printk(mci, level, fmt, arg...) \ 25 edac_mc_chipset_printk(mci, level, "skx", fmt, ##arg) 26 27 static struct list_head *skx_edac_list; 28 29 static u64 skx_tolm, skx_tohm; 30 static int skx_num_sockets; 31 static unsigned int nvdimm_count; 32 33 #define MASK26 0x3FFFFFF /* Mask for 2^26 */ 34 #define MASK29 0x1FFFFFFF /* Mask for 2^29 */ 35 36 static struct skx_dev *get_skx_dev(struct pci_bus *bus, u8 idx) 37 { 38 struct skx_dev *d; 39 40 list_for_each_entry(d, skx_edac_list, list) { 41 if (d->seg == pci_domain_nr(bus) && d->bus[idx] == bus->number) 42 return d; 43 } 44 45 return NULL; 46 } 47 48 enum munittype { 49 CHAN0, CHAN1, CHAN2, SAD_ALL, UTIL_ALL, SAD, 50 ERRCHAN0, ERRCHAN1, ERRCHAN2, 51 }; 52 53 struct munit { 54 u16 did; 55 u16 devfn[SKX_NUM_IMC]; 56 u8 busidx; 57 u8 per_socket; 58 enum munittype mtype; 59 }; 60 61 /* 62 * List of PCI device ids that we need together with some device 63 * number and function numbers to tell which memory controller the 64 * device belongs to. 65 */ 66 static const struct munit skx_all_munits[] = { 67 { 0x2054, { }, 1, 1, SAD_ALL }, 68 { 0x2055, { }, 1, 1, UTIL_ALL }, 69 { 0x2040, { PCI_DEVFN(10, 0), PCI_DEVFN(12, 0) }, 2, 2, CHAN0 }, 70 { 0x2044, { PCI_DEVFN(10, 4), PCI_DEVFN(12, 4) }, 2, 2, CHAN1 }, 71 { 0x2048, { PCI_DEVFN(11, 0), PCI_DEVFN(13, 0) }, 2, 2, CHAN2 }, 72 { 0x2043, { PCI_DEVFN(10, 3), PCI_DEVFN(12, 3) }, 2, 2, ERRCHAN0 }, 73 { 0x2047, { PCI_DEVFN(10, 7), PCI_DEVFN(12, 7) }, 2, 2, ERRCHAN1 }, 74 { 0x204b, { PCI_DEVFN(11, 3), PCI_DEVFN(13, 3) }, 2, 2, ERRCHAN2 }, 75 { 0x208e, { }, 1, 0, SAD }, 76 { } 77 }; 78 79 static int get_all_munits(const struct munit *m) 80 { 81 struct pci_dev *pdev, *prev; 82 struct skx_dev *d; 83 u32 reg; 84 int i = 0, ndev = 0; 85 86 prev = NULL; 87 for (;;) { 88 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, m->did, prev); 89 if (!pdev) 90 break; 91 ndev++; 92 if (m->per_socket == SKX_NUM_IMC) { 93 for (i = 0; i < SKX_NUM_IMC; i++) 94 if (m->devfn[i] == pdev->devfn) 95 break; 96 if (i == SKX_NUM_IMC) 97 goto fail; 98 } 99 d = get_skx_dev(pdev->bus, m->busidx); 100 if (!d) 101 goto fail; 102 103 /* Be sure that the device is enabled */ 104 if (unlikely(pci_enable_device(pdev) < 0)) { 105 skx_printk(KERN_ERR, "Couldn't enable device %04x:%04x\n", 106 PCI_VENDOR_ID_INTEL, m->did); 107 goto fail; 108 } 109 110 switch (m->mtype) { 111 case CHAN0: 112 case CHAN1: 113 case CHAN2: 114 pci_dev_get(pdev); 115 d->imc[i].chan[m->mtype].cdev = pdev; 116 break; 117 case ERRCHAN0: 118 case ERRCHAN1: 119 case ERRCHAN2: 120 pci_dev_get(pdev); 121 d->imc[i].chan[m->mtype - ERRCHAN0].edev = pdev; 122 break; 123 case SAD_ALL: 124 pci_dev_get(pdev); 125 d->sad_all = pdev; 126 break; 127 case UTIL_ALL: 128 pci_dev_get(pdev); 129 d->util_all = pdev; 130 break; 131 case SAD: 132 /* 133 * one of these devices per core, including cores 134 * that don't exist on this SKU. Ignore any that 135 * read a route table of zero, make sure all the 136 * non-zero values match. 137 */ 138 pci_read_config_dword(pdev, 0xB4, ®); 139 if (reg != 0) { 140 if (d->mcroute == 0) { 141 d->mcroute = reg; 142 } else if (d->mcroute != reg) { 143 skx_printk(KERN_ERR, "mcroute mismatch\n"); 144 goto fail; 145 } 146 } 147 ndev--; 148 break; 149 } 150 151 prev = pdev; 152 } 153 154 return ndev; 155 fail: 156 pci_dev_put(pdev); 157 return -ENODEV; 158 } 159 160 static struct res_config skx_cfg = { 161 .type = SKX, 162 .decs_did = 0x2016, 163 .busno_cfg_offset = 0xcc, 164 }; 165 166 static const struct x86_cpu_id skx_cpuids[] = { 167 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &skx_cfg), 168 { } 169 }; 170 MODULE_DEVICE_TABLE(x86cpu, skx_cpuids); 171 172 static bool skx_check_ecc(u32 mcmtr) 173 { 174 return !!GET_BITFIELD(mcmtr, 2, 2); 175 } 176 177 static int skx_get_dimm_config(struct mem_ctl_info *mci) 178 { 179 struct skx_pvt *pvt = mci->pvt_info; 180 u32 mtr, mcmtr, amap, mcddrtcfg; 181 struct skx_imc *imc = pvt->imc; 182 struct dimm_info *dimm; 183 int i, j; 184 int ndimms; 185 186 /* Only the mcmtr on the first channel is effective */ 187 pci_read_config_dword(imc->chan[0].cdev, 0x87c, &mcmtr); 188 189 for (i = 0; i < SKX_NUM_CHANNELS; i++) { 190 ndimms = 0; 191 pci_read_config_dword(imc->chan[i].cdev, 0x8C, &amap); 192 pci_read_config_dword(imc->chan[i].cdev, 0x400, &mcddrtcfg); 193 for (j = 0; j < SKX_NUM_DIMMS; j++) { 194 dimm = edac_get_dimm(mci, i, j, 0); 195 pci_read_config_dword(imc->chan[i].cdev, 196 0x80 + 4 * j, &mtr); 197 if (IS_DIMM_PRESENT(mtr)) { 198 ndimms += skx_get_dimm_info(mtr, mcmtr, amap, dimm, imc, i, j); 199 } else if (IS_NVDIMM_PRESENT(mcddrtcfg, j)) { 200 ndimms += skx_get_nvdimm_info(dimm, imc, i, j, 201 EDAC_MOD_STR); 202 nvdimm_count++; 203 } 204 } 205 if (ndimms && !skx_check_ecc(mcmtr)) { 206 skx_printk(KERN_ERR, "ECC is disabled on imc %d\n", imc->mc); 207 return -ENODEV; 208 } 209 } 210 211 return 0; 212 } 213 214 #define SKX_MAX_SAD 24 215 216 #define SKX_GET_SAD(d, i, reg) \ 217 pci_read_config_dword((d)->sad_all, 0x60 + 8 * (i), &(reg)) 218 #define SKX_GET_ILV(d, i, reg) \ 219 pci_read_config_dword((d)->sad_all, 0x64 + 8 * (i), &(reg)) 220 221 #define SKX_SAD_MOD3MODE(sad) GET_BITFIELD((sad), 30, 31) 222 #define SKX_SAD_MOD3(sad) GET_BITFIELD((sad), 27, 27) 223 #define SKX_SAD_LIMIT(sad) (((u64)GET_BITFIELD((sad), 7, 26) << 26) | MASK26) 224 #define SKX_SAD_MOD3ASMOD2(sad) GET_BITFIELD((sad), 5, 6) 225 #define SKX_SAD_ATTR(sad) GET_BITFIELD((sad), 3, 4) 226 #define SKX_SAD_INTERLEAVE(sad) GET_BITFIELD((sad), 1, 2) 227 #define SKX_SAD_ENABLE(sad) GET_BITFIELD((sad), 0, 0) 228 229 #define SKX_ILV_REMOTE(tgt) (((tgt) & 8) == 0) 230 #define SKX_ILV_TARGET(tgt) ((tgt) & 7) 231 232 static void skx_show_retry_rd_err_log(struct decoded_addr *res, 233 char *msg, int len) 234 { 235 u32 log0, log1, log2, log3, log4; 236 u32 corr0, corr1, corr2, corr3; 237 struct pci_dev *edev; 238 int n; 239 240 edev = res->dev->imc[res->imc].chan[res->channel].edev; 241 242 pci_read_config_dword(edev, 0x154, &log0); 243 pci_read_config_dword(edev, 0x148, &log1); 244 pci_read_config_dword(edev, 0x150, &log2); 245 pci_read_config_dword(edev, 0x15c, &log3); 246 pci_read_config_dword(edev, 0x114, &log4); 247 248 n = snprintf(msg, len, " retry_rd_err_log[%.8x %.8x %.8x %.8x %.8x]", 249 log0, log1, log2, log3, log4); 250 251 pci_read_config_dword(edev, 0x104, &corr0); 252 pci_read_config_dword(edev, 0x108, &corr1); 253 pci_read_config_dword(edev, 0x10c, &corr2); 254 pci_read_config_dword(edev, 0x110, &corr3); 255 256 if (len - n > 0) 257 snprintf(msg + n, len - n, 258 " correrrcnt[%.4x %.4x %.4x %.4x %.4x %.4x %.4x %.4x]", 259 corr0 & 0xffff, corr0 >> 16, 260 corr1 & 0xffff, corr1 >> 16, 261 corr2 & 0xffff, corr2 >> 16, 262 corr3 & 0xffff, corr3 >> 16); 263 } 264 265 static bool skx_sad_decode(struct decoded_addr *res) 266 { 267 struct skx_dev *d = list_first_entry(skx_edac_list, typeof(*d), list); 268 u64 addr = res->addr; 269 int i, idx, tgt, lchan, shift; 270 u32 sad, ilv; 271 u64 limit, prev_limit; 272 int remote = 0; 273 274 /* Simple sanity check for I/O space or out of range */ 275 if (addr >= skx_tohm || (addr >= skx_tolm && addr < BIT_ULL(32))) { 276 edac_dbg(0, "Address 0x%llx out of range\n", addr); 277 return false; 278 } 279 280 restart: 281 prev_limit = 0; 282 for (i = 0; i < SKX_MAX_SAD; i++) { 283 SKX_GET_SAD(d, i, sad); 284 limit = SKX_SAD_LIMIT(sad); 285 if (SKX_SAD_ENABLE(sad)) { 286 if (addr >= prev_limit && addr <= limit) 287 goto sad_found; 288 } 289 prev_limit = limit + 1; 290 } 291 edac_dbg(0, "No SAD entry for 0x%llx\n", addr); 292 return false; 293 294 sad_found: 295 SKX_GET_ILV(d, i, ilv); 296 297 switch (SKX_SAD_INTERLEAVE(sad)) { 298 case 0: 299 idx = GET_BITFIELD(addr, 6, 8); 300 break; 301 case 1: 302 idx = GET_BITFIELD(addr, 8, 10); 303 break; 304 case 2: 305 idx = GET_BITFIELD(addr, 12, 14); 306 break; 307 case 3: 308 idx = GET_BITFIELD(addr, 30, 32); 309 break; 310 } 311 312 tgt = GET_BITFIELD(ilv, 4 * idx, 4 * idx + 3); 313 314 /* If point to another node, find it and start over */ 315 if (SKX_ILV_REMOTE(tgt)) { 316 if (remote) { 317 edac_dbg(0, "Double remote!\n"); 318 return false; 319 } 320 remote = 1; 321 list_for_each_entry(d, skx_edac_list, list) { 322 if (d->imc[0].src_id == SKX_ILV_TARGET(tgt)) 323 goto restart; 324 } 325 edac_dbg(0, "Can't find node %d\n", SKX_ILV_TARGET(tgt)); 326 return false; 327 } 328 329 if (SKX_SAD_MOD3(sad) == 0) { 330 lchan = SKX_ILV_TARGET(tgt); 331 } else { 332 switch (SKX_SAD_MOD3MODE(sad)) { 333 case 0: 334 shift = 6; 335 break; 336 case 1: 337 shift = 8; 338 break; 339 case 2: 340 shift = 12; 341 break; 342 default: 343 edac_dbg(0, "illegal mod3mode\n"); 344 return false; 345 } 346 switch (SKX_SAD_MOD3ASMOD2(sad)) { 347 case 0: 348 lchan = (addr >> shift) % 3; 349 break; 350 case 1: 351 lchan = (addr >> shift) % 2; 352 break; 353 case 2: 354 lchan = (addr >> shift) % 2; 355 lchan = (lchan << 1) | !lchan; 356 break; 357 case 3: 358 lchan = ((addr >> shift) % 2) << 1; 359 break; 360 } 361 lchan = (lchan << 1) | (SKX_ILV_TARGET(tgt) & 1); 362 } 363 364 res->dev = d; 365 res->socket = d->imc[0].src_id; 366 res->imc = GET_BITFIELD(d->mcroute, lchan * 3, lchan * 3 + 2); 367 res->channel = GET_BITFIELD(d->mcroute, lchan * 2 + 18, lchan * 2 + 19); 368 369 edac_dbg(2, "0x%llx: socket=%d imc=%d channel=%d\n", 370 res->addr, res->socket, res->imc, res->channel); 371 return true; 372 } 373 374 #define SKX_MAX_TAD 8 375 376 #define SKX_GET_TADBASE(d, mc, i, reg) \ 377 pci_read_config_dword((d)->imc[mc].chan[0].cdev, 0x850 + 4 * (i), &(reg)) 378 #define SKX_GET_TADWAYNESS(d, mc, i, reg) \ 379 pci_read_config_dword((d)->imc[mc].chan[0].cdev, 0x880 + 4 * (i), &(reg)) 380 #define SKX_GET_TADCHNILVOFFSET(d, mc, ch, i, reg) \ 381 pci_read_config_dword((d)->imc[mc].chan[ch].cdev, 0x90 + 4 * (i), &(reg)) 382 383 #define SKX_TAD_BASE(b) ((u64)GET_BITFIELD((b), 12, 31) << 26) 384 #define SKX_TAD_SKT_GRAN(b) GET_BITFIELD((b), 4, 5) 385 #define SKX_TAD_CHN_GRAN(b) GET_BITFIELD((b), 6, 7) 386 #define SKX_TAD_LIMIT(b) (((u64)GET_BITFIELD((b), 12, 31) << 26) | MASK26) 387 #define SKX_TAD_OFFSET(b) ((u64)GET_BITFIELD((b), 4, 23) << 26) 388 #define SKX_TAD_SKTWAYS(b) (1 << GET_BITFIELD((b), 10, 11)) 389 #define SKX_TAD_CHNWAYS(b) (GET_BITFIELD((b), 8, 9) + 1) 390 391 /* which bit used for both socket and channel interleave */ 392 static int skx_granularity[] = { 6, 8, 12, 30 }; 393 394 static u64 skx_do_interleave(u64 addr, int shift, int ways, u64 lowbits) 395 { 396 addr >>= shift; 397 addr /= ways; 398 addr <<= shift; 399 400 return addr | (lowbits & ((1ull << shift) - 1)); 401 } 402 403 static bool skx_tad_decode(struct decoded_addr *res) 404 { 405 int i; 406 u32 base, wayness, chnilvoffset; 407 int skt_interleave_bit, chn_interleave_bit; 408 u64 channel_addr; 409 410 for (i = 0; i < SKX_MAX_TAD; i++) { 411 SKX_GET_TADBASE(res->dev, res->imc, i, base); 412 SKX_GET_TADWAYNESS(res->dev, res->imc, i, wayness); 413 if (SKX_TAD_BASE(base) <= res->addr && res->addr <= SKX_TAD_LIMIT(wayness)) 414 goto tad_found; 415 } 416 edac_dbg(0, "No TAD entry for 0x%llx\n", res->addr); 417 return false; 418 419 tad_found: 420 res->sktways = SKX_TAD_SKTWAYS(wayness); 421 res->chanways = SKX_TAD_CHNWAYS(wayness); 422 skt_interleave_bit = skx_granularity[SKX_TAD_SKT_GRAN(base)]; 423 chn_interleave_bit = skx_granularity[SKX_TAD_CHN_GRAN(base)]; 424 425 SKX_GET_TADCHNILVOFFSET(res->dev, res->imc, res->channel, i, chnilvoffset); 426 channel_addr = res->addr - SKX_TAD_OFFSET(chnilvoffset); 427 428 if (res->chanways == 3 && skt_interleave_bit > chn_interleave_bit) { 429 /* Must handle channel first, then socket */ 430 channel_addr = skx_do_interleave(channel_addr, chn_interleave_bit, 431 res->chanways, channel_addr); 432 channel_addr = skx_do_interleave(channel_addr, skt_interleave_bit, 433 res->sktways, channel_addr); 434 } else { 435 /* Handle socket then channel. Preserve low bits from original address */ 436 channel_addr = skx_do_interleave(channel_addr, skt_interleave_bit, 437 res->sktways, res->addr); 438 channel_addr = skx_do_interleave(channel_addr, chn_interleave_bit, 439 res->chanways, res->addr); 440 } 441 442 res->chan_addr = channel_addr; 443 444 edac_dbg(2, "0x%llx: chan_addr=0x%llx sktways=%d chanways=%d\n", 445 res->addr, res->chan_addr, res->sktways, res->chanways); 446 return true; 447 } 448 449 #define SKX_MAX_RIR 4 450 451 #define SKX_GET_RIRWAYNESS(d, mc, ch, i, reg) \ 452 pci_read_config_dword((d)->imc[mc].chan[ch].cdev, \ 453 0x108 + 4 * (i), &(reg)) 454 #define SKX_GET_RIRILV(d, mc, ch, idx, i, reg) \ 455 pci_read_config_dword((d)->imc[mc].chan[ch].cdev, \ 456 0x120 + 16 * (idx) + 4 * (i), &(reg)) 457 458 #define SKX_RIR_VALID(b) GET_BITFIELD((b), 31, 31) 459 #define SKX_RIR_LIMIT(b) (((u64)GET_BITFIELD((b), 1, 11) << 29) | MASK29) 460 #define SKX_RIR_WAYS(b) (1 << GET_BITFIELD((b), 28, 29)) 461 #define SKX_RIR_CHAN_RANK(b) GET_BITFIELD((b), 16, 19) 462 #define SKX_RIR_OFFSET(b) ((u64)(GET_BITFIELD((b), 2, 15) << 26)) 463 464 static bool skx_rir_decode(struct decoded_addr *res) 465 { 466 int i, idx, chan_rank; 467 int shift; 468 u32 rirway, rirlv; 469 u64 rank_addr, prev_limit = 0, limit; 470 471 if (res->dev->imc[res->imc].chan[res->channel].dimms[0].close_pg) 472 shift = 6; 473 else 474 shift = 13; 475 476 for (i = 0; i < SKX_MAX_RIR; i++) { 477 SKX_GET_RIRWAYNESS(res->dev, res->imc, res->channel, i, rirway); 478 limit = SKX_RIR_LIMIT(rirway); 479 if (SKX_RIR_VALID(rirway)) { 480 if (prev_limit <= res->chan_addr && 481 res->chan_addr <= limit) 482 goto rir_found; 483 } 484 prev_limit = limit; 485 } 486 edac_dbg(0, "No RIR entry for 0x%llx\n", res->addr); 487 return false; 488 489 rir_found: 490 rank_addr = res->chan_addr >> shift; 491 rank_addr /= SKX_RIR_WAYS(rirway); 492 rank_addr <<= shift; 493 rank_addr |= res->chan_addr & GENMASK_ULL(shift - 1, 0); 494 495 res->rank_address = rank_addr; 496 idx = (res->chan_addr >> shift) % SKX_RIR_WAYS(rirway); 497 498 SKX_GET_RIRILV(res->dev, res->imc, res->channel, idx, i, rirlv); 499 res->rank_address = rank_addr - SKX_RIR_OFFSET(rirlv); 500 chan_rank = SKX_RIR_CHAN_RANK(rirlv); 501 res->channel_rank = chan_rank; 502 res->dimm = chan_rank / 4; 503 res->rank = chan_rank % 4; 504 505 edac_dbg(2, "0x%llx: dimm=%d rank=%d chan_rank=%d rank_addr=0x%llx\n", 506 res->addr, res->dimm, res->rank, 507 res->channel_rank, res->rank_address); 508 return true; 509 } 510 511 static u8 skx_close_row[] = { 512 15, 16, 17, 18, 20, 21, 22, 28, 10, 11, 12, 13, 29, 30, 31, 32, 33 513 }; 514 515 static u8 skx_close_column[] = { 516 3, 4, 5, 14, 19, 23, 24, 25, 26, 27 517 }; 518 519 static u8 skx_open_row[] = { 520 14, 15, 16, 20, 28, 21, 22, 23, 24, 25, 26, 27, 29, 30, 31, 32, 33 521 }; 522 523 static u8 skx_open_column[] = { 524 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 525 }; 526 527 static u8 skx_open_fine_column[] = { 528 3, 4, 5, 7, 8, 9, 10, 11, 12, 13 529 }; 530 531 static int skx_bits(u64 addr, int nbits, u8 *bits) 532 { 533 int i, res = 0; 534 535 for (i = 0; i < nbits; i++) 536 res |= ((addr >> bits[i]) & 1) << i; 537 return res; 538 } 539 540 static int skx_bank_bits(u64 addr, int b0, int b1, int do_xor, int x0, int x1) 541 { 542 int ret = GET_BITFIELD(addr, b0, b0) | (GET_BITFIELD(addr, b1, b1) << 1); 543 544 if (do_xor) 545 ret ^= GET_BITFIELD(addr, x0, x0) | (GET_BITFIELD(addr, x1, x1) << 1); 546 547 return ret; 548 } 549 550 static bool skx_mad_decode(struct decoded_addr *r) 551 { 552 struct skx_dimm *dimm = &r->dev->imc[r->imc].chan[r->channel].dimms[r->dimm]; 553 int bg0 = dimm->fine_grain_bank ? 6 : 13; 554 555 if (dimm->close_pg) { 556 r->row = skx_bits(r->rank_address, dimm->rowbits, skx_close_row); 557 r->column = skx_bits(r->rank_address, dimm->colbits, skx_close_column); 558 r->column |= 0x400; /* C10 is autoprecharge, always set */ 559 r->bank_address = skx_bank_bits(r->rank_address, 8, 9, dimm->bank_xor_enable, 22, 28); 560 r->bank_group = skx_bank_bits(r->rank_address, 6, 7, dimm->bank_xor_enable, 20, 21); 561 } else { 562 r->row = skx_bits(r->rank_address, dimm->rowbits, skx_open_row); 563 if (dimm->fine_grain_bank) 564 r->column = skx_bits(r->rank_address, dimm->colbits, skx_open_fine_column); 565 else 566 r->column = skx_bits(r->rank_address, dimm->colbits, skx_open_column); 567 r->bank_address = skx_bank_bits(r->rank_address, 18, 19, dimm->bank_xor_enable, 22, 23); 568 r->bank_group = skx_bank_bits(r->rank_address, bg0, 17, dimm->bank_xor_enable, 20, 21); 569 } 570 r->row &= (1u << dimm->rowbits) - 1; 571 572 edac_dbg(2, "0x%llx: row=0x%x col=0x%x bank_addr=%d bank_group=%d\n", 573 r->addr, r->row, r->column, r->bank_address, 574 r->bank_group); 575 return true; 576 } 577 578 static bool skx_decode(struct decoded_addr *res) 579 { 580 return skx_sad_decode(res) && skx_tad_decode(res) && 581 skx_rir_decode(res) && skx_mad_decode(res); 582 } 583 584 static struct notifier_block skx_mce_dec = { 585 .notifier_call = skx_mce_check_error, 586 .priority = MCE_PRIO_EDAC, 587 }; 588 589 #ifdef CONFIG_EDAC_DEBUG 590 /* 591 * Debug feature. 592 * Exercise the address decode logic by writing an address to 593 * /sys/kernel/debug/edac/skx_test/addr. 594 */ 595 static struct dentry *skx_test; 596 597 static int debugfs_u64_set(void *data, u64 val) 598 { 599 struct mce m; 600 601 pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val); 602 603 memset(&m, 0, sizeof(m)); 604 /* ADDRV + MemRd + Unknown channel */ 605 m.status = MCI_STATUS_ADDRV + 0x90; 606 /* One corrected error */ 607 m.status |= BIT_ULL(MCI_STATUS_CEC_SHIFT); 608 m.addr = val; 609 skx_mce_check_error(NULL, 0, &m); 610 611 return 0; 612 } 613 DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n"); 614 615 static void setup_skx_debug(void) 616 { 617 skx_test = edac_debugfs_create_dir("skx_test"); 618 if (!skx_test) 619 return; 620 621 if (!edac_debugfs_create_file("addr", 0200, skx_test, 622 NULL, &fops_u64_wo)) { 623 debugfs_remove(skx_test); 624 skx_test = NULL; 625 } 626 } 627 628 static void teardown_skx_debug(void) 629 { 630 debugfs_remove_recursive(skx_test); 631 } 632 #else 633 static inline void setup_skx_debug(void) {} 634 static inline void teardown_skx_debug(void) {} 635 #endif /*CONFIG_EDAC_DEBUG*/ 636 637 /* 638 * skx_init: 639 * make sure we are running on the correct cpu model 640 * search for all the devices we need 641 * check which DIMMs are present. 642 */ 643 static int __init skx_init(void) 644 { 645 const struct x86_cpu_id *id; 646 struct res_config *cfg; 647 const struct munit *m; 648 const char *owner; 649 int rc = 0, i, off[3] = {0xd0, 0xd4, 0xd8}; 650 u8 mc = 0, src_id, node_id; 651 struct skx_dev *d; 652 653 edac_dbg(2, "\n"); 654 655 owner = edac_get_owner(); 656 if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR))) 657 return -EBUSY; 658 659 id = x86_match_cpu(skx_cpuids); 660 if (!id) 661 return -ENODEV; 662 663 cfg = (struct res_config *)id->driver_data; 664 665 rc = skx_get_hi_lo(0x2034, off, &skx_tolm, &skx_tohm); 666 if (rc) 667 return rc; 668 669 rc = skx_get_all_bus_mappings(cfg, &skx_edac_list); 670 if (rc < 0) 671 goto fail; 672 if (rc == 0) { 673 edac_dbg(2, "No memory controllers found\n"); 674 return -ENODEV; 675 } 676 skx_num_sockets = rc; 677 678 for (m = skx_all_munits; m->did; m++) { 679 rc = get_all_munits(m); 680 if (rc < 0) 681 goto fail; 682 if (rc != m->per_socket * skx_num_sockets) { 683 edac_dbg(2, "Expected %d, got %d of 0x%x\n", 684 m->per_socket * skx_num_sockets, rc, m->did); 685 rc = -ENODEV; 686 goto fail; 687 } 688 } 689 690 list_for_each_entry(d, skx_edac_list, list) { 691 rc = skx_get_src_id(d, 0xf0, &src_id); 692 if (rc < 0) 693 goto fail; 694 rc = skx_get_node_id(d, &node_id); 695 if (rc < 0) 696 goto fail; 697 edac_dbg(2, "src_id=%d node_id=%d\n", src_id, node_id); 698 for (i = 0; i < SKX_NUM_IMC; i++) { 699 d->imc[i].mc = mc++; 700 d->imc[i].lmc = i; 701 d->imc[i].src_id = src_id; 702 d->imc[i].node_id = node_id; 703 rc = skx_register_mci(&d->imc[i], d->imc[i].chan[0].cdev, 704 "Skylake Socket", EDAC_MOD_STR, 705 skx_get_dimm_config); 706 if (rc < 0) 707 goto fail; 708 } 709 } 710 711 skx_set_decode(skx_decode, skx_show_retry_rd_err_log); 712 713 if (nvdimm_count && skx_adxl_get() == -ENODEV) 714 skx_printk(KERN_NOTICE, "Only decoding DDR4 address!\n"); 715 716 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 717 opstate_init(); 718 719 setup_skx_debug(); 720 721 mce_register_decode_chain(&skx_mce_dec); 722 723 return 0; 724 fail: 725 skx_remove(); 726 return rc; 727 } 728 729 static void __exit skx_exit(void) 730 { 731 edac_dbg(2, "\n"); 732 mce_unregister_decode_chain(&skx_mce_dec); 733 teardown_skx_debug(); 734 if (nvdimm_count) 735 skx_adxl_put(); 736 skx_remove(); 737 } 738 739 module_init(skx_init); 740 module_exit(skx_exit); 741 742 module_param(edac_op_state, int, 0444); 743 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); 744 745 MODULE_LICENSE("GPL v2"); 746 MODULE_AUTHOR("Tony Luck"); 747 MODULE_DESCRIPTION("MC Driver for Intel Skylake server processors"); 748