1 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module 2 * 3 * This driver supports the memory controllers found on the Intel 4 * processor family Sandy Bridge. 5 * 6 * This file may be distributed under the terms of the 7 * GNU General Public License version 2 only. 8 * 9 * Copyright (c) 2011 by: 10 * Mauro Carvalho Chehab <mchehab@redhat.com> 11 */ 12 13 #include <linux/module.h> 14 #include <linux/init.h> 15 #include <linux/pci.h> 16 #include <linux/pci_ids.h> 17 #include <linux/slab.h> 18 #include <linux/delay.h> 19 #include <linux/edac.h> 20 #include <linux/mmzone.h> 21 #include <linux/smp.h> 22 #include <linux/bitmap.h> 23 #include <linux/math64.h> 24 #include <asm/processor.h> 25 #include <asm/mce.h> 26 27 #include "edac_core.h" 28 29 /* Static vars */ 30 static LIST_HEAD(sbridge_edac_list); 31 static DEFINE_MUTEX(sbridge_edac_lock); 32 static int probed; 33 34 /* 35 * Alter this version for the module when modifications are made 36 */ 37 #define SBRIDGE_REVISION " Ver: 1.0.0 " 38 #define EDAC_MOD_STR "sbridge_edac" 39 40 /* 41 * Debug macros 42 */ 43 #define sbridge_printk(level, fmt, arg...) \ 44 edac_printk(level, "sbridge", fmt, ##arg) 45 46 #define sbridge_mc_printk(mci, level, fmt, arg...) \ 47 edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg) 48 49 /* 50 * Get a bit field at register value <v>, from bit <lo> to bit <hi> 51 */ 52 #define GET_BITFIELD(v, lo, hi) \ 53 (((v) & ((1ULL << ((hi) - (lo) + 1)) - 1) << (lo)) >> (lo)) 54 55 /* 56 * sbridge Memory Controller Registers 57 */ 58 59 /* 60 * FIXME: For now, let's order by device function, as it makes 61 * easier for driver's development process. This table should be 62 * moved to pci_id.h when submitted upstream 63 */ 64 #define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0 0x3cf4 /* 12.6 */ 65 #define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1 0x3cf6 /* 12.7 */ 66 #define PCI_DEVICE_ID_INTEL_SBRIDGE_BR 0x3cf5 /* 13.6 */ 67 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0 0x3ca0 /* 14.0 */ 68 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA 0x3ca8 /* 15.0 */ 69 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS 0x3c71 /* 15.1 */ 70 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0 0x3caa /* 15.2 */ 71 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1 0x3cab /* 15.3 */ 72 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2 0x3cac /* 15.4 */ 73 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3 0x3cad /* 15.5 */ 74 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO 0x3cb8 /* 17.0 */ 75 76 /* 77 * Currently, unused, but will be needed in the future 78 * implementations, as they hold the error counters 79 */ 80 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR0 0x3c72 /* 16.2 */ 81 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR1 0x3c73 /* 16.3 */ 82 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR2 0x3c76 /* 16.6 */ 83 #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR3 0x3c77 /* 16.7 */ 84 85 /* Devices 12 Function 6, Offsets 0x80 to 0xcc */ 86 static const u32 dram_rule[] = { 87 0x80, 0x88, 0x90, 0x98, 0xa0, 88 0xa8, 0xb0, 0xb8, 0xc0, 0xc8, 89 }; 90 #define MAX_SAD ARRAY_SIZE(dram_rule) 91 92 #define SAD_LIMIT(reg) ((GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff) 93 #define DRAM_ATTR(reg) GET_BITFIELD(reg, 2, 3) 94 #define INTERLEAVE_MODE(reg) GET_BITFIELD(reg, 1, 1) 95 #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0) 96 97 static char *get_dram_attr(u32 reg) 98 { 99 switch(DRAM_ATTR(reg)) { 100 case 0: 101 return "DRAM"; 102 case 1: 103 return "MMCFG"; 104 case 2: 105 return "NXM"; 106 default: 107 return "unknown"; 108 } 109 } 110 111 static const u32 interleave_list[] = { 112 0x84, 0x8c, 0x94, 0x9c, 0xa4, 113 0xac, 0xb4, 0xbc, 0xc4, 0xcc, 114 }; 115 #define MAX_INTERLEAVE ARRAY_SIZE(interleave_list) 116 117 #define SAD_PKG0(reg) GET_BITFIELD(reg, 0, 2) 118 #define SAD_PKG1(reg) GET_BITFIELD(reg, 3, 5) 119 #define SAD_PKG2(reg) GET_BITFIELD(reg, 8, 10) 120 #define SAD_PKG3(reg) GET_BITFIELD(reg, 11, 13) 121 #define SAD_PKG4(reg) GET_BITFIELD(reg, 16, 18) 122 #define SAD_PKG5(reg) GET_BITFIELD(reg, 19, 21) 123 #define SAD_PKG6(reg) GET_BITFIELD(reg, 24, 26) 124 #define SAD_PKG7(reg) GET_BITFIELD(reg, 27, 29) 125 126 static inline int sad_pkg(u32 reg, int interleave) 127 { 128 switch (interleave) { 129 case 0: 130 return SAD_PKG0(reg); 131 case 1: 132 return SAD_PKG1(reg); 133 case 2: 134 return SAD_PKG2(reg); 135 case 3: 136 return SAD_PKG3(reg); 137 case 4: 138 return SAD_PKG4(reg); 139 case 5: 140 return SAD_PKG5(reg); 141 case 6: 142 return SAD_PKG6(reg); 143 case 7: 144 return SAD_PKG7(reg); 145 default: 146 return -EINVAL; 147 } 148 } 149 150 /* Devices 12 Function 7 */ 151 152 #define TOLM 0x80 153 #define TOHM 0x84 154 155 #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff) 156 #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff) 157 158 /* Device 13 Function 6 */ 159 160 #define SAD_TARGET 0xf0 161 162 #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11) 163 164 #define SAD_CONTROL 0xf4 165 166 #define NODE_ID(reg) GET_BITFIELD(reg, 0, 2) 167 168 /* Device 14 function 0 */ 169 170 static const u32 tad_dram_rule[] = { 171 0x40, 0x44, 0x48, 0x4c, 172 0x50, 0x54, 0x58, 0x5c, 173 0x60, 0x64, 0x68, 0x6c, 174 }; 175 #define MAX_TAD ARRAY_SIZE(tad_dram_rule) 176 177 #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff) 178 #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11) 179 #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9) 180 #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7) 181 #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5) 182 #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3) 183 #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1) 184 185 /* Device 15, function 0 */ 186 187 #define MCMTR 0x7c 188 189 #define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2) 190 #define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1) 191 #define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0) 192 193 /* Device 15, function 1 */ 194 195 #define RASENABLES 0xac 196 #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0) 197 198 /* Device 15, functions 2-5 */ 199 200 static const int mtr_regs[] = { 201 0x80, 0x84, 0x88, 202 }; 203 204 #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19) 205 #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14) 206 #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13) 207 #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4) 208 #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1) 209 210 static const u32 tad_ch_nilv_offset[] = { 211 0x90, 0x94, 0x98, 0x9c, 212 0xa0, 0xa4, 0xa8, 0xac, 213 0xb0, 0xb4, 0xb8, 0xbc, 214 }; 215 #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29) 216 #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26) 217 218 static const u32 rir_way_limit[] = { 219 0x108, 0x10c, 0x110, 0x114, 0x118, 220 }; 221 #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit) 222 223 #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31) 224 #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29) 225 #define RIR_LIMIT(reg) ((GET_BITFIELD(reg, 1, 10) << 29)| 0x1fffffff) 226 227 #define MAX_RIR_WAY 8 228 229 static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = { 230 { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c }, 231 { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c }, 232 { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c }, 233 { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c }, 234 { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc }, 235 }; 236 237 #define RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19) 238 #define RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14) 239 240 /* Device 16, functions 2-7 */ 241 242 /* 243 * FIXME: Implement the error count reads directly 244 */ 245 246 static const u32 correrrcnt[] = { 247 0x104, 0x108, 0x10c, 0x110, 248 }; 249 250 #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31) 251 #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30) 252 #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15) 253 #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14) 254 255 static const u32 correrrthrsld[] = { 256 0x11c, 0x120, 0x124, 0x128, 257 }; 258 259 #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30) 260 #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14) 261 262 263 /* Device 17, function 0 */ 264 265 #define RANK_CFG_A 0x0328 266 267 #define IS_RDIMM_ENABLED(reg) GET_BITFIELD(reg, 11, 11) 268 269 /* 270 * sbridge structs 271 */ 272 273 #define NUM_CHANNELS 4 274 #define MAX_DIMMS 3 /* Max DIMMS per channel */ 275 276 struct sbridge_info { 277 u32 mcmtr; 278 }; 279 280 struct sbridge_channel { 281 u32 ranks; 282 u32 dimms; 283 }; 284 285 struct pci_id_descr { 286 int dev; 287 int func; 288 int dev_id; 289 int optional; 290 }; 291 292 struct pci_id_table { 293 const struct pci_id_descr *descr; 294 int n_devs; 295 }; 296 297 struct sbridge_dev { 298 struct list_head list; 299 u8 bus, mc; 300 u8 node_id, source_id; 301 struct pci_dev **pdev; 302 int n_devs; 303 struct mem_ctl_info *mci; 304 }; 305 306 struct sbridge_pvt { 307 struct pci_dev *pci_ta, *pci_ddrio, *pci_ras; 308 struct pci_dev *pci_sad0, *pci_sad1, *pci_ha0; 309 struct pci_dev *pci_br; 310 struct pci_dev *pci_tad[NUM_CHANNELS]; 311 312 struct sbridge_dev *sbridge_dev; 313 314 struct sbridge_info info; 315 struct sbridge_channel channel[NUM_CHANNELS]; 316 317 /* Memory type detection */ 318 bool is_mirrored, is_lockstep, is_close_pg; 319 320 /* Fifo double buffers */ 321 struct mce mce_entry[MCE_LOG_LEN]; 322 struct mce mce_outentry[MCE_LOG_LEN]; 323 324 /* Fifo in/out counters */ 325 unsigned mce_in, mce_out; 326 327 /* Count indicator to show errors not got */ 328 unsigned mce_overrun; 329 330 /* Memory description */ 331 u64 tolm, tohm; 332 }; 333 334 #define PCI_DESCR(device, function, device_id) \ 335 .dev = (device), \ 336 .func = (function), \ 337 .dev_id = (device_id) 338 339 static const struct pci_id_descr pci_dev_descr_sbridge[] = { 340 /* Processor Home Agent */ 341 { PCI_DESCR(14, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0) }, 342 343 /* Memory controller */ 344 { PCI_DESCR(15, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA) }, 345 { PCI_DESCR(15, 1, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS) }, 346 { PCI_DESCR(15, 2, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0) }, 347 { PCI_DESCR(15, 3, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1) }, 348 { PCI_DESCR(15, 4, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2) }, 349 { PCI_DESCR(15, 5, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3) }, 350 { PCI_DESCR(17, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO) }, 351 352 /* System Address Decoder */ 353 { PCI_DESCR(12, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0) }, 354 { PCI_DESCR(12, 7, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1) }, 355 356 /* Broadcast Registers */ 357 { PCI_DESCR(13, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_BR) }, 358 }; 359 360 #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) } 361 static const struct pci_id_table pci_dev_descr_sbridge_table[] = { 362 PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge), 363 {0,} /* 0 terminated list. */ 364 }; 365 366 /* 367 * pci_device_id table for which devices we are looking for 368 */ 369 static DEFINE_PCI_DEVICE_TABLE(sbridge_pci_tbl) = { 370 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA)}, 371 {0,} /* 0 terminated list. */ 372 }; 373 374 375 /**************************************************************************** 376 Ancillary status routines 377 ****************************************************************************/ 378 379 static inline int numrank(u32 mtr) 380 { 381 int ranks = (1 << RANK_CNT_BITS(mtr)); 382 383 if (ranks > 4) { 384 edac_dbg(0, "Invalid number of ranks: %d (max = 4) raw value = %x (%04x)\n", 385 ranks, (unsigned int)RANK_CNT_BITS(mtr), mtr); 386 return -EINVAL; 387 } 388 389 return ranks; 390 } 391 392 static inline int numrow(u32 mtr) 393 { 394 int rows = (RANK_WIDTH_BITS(mtr) + 12); 395 396 if (rows < 13 || rows > 18) { 397 edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n", 398 rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr); 399 return -EINVAL; 400 } 401 402 return 1 << rows; 403 } 404 405 static inline int numcol(u32 mtr) 406 { 407 int cols = (COL_WIDTH_BITS(mtr) + 10); 408 409 if (cols > 12) { 410 edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n", 411 cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr); 412 return -EINVAL; 413 } 414 415 return 1 << cols; 416 } 417 418 static struct sbridge_dev *get_sbridge_dev(u8 bus) 419 { 420 struct sbridge_dev *sbridge_dev; 421 422 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { 423 if (sbridge_dev->bus == bus) 424 return sbridge_dev; 425 } 426 427 return NULL; 428 } 429 430 static struct sbridge_dev *alloc_sbridge_dev(u8 bus, 431 const struct pci_id_table *table) 432 { 433 struct sbridge_dev *sbridge_dev; 434 435 sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL); 436 if (!sbridge_dev) 437 return NULL; 438 439 sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs, 440 GFP_KERNEL); 441 if (!sbridge_dev->pdev) { 442 kfree(sbridge_dev); 443 return NULL; 444 } 445 446 sbridge_dev->bus = bus; 447 sbridge_dev->n_devs = table->n_devs; 448 list_add_tail(&sbridge_dev->list, &sbridge_edac_list); 449 450 return sbridge_dev; 451 } 452 453 static void free_sbridge_dev(struct sbridge_dev *sbridge_dev) 454 { 455 list_del(&sbridge_dev->list); 456 kfree(sbridge_dev->pdev); 457 kfree(sbridge_dev); 458 } 459 460 /**************************************************************************** 461 Memory check routines 462 ****************************************************************************/ 463 static struct pci_dev *get_pdev_slot_func(u8 bus, unsigned slot, 464 unsigned func) 465 { 466 struct sbridge_dev *sbridge_dev = get_sbridge_dev(bus); 467 int i; 468 469 if (!sbridge_dev) 470 return NULL; 471 472 for (i = 0; i < sbridge_dev->n_devs; i++) { 473 if (!sbridge_dev->pdev[i]) 474 continue; 475 476 if (PCI_SLOT(sbridge_dev->pdev[i]->devfn) == slot && 477 PCI_FUNC(sbridge_dev->pdev[i]->devfn) == func) { 478 edac_dbg(1, "Associated %02x.%02x.%d with %p\n", 479 bus, slot, func, sbridge_dev->pdev[i]); 480 return sbridge_dev->pdev[i]; 481 } 482 } 483 484 return NULL; 485 } 486 487 /** 488 * check_if_ecc_is_active() - Checks if ECC is active 489 * bus: Device bus 490 */ 491 static int check_if_ecc_is_active(const u8 bus) 492 { 493 struct pci_dev *pdev = NULL; 494 u32 mcmtr; 495 496 pdev = get_pdev_slot_func(bus, 15, 0); 497 if (!pdev) { 498 sbridge_printk(KERN_ERR, "Couldn't find PCI device " 499 "%2x.%02d.%d!!!\n", 500 bus, 15, 0); 501 return -ENODEV; 502 } 503 504 pci_read_config_dword(pdev, MCMTR, &mcmtr); 505 if (!IS_ECC_ENABLED(mcmtr)) { 506 sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n"); 507 return -ENODEV; 508 } 509 return 0; 510 } 511 512 static int get_dimm_config(struct mem_ctl_info *mci) 513 { 514 struct sbridge_pvt *pvt = mci->pvt_info; 515 struct dimm_info *dimm; 516 int i, j, banks, ranks, rows, cols, size, npages; 517 u32 reg; 518 enum edac_type mode; 519 enum mem_type mtype; 520 521 pci_read_config_dword(pvt->pci_br, SAD_TARGET, ®); 522 pvt->sbridge_dev->source_id = SOURCE_ID(reg); 523 524 pci_read_config_dword(pvt->pci_br, SAD_CONTROL, ®); 525 pvt->sbridge_dev->node_id = NODE_ID(reg); 526 edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n", 527 pvt->sbridge_dev->mc, 528 pvt->sbridge_dev->node_id, 529 pvt->sbridge_dev->source_id); 530 531 pci_read_config_dword(pvt->pci_ras, RASENABLES, ®); 532 if (IS_MIRROR_ENABLED(reg)) { 533 edac_dbg(0, "Memory mirror is enabled\n"); 534 pvt->is_mirrored = true; 535 } else { 536 edac_dbg(0, "Memory mirror is disabled\n"); 537 pvt->is_mirrored = false; 538 } 539 540 pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr); 541 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) { 542 edac_dbg(0, "Lockstep is enabled\n"); 543 mode = EDAC_S8ECD8ED; 544 pvt->is_lockstep = true; 545 } else { 546 edac_dbg(0, "Lockstep is disabled\n"); 547 mode = EDAC_S4ECD4ED; 548 pvt->is_lockstep = false; 549 } 550 if (IS_CLOSE_PG(pvt->info.mcmtr)) { 551 edac_dbg(0, "address map is on closed page mode\n"); 552 pvt->is_close_pg = true; 553 } else { 554 edac_dbg(0, "address map is on open page mode\n"); 555 pvt->is_close_pg = false; 556 } 557 558 pci_read_config_dword(pvt->pci_ddrio, RANK_CFG_A, ®); 559 if (IS_RDIMM_ENABLED(reg)) { 560 /* FIXME: Can also be LRDIMM */ 561 edac_dbg(0, "Memory is registered\n"); 562 mtype = MEM_RDDR3; 563 } else { 564 edac_dbg(0, "Memory is unregistered\n"); 565 mtype = MEM_DDR3; 566 } 567 568 /* On all supported DDR3 DIMM types, there are 8 banks available */ 569 banks = 8; 570 571 for (i = 0; i < NUM_CHANNELS; i++) { 572 u32 mtr; 573 574 for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) { 575 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, 576 i, j, 0); 577 pci_read_config_dword(pvt->pci_tad[i], 578 mtr_regs[j], &mtr); 579 edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr); 580 if (IS_DIMM_PRESENT(mtr)) { 581 pvt->channel[i].dimms++; 582 583 ranks = numrank(mtr); 584 rows = numrow(mtr); 585 cols = numcol(mtr); 586 587 /* DDR3 has 8 I/O banks */ 588 size = (rows * cols * banks * ranks) >> (20 - 3); 589 npages = MiB_TO_PAGES(size); 590 591 edac_dbg(0, "mc#%d: channel %d, dimm %d, %d Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n", 592 pvt->sbridge_dev->mc, i, j, 593 size, npages, 594 banks, ranks, rows, cols); 595 596 dimm->nr_pages = npages; 597 dimm->grain = 32; 598 dimm->dtype = (banks == 8) ? DEV_X8 : DEV_X4; 599 dimm->mtype = mtype; 600 dimm->edac_mode = mode; 601 snprintf(dimm->label, sizeof(dimm->label), 602 "CPU_SrcID#%u_Channel#%u_DIMM#%u", 603 pvt->sbridge_dev->source_id, i, j); 604 } 605 } 606 } 607 608 return 0; 609 } 610 611 static void get_memory_layout(const struct mem_ctl_info *mci) 612 { 613 struct sbridge_pvt *pvt = mci->pvt_info; 614 int i, j, k, n_sads, n_tads, sad_interl; 615 u32 reg; 616 u64 limit, prv = 0; 617 u64 tmp_mb; 618 u32 mb, kb; 619 u32 rir_way; 620 621 /* 622 * Step 1) Get TOLM/TOHM ranges 623 */ 624 625 /* Address range is 32:28 */ 626 pci_read_config_dword(pvt->pci_sad1, TOLM, 627 ®); 628 pvt->tolm = GET_TOLM(reg); 629 tmp_mb = (1 + pvt->tolm) >> 20; 630 631 mb = div_u64_rem(tmp_mb, 1000, &kb); 632 edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n", mb, kb, (u64)pvt->tolm); 633 634 /* Address range is already 45:25 */ 635 pci_read_config_dword(pvt->pci_sad1, TOHM, 636 ®); 637 pvt->tohm = GET_TOHM(reg); 638 tmp_mb = (1 + pvt->tohm) >> 20; 639 640 mb = div_u64_rem(tmp_mb, 1000, &kb); 641 edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)", mb, kb, (u64)pvt->tohm); 642 643 /* 644 * Step 2) Get SAD range and SAD Interleave list 645 * TAD registers contain the interleave wayness. However, it 646 * seems simpler to just discover it indirectly, with the 647 * algorithm bellow. 648 */ 649 prv = 0; 650 for (n_sads = 0; n_sads < MAX_SAD; n_sads++) { 651 /* SAD_LIMIT Address range is 45:26 */ 652 pci_read_config_dword(pvt->pci_sad0, dram_rule[n_sads], 653 ®); 654 limit = SAD_LIMIT(reg); 655 656 if (!DRAM_RULE_ENABLE(reg)) 657 continue; 658 659 if (limit <= prv) 660 break; 661 662 tmp_mb = (limit + 1) >> 20; 663 mb = div_u64_rem(tmp_mb, 1000, &kb); 664 edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n", 665 n_sads, 666 get_dram_attr(reg), 667 mb, kb, 668 ((u64)tmp_mb) << 20L, 669 INTERLEAVE_MODE(reg) ? "8:6" : "[8:6]XOR[18:16]", 670 reg); 671 prv = limit; 672 673 pci_read_config_dword(pvt->pci_sad0, interleave_list[n_sads], 674 ®); 675 sad_interl = sad_pkg(reg, 0); 676 for (j = 0; j < 8; j++) { 677 if (j > 0 && sad_interl == sad_pkg(reg, j)) 678 break; 679 680 edac_dbg(0, "SAD#%d, interleave #%d: %d\n", 681 n_sads, j, sad_pkg(reg, j)); 682 } 683 } 684 685 /* 686 * Step 3) Get TAD range 687 */ 688 prv = 0; 689 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) { 690 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads], 691 ®); 692 limit = TAD_LIMIT(reg); 693 if (limit <= prv) 694 break; 695 tmp_mb = (limit + 1) >> 20; 696 697 mb = div_u64_rem(tmp_mb, 1000, &kb); 698 edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n", 699 n_tads, mb, kb, 700 ((u64)tmp_mb) << 20L, 701 (u32)TAD_SOCK(reg), 702 (u32)TAD_CH(reg), 703 (u32)TAD_TGT0(reg), 704 (u32)TAD_TGT1(reg), 705 (u32)TAD_TGT2(reg), 706 (u32)TAD_TGT3(reg), 707 reg); 708 prv = limit; 709 } 710 711 /* 712 * Step 4) Get TAD offsets, per each channel 713 */ 714 for (i = 0; i < NUM_CHANNELS; i++) { 715 if (!pvt->channel[i].dimms) 716 continue; 717 for (j = 0; j < n_tads; j++) { 718 pci_read_config_dword(pvt->pci_tad[i], 719 tad_ch_nilv_offset[j], 720 ®); 721 tmp_mb = TAD_OFFSET(reg) >> 20; 722 mb = div_u64_rem(tmp_mb, 1000, &kb); 723 edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n", 724 i, j, 725 mb, kb, 726 ((u64)tmp_mb) << 20L, 727 reg); 728 } 729 } 730 731 /* 732 * Step 6) Get RIR Wayness/Limit, per each channel 733 */ 734 for (i = 0; i < NUM_CHANNELS; i++) { 735 if (!pvt->channel[i].dimms) 736 continue; 737 for (j = 0; j < MAX_RIR_RANGES; j++) { 738 pci_read_config_dword(pvt->pci_tad[i], 739 rir_way_limit[j], 740 ®); 741 742 if (!IS_RIR_VALID(reg)) 743 continue; 744 745 tmp_mb = RIR_LIMIT(reg) >> 20; 746 rir_way = 1 << RIR_WAY(reg); 747 mb = div_u64_rem(tmp_mb, 1000, &kb); 748 edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n", 749 i, j, 750 mb, kb, 751 ((u64)tmp_mb) << 20L, 752 rir_way, 753 reg); 754 755 for (k = 0; k < rir_way; k++) { 756 pci_read_config_dword(pvt->pci_tad[i], 757 rir_offset[j][k], 758 ®); 759 tmp_mb = RIR_OFFSET(reg) << 6; 760 761 mb = div_u64_rem(tmp_mb, 1000, &kb); 762 edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n", 763 i, j, k, 764 mb, kb, 765 ((u64)tmp_mb) << 20L, 766 (u32)RIR_RNK_TGT(reg), 767 reg); 768 } 769 } 770 } 771 } 772 773 struct mem_ctl_info *get_mci_for_node_id(u8 node_id) 774 { 775 struct sbridge_dev *sbridge_dev; 776 777 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { 778 if (sbridge_dev->node_id == node_id) 779 return sbridge_dev->mci; 780 } 781 return NULL; 782 } 783 784 static int get_memory_error_data(struct mem_ctl_info *mci, 785 u64 addr, 786 u8 *socket, 787 long *channel_mask, 788 u8 *rank, 789 char **area_type, char *msg) 790 { 791 struct mem_ctl_info *new_mci; 792 struct sbridge_pvt *pvt = mci->pvt_info; 793 int n_rir, n_sads, n_tads, sad_way, sck_xch; 794 int sad_interl, idx, base_ch; 795 int interleave_mode; 796 unsigned sad_interleave[MAX_INTERLEAVE]; 797 u32 reg; 798 u8 ch_way,sck_way; 799 u32 tad_offset; 800 u32 rir_way; 801 u32 mb, kb; 802 u64 ch_addr, offset, limit, prv = 0; 803 804 805 /* 806 * Step 0) Check if the address is at special memory ranges 807 * The check bellow is probably enough to fill all cases where 808 * the error is not inside a memory, except for the legacy 809 * range (e. g. VGA addresses). It is unlikely, however, that the 810 * memory controller would generate an error on that range. 811 */ 812 if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) { 813 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr); 814 return -EINVAL; 815 } 816 if (addr >= (u64)pvt->tohm) { 817 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr); 818 return -EINVAL; 819 } 820 821 /* 822 * Step 1) Get socket 823 */ 824 for (n_sads = 0; n_sads < MAX_SAD; n_sads++) { 825 pci_read_config_dword(pvt->pci_sad0, dram_rule[n_sads], 826 ®); 827 828 if (!DRAM_RULE_ENABLE(reg)) 829 continue; 830 831 limit = SAD_LIMIT(reg); 832 if (limit <= prv) { 833 sprintf(msg, "Can't discover the memory socket"); 834 return -EINVAL; 835 } 836 if (addr <= limit) 837 break; 838 prv = limit; 839 } 840 if (n_sads == MAX_SAD) { 841 sprintf(msg, "Can't discover the memory socket"); 842 return -EINVAL; 843 } 844 *area_type = get_dram_attr(reg); 845 interleave_mode = INTERLEAVE_MODE(reg); 846 847 pci_read_config_dword(pvt->pci_sad0, interleave_list[n_sads], 848 ®); 849 sad_interl = sad_pkg(reg, 0); 850 for (sad_way = 0; sad_way < 8; sad_way++) { 851 if (sad_way > 0 && sad_interl == sad_pkg(reg, sad_way)) 852 break; 853 sad_interleave[sad_way] = sad_pkg(reg, sad_way); 854 edac_dbg(0, "SAD interleave #%d: %d\n", 855 sad_way, sad_interleave[sad_way]); 856 } 857 edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n", 858 pvt->sbridge_dev->mc, 859 n_sads, 860 addr, 861 limit, 862 sad_way + 7, 863 interleave_mode ? "" : "XOR[18:16]"); 864 if (interleave_mode) 865 idx = ((addr >> 6) ^ (addr >> 16)) & 7; 866 else 867 idx = (addr >> 6) & 7; 868 switch (sad_way) { 869 case 1: 870 idx = 0; 871 break; 872 case 2: 873 idx = idx & 1; 874 break; 875 case 4: 876 idx = idx & 3; 877 break; 878 case 8: 879 break; 880 default: 881 sprintf(msg, "Can't discover socket interleave"); 882 return -EINVAL; 883 } 884 *socket = sad_interleave[idx]; 885 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n", 886 idx, sad_way, *socket); 887 888 /* 889 * Move to the proper node structure, in order to access the 890 * right PCI registers 891 */ 892 new_mci = get_mci_for_node_id(*socket); 893 if (!new_mci) { 894 sprintf(msg, "Struct for socket #%u wasn't initialized", 895 *socket); 896 return -EINVAL; 897 } 898 mci = new_mci; 899 pvt = mci->pvt_info; 900 901 /* 902 * Step 2) Get memory channel 903 */ 904 prv = 0; 905 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) { 906 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads], 907 ®); 908 limit = TAD_LIMIT(reg); 909 if (limit <= prv) { 910 sprintf(msg, "Can't discover the memory channel"); 911 return -EINVAL; 912 } 913 if (addr <= limit) 914 break; 915 prv = limit; 916 } 917 ch_way = TAD_CH(reg) + 1; 918 sck_way = TAD_SOCK(reg) + 1; 919 /* 920 * FIXME: Is it right to always use channel 0 for offsets? 921 */ 922 pci_read_config_dword(pvt->pci_tad[0], 923 tad_ch_nilv_offset[n_tads], 924 &tad_offset); 925 926 if (ch_way == 3) 927 idx = addr >> 6; 928 else 929 idx = addr >> (6 + sck_way); 930 idx = idx % ch_way; 931 932 /* 933 * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ??? 934 */ 935 switch (idx) { 936 case 0: 937 base_ch = TAD_TGT0(reg); 938 break; 939 case 1: 940 base_ch = TAD_TGT1(reg); 941 break; 942 case 2: 943 base_ch = TAD_TGT2(reg); 944 break; 945 case 3: 946 base_ch = TAD_TGT3(reg); 947 break; 948 default: 949 sprintf(msg, "Can't discover the TAD target"); 950 return -EINVAL; 951 } 952 *channel_mask = 1 << base_ch; 953 954 if (pvt->is_mirrored) { 955 *channel_mask |= 1 << ((base_ch + 2) % 4); 956 switch(ch_way) { 957 case 2: 958 case 4: 959 sck_xch = 1 << sck_way * (ch_way >> 1); 960 break; 961 default: 962 sprintf(msg, "Invalid mirror set. Can't decode addr"); 963 return -EINVAL; 964 } 965 } else 966 sck_xch = (1 << sck_way) * ch_way; 967 968 if (pvt->is_lockstep) 969 *channel_mask |= 1 << ((base_ch + 1) % 4); 970 971 offset = TAD_OFFSET(tad_offset); 972 973 edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n", 974 n_tads, 975 addr, 976 limit, 977 (u32)TAD_SOCK(reg), 978 ch_way, 979 offset, 980 idx, 981 base_ch, 982 *channel_mask); 983 984 /* Calculate channel address */ 985 /* Remove the TAD offset */ 986 987 if (offset > addr) { 988 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!", 989 offset, addr); 990 return -EINVAL; 991 } 992 addr -= offset; 993 /* Store the low bits [0:6] of the addr */ 994 ch_addr = addr & 0x7f; 995 /* Remove socket wayness and remove 6 bits */ 996 addr >>= 6; 997 addr = div_u64(addr, sck_xch); 998 #if 0 999 /* Divide by channel way */ 1000 addr = addr / ch_way; 1001 #endif 1002 /* Recover the last 6 bits */ 1003 ch_addr |= addr << 6; 1004 1005 /* 1006 * Step 3) Decode rank 1007 */ 1008 for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) { 1009 pci_read_config_dword(pvt->pci_tad[base_ch], 1010 rir_way_limit[n_rir], 1011 ®); 1012 1013 if (!IS_RIR_VALID(reg)) 1014 continue; 1015 1016 limit = RIR_LIMIT(reg); 1017 mb = div_u64_rem(limit >> 20, 1000, &kb); 1018 edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n", 1019 n_rir, 1020 mb, kb, 1021 limit, 1022 1 << RIR_WAY(reg)); 1023 if (ch_addr <= limit) 1024 break; 1025 } 1026 if (n_rir == MAX_RIR_RANGES) { 1027 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx", 1028 ch_addr); 1029 return -EINVAL; 1030 } 1031 rir_way = RIR_WAY(reg); 1032 if (pvt->is_close_pg) 1033 idx = (ch_addr >> 6); 1034 else 1035 idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */ 1036 idx %= 1 << rir_way; 1037 1038 pci_read_config_dword(pvt->pci_tad[base_ch], 1039 rir_offset[n_rir][idx], 1040 ®); 1041 *rank = RIR_RNK_TGT(reg); 1042 1043 edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n", 1044 n_rir, 1045 ch_addr, 1046 limit, 1047 rir_way, 1048 idx); 1049 1050 return 0; 1051 } 1052 1053 /**************************************************************************** 1054 Device initialization routines: put/get, init/exit 1055 ****************************************************************************/ 1056 1057 /* 1058 * sbridge_put_all_devices 'put' all the devices that we have 1059 * reserved via 'get' 1060 */ 1061 static void sbridge_put_devices(struct sbridge_dev *sbridge_dev) 1062 { 1063 int i; 1064 1065 edac_dbg(0, "\n"); 1066 for (i = 0; i < sbridge_dev->n_devs; i++) { 1067 struct pci_dev *pdev = sbridge_dev->pdev[i]; 1068 if (!pdev) 1069 continue; 1070 edac_dbg(0, "Removing dev %02x:%02x.%d\n", 1071 pdev->bus->number, 1072 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 1073 pci_dev_put(pdev); 1074 } 1075 } 1076 1077 static void sbridge_put_all_devices(void) 1078 { 1079 struct sbridge_dev *sbridge_dev, *tmp; 1080 1081 list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) { 1082 sbridge_put_devices(sbridge_dev); 1083 free_sbridge_dev(sbridge_dev); 1084 } 1085 } 1086 1087 /* 1088 * sbridge_get_all_devices Find and perform 'get' operation on the MCH's 1089 * device/functions we want to reference for this driver 1090 * 1091 * Need to 'get' device 16 func 1 and func 2 1092 */ 1093 static int sbridge_get_onedevice(struct pci_dev **prev, 1094 u8 *num_mc, 1095 const struct pci_id_table *table, 1096 const unsigned devno) 1097 { 1098 struct sbridge_dev *sbridge_dev; 1099 const struct pci_id_descr *dev_descr = &table->descr[devno]; 1100 1101 struct pci_dev *pdev = NULL; 1102 u8 bus = 0; 1103 1104 sbridge_printk(KERN_INFO, 1105 "Seeking for: dev %02x.%d PCI ID %04x:%04x\n", 1106 dev_descr->dev, dev_descr->func, 1107 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 1108 1109 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 1110 dev_descr->dev_id, *prev); 1111 1112 if (!pdev) { 1113 if (*prev) { 1114 *prev = pdev; 1115 return 0; 1116 } 1117 1118 if (dev_descr->optional) 1119 return 0; 1120 1121 if (devno == 0) 1122 return -ENODEV; 1123 1124 sbridge_printk(KERN_INFO, 1125 "Device not found: dev %02x.%d PCI ID %04x:%04x\n", 1126 dev_descr->dev, dev_descr->func, 1127 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 1128 1129 /* End of list, leave */ 1130 return -ENODEV; 1131 } 1132 bus = pdev->bus->number; 1133 1134 sbridge_dev = get_sbridge_dev(bus); 1135 if (!sbridge_dev) { 1136 sbridge_dev = alloc_sbridge_dev(bus, table); 1137 if (!sbridge_dev) { 1138 pci_dev_put(pdev); 1139 return -ENOMEM; 1140 } 1141 (*num_mc)++; 1142 } 1143 1144 if (sbridge_dev->pdev[devno]) { 1145 sbridge_printk(KERN_ERR, 1146 "Duplicated device for " 1147 "dev %02x:%d.%d PCI ID %04x:%04x\n", 1148 bus, dev_descr->dev, dev_descr->func, 1149 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 1150 pci_dev_put(pdev); 1151 return -ENODEV; 1152 } 1153 1154 sbridge_dev->pdev[devno] = pdev; 1155 1156 /* Sanity check */ 1157 if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev || 1158 PCI_FUNC(pdev->devfn) != dev_descr->func)) { 1159 sbridge_printk(KERN_ERR, 1160 "Device PCI ID %04x:%04x " 1161 "has dev %02x:%d.%d instead of dev %02x:%02x.%d\n", 1162 PCI_VENDOR_ID_INTEL, dev_descr->dev_id, 1163 bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 1164 bus, dev_descr->dev, dev_descr->func); 1165 return -ENODEV; 1166 } 1167 1168 /* Be sure that the device is enabled */ 1169 if (unlikely(pci_enable_device(pdev) < 0)) { 1170 sbridge_printk(KERN_ERR, 1171 "Couldn't enable " 1172 "dev %02x:%d.%d PCI ID %04x:%04x\n", 1173 bus, dev_descr->dev, dev_descr->func, 1174 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 1175 return -ENODEV; 1176 } 1177 1178 edac_dbg(0, "Detected dev %02x:%d.%d PCI ID %04x:%04x\n", 1179 bus, dev_descr->dev, dev_descr->func, 1180 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 1181 1182 /* 1183 * As stated on drivers/pci/search.c, the reference count for 1184 * @from is always decremented if it is not %NULL. So, as we need 1185 * to get all devices up to null, we need to do a get for the device 1186 */ 1187 pci_dev_get(pdev); 1188 1189 *prev = pdev; 1190 1191 return 0; 1192 } 1193 1194 static int sbridge_get_all_devices(u8 *num_mc) 1195 { 1196 int i, rc; 1197 struct pci_dev *pdev = NULL; 1198 const struct pci_id_table *table = pci_dev_descr_sbridge_table; 1199 1200 while (table && table->descr) { 1201 for (i = 0; i < table->n_devs; i++) { 1202 pdev = NULL; 1203 do { 1204 rc = sbridge_get_onedevice(&pdev, num_mc, 1205 table, i); 1206 if (rc < 0) { 1207 if (i == 0) { 1208 i = table->n_devs; 1209 break; 1210 } 1211 sbridge_put_all_devices(); 1212 return -ENODEV; 1213 } 1214 } while (pdev); 1215 } 1216 table++; 1217 } 1218 1219 return 0; 1220 } 1221 1222 static int mci_bind_devs(struct mem_ctl_info *mci, 1223 struct sbridge_dev *sbridge_dev) 1224 { 1225 struct sbridge_pvt *pvt = mci->pvt_info; 1226 struct pci_dev *pdev; 1227 int i, func, slot; 1228 1229 for (i = 0; i < sbridge_dev->n_devs; i++) { 1230 pdev = sbridge_dev->pdev[i]; 1231 if (!pdev) 1232 continue; 1233 slot = PCI_SLOT(pdev->devfn); 1234 func = PCI_FUNC(pdev->devfn); 1235 switch (slot) { 1236 case 12: 1237 switch (func) { 1238 case 6: 1239 pvt->pci_sad0 = pdev; 1240 break; 1241 case 7: 1242 pvt->pci_sad1 = pdev; 1243 break; 1244 default: 1245 goto error; 1246 } 1247 break; 1248 case 13: 1249 switch (func) { 1250 case 6: 1251 pvt->pci_br = pdev; 1252 break; 1253 default: 1254 goto error; 1255 } 1256 break; 1257 case 14: 1258 switch (func) { 1259 case 0: 1260 pvt->pci_ha0 = pdev; 1261 break; 1262 default: 1263 goto error; 1264 } 1265 break; 1266 case 15: 1267 switch (func) { 1268 case 0: 1269 pvt->pci_ta = pdev; 1270 break; 1271 case 1: 1272 pvt->pci_ras = pdev; 1273 break; 1274 case 2: 1275 case 3: 1276 case 4: 1277 case 5: 1278 pvt->pci_tad[func - 2] = pdev; 1279 break; 1280 default: 1281 goto error; 1282 } 1283 break; 1284 case 17: 1285 switch (func) { 1286 case 0: 1287 pvt->pci_ddrio = pdev; 1288 break; 1289 default: 1290 goto error; 1291 } 1292 break; 1293 default: 1294 goto error; 1295 } 1296 1297 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", 1298 sbridge_dev->bus, 1299 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 1300 pdev); 1301 } 1302 1303 /* Check if everything were registered */ 1304 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 || 1305 !pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta || 1306 !pvt->pci_ddrio) 1307 goto enodev; 1308 1309 for (i = 0; i < NUM_CHANNELS; i++) { 1310 if (!pvt->pci_tad[i]) 1311 goto enodev; 1312 } 1313 return 0; 1314 1315 enodev: 1316 sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); 1317 return -ENODEV; 1318 1319 error: 1320 sbridge_printk(KERN_ERR, "Device %d, function %d " 1321 "is out of the expected range\n", 1322 slot, func); 1323 return -EINVAL; 1324 } 1325 1326 /**************************************************************************** 1327 Error check routines 1328 ****************************************************************************/ 1329 1330 /* 1331 * While Sandy Bridge has error count registers, SMI BIOS read values from 1332 * and resets the counters. So, they are not reliable for the OS to read 1333 * from them. So, we have no option but to just trust on whatever MCE is 1334 * telling us about the errors. 1335 */ 1336 static void sbridge_mce_output_error(struct mem_ctl_info *mci, 1337 const struct mce *m) 1338 { 1339 struct mem_ctl_info *new_mci; 1340 struct sbridge_pvt *pvt = mci->pvt_info; 1341 enum hw_event_mc_err_type tp_event; 1342 char *type, *optype, msg[256]; 1343 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0); 1344 bool overflow = GET_BITFIELD(m->status, 62, 62); 1345 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61); 1346 bool recoverable = GET_BITFIELD(m->status, 56, 56); 1347 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52); 1348 u32 mscod = GET_BITFIELD(m->status, 16, 31); 1349 u32 errcode = GET_BITFIELD(m->status, 0, 15); 1350 u32 channel = GET_BITFIELD(m->status, 0, 3); 1351 u32 optypenum = GET_BITFIELD(m->status, 4, 6); 1352 long channel_mask, first_channel; 1353 u8 rank, socket; 1354 int rc, dimm; 1355 char *area_type = NULL; 1356 1357 if (uncorrected_error) { 1358 if (ripv) { 1359 type = "FATAL"; 1360 tp_event = HW_EVENT_ERR_FATAL; 1361 } else { 1362 type = "NON_FATAL"; 1363 tp_event = HW_EVENT_ERR_UNCORRECTED; 1364 } 1365 } else { 1366 type = "CORRECTED"; 1367 tp_event = HW_EVENT_ERR_CORRECTED; 1368 } 1369 1370 /* 1371 * According with Table 15-9 of the Intel Architecture spec vol 3A, 1372 * memory errors should fit in this mask: 1373 * 000f 0000 1mmm cccc (binary) 1374 * where: 1375 * f = Correction Report Filtering Bit. If 1, subsequent errors 1376 * won't be shown 1377 * mmm = error type 1378 * cccc = channel 1379 * If the mask doesn't match, report an error to the parsing logic 1380 */ 1381 if (! ((errcode & 0xef80) == 0x80)) { 1382 optype = "Can't parse: it is not a mem"; 1383 } else { 1384 switch (optypenum) { 1385 case 0: 1386 optype = "generic undef request error"; 1387 break; 1388 case 1: 1389 optype = "memory read error"; 1390 break; 1391 case 2: 1392 optype = "memory write error"; 1393 break; 1394 case 3: 1395 optype = "addr/cmd error"; 1396 break; 1397 case 4: 1398 optype = "memory scrubbing error"; 1399 break; 1400 default: 1401 optype = "reserved"; 1402 break; 1403 } 1404 } 1405 1406 rc = get_memory_error_data(mci, m->addr, &socket, 1407 &channel_mask, &rank, &area_type, msg); 1408 if (rc < 0) 1409 goto err_parsing; 1410 new_mci = get_mci_for_node_id(socket); 1411 if (!new_mci) { 1412 strcpy(msg, "Error: socket got corrupted!"); 1413 goto err_parsing; 1414 } 1415 mci = new_mci; 1416 pvt = mci->pvt_info; 1417 1418 first_channel = find_first_bit(&channel_mask, NUM_CHANNELS); 1419 1420 if (rank < 4) 1421 dimm = 0; 1422 else if (rank < 8) 1423 dimm = 1; 1424 else 1425 dimm = 2; 1426 1427 1428 /* 1429 * FIXME: On some memory configurations (mirror, lockstep), the 1430 * Memory Controller can't point the error to a single DIMM. The 1431 * EDAC core should be handling the channel mask, in order to point 1432 * to the group of dimm's where the error may be happening. 1433 */ 1434 snprintf(msg, sizeof(msg), 1435 "%s%s area:%s err_code:%04x:%04x socket:%d channel_mask:%ld rank:%d", 1436 overflow ? " OVERFLOW" : "", 1437 (uncorrected_error && recoverable) ? " recoverable" : "", 1438 area_type, 1439 mscod, errcode, 1440 socket, 1441 channel_mask, 1442 rank); 1443 1444 edac_dbg(0, "%s\n", msg); 1445 1446 /* FIXME: need support for channel mask */ 1447 1448 /* Call the helper to output message */ 1449 edac_mc_handle_error(tp_event, mci, core_err_cnt, 1450 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, 1451 channel, dimm, -1, 1452 optype, msg); 1453 return; 1454 err_parsing: 1455 edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0, 1456 -1, -1, -1, 1457 msg, ""); 1458 1459 } 1460 1461 /* 1462 * sbridge_check_error Retrieve and process errors reported by the 1463 * hardware. Called by the Core module. 1464 */ 1465 static void sbridge_check_error(struct mem_ctl_info *mci) 1466 { 1467 struct sbridge_pvt *pvt = mci->pvt_info; 1468 int i; 1469 unsigned count = 0; 1470 struct mce *m; 1471 1472 /* 1473 * MCE first step: Copy all mce errors into a temporary buffer 1474 * We use a double buffering here, to reduce the risk of 1475 * loosing an error. 1476 */ 1477 smp_rmb(); 1478 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in) 1479 % MCE_LOG_LEN; 1480 if (!count) 1481 return; 1482 1483 m = pvt->mce_outentry; 1484 if (pvt->mce_in + count > MCE_LOG_LEN) { 1485 unsigned l = MCE_LOG_LEN - pvt->mce_in; 1486 1487 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l); 1488 smp_wmb(); 1489 pvt->mce_in = 0; 1490 count -= l; 1491 m += l; 1492 } 1493 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count); 1494 smp_wmb(); 1495 pvt->mce_in += count; 1496 1497 smp_rmb(); 1498 if (pvt->mce_overrun) { 1499 sbridge_printk(KERN_ERR, "Lost %d memory errors\n", 1500 pvt->mce_overrun); 1501 smp_wmb(); 1502 pvt->mce_overrun = 0; 1503 } 1504 1505 /* 1506 * MCE second step: parse errors and display 1507 */ 1508 for (i = 0; i < count; i++) 1509 sbridge_mce_output_error(mci, &pvt->mce_outentry[i]); 1510 } 1511 1512 /* 1513 * sbridge_mce_check_error Replicates mcelog routine to get errors 1514 * This routine simply queues mcelog errors, and 1515 * return. The error itself should be handled later 1516 * by sbridge_check_error. 1517 * WARNING: As this routine should be called at NMI time, extra care should 1518 * be taken to avoid deadlocks, and to be as fast as possible. 1519 */ 1520 static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val, 1521 void *data) 1522 { 1523 struct mce *mce = (struct mce *)data; 1524 struct mem_ctl_info *mci; 1525 struct sbridge_pvt *pvt; 1526 1527 mci = get_mci_for_node_id(mce->socketid); 1528 if (!mci) 1529 return NOTIFY_BAD; 1530 pvt = mci->pvt_info; 1531 1532 /* 1533 * Just let mcelog handle it if the error is 1534 * outside the memory controller. A memory error 1535 * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0. 1536 * bit 12 has an special meaning. 1537 */ 1538 if ((mce->status & 0xefff) >> 7 != 1) 1539 return NOTIFY_DONE; 1540 1541 printk("sbridge: HANDLING MCE MEMORY ERROR\n"); 1542 1543 printk("CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n", 1544 mce->extcpu, mce->mcgstatus, mce->bank, mce->status); 1545 printk("TSC %llx ", mce->tsc); 1546 printk("ADDR %llx ", mce->addr); 1547 printk("MISC %llx ", mce->misc); 1548 1549 printk("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n", 1550 mce->cpuvendor, mce->cpuid, mce->time, 1551 mce->socketid, mce->apicid); 1552 1553 /* Only handle if it is the right mc controller */ 1554 if (cpu_data(mce->cpu).phys_proc_id != pvt->sbridge_dev->mc) 1555 return NOTIFY_DONE; 1556 1557 smp_rmb(); 1558 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) { 1559 smp_wmb(); 1560 pvt->mce_overrun++; 1561 return NOTIFY_DONE; 1562 } 1563 1564 /* Copy memory error at the ringbuffer */ 1565 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce)); 1566 smp_wmb(); 1567 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN; 1568 1569 /* Handle fatal errors immediately */ 1570 if (mce->mcgstatus & 1) 1571 sbridge_check_error(mci); 1572 1573 /* Advice mcelog that the error were handled */ 1574 return NOTIFY_STOP; 1575 } 1576 1577 static struct notifier_block sbridge_mce_dec = { 1578 .notifier_call = sbridge_mce_check_error, 1579 }; 1580 1581 /**************************************************************************** 1582 EDAC register/unregister logic 1583 ****************************************************************************/ 1584 1585 static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev) 1586 { 1587 struct mem_ctl_info *mci = sbridge_dev->mci; 1588 struct sbridge_pvt *pvt; 1589 1590 if (unlikely(!mci || !mci->pvt_info)) { 1591 edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev); 1592 1593 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n"); 1594 return; 1595 } 1596 1597 pvt = mci->pvt_info; 1598 1599 edac_dbg(0, "MC: mci = %p, dev = %p\n", 1600 mci, &sbridge_dev->pdev[0]->dev); 1601 1602 /* Remove MC sysfs nodes */ 1603 edac_mc_del_mc(mci->pdev); 1604 1605 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name); 1606 kfree(mci->ctl_name); 1607 edac_mc_free(mci); 1608 sbridge_dev->mci = NULL; 1609 } 1610 1611 static int sbridge_register_mci(struct sbridge_dev *sbridge_dev) 1612 { 1613 struct mem_ctl_info *mci; 1614 struct edac_mc_layer layers[2]; 1615 struct sbridge_pvt *pvt; 1616 int rc; 1617 1618 /* Check the number of active and not disabled channels */ 1619 rc = check_if_ecc_is_active(sbridge_dev->bus); 1620 if (unlikely(rc < 0)) 1621 return rc; 1622 1623 /* allocate a new MC control structure */ 1624 layers[0].type = EDAC_MC_LAYER_CHANNEL; 1625 layers[0].size = NUM_CHANNELS; 1626 layers[0].is_virt_csrow = false; 1627 layers[1].type = EDAC_MC_LAYER_SLOT; 1628 layers[1].size = MAX_DIMMS; 1629 layers[1].is_virt_csrow = true; 1630 mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers, 1631 sizeof(*pvt)); 1632 1633 if (unlikely(!mci)) 1634 return -ENOMEM; 1635 1636 edac_dbg(0, "MC: mci = %p, dev = %p\n", 1637 mci, &sbridge_dev->pdev[0]->dev); 1638 1639 pvt = mci->pvt_info; 1640 memset(pvt, 0, sizeof(*pvt)); 1641 1642 /* Associate sbridge_dev and mci for future usage */ 1643 pvt->sbridge_dev = sbridge_dev; 1644 sbridge_dev->mci = mci; 1645 1646 mci->mtype_cap = MEM_FLAG_DDR3; 1647 mci->edac_ctl_cap = EDAC_FLAG_NONE; 1648 mci->edac_cap = EDAC_FLAG_NONE; 1649 mci->mod_name = "sbridge_edac.c"; 1650 mci->mod_ver = SBRIDGE_REVISION; 1651 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx); 1652 mci->dev_name = pci_name(sbridge_dev->pdev[0]); 1653 mci->ctl_page_to_phys = NULL; 1654 1655 /* Set the function pointer to an actual operation function */ 1656 mci->edac_check = sbridge_check_error; 1657 1658 /* Store pci devices at mci for faster access */ 1659 rc = mci_bind_devs(mci, sbridge_dev); 1660 if (unlikely(rc < 0)) 1661 goto fail0; 1662 1663 /* Get dimm basic config and the memory layout */ 1664 get_dimm_config(mci); 1665 get_memory_layout(mci); 1666 1667 /* record ptr to the generic device */ 1668 mci->pdev = &sbridge_dev->pdev[0]->dev; 1669 1670 /* add this new MC control structure to EDAC's list of MCs */ 1671 if (unlikely(edac_mc_add_mc(mci))) { 1672 edac_dbg(0, "MC: failed edac_mc_add_mc()\n"); 1673 rc = -EINVAL; 1674 goto fail0; 1675 } 1676 1677 return 0; 1678 1679 fail0: 1680 kfree(mci->ctl_name); 1681 edac_mc_free(mci); 1682 sbridge_dev->mci = NULL; 1683 return rc; 1684 } 1685 1686 /* 1687 * sbridge_probe Probe for ONE instance of device to see if it is 1688 * present. 1689 * return: 1690 * 0 for FOUND a device 1691 * < 0 for error code 1692 */ 1693 1694 static int __devinit sbridge_probe(struct pci_dev *pdev, 1695 const struct pci_device_id *id) 1696 { 1697 int rc; 1698 u8 mc, num_mc = 0; 1699 struct sbridge_dev *sbridge_dev; 1700 1701 /* get the pci devices we want to reserve for our use */ 1702 mutex_lock(&sbridge_edac_lock); 1703 1704 /* 1705 * All memory controllers are allocated at the first pass. 1706 */ 1707 if (unlikely(probed >= 1)) { 1708 mutex_unlock(&sbridge_edac_lock); 1709 return -ENODEV; 1710 } 1711 probed++; 1712 1713 rc = sbridge_get_all_devices(&num_mc); 1714 if (unlikely(rc < 0)) 1715 goto fail0; 1716 mc = 0; 1717 1718 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { 1719 edac_dbg(0, "Registering MC#%d (%d of %d)\n", 1720 mc, mc + 1, num_mc); 1721 sbridge_dev->mc = mc++; 1722 rc = sbridge_register_mci(sbridge_dev); 1723 if (unlikely(rc < 0)) 1724 goto fail1; 1725 } 1726 1727 sbridge_printk(KERN_INFO, "Driver loaded.\n"); 1728 1729 mutex_unlock(&sbridge_edac_lock); 1730 return 0; 1731 1732 fail1: 1733 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) 1734 sbridge_unregister_mci(sbridge_dev); 1735 1736 sbridge_put_all_devices(); 1737 fail0: 1738 mutex_unlock(&sbridge_edac_lock); 1739 return rc; 1740 } 1741 1742 /* 1743 * sbridge_remove destructor for one instance of device 1744 * 1745 */ 1746 static void __devexit sbridge_remove(struct pci_dev *pdev) 1747 { 1748 struct sbridge_dev *sbridge_dev; 1749 1750 edac_dbg(0, "\n"); 1751 1752 /* 1753 * we have a trouble here: pdev value for removal will be wrong, since 1754 * it will point to the X58 register used to detect that the machine 1755 * is a Nehalem or upper design. However, due to the way several PCI 1756 * devices are grouped together to provide MC functionality, we need 1757 * to use a different method for releasing the devices 1758 */ 1759 1760 mutex_lock(&sbridge_edac_lock); 1761 1762 if (unlikely(!probed)) { 1763 mutex_unlock(&sbridge_edac_lock); 1764 return; 1765 } 1766 1767 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) 1768 sbridge_unregister_mci(sbridge_dev); 1769 1770 /* Release PCI resources */ 1771 sbridge_put_all_devices(); 1772 1773 probed--; 1774 1775 mutex_unlock(&sbridge_edac_lock); 1776 } 1777 1778 MODULE_DEVICE_TABLE(pci, sbridge_pci_tbl); 1779 1780 /* 1781 * sbridge_driver pci_driver structure for this module 1782 * 1783 */ 1784 static struct pci_driver sbridge_driver = { 1785 .name = "sbridge_edac", 1786 .probe = sbridge_probe, 1787 .remove = __devexit_p(sbridge_remove), 1788 .id_table = sbridge_pci_tbl, 1789 }; 1790 1791 /* 1792 * sbridge_init Module entry function 1793 * Try to initialize this module for its devices 1794 */ 1795 static int __init sbridge_init(void) 1796 { 1797 int pci_rc; 1798 1799 edac_dbg(2, "\n"); 1800 1801 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 1802 opstate_init(); 1803 1804 pci_rc = pci_register_driver(&sbridge_driver); 1805 1806 if (pci_rc >= 0) { 1807 mce_register_decode_chain(&sbridge_mce_dec); 1808 return 0; 1809 } 1810 1811 sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n", 1812 pci_rc); 1813 1814 return pci_rc; 1815 } 1816 1817 /* 1818 * sbridge_exit() Module exit function 1819 * Unregister the driver 1820 */ 1821 static void __exit sbridge_exit(void) 1822 { 1823 edac_dbg(2, "\n"); 1824 pci_unregister_driver(&sbridge_driver); 1825 mce_unregister_decode_chain(&sbridge_mce_dec); 1826 } 1827 1828 module_init(sbridge_init); 1829 module_exit(sbridge_exit); 1830 1831 module_param(edac_op_state, int, 0444); 1832 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); 1833 1834 MODULE_LICENSE("GPL"); 1835 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); 1836 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); 1837 MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge memory controllers - " 1838 SBRIDGE_REVISION); 1839