xref: /openbmc/linux/drivers/edac/sb_edac.c (revision 110e6f26)
1 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
2  *
3  * This driver supports the memory controllers found on the Intel
4  * processor family Sandy Bridge.
5  *
6  * This file may be distributed under the terms of the
7  * GNU General Public License version 2 only.
8  *
9  * Copyright (c) 2011 by:
10  *	 Mauro Carvalho Chehab
11  */
12 
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/pci_ids.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/edac.h>
20 #include <linux/mmzone.h>
21 #include <linux/smp.h>
22 #include <linux/bitmap.h>
23 #include <linux/math64.h>
24 #include <asm/processor.h>
25 #include <asm/mce.h>
26 
27 #include "edac_core.h"
28 
29 /* Static vars */
30 static LIST_HEAD(sbridge_edac_list);
31 static DEFINE_MUTEX(sbridge_edac_lock);
32 static int probed;
33 
34 /*
35  * Alter this version for the module when modifications are made
36  */
37 #define SBRIDGE_REVISION    " Ver: 1.1.1 "
38 #define EDAC_MOD_STR      "sbridge_edac"
39 
40 /*
41  * Debug macros
42  */
43 #define sbridge_printk(level, fmt, arg...)			\
44 	edac_printk(level, "sbridge", fmt, ##arg)
45 
46 #define sbridge_mc_printk(mci, level, fmt, arg...)		\
47 	edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)
48 
49 /*
50  * Get a bit field at register value <v>, from bit <lo> to bit <hi>
51  */
52 #define GET_BITFIELD(v, lo, hi)	\
53 	(((v) & GENMASK_ULL(hi, lo)) >> (lo))
54 
55 /* Devices 12 Function 6, Offsets 0x80 to 0xcc */
56 static const u32 sbridge_dram_rule[] = {
57 	0x80, 0x88, 0x90, 0x98, 0xa0,
58 	0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
59 };
60 
61 static const u32 ibridge_dram_rule[] = {
62 	0x60, 0x68, 0x70, 0x78, 0x80,
63 	0x88, 0x90, 0x98, 0xa0,	0xa8,
64 	0xb0, 0xb8, 0xc0, 0xc8, 0xd0,
65 	0xd8, 0xe0, 0xe8, 0xf0, 0xf8,
66 };
67 
68 static const u32 knl_dram_rule[] = {
69 	0x60, 0x68, 0x70, 0x78, 0x80, /* 0-4 */
70 	0x88, 0x90, 0x98, 0xa0, 0xa8, /* 5-9 */
71 	0xb0, 0xb8, 0xc0, 0xc8, 0xd0, /* 10-14 */
72 	0xd8, 0xe0, 0xe8, 0xf0, 0xf8, /* 15-19 */
73 	0x100, 0x108, 0x110, 0x118,   /* 20-23 */
74 };
75 
76 #define DRAM_RULE_ENABLE(reg)	GET_BITFIELD(reg, 0,  0)
77 #define A7MODE(reg)		GET_BITFIELD(reg, 26, 26)
78 
79 static char *show_dram_attr(u32 attr)
80 {
81 	switch (attr) {
82 		case 0:
83 			return "DRAM";
84 		case 1:
85 			return "MMCFG";
86 		case 2:
87 			return "NXM";
88 		default:
89 			return "unknown";
90 	}
91 }
92 
93 static const u32 sbridge_interleave_list[] = {
94 	0x84, 0x8c, 0x94, 0x9c, 0xa4,
95 	0xac, 0xb4, 0xbc, 0xc4, 0xcc,
96 };
97 
98 static const u32 ibridge_interleave_list[] = {
99 	0x64, 0x6c, 0x74, 0x7c, 0x84,
100 	0x8c, 0x94, 0x9c, 0xa4, 0xac,
101 	0xb4, 0xbc, 0xc4, 0xcc, 0xd4,
102 	0xdc, 0xe4, 0xec, 0xf4, 0xfc,
103 };
104 
105 static const u32 knl_interleave_list[] = {
106 	0x64, 0x6c, 0x74, 0x7c, 0x84, /* 0-4 */
107 	0x8c, 0x94, 0x9c, 0xa4, 0xac, /* 5-9 */
108 	0xb4, 0xbc, 0xc4, 0xcc, 0xd4, /* 10-14 */
109 	0xdc, 0xe4, 0xec, 0xf4, 0xfc, /* 15-19 */
110 	0x104, 0x10c, 0x114, 0x11c,   /* 20-23 */
111 };
112 
113 struct interleave_pkg {
114 	unsigned char start;
115 	unsigned char end;
116 };
117 
118 static const struct interleave_pkg sbridge_interleave_pkg[] = {
119 	{ 0, 2 },
120 	{ 3, 5 },
121 	{ 8, 10 },
122 	{ 11, 13 },
123 	{ 16, 18 },
124 	{ 19, 21 },
125 	{ 24, 26 },
126 	{ 27, 29 },
127 };
128 
129 static const struct interleave_pkg ibridge_interleave_pkg[] = {
130 	{ 0, 3 },
131 	{ 4, 7 },
132 	{ 8, 11 },
133 	{ 12, 15 },
134 	{ 16, 19 },
135 	{ 20, 23 },
136 	{ 24, 27 },
137 	{ 28, 31 },
138 };
139 
140 static inline int sad_pkg(const struct interleave_pkg *table, u32 reg,
141 			  int interleave)
142 {
143 	return GET_BITFIELD(reg, table[interleave].start,
144 			    table[interleave].end);
145 }
146 
147 /* Devices 12 Function 7 */
148 
149 #define TOLM		0x80
150 #define TOHM		0x84
151 #define HASWELL_TOLM	0xd0
152 #define HASWELL_TOHM_0	0xd4
153 #define HASWELL_TOHM_1	0xd8
154 #define KNL_TOLM	0xd0
155 #define KNL_TOHM_0	0xd4
156 #define KNL_TOHM_1	0xd8
157 
158 #define GET_TOLM(reg)		((GET_BITFIELD(reg, 0,  3) << 28) | 0x3ffffff)
159 #define GET_TOHM(reg)		((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
160 
161 /* Device 13 Function 6 */
162 
163 #define SAD_TARGET	0xf0
164 
165 #define SOURCE_ID(reg)		GET_BITFIELD(reg, 9, 11)
166 
167 #define SOURCE_ID_KNL(reg)	GET_BITFIELD(reg, 12, 14)
168 
169 #define SAD_CONTROL	0xf4
170 
171 /* Device 14 function 0 */
172 
173 static const u32 tad_dram_rule[] = {
174 	0x40, 0x44, 0x48, 0x4c,
175 	0x50, 0x54, 0x58, 0x5c,
176 	0x60, 0x64, 0x68, 0x6c,
177 };
178 #define MAX_TAD	ARRAY_SIZE(tad_dram_rule)
179 
180 #define TAD_LIMIT(reg)		((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
181 #define TAD_SOCK(reg)		GET_BITFIELD(reg, 10, 11)
182 #define TAD_CH(reg)		GET_BITFIELD(reg,  8,  9)
183 #define TAD_TGT3(reg)		GET_BITFIELD(reg,  6,  7)
184 #define TAD_TGT2(reg)		GET_BITFIELD(reg,  4,  5)
185 #define TAD_TGT1(reg)		GET_BITFIELD(reg,  2,  3)
186 #define TAD_TGT0(reg)		GET_BITFIELD(reg,  0,  1)
187 
188 /* Device 15, function 0 */
189 
190 #define MCMTR			0x7c
191 #define KNL_MCMTR		0x624
192 
193 #define IS_ECC_ENABLED(mcmtr)		GET_BITFIELD(mcmtr, 2, 2)
194 #define IS_LOCKSTEP_ENABLED(mcmtr)	GET_BITFIELD(mcmtr, 1, 1)
195 #define IS_CLOSE_PG(mcmtr)		GET_BITFIELD(mcmtr, 0, 0)
196 
197 /* Device 15, function 1 */
198 
199 #define RASENABLES		0xac
200 #define IS_MIRROR_ENABLED(reg)		GET_BITFIELD(reg, 0, 0)
201 
202 /* Device 15, functions 2-5 */
203 
204 static const int mtr_regs[] = {
205 	0x80, 0x84, 0x88,
206 };
207 
208 static const int knl_mtr_reg = 0xb60;
209 
210 #define RANK_DISABLE(mtr)		GET_BITFIELD(mtr, 16, 19)
211 #define IS_DIMM_PRESENT(mtr)		GET_BITFIELD(mtr, 14, 14)
212 #define RANK_CNT_BITS(mtr)		GET_BITFIELD(mtr, 12, 13)
213 #define RANK_WIDTH_BITS(mtr)		GET_BITFIELD(mtr, 2, 4)
214 #define COL_WIDTH_BITS(mtr)		GET_BITFIELD(mtr, 0, 1)
215 
216 static const u32 tad_ch_nilv_offset[] = {
217 	0x90, 0x94, 0x98, 0x9c,
218 	0xa0, 0xa4, 0xa8, 0xac,
219 	0xb0, 0xb4, 0xb8, 0xbc,
220 };
221 #define CHN_IDX_OFFSET(reg)		GET_BITFIELD(reg, 28, 29)
222 #define TAD_OFFSET(reg)			(GET_BITFIELD(reg,  6, 25) << 26)
223 
224 static const u32 rir_way_limit[] = {
225 	0x108, 0x10c, 0x110, 0x114, 0x118,
226 };
227 #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
228 
229 #define IS_RIR_VALID(reg)	GET_BITFIELD(reg, 31, 31)
230 #define RIR_WAY(reg)		GET_BITFIELD(reg, 28, 29)
231 
232 #define MAX_RIR_WAY	8
233 
234 static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = {
235 	{ 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c },
236 	{ 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c },
237 	{ 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c },
238 	{ 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c },
239 	{ 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc },
240 };
241 
242 #define RIR_RNK_TGT(reg)		GET_BITFIELD(reg, 16, 19)
243 #define RIR_OFFSET(reg)		GET_BITFIELD(reg,  2, 14)
244 
245 /* Device 16, functions 2-7 */
246 
247 /*
248  * FIXME: Implement the error count reads directly
249  */
250 
251 static const u32 correrrcnt[] = {
252 	0x104, 0x108, 0x10c, 0x110,
253 };
254 
255 #define RANK_ODD_OV(reg)		GET_BITFIELD(reg, 31, 31)
256 #define RANK_ODD_ERR_CNT(reg)		GET_BITFIELD(reg, 16, 30)
257 #define RANK_EVEN_OV(reg)		GET_BITFIELD(reg, 15, 15)
258 #define RANK_EVEN_ERR_CNT(reg)		GET_BITFIELD(reg,  0, 14)
259 
260 static const u32 correrrthrsld[] = {
261 	0x11c, 0x120, 0x124, 0x128,
262 };
263 
264 #define RANK_ODD_ERR_THRSLD(reg)	GET_BITFIELD(reg, 16, 30)
265 #define RANK_EVEN_ERR_THRSLD(reg)	GET_BITFIELD(reg,  0, 14)
266 
267 
268 /* Device 17, function 0 */
269 
270 #define SB_RANK_CFG_A		0x0328
271 
272 #define IB_RANK_CFG_A		0x0320
273 
274 /*
275  * sbridge structs
276  */
277 
278 #define NUM_CHANNELS		8	/* 2MC per socket, four chan per MC */
279 #define MAX_DIMMS		3	/* Max DIMMS per channel */
280 #define KNL_MAX_CHAS		38	/* KNL max num. of Cache Home Agents */
281 #define KNL_MAX_CHANNELS	6	/* KNL max num. of PCI channels */
282 #define KNL_MAX_EDCS		8	/* Embedded DRAM controllers */
283 #define CHANNEL_UNSPECIFIED	0xf	/* Intel IA32 SDM 15-14 */
284 
285 enum type {
286 	SANDY_BRIDGE,
287 	IVY_BRIDGE,
288 	HASWELL,
289 	BROADWELL,
290 	KNIGHTS_LANDING,
291 };
292 
293 struct sbridge_pvt;
294 struct sbridge_info {
295 	enum type	type;
296 	u32		mcmtr;
297 	u32		rankcfgr;
298 	u64		(*get_tolm)(struct sbridge_pvt *pvt);
299 	u64		(*get_tohm)(struct sbridge_pvt *pvt);
300 	u64		(*rir_limit)(u32 reg);
301 	u64		(*sad_limit)(u32 reg);
302 	u32		(*interleave_mode)(u32 reg);
303 	char*		(*show_interleave_mode)(u32 reg);
304 	u32		(*dram_attr)(u32 reg);
305 	const u32	*dram_rule;
306 	const u32	*interleave_list;
307 	const struct interleave_pkg *interleave_pkg;
308 	u8		max_sad;
309 	u8		max_interleave;
310 	u8		(*get_node_id)(struct sbridge_pvt *pvt);
311 	enum mem_type	(*get_memory_type)(struct sbridge_pvt *pvt);
312 	enum dev_type	(*get_width)(struct sbridge_pvt *pvt, u32 mtr);
313 	struct pci_dev	*pci_vtd;
314 };
315 
316 struct sbridge_channel {
317 	u32		ranks;
318 	u32		dimms;
319 };
320 
321 struct pci_id_descr {
322 	int			dev_id;
323 	int			optional;
324 };
325 
326 struct pci_id_table {
327 	const struct pci_id_descr	*descr;
328 	int				n_devs;
329 };
330 
331 struct sbridge_dev {
332 	struct list_head	list;
333 	u8			bus, mc;
334 	u8			node_id, source_id;
335 	struct pci_dev		**pdev;
336 	int			n_devs;
337 	struct mem_ctl_info	*mci;
338 };
339 
340 struct knl_pvt {
341 	struct pci_dev          *pci_cha[KNL_MAX_CHAS];
342 	struct pci_dev          *pci_channel[KNL_MAX_CHANNELS];
343 	struct pci_dev          *pci_mc0;
344 	struct pci_dev          *pci_mc1;
345 	struct pci_dev          *pci_mc0_misc;
346 	struct pci_dev          *pci_mc1_misc;
347 	struct pci_dev          *pci_mc_info; /* tolm, tohm */
348 };
349 
350 struct sbridge_pvt {
351 	struct pci_dev		*pci_ta, *pci_ddrio, *pci_ras;
352 	struct pci_dev		*pci_sad0, *pci_sad1;
353 	struct pci_dev		*pci_ha0, *pci_ha1;
354 	struct pci_dev		*pci_br0, *pci_br1;
355 	struct pci_dev		*pci_ha1_ta;
356 	struct pci_dev		*pci_tad[NUM_CHANNELS];
357 
358 	struct sbridge_dev	*sbridge_dev;
359 
360 	struct sbridge_info	info;
361 	struct sbridge_channel	channel[NUM_CHANNELS];
362 
363 	/* Memory type detection */
364 	bool			is_mirrored, is_lockstep, is_close_pg;
365 
366 	/* Fifo double buffers */
367 	struct mce		mce_entry[MCE_LOG_LEN];
368 	struct mce		mce_outentry[MCE_LOG_LEN];
369 
370 	/* Fifo in/out counters */
371 	unsigned		mce_in, mce_out;
372 
373 	/* Count indicator to show errors not got */
374 	unsigned		mce_overrun;
375 
376 	/* Memory description */
377 	u64			tolm, tohm;
378 	struct knl_pvt knl;
379 };
380 
381 #define PCI_DESCR(device_id, opt)	\
382 	.dev_id = (device_id),		\
383 	.optional = opt
384 
385 static const struct pci_id_descr pci_dev_descr_sbridge[] = {
386 		/* Processor Home Agent */
387 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0)	},
388 
389 		/* Memory controller */
390 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0)	},
391 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0)	},
392 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0)	},
393 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0)	},
394 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0)	},
395 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0)	},
396 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1)	},
397 
398 		/* System Address Decoder */
399 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0)	},
400 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0)	},
401 
402 		/* Broadcast Registers */
403 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0)		},
404 };
405 
406 #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
407 static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
408 	PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge),
409 	{0,}			/* 0 terminated list. */
410 };
411 
412 /* This changes depending if 1HA or 2HA:
413  * 1HA:
414  *	0x0eb8 (17.0) is DDRIO0
415  * 2HA:
416  *	0x0ebc (17.4) is DDRIO0
417  */
418 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0	0x0eb8
419 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0	0x0ebc
420 
421 /* pci ids */
422 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0		0x0ea0
423 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA		0x0ea8
424 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS		0x0e71
425 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0	0x0eaa
426 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1	0x0eab
427 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2	0x0eac
428 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3	0x0ead
429 #define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD			0x0ec8
430 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0			0x0ec9
431 #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1			0x0eca
432 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1		0x0e60
433 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA		0x0e68
434 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS		0x0e79
435 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0	0x0e6a
436 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1	0x0e6b
437 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2	0x0e6c
438 #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3	0x0e6d
439 
440 static const struct pci_id_descr pci_dev_descr_ibridge[] = {
441 		/* Processor Home Agent */
442 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0)		},
443 
444 		/* Memory controller */
445 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0)		},
446 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0)		},
447 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0)	},
448 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0)	},
449 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0)	},
450 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0)	},
451 
452 		/* System Address Decoder */
453 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0)			},
454 
455 		/* Broadcast Registers */
456 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1)			},
457 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0)			},
458 
459 		/* Optional, mode 2HA */
460 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1)		},
461 #if 0
462 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1)	},
463 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1)	},
464 #endif
465 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1)	},
466 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1)	},
467 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2, 1)	},
468 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3, 1)	},
469 
470 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1)	},
471 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1)	},
472 };
473 
474 static const struct pci_id_table pci_dev_descr_ibridge_table[] = {
475 	PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge),
476 	{0,}			/* 0 terminated list. */
477 };
478 
479 /* Haswell support */
480 /* EN processor:
481  *	- 1 IMC
482  *	- 3 DDR3 channels, 2 DPC per channel
483  * EP processor:
484  *	- 1 or 2 IMC
485  *	- 4 DDR4 channels, 3 DPC per channel
486  * EP 4S processor:
487  *	- 2 IMC
488  *	- 4 DDR4 channels, 3 DPC per channel
489  * EX processor:
490  *	- 2 IMC
491  *	- each IMC interfaces with a SMI 2 channel
492  *	- each SMI channel interfaces with a scalable memory buffer
493  *	- each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
494  */
495 #define HASWELL_DDRCRCLKCONTROLS 0xa10 /* Ditto on Broadwell */
496 #define HASWELL_HASYSDEFEATURE2 0x84
497 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28
498 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0	0x2fa0
499 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1	0x2f60
500 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA	0x2fa8
501 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL 0x2f71
502 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA	0x2f68
503 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL 0x2f79
504 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc
505 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd
506 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa
507 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab
508 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac
509 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad
510 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a
511 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b
512 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c
513 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d
514 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd
515 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1 0x2fbf
516 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2 0x2fb9
517 #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3 0x2fbb
518 static const struct pci_id_descr pci_dev_descr_haswell[] = {
519 	/* first item must be the HA */
520 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0)		},
521 
522 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0)	},
523 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0)	},
524 
525 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1)		},
526 
527 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0)		},
528 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL, 0)	},
529 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0)	},
530 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0)	},
531 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1)	},
532 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1)	},
533 
534 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1)		},
535 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1, 1)		},
536 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2, 1)		},
537 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3, 1)		},
538 
539 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1)		},
540 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL, 1)	},
541 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1)	},
542 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1)	},
543 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1)	},
544 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1)	},
545 };
546 
547 static const struct pci_id_table pci_dev_descr_haswell_table[] = {
548 	PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell),
549 	{0,}			/* 0 terminated list. */
550 };
551 
552 /* Knight's Landing Support */
553 /*
554  * KNL's memory channels are swizzled between memory controllers.
555  * MC0 is mapped to CH3,5,6 and MC1 is mapped to CH0,1,2
556  */
557 #define knl_channel_remap(channel) ((channel + 3) % 6)
558 
559 /* Memory controller, TAD tables, error injection - 2-8-0, 2-9-0 (2 of these) */
560 #define PCI_DEVICE_ID_INTEL_KNL_IMC_MC       0x7840
561 /* DRAM channel stuff; bank addrs, dimmmtr, etc.. 2-8-2 - 2-9-4 (6 of these) */
562 #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHANNEL  0x7843
563 /* kdrwdbu TAD limits/offsets, MCMTR - 2-10-1, 2-11-1 (2 of these) */
564 #define PCI_DEVICE_ID_INTEL_KNL_IMC_TA       0x7844
565 /* CHA broadcast registers, dram rules - 1-29-0 (1 of these) */
566 #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0     0x782a
567 /* SAD target - 1-29-1 (1 of these) */
568 #define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1     0x782b
569 /* Caching / Home Agent */
570 #define PCI_DEVICE_ID_INTEL_KNL_IMC_CHA      0x782c
571 /* Device with TOLM and TOHM, 0-5-0 (1 of these) */
572 #define PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM    0x7810
573 
574 /*
575  * KNL differs from SB, IB, and Haswell in that it has multiple
576  * instances of the same device with the same device ID, so we handle that
577  * by creating as many copies in the table as we expect to find.
578  * (Like device ID must be grouped together.)
579  */
580 
581 static const struct pci_id_descr pci_dev_descr_knl[] = {
582 	[0]         = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0, 0) },
583 	[1]         = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1, 0) },
584 	[2 ... 3]   = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_MC, 0)},
585 	[4 ... 41]  = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHA, 0) },
586 	[42 ... 47] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHANNEL, 0) },
587 	[48]        = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TA, 0) },
588 	[49]        = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM, 0) },
589 };
590 
591 static const struct pci_id_table pci_dev_descr_knl_table[] = {
592 	PCI_ID_TABLE_ENTRY(pci_dev_descr_knl),
593 	{0,}
594 };
595 
596 /*
597  * Broadwell support
598  *
599  * DE processor:
600  *	- 1 IMC
601  *	- 2 DDR3 channels, 2 DPC per channel
602  * EP processor:
603  *	- 1 or 2 IMC
604  *	- 4 DDR4 channels, 3 DPC per channel
605  * EP 4S processor:
606  *	- 2 IMC
607  *	- 4 DDR4 channels, 3 DPC per channel
608  * EX processor:
609  *	- 2 IMC
610  *	- each IMC interfaces with a SMI 2 channel
611  *	- each SMI channel interfaces with a scalable memory buffer
612  *	- each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
613  */
614 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC 0x6f28
615 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0	0x6fa0
616 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1	0x6f60
617 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA	0x6fa8
618 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL 0x6f71
619 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA	0x6f68
620 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_THERMAL 0x6f79
621 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0 0x6ffc
622 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1 0x6ffd
623 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0 0x6faa
624 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1 0x6fab
625 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2 0x6fac
626 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3 0x6fad
627 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 0x6f6a
628 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1 0x6f6b
629 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2 0x6f6c
630 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3 0x6f6d
631 #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0 0x6faf
632 
633 static const struct pci_id_descr pci_dev_descr_broadwell[] = {
634 	/* first item must be the HA */
635 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0, 0)		},
636 
637 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0, 0)	},
638 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1, 0)	},
639 
640 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1, 1)		},
641 
642 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA, 0)	},
643 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL, 0)	},
644 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0, 0)	},
645 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1, 0)	},
646 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2, 1)	},
647 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3, 1)	},
648 
649 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0, 1)	},
650 
651 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA, 1)	},
652 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_THERMAL, 1)	},
653 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0, 1)	},
654 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1, 1)	},
655 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2, 1)	},
656 	{ PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3, 1)	},
657 };
658 
659 static const struct pci_id_table pci_dev_descr_broadwell_table[] = {
660 	PCI_ID_TABLE_ENTRY(pci_dev_descr_broadwell),
661 	{0,}			/* 0 terminated list. */
662 };
663 
664 /*
665  *	pci_device_id	table for which devices we are looking for
666  */
667 static const struct pci_device_id sbridge_pci_tbl[] = {
668 	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0)},
669 	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA)},
670 	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0)},
671 	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0)},
672 	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0)},
673 	{0,}			/* 0 terminated list. */
674 };
675 
676 
677 /****************************************************************************
678 			Ancillary status routines
679  ****************************************************************************/
680 
681 static inline int numrank(enum type type, u32 mtr)
682 {
683 	int ranks = (1 << RANK_CNT_BITS(mtr));
684 	int max = 4;
685 
686 	if (type == HASWELL || type == BROADWELL || type == KNIGHTS_LANDING)
687 		max = 8;
688 
689 	if (ranks > max) {
690 		edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n",
691 			 ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr);
692 		return -EINVAL;
693 	}
694 
695 	return ranks;
696 }
697 
698 static inline int numrow(u32 mtr)
699 {
700 	int rows = (RANK_WIDTH_BITS(mtr) + 12);
701 
702 	if (rows < 13 || rows > 18) {
703 		edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n",
704 			 rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr);
705 		return -EINVAL;
706 	}
707 
708 	return 1 << rows;
709 }
710 
711 static inline int numcol(u32 mtr)
712 {
713 	int cols = (COL_WIDTH_BITS(mtr) + 10);
714 
715 	if (cols > 12) {
716 		edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n",
717 			 cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr);
718 		return -EINVAL;
719 	}
720 
721 	return 1 << cols;
722 }
723 
724 static struct sbridge_dev *get_sbridge_dev(u8 bus, int multi_bus)
725 {
726 	struct sbridge_dev *sbridge_dev;
727 
728 	/*
729 	 * If we have devices scattered across several busses that pertain
730 	 * to the same memory controller, we'll lump them all together.
731 	 */
732 	if (multi_bus) {
733 		return list_first_entry_or_null(&sbridge_edac_list,
734 				struct sbridge_dev, list);
735 	}
736 
737 	list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
738 		if (sbridge_dev->bus == bus)
739 			return sbridge_dev;
740 	}
741 
742 	return NULL;
743 }
744 
745 static struct sbridge_dev *alloc_sbridge_dev(u8 bus,
746 					   const struct pci_id_table *table)
747 {
748 	struct sbridge_dev *sbridge_dev;
749 
750 	sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL);
751 	if (!sbridge_dev)
752 		return NULL;
753 
754 	sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs,
755 				   GFP_KERNEL);
756 	if (!sbridge_dev->pdev) {
757 		kfree(sbridge_dev);
758 		return NULL;
759 	}
760 
761 	sbridge_dev->bus = bus;
762 	sbridge_dev->n_devs = table->n_devs;
763 	list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
764 
765 	return sbridge_dev;
766 }
767 
768 static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)
769 {
770 	list_del(&sbridge_dev->list);
771 	kfree(sbridge_dev->pdev);
772 	kfree(sbridge_dev);
773 }
774 
775 static u64 sbridge_get_tolm(struct sbridge_pvt *pvt)
776 {
777 	u32 reg;
778 
779 	/* Address range is 32:28 */
780 	pci_read_config_dword(pvt->pci_sad1, TOLM, &reg);
781 	return GET_TOLM(reg);
782 }
783 
784 static u64 sbridge_get_tohm(struct sbridge_pvt *pvt)
785 {
786 	u32 reg;
787 
788 	pci_read_config_dword(pvt->pci_sad1, TOHM, &reg);
789 	return GET_TOHM(reg);
790 }
791 
792 static u64 ibridge_get_tolm(struct sbridge_pvt *pvt)
793 {
794 	u32 reg;
795 
796 	pci_read_config_dword(pvt->pci_br1, TOLM, &reg);
797 
798 	return GET_TOLM(reg);
799 }
800 
801 static u64 ibridge_get_tohm(struct sbridge_pvt *pvt)
802 {
803 	u32 reg;
804 
805 	pci_read_config_dword(pvt->pci_br1, TOHM, &reg);
806 
807 	return GET_TOHM(reg);
808 }
809 
810 static u64 rir_limit(u32 reg)
811 {
812 	return ((u64)GET_BITFIELD(reg,  1, 10) << 29) | 0x1fffffff;
813 }
814 
815 static u64 sad_limit(u32 reg)
816 {
817 	return (GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff;
818 }
819 
820 static u32 interleave_mode(u32 reg)
821 {
822 	return GET_BITFIELD(reg, 1, 1);
823 }
824 
825 char *show_interleave_mode(u32 reg)
826 {
827 	return interleave_mode(reg) ? "8:6" : "[8:6]XOR[18:16]";
828 }
829 
830 static u32 dram_attr(u32 reg)
831 {
832 	return GET_BITFIELD(reg, 2, 3);
833 }
834 
835 static u64 knl_sad_limit(u32 reg)
836 {
837 	return (GET_BITFIELD(reg, 7, 26) << 26) | 0x3ffffff;
838 }
839 
840 static u32 knl_interleave_mode(u32 reg)
841 {
842 	return GET_BITFIELD(reg, 1, 2);
843 }
844 
845 static char *knl_show_interleave_mode(u32 reg)
846 {
847 	char *s;
848 
849 	switch (knl_interleave_mode(reg)) {
850 	case 0:
851 		s = "use address bits [8:6]";
852 		break;
853 	case 1:
854 		s = "use address bits [10:8]";
855 		break;
856 	case 2:
857 		s = "use address bits [14:12]";
858 		break;
859 	case 3:
860 		s = "use address bits [32:30]";
861 		break;
862 	default:
863 		WARN_ON(1);
864 		break;
865 	}
866 
867 	return s;
868 }
869 
870 static u32 dram_attr_knl(u32 reg)
871 {
872 	return GET_BITFIELD(reg, 3, 4);
873 }
874 
875 
876 static enum mem_type get_memory_type(struct sbridge_pvt *pvt)
877 {
878 	u32 reg;
879 	enum mem_type mtype;
880 
881 	if (pvt->pci_ddrio) {
882 		pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr,
883 				      &reg);
884 		if (GET_BITFIELD(reg, 11, 11))
885 			/* FIXME: Can also be LRDIMM */
886 			mtype = MEM_RDDR3;
887 		else
888 			mtype = MEM_DDR3;
889 	} else
890 		mtype = MEM_UNKNOWN;
891 
892 	return mtype;
893 }
894 
895 static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt)
896 {
897 	u32 reg;
898 	bool registered = false;
899 	enum mem_type mtype = MEM_UNKNOWN;
900 
901 	if (!pvt->pci_ddrio)
902 		goto out;
903 
904 	pci_read_config_dword(pvt->pci_ddrio,
905 			      HASWELL_DDRCRCLKCONTROLS, &reg);
906 	/* Is_Rdimm */
907 	if (GET_BITFIELD(reg, 16, 16))
908 		registered = true;
909 
910 	pci_read_config_dword(pvt->pci_ta, MCMTR, &reg);
911 	if (GET_BITFIELD(reg, 14, 14)) {
912 		if (registered)
913 			mtype = MEM_RDDR4;
914 		else
915 			mtype = MEM_DDR4;
916 	} else {
917 		if (registered)
918 			mtype = MEM_RDDR3;
919 		else
920 			mtype = MEM_DDR3;
921 	}
922 
923 out:
924 	return mtype;
925 }
926 
927 static enum dev_type knl_get_width(struct sbridge_pvt *pvt, u32 mtr)
928 {
929 	/* for KNL value is fixed */
930 	return DEV_X16;
931 }
932 
933 static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
934 {
935 	/* there's no way to figure out */
936 	return DEV_UNKNOWN;
937 }
938 
939 static enum dev_type __ibridge_get_width(u32 mtr)
940 {
941 	enum dev_type type;
942 
943 	switch (mtr) {
944 	case 3:
945 		type = DEV_UNKNOWN;
946 		break;
947 	case 2:
948 		type = DEV_X16;
949 		break;
950 	case 1:
951 		type = DEV_X8;
952 		break;
953 	case 0:
954 		type = DEV_X4;
955 		break;
956 	}
957 
958 	return type;
959 }
960 
961 static enum dev_type ibridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
962 {
963 	/*
964 	 * ddr3_width on the documentation but also valid for DDR4 on
965 	 * Haswell
966 	 */
967 	return __ibridge_get_width(GET_BITFIELD(mtr, 7, 8));
968 }
969 
970 static enum dev_type broadwell_get_width(struct sbridge_pvt *pvt, u32 mtr)
971 {
972 	/* ddr3_width on the documentation but also valid for DDR4 */
973 	return __ibridge_get_width(GET_BITFIELD(mtr, 8, 9));
974 }
975 
976 static enum mem_type knl_get_memory_type(struct sbridge_pvt *pvt)
977 {
978 	/* DDR4 RDIMMS and LRDIMMS are supported */
979 	return MEM_RDDR4;
980 }
981 
982 static u8 get_node_id(struct sbridge_pvt *pvt)
983 {
984 	u32 reg;
985 	pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, &reg);
986 	return GET_BITFIELD(reg, 0, 2);
987 }
988 
989 static u8 haswell_get_node_id(struct sbridge_pvt *pvt)
990 {
991 	u32 reg;
992 
993 	pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, &reg);
994 	return GET_BITFIELD(reg, 0, 3);
995 }
996 
997 static u8 knl_get_node_id(struct sbridge_pvt *pvt)
998 {
999 	u32 reg;
1000 
1001 	pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, &reg);
1002 	return GET_BITFIELD(reg, 0, 2);
1003 }
1004 
1005 
1006 static u64 haswell_get_tolm(struct sbridge_pvt *pvt)
1007 {
1008 	u32 reg;
1009 
1010 	pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, &reg);
1011 	return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
1012 }
1013 
1014 static u64 haswell_get_tohm(struct sbridge_pvt *pvt)
1015 {
1016 	u64 rc;
1017 	u32 reg;
1018 
1019 	pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, &reg);
1020 	rc = GET_BITFIELD(reg, 26, 31);
1021 	pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, &reg);
1022 	rc = ((reg << 6) | rc) << 26;
1023 
1024 	return rc | 0x1ffffff;
1025 }
1026 
1027 static u64 knl_get_tolm(struct sbridge_pvt *pvt)
1028 {
1029 	u32 reg;
1030 
1031 	pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOLM, &reg);
1032 	return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
1033 }
1034 
1035 static u64 knl_get_tohm(struct sbridge_pvt *pvt)
1036 {
1037 	u64 rc;
1038 	u32 reg_lo, reg_hi;
1039 
1040 	pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_0, &reg_lo);
1041 	pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_1, &reg_hi);
1042 	rc = ((u64)reg_hi << 32) | reg_lo;
1043 	return rc | 0x3ffffff;
1044 }
1045 
1046 
1047 static u64 haswell_rir_limit(u32 reg)
1048 {
1049 	return (((u64)GET_BITFIELD(reg,  1, 11) + 1) << 29) - 1;
1050 }
1051 
1052 static inline u8 sad_pkg_socket(u8 pkg)
1053 {
1054 	/* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */
1055 	return ((pkg >> 3) << 2) | (pkg & 0x3);
1056 }
1057 
1058 static inline u8 sad_pkg_ha(u8 pkg)
1059 {
1060 	return (pkg >> 2) & 0x1;
1061 }
1062 
1063 /****************************************************************************
1064 			Memory check routines
1065  ****************************************************************************/
1066 static struct pci_dev *get_pdev_same_bus(u8 bus, u32 id)
1067 {
1068 	struct pci_dev *pdev = NULL;
1069 
1070 	do {
1071 		pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, pdev);
1072 		if (pdev && pdev->bus->number == bus)
1073 			break;
1074 	} while (pdev);
1075 
1076 	return pdev;
1077 }
1078 
1079 /**
1080  * check_if_ecc_is_active() - Checks if ECC is active
1081  * @bus:	Device bus
1082  * @type:	Memory controller type
1083  * returns: 0 in case ECC is active, -ENODEV if it can't be determined or
1084  *	    disabled
1085  */
1086 static int check_if_ecc_is_active(const u8 bus, enum type type)
1087 {
1088 	struct pci_dev *pdev = NULL;
1089 	u32 mcmtr, id;
1090 
1091 	switch (type) {
1092 	case IVY_BRIDGE:
1093 		id = PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA;
1094 		break;
1095 	case HASWELL:
1096 		id = PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA;
1097 		break;
1098 	case SANDY_BRIDGE:
1099 		id = PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA;
1100 		break;
1101 	case BROADWELL:
1102 		id = PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA;
1103 		break;
1104 	case KNIGHTS_LANDING:
1105 		/*
1106 		 * KNL doesn't group things by bus the same way
1107 		 * SB/IB/Haswell does.
1108 		 */
1109 		id = PCI_DEVICE_ID_INTEL_KNL_IMC_TA;
1110 		break;
1111 	default:
1112 		return -ENODEV;
1113 	}
1114 
1115 	if (type != KNIGHTS_LANDING)
1116 		pdev = get_pdev_same_bus(bus, id);
1117 	else
1118 		pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, 0);
1119 
1120 	if (!pdev) {
1121 		sbridge_printk(KERN_ERR, "Couldn't find PCI device "
1122 					"%04x:%04x! on bus %02d\n",
1123 					PCI_VENDOR_ID_INTEL, id, bus);
1124 		return -ENODEV;
1125 	}
1126 
1127 	pci_read_config_dword(pdev,
1128 			type == KNIGHTS_LANDING ? KNL_MCMTR : MCMTR, &mcmtr);
1129 	if (!IS_ECC_ENABLED(mcmtr)) {
1130 		sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n");
1131 		return -ENODEV;
1132 	}
1133 	return 0;
1134 }
1135 
1136 /* Low bits of TAD limit, and some metadata. */
1137 static const u32 knl_tad_dram_limit_lo[] = {
1138 	0x400, 0x500, 0x600, 0x700,
1139 	0x800, 0x900, 0xa00, 0xb00,
1140 };
1141 
1142 /* Low bits of TAD offset. */
1143 static const u32 knl_tad_dram_offset_lo[] = {
1144 	0x404, 0x504, 0x604, 0x704,
1145 	0x804, 0x904, 0xa04, 0xb04,
1146 };
1147 
1148 /* High 16 bits of TAD limit and offset. */
1149 static const u32 knl_tad_dram_hi[] = {
1150 	0x408, 0x508, 0x608, 0x708,
1151 	0x808, 0x908, 0xa08, 0xb08,
1152 };
1153 
1154 /* Number of ways a tad entry is interleaved. */
1155 static const u32 knl_tad_ways[] = {
1156 	8, 6, 4, 3, 2, 1,
1157 };
1158 
1159 /*
1160  * Retrieve the n'th Target Address Decode table entry
1161  * from the memory controller's TAD table.
1162  *
1163  * @pvt:	driver private data
1164  * @entry:	which entry you want to retrieve
1165  * @mc:		which memory controller (0 or 1)
1166  * @offset:	output tad range offset
1167  * @limit:	output address of first byte above tad range
1168  * @ways:	output number of interleave ways
1169  *
1170  * The offset value has curious semantics.  It's a sort of running total
1171  * of the sizes of all the memory regions that aren't mapped in this
1172  * tad table.
1173  */
1174 static int knl_get_tad(const struct sbridge_pvt *pvt,
1175 		const int entry,
1176 		const int mc,
1177 		u64 *offset,
1178 		u64 *limit,
1179 		int *ways)
1180 {
1181 	u32 reg_limit_lo, reg_offset_lo, reg_hi;
1182 	struct pci_dev *pci_mc;
1183 	int way_id;
1184 
1185 	switch (mc) {
1186 	case 0:
1187 		pci_mc = pvt->knl.pci_mc0;
1188 		break;
1189 	case 1:
1190 		pci_mc = pvt->knl.pci_mc1;
1191 		break;
1192 	default:
1193 		WARN_ON(1);
1194 		return -EINVAL;
1195 	}
1196 
1197 	pci_read_config_dword(pci_mc,
1198 			knl_tad_dram_limit_lo[entry], &reg_limit_lo);
1199 	pci_read_config_dword(pci_mc,
1200 			knl_tad_dram_offset_lo[entry], &reg_offset_lo);
1201 	pci_read_config_dword(pci_mc,
1202 			knl_tad_dram_hi[entry], &reg_hi);
1203 
1204 	/* Is this TAD entry enabled? */
1205 	if (!GET_BITFIELD(reg_limit_lo, 0, 0))
1206 		return -ENODEV;
1207 
1208 	way_id = GET_BITFIELD(reg_limit_lo, 3, 5);
1209 
1210 	if (way_id < ARRAY_SIZE(knl_tad_ways)) {
1211 		*ways = knl_tad_ways[way_id];
1212 	} else {
1213 		*ways = 0;
1214 		sbridge_printk(KERN_ERR,
1215 				"Unexpected value %d in mc_tad_limit_lo wayness field\n",
1216 				way_id);
1217 		return -ENODEV;
1218 	}
1219 
1220 	/*
1221 	 * The least significant 6 bits of base and limit are truncated.
1222 	 * For limit, we fill the missing bits with 1s.
1223 	 */
1224 	*offset = ((u64) GET_BITFIELD(reg_offset_lo, 6, 31) << 6) |
1225 				((u64) GET_BITFIELD(reg_hi, 0,  15) << 32);
1226 	*limit = ((u64) GET_BITFIELD(reg_limit_lo,  6, 31) << 6) | 63 |
1227 				((u64) GET_BITFIELD(reg_hi, 16, 31) << 32);
1228 
1229 	return 0;
1230 }
1231 
1232 /* Determine which memory controller is responsible for a given channel. */
1233 static int knl_channel_mc(int channel)
1234 {
1235 	WARN_ON(channel < 0 || channel >= 6);
1236 
1237 	return channel < 3 ? 1 : 0;
1238 }
1239 
1240 /*
1241  * Get the Nth entry from EDC_ROUTE_TABLE register.
1242  * (This is the per-tile mapping of logical interleave targets to
1243  *  physical EDC modules.)
1244  *
1245  * entry 0: 0:2
1246  *       1: 3:5
1247  *       2: 6:8
1248  *       3: 9:11
1249  *       4: 12:14
1250  *       5: 15:17
1251  *       6: 18:20
1252  *       7: 21:23
1253  * reserved: 24:31
1254  */
1255 static u32 knl_get_edc_route(int entry, u32 reg)
1256 {
1257 	WARN_ON(entry >= KNL_MAX_EDCS);
1258 	return GET_BITFIELD(reg, entry*3, (entry*3)+2);
1259 }
1260 
1261 /*
1262  * Get the Nth entry from MC_ROUTE_TABLE register.
1263  * (This is the per-tile mapping of logical interleave targets to
1264  *  physical DRAM channels modules.)
1265  *
1266  * entry 0: mc 0:2   channel 18:19
1267  *       1: mc 3:5   channel 20:21
1268  *       2: mc 6:8   channel 22:23
1269  *       3: mc 9:11  channel 24:25
1270  *       4: mc 12:14 channel 26:27
1271  *       5: mc 15:17 channel 28:29
1272  * reserved: 30:31
1273  *
1274  * Though we have 3 bits to identify the MC, we should only see
1275  * the values 0 or 1.
1276  */
1277 
1278 static u32 knl_get_mc_route(int entry, u32 reg)
1279 {
1280 	int mc, chan;
1281 
1282 	WARN_ON(entry >= KNL_MAX_CHANNELS);
1283 
1284 	mc = GET_BITFIELD(reg, entry*3, (entry*3)+2);
1285 	chan = GET_BITFIELD(reg, (entry*2) + 18, (entry*2) + 18 + 1);
1286 
1287 	return knl_channel_remap(mc*3 + chan);
1288 }
1289 
1290 /*
1291  * Render the EDC_ROUTE register in human-readable form.
1292  * Output string s should be at least KNL_MAX_EDCS*2 bytes.
1293  */
1294 static void knl_show_edc_route(u32 reg, char *s)
1295 {
1296 	int i;
1297 
1298 	for (i = 0; i < KNL_MAX_EDCS; i++) {
1299 		s[i*2] = knl_get_edc_route(i, reg) + '0';
1300 		s[i*2+1] = '-';
1301 	}
1302 
1303 	s[KNL_MAX_EDCS*2 - 1] = '\0';
1304 }
1305 
1306 /*
1307  * Render the MC_ROUTE register in human-readable form.
1308  * Output string s should be at least KNL_MAX_CHANNELS*2 bytes.
1309  */
1310 static void knl_show_mc_route(u32 reg, char *s)
1311 {
1312 	int i;
1313 
1314 	for (i = 0; i < KNL_MAX_CHANNELS; i++) {
1315 		s[i*2] = knl_get_mc_route(i, reg) + '0';
1316 		s[i*2+1] = '-';
1317 	}
1318 
1319 	s[KNL_MAX_CHANNELS*2 - 1] = '\0';
1320 }
1321 
1322 #define KNL_EDC_ROUTE 0xb8
1323 #define KNL_MC_ROUTE 0xb4
1324 
1325 /* Is this dram rule backed by regular DRAM in flat mode? */
1326 #define KNL_EDRAM(reg) GET_BITFIELD(reg, 29, 29)
1327 
1328 /* Is this dram rule cached? */
1329 #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28)
1330 
1331 /* Is this rule backed by edc ? */
1332 #define KNL_EDRAM_ONLY(reg) GET_BITFIELD(reg, 29, 29)
1333 
1334 /* Is this rule backed by DRAM, cacheable in EDRAM? */
1335 #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28)
1336 
1337 /* Is this rule mod3? */
1338 #define KNL_MOD3(reg) GET_BITFIELD(reg, 27, 27)
1339 
1340 /*
1341  * Figure out how big our RAM modules are.
1342  *
1343  * The DIMMMTR register in KNL doesn't tell us the size of the DIMMs, so we
1344  * have to figure this out from the SAD rules, interleave lists, route tables,
1345  * and TAD rules.
1346  *
1347  * SAD rules can have holes in them (e.g. the 3G-4G hole), so we have to
1348  * inspect the TAD rules to figure out how large the SAD regions really are.
1349  *
1350  * When we know the real size of a SAD region and how many ways it's
1351  * interleaved, we know the individual contribution of each channel to
1352  * TAD is size/ways.
1353  *
1354  * Finally, we have to check whether each channel participates in each SAD
1355  * region.
1356  *
1357  * Fortunately, KNL only supports one DIMM per channel, so once we know how
1358  * much memory the channel uses, we know the DIMM is at least that large.
1359  * (The BIOS might possibly choose not to map all available memory, in which
1360  * case we will underreport the size of the DIMM.)
1361  *
1362  * In theory, we could try to determine the EDC sizes as well, but that would
1363  * only work in flat mode, not in cache mode.
1364  *
1365  * @mc_sizes: Output sizes of channels (must have space for KNL_MAX_CHANNELS
1366  *            elements)
1367  */
1368 static int knl_get_dimm_capacity(struct sbridge_pvt *pvt, u64 *mc_sizes)
1369 {
1370 	u64 sad_base, sad_size, sad_limit = 0;
1371 	u64 tad_base, tad_size, tad_limit, tad_deadspace, tad_livespace;
1372 	int sad_rule = 0;
1373 	int tad_rule = 0;
1374 	int intrlv_ways, tad_ways;
1375 	u32 first_pkg, pkg;
1376 	int i;
1377 	u64 sad_actual_size[2]; /* sad size accounting for holes, per mc */
1378 	u32 dram_rule, interleave_reg;
1379 	u32 mc_route_reg[KNL_MAX_CHAS];
1380 	u32 edc_route_reg[KNL_MAX_CHAS];
1381 	int edram_only;
1382 	char edc_route_string[KNL_MAX_EDCS*2];
1383 	char mc_route_string[KNL_MAX_CHANNELS*2];
1384 	int cur_reg_start;
1385 	int mc;
1386 	int channel;
1387 	int way;
1388 	int participants[KNL_MAX_CHANNELS];
1389 	int participant_count = 0;
1390 
1391 	for (i = 0; i < KNL_MAX_CHANNELS; i++)
1392 		mc_sizes[i] = 0;
1393 
1394 	/* Read the EDC route table in each CHA. */
1395 	cur_reg_start = 0;
1396 	for (i = 0; i < KNL_MAX_CHAS; i++) {
1397 		pci_read_config_dword(pvt->knl.pci_cha[i],
1398 				KNL_EDC_ROUTE, &edc_route_reg[i]);
1399 
1400 		if (i > 0 && edc_route_reg[i] != edc_route_reg[i-1]) {
1401 			knl_show_edc_route(edc_route_reg[i-1],
1402 					edc_route_string);
1403 			if (cur_reg_start == i-1)
1404 				edac_dbg(0, "edc route table for CHA %d: %s\n",
1405 					cur_reg_start, edc_route_string);
1406 			else
1407 				edac_dbg(0, "edc route table for CHA %d-%d: %s\n",
1408 					cur_reg_start, i-1, edc_route_string);
1409 			cur_reg_start = i;
1410 		}
1411 	}
1412 	knl_show_edc_route(edc_route_reg[i-1], edc_route_string);
1413 	if (cur_reg_start == i-1)
1414 		edac_dbg(0, "edc route table for CHA %d: %s\n",
1415 			cur_reg_start, edc_route_string);
1416 	else
1417 		edac_dbg(0, "edc route table for CHA %d-%d: %s\n",
1418 			cur_reg_start, i-1, edc_route_string);
1419 
1420 	/* Read the MC route table in each CHA. */
1421 	cur_reg_start = 0;
1422 	for (i = 0; i < KNL_MAX_CHAS; i++) {
1423 		pci_read_config_dword(pvt->knl.pci_cha[i],
1424 			KNL_MC_ROUTE, &mc_route_reg[i]);
1425 
1426 		if (i > 0 && mc_route_reg[i] != mc_route_reg[i-1]) {
1427 			knl_show_mc_route(mc_route_reg[i-1], mc_route_string);
1428 			if (cur_reg_start == i-1)
1429 				edac_dbg(0, "mc route table for CHA %d: %s\n",
1430 					cur_reg_start, mc_route_string);
1431 			else
1432 				edac_dbg(0, "mc route table for CHA %d-%d: %s\n",
1433 					cur_reg_start, i-1, mc_route_string);
1434 			cur_reg_start = i;
1435 		}
1436 	}
1437 	knl_show_mc_route(mc_route_reg[i-1], mc_route_string);
1438 	if (cur_reg_start == i-1)
1439 		edac_dbg(0, "mc route table for CHA %d: %s\n",
1440 			cur_reg_start, mc_route_string);
1441 	else
1442 		edac_dbg(0, "mc route table for CHA %d-%d: %s\n",
1443 			cur_reg_start, i-1, mc_route_string);
1444 
1445 	/* Process DRAM rules */
1446 	for (sad_rule = 0; sad_rule < pvt->info.max_sad; sad_rule++) {
1447 		/* previous limit becomes the new base */
1448 		sad_base = sad_limit;
1449 
1450 		pci_read_config_dword(pvt->pci_sad0,
1451 			pvt->info.dram_rule[sad_rule], &dram_rule);
1452 
1453 		if (!DRAM_RULE_ENABLE(dram_rule))
1454 			break;
1455 
1456 		edram_only = KNL_EDRAM_ONLY(dram_rule);
1457 
1458 		sad_limit = pvt->info.sad_limit(dram_rule)+1;
1459 		sad_size = sad_limit - sad_base;
1460 
1461 		pci_read_config_dword(pvt->pci_sad0,
1462 			pvt->info.interleave_list[sad_rule], &interleave_reg);
1463 
1464 		/*
1465 		 * Find out how many ways this dram rule is interleaved.
1466 		 * We stop when we see the first channel again.
1467 		 */
1468 		first_pkg = sad_pkg(pvt->info.interleave_pkg,
1469 						interleave_reg, 0);
1470 		for (intrlv_ways = 1; intrlv_ways < 8; intrlv_ways++) {
1471 			pkg = sad_pkg(pvt->info.interleave_pkg,
1472 						interleave_reg, intrlv_ways);
1473 
1474 			if ((pkg & 0x8) == 0) {
1475 				/*
1476 				 * 0 bit means memory is non-local,
1477 				 * which KNL doesn't support
1478 				 */
1479 				edac_dbg(0, "Unexpected interleave target %d\n",
1480 					pkg);
1481 				return -1;
1482 			}
1483 
1484 			if (pkg == first_pkg)
1485 				break;
1486 		}
1487 		if (KNL_MOD3(dram_rule))
1488 			intrlv_ways *= 3;
1489 
1490 		edac_dbg(3, "dram rule %d (base 0x%llx, limit 0x%llx), %d way interleave%s\n",
1491 			sad_rule,
1492 			sad_base,
1493 			sad_limit,
1494 			intrlv_ways,
1495 			edram_only ? ", EDRAM" : "");
1496 
1497 		/*
1498 		 * Find out how big the SAD region really is by iterating
1499 		 * over TAD tables (SAD regions may contain holes).
1500 		 * Each memory controller might have a different TAD table, so
1501 		 * we have to look at both.
1502 		 *
1503 		 * Livespace is the memory that's mapped in this TAD table,
1504 		 * deadspace is the holes (this could be the MMIO hole, or it
1505 		 * could be memory that's mapped by the other TAD table but
1506 		 * not this one).
1507 		 */
1508 		for (mc = 0; mc < 2; mc++) {
1509 			sad_actual_size[mc] = 0;
1510 			tad_livespace = 0;
1511 			for (tad_rule = 0;
1512 					tad_rule < ARRAY_SIZE(
1513 						knl_tad_dram_limit_lo);
1514 					tad_rule++) {
1515 				if (knl_get_tad(pvt,
1516 						tad_rule,
1517 						mc,
1518 						&tad_deadspace,
1519 						&tad_limit,
1520 						&tad_ways))
1521 					break;
1522 
1523 				tad_size = (tad_limit+1) -
1524 					(tad_livespace + tad_deadspace);
1525 				tad_livespace += tad_size;
1526 				tad_base = (tad_limit+1) - tad_size;
1527 
1528 				if (tad_base < sad_base) {
1529 					if (tad_limit > sad_base)
1530 						edac_dbg(0, "TAD region overlaps lower SAD boundary -- TAD tables may be configured incorrectly.\n");
1531 				} else if (tad_base < sad_limit) {
1532 					if (tad_limit+1 > sad_limit) {
1533 						edac_dbg(0, "TAD region overlaps upper SAD boundary -- TAD tables may be configured incorrectly.\n");
1534 					} else {
1535 						/* TAD region is completely inside SAD region */
1536 						edac_dbg(3, "TAD region %d 0x%llx - 0x%llx (%lld bytes) table%d\n",
1537 							tad_rule, tad_base,
1538 							tad_limit, tad_size,
1539 							mc);
1540 						sad_actual_size[mc] += tad_size;
1541 					}
1542 				}
1543 				tad_base = tad_limit+1;
1544 			}
1545 		}
1546 
1547 		for (mc = 0; mc < 2; mc++) {
1548 			edac_dbg(3, " total TAD DRAM footprint in table%d : 0x%llx (%lld bytes)\n",
1549 				mc, sad_actual_size[mc], sad_actual_size[mc]);
1550 		}
1551 
1552 		/* Ignore EDRAM rule */
1553 		if (edram_only)
1554 			continue;
1555 
1556 		/* Figure out which channels participate in interleave. */
1557 		for (channel = 0; channel < KNL_MAX_CHANNELS; channel++)
1558 			participants[channel] = 0;
1559 
1560 		/* For each channel, does at least one CHA have
1561 		 * this channel mapped to the given target?
1562 		 */
1563 		for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) {
1564 			for (way = 0; way < intrlv_ways; way++) {
1565 				int target;
1566 				int cha;
1567 
1568 				if (KNL_MOD3(dram_rule))
1569 					target = way;
1570 				else
1571 					target = 0x7 & sad_pkg(
1572 				pvt->info.interleave_pkg, interleave_reg, way);
1573 
1574 				for (cha = 0; cha < KNL_MAX_CHAS; cha++) {
1575 					if (knl_get_mc_route(target,
1576 						mc_route_reg[cha]) == channel
1577 						&& !participants[channel]) {
1578 						participant_count++;
1579 						participants[channel] = 1;
1580 						break;
1581 					}
1582 				}
1583 			}
1584 		}
1585 
1586 		if (participant_count != intrlv_ways)
1587 			edac_dbg(0, "participant_count (%d) != interleave_ways (%d): DIMM size may be incorrect\n",
1588 				participant_count, intrlv_ways);
1589 
1590 		for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) {
1591 			mc = knl_channel_mc(channel);
1592 			if (participants[channel]) {
1593 				edac_dbg(4, "mc channel %d contributes %lld bytes via sad entry %d\n",
1594 					channel,
1595 					sad_actual_size[mc]/intrlv_ways,
1596 					sad_rule);
1597 				mc_sizes[channel] +=
1598 					sad_actual_size[mc]/intrlv_ways;
1599 			}
1600 		}
1601 	}
1602 
1603 	return 0;
1604 }
1605 
1606 static int get_dimm_config(struct mem_ctl_info *mci)
1607 {
1608 	struct sbridge_pvt *pvt = mci->pvt_info;
1609 	struct dimm_info *dimm;
1610 	unsigned i, j, banks, ranks, rows, cols, npages;
1611 	u64 size;
1612 	u32 reg;
1613 	enum edac_type mode;
1614 	enum mem_type mtype;
1615 	int channels = pvt->info.type == KNIGHTS_LANDING ?
1616 		KNL_MAX_CHANNELS : NUM_CHANNELS;
1617 	u64 knl_mc_sizes[KNL_MAX_CHANNELS];
1618 
1619 	if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL ||
1620 			pvt->info.type == KNIGHTS_LANDING)
1621 		pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, &reg);
1622 	else
1623 		pci_read_config_dword(pvt->pci_br0, SAD_TARGET, &reg);
1624 
1625 	if (pvt->info.type == KNIGHTS_LANDING)
1626 		pvt->sbridge_dev->source_id = SOURCE_ID_KNL(reg);
1627 	else
1628 		pvt->sbridge_dev->source_id = SOURCE_ID(reg);
1629 
1630 	pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt);
1631 	edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n",
1632 		 pvt->sbridge_dev->mc,
1633 		 pvt->sbridge_dev->node_id,
1634 		 pvt->sbridge_dev->source_id);
1635 
1636 	/* KNL doesn't support mirroring or lockstep,
1637 	 * and is always closed page
1638 	 */
1639 	if (pvt->info.type == KNIGHTS_LANDING) {
1640 		mode = EDAC_S4ECD4ED;
1641 		pvt->is_mirrored = false;
1642 
1643 		if (knl_get_dimm_capacity(pvt, knl_mc_sizes) != 0)
1644 			return -1;
1645 	} else {
1646 		pci_read_config_dword(pvt->pci_ras, RASENABLES, &reg);
1647 		if (IS_MIRROR_ENABLED(reg)) {
1648 			edac_dbg(0, "Memory mirror is enabled\n");
1649 			pvt->is_mirrored = true;
1650 		} else {
1651 			edac_dbg(0, "Memory mirror is disabled\n");
1652 			pvt->is_mirrored = false;
1653 		}
1654 
1655 		pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr);
1656 		if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
1657 			edac_dbg(0, "Lockstep is enabled\n");
1658 			mode = EDAC_S8ECD8ED;
1659 			pvt->is_lockstep = true;
1660 		} else {
1661 			edac_dbg(0, "Lockstep is disabled\n");
1662 			mode = EDAC_S4ECD4ED;
1663 			pvt->is_lockstep = false;
1664 		}
1665 		if (IS_CLOSE_PG(pvt->info.mcmtr)) {
1666 			edac_dbg(0, "address map is on closed page mode\n");
1667 			pvt->is_close_pg = true;
1668 		} else {
1669 			edac_dbg(0, "address map is on open page mode\n");
1670 			pvt->is_close_pg = false;
1671 		}
1672 	}
1673 
1674 	mtype = pvt->info.get_memory_type(pvt);
1675 	if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4)
1676 		edac_dbg(0, "Memory is registered\n");
1677 	else if (mtype == MEM_UNKNOWN)
1678 		edac_dbg(0, "Cannot determine memory type\n");
1679 	else
1680 		edac_dbg(0, "Memory is unregistered\n");
1681 
1682 	if (mtype == MEM_DDR4 || mtype == MEM_RDDR4)
1683 		banks = 16;
1684 	else
1685 		banks = 8;
1686 
1687 	for (i = 0; i < channels; i++) {
1688 		u32 mtr;
1689 
1690 		int max_dimms_per_channel;
1691 
1692 		if (pvt->info.type == KNIGHTS_LANDING) {
1693 			max_dimms_per_channel = 1;
1694 			if (!pvt->knl.pci_channel[i])
1695 				continue;
1696 		} else {
1697 			max_dimms_per_channel = ARRAY_SIZE(mtr_regs);
1698 			if (!pvt->pci_tad[i])
1699 				continue;
1700 		}
1701 
1702 		for (j = 0; j < max_dimms_per_channel; j++) {
1703 			dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
1704 				       i, j, 0);
1705 			if (pvt->info.type == KNIGHTS_LANDING) {
1706 				pci_read_config_dword(pvt->knl.pci_channel[i],
1707 					knl_mtr_reg, &mtr);
1708 			} else {
1709 				pci_read_config_dword(pvt->pci_tad[i],
1710 					mtr_regs[j], &mtr);
1711 			}
1712 			edac_dbg(4, "Channel #%d  MTR%d = %x\n", i, j, mtr);
1713 			if (IS_DIMM_PRESENT(mtr)) {
1714 				pvt->channel[i].dimms++;
1715 
1716 				ranks = numrank(pvt->info.type, mtr);
1717 
1718 				if (pvt->info.type == KNIGHTS_LANDING) {
1719 					/* For DDR4, this is fixed. */
1720 					cols = 1 << 10;
1721 					rows = knl_mc_sizes[i] /
1722 						((u64) cols * ranks * banks * 8);
1723 				} else {
1724 					rows = numrow(mtr);
1725 					cols = numcol(mtr);
1726 				}
1727 
1728 				size = ((u64)rows * cols * banks * ranks) >> (20 - 3);
1729 				npages = MiB_TO_PAGES(size);
1730 
1731 				edac_dbg(0, "mc#%d: ha %d channel %d, dimm %d, %lld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
1732 					 pvt->sbridge_dev->mc, i/4, i%4, j,
1733 					 size, npages,
1734 					 banks, ranks, rows, cols);
1735 
1736 				dimm->nr_pages = npages;
1737 				dimm->grain = 32;
1738 				dimm->dtype = pvt->info.get_width(pvt, mtr);
1739 				dimm->mtype = mtype;
1740 				dimm->edac_mode = mode;
1741 				snprintf(dimm->label, sizeof(dimm->label),
1742 					 "CPU_SrcID#%u_Ha#%u_Chan#%u_DIMM#%u",
1743 					 pvt->sbridge_dev->source_id, i/4, i%4, j);
1744 			}
1745 		}
1746 	}
1747 
1748 	return 0;
1749 }
1750 
1751 static void get_memory_layout(const struct mem_ctl_info *mci)
1752 {
1753 	struct sbridge_pvt *pvt = mci->pvt_info;
1754 	int i, j, k, n_sads, n_tads, sad_interl;
1755 	u32 reg;
1756 	u64 limit, prv = 0;
1757 	u64 tmp_mb;
1758 	u32 gb, mb;
1759 	u32 rir_way;
1760 
1761 	/*
1762 	 * Step 1) Get TOLM/TOHM ranges
1763 	 */
1764 
1765 	pvt->tolm = pvt->info.get_tolm(pvt);
1766 	tmp_mb = (1 + pvt->tolm) >> 20;
1767 
1768 	gb = div_u64_rem(tmp_mb, 1024, &mb);
1769 	edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n",
1770 		gb, (mb*1000)/1024, (u64)pvt->tolm);
1771 
1772 	/* Address range is already 45:25 */
1773 	pvt->tohm = pvt->info.get_tohm(pvt);
1774 	tmp_mb = (1 + pvt->tohm) >> 20;
1775 
1776 	gb = div_u64_rem(tmp_mb, 1024, &mb);
1777 	edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n",
1778 		gb, (mb*1000)/1024, (u64)pvt->tohm);
1779 
1780 	/*
1781 	 * Step 2) Get SAD range and SAD Interleave list
1782 	 * TAD registers contain the interleave wayness. However, it
1783 	 * seems simpler to just discover it indirectly, with the
1784 	 * algorithm bellow.
1785 	 */
1786 	prv = 0;
1787 	for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1788 		/* SAD_LIMIT Address range is 45:26 */
1789 		pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1790 				      &reg);
1791 		limit = pvt->info.sad_limit(reg);
1792 
1793 		if (!DRAM_RULE_ENABLE(reg))
1794 			continue;
1795 
1796 		if (limit <= prv)
1797 			break;
1798 
1799 		tmp_mb = (limit + 1) >> 20;
1800 		gb = div_u64_rem(tmp_mb, 1024, &mb);
1801 		edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n",
1802 			 n_sads,
1803 			 show_dram_attr(pvt->info.dram_attr(reg)),
1804 			 gb, (mb*1000)/1024,
1805 			 ((u64)tmp_mb) << 20L,
1806 			 pvt->info.show_interleave_mode(reg),
1807 			 reg);
1808 		prv = limit;
1809 
1810 		pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1811 				      &reg);
1812 		sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1813 		for (j = 0; j < 8; j++) {
1814 			u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j);
1815 			if (j > 0 && sad_interl == pkg)
1816 				break;
1817 
1818 			edac_dbg(0, "SAD#%d, interleave #%d: %d\n",
1819 				 n_sads, j, pkg);
1820 		}
1821 	}
1822 
1823 	if (pvt->info.type == KNIGHTS_LANDING)
1824 		return;
1825 
1826 	/*
1827 	 * Step 3) Get TAD range
1828 	 */
1829 	prv = 0;
1830 	for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
1831 		pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
1832 				      &reg);
1833 		limit = TAD_LIMIT(reg);
1834 		if (limit <= prv)
1835 			break;
1836 		tmp_mb = (limit + 1) >> 20;
1837 
1838 		gb = div_u64_rem(tmp_mb, 1024, &mb);
1839 		edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
1840 			 n_tads, gb, (mb*1000)/1024,
1841 			 ((u64)tmp_mb) << 20L,
1842 			 (u32)(1 << TAD_SOCK(reg)),
1843 			 (u32)TAD_CH(reg) + 1,
1844 			 (u32)TAD_TGT0(reg),
1845 			 (u32)TAD_TGT1(reg),
1846 			 (u32)TAD_TGT2(reg),
1847 			 (u32)TAD_TGT3(reg),
1848 			 reg);
1849 		prv = limit;
1850 	}
1851 
1852 	/*
1853 	 * Step 4) Get TAD offsets, per each channel
1854 	 */
1855 	for (i = 0; i < NUM_CHANNELS; i++) {
1856 		if (!pvt->channel[i].dimms)
1857 			continue;
1858 		for (j = 0; j < n_tads; j++) {
1859 			pci_read_config_dword(pvt->pci_tad[i],
1860 					      tad_ch_nilv_offset[j],
1861 					      &reg);
1862 			tmp_mb = TAD_OFFSET(reg) >> 20;
1863 			gb = div_u64_rem(tmp_mb, 1024, &mb);
1864 			edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
1865 				 i, j,
1866 				 gb, (mb*1000)/1024,
1867 				 ((u64)tmp_mb) << 20L,
1868 				 reg);
1869 		}
1870 	}
1871 
1872 	/*
1873 	 * Step 6) Get RIR Wayness/Limit, per each channel
1874 	 */
1875 	for (i = 0; i < NUM_CHANNELS; i++) {
1876 		if (!pvt->channel[i].dimms)
1877 			continue;
1878 		for (j = 0; j < MAX_RIR_RANGES; j++) {
1879 			pci_read_config_dword(pvt->pci_tad[i],
1880 					      rir_way_limit[j],
1881 					      &reg);
1882 
1883 			if (!IS_RIR_VALID(reg))
1884 				continue;
1885 
1886 			tmp_mb = pvt->info.rir_limit(reg) >> 20;
1887 			rir_way = 1 << RIR_WAY(reg);
1888 			gb = div_u64_rem(tmp_mb, 1024, &mb);
1889 			edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
1890 				 i, j,
1891 				 gb, (mb*1000)/1024,
1892 				 ((u64)tmp_mb) << 20L,
1893 				 rir_way,
1894 				 reg);
1895 
1896 			for (k = 0; k < rir_way; k++) {
1897 				pci_read_config_dword(pvt->pci_tad[i],
1898 						      rir_offset[j][k],
1899 						      &reg);
1900 				tmp_mb = RIR_OFFSET(reg) << 6;
1901 
1902 				gb = div_u64_rem(tmp_mb, 1024, &mb);
1903 				edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
1904 					 i, j, k,
1905 					 gb, (mb*1000)/1024,
1906 					 ((u64)tmp_mb) << 20L,
1907 					 (u32)RIR_RNK_TGT(reg),
1908 					 reg);
1909 			}
1910 		}
1911 	}
1912 }
1913 
1914 static struct mem_ctl_info *get_mci_for_node_id(u8 node_id)
1915 {
1916 	struct sbridge_dev *sbridge_dev;
1917 
1918 	list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
1919 		if (sbridge_dev->node_id == node_id)
1920 			return sbridge_dev->mci;
1921 	}
1922 	return NULL;
1923 }
1924 
1925 static int get_memory_error_data(struct mem_ctl_info *mci,
1926 				 u64 addr,
1927 				 u8 *socket, u8 *ha,
1928 				 long *channel_mask,
1929 				 u8 *rank,
1930 				 char **area_type, char *msg)
1931 {
1932 	struct mem_ctl_info	*new_mci;
1933 	struct sbridge_pvt *pvt = mci->pvt_info;
1934 	struct pci_dev		*pci_ha;
1935 	int			n_rir, n_sads, n_tads, sad_way, sck_xch;
1936 	int			sad_interl, idx, base_ch;
1937 	int			interleave_mode, shiftup = 0;
1938 	unsigned		sad_interleave[pvt->info.max_interleave];
1939 	u32			reg, dram_rule;
1940 	u8			ch_way, sck_way, pkg, sad_ha = 0, ch_add = 0;
1941 	u32			tad_offset;
1942 	u32			rir_way;
1943 	u32			mb, gb;
1944 	u64			ch_addr, offset, limit = 0, prv = 0;
1945 
1946 
1947 	/*
1948 	 * Step 0) Check if the address is at special memory ranges
1949 	 * The check bellow is probably enough to fill all cases where
1950 	 * the error is not inside a memory, except for the legacy
1951 	 * range (e. g. VGA addresses). It is unlikely, however, that the
1952 	 * memory controller would generate an error on that range.
1953 	 */
1954 	if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
1955 		sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr);
1956 		return -EINVAL;
1957 	}
1958 	if (addr >= (u64)pvt->tohm) {
1959 		sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr);
1960 		return -EINVAL;
1961 	}
1962 
1963 	/*
1964 	 * Step 1) Get socket
1965 	 */
1966 	for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1967 		pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
1968 				      &reg);
1969 
1970 		if (!DRAM_RULE_ENABLE(reg))
1971 			continue;
1972 
1973 		limit = pvt->info.sad_limit(reg);
1974 		if (limit <= prv) {
1975 			sprintf(msg, "Can't discover the memory socket");
1976 			return -EINVAL;
1977 		}
1978 		if  (addr <= limit)
1979 			break;
1980 		prv = limit;
1981 	}
1982 	if (n_sads == pvt->info.max_sad) {
1983 		sprintf(msg, "Can't discover the memory socket");
1984 		return -EINVAL;
1985 	}
1986 	dram_rule = reg;
1987 	*area_type = show_dram_attr(pvt->info.dram_attr(dram_rule));
1988 	interleave_mode = pvt->info.interleave_mode(dram_rule);
1989 
1990 	pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
1991 			      &reg);
1992 
1993 	if (pvt->info.type == SANDY_BRIDGE) {
1994 		sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1995 		for (sad_way = 0; sad_way < 8; sad_way++) {
1996 			u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way);
1997 			if (sad_way > 0 && sad_interl == pkg)
1998 				break;
1999 			sad_interleave[sad_way] = pkg;
2000 			edac_dbg(0, "SAD interleave #%d: %d\n",
2001 				 sad_way, sad_interleave[sad_way]);
2002 		}
2003 		edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
2004 			 pvt->sbridge_dev->mc,
2005 			 n_sads,
2006 			 addr,
2007 			 limit,
2008 			 sad_way + 7,
2009 			 !interleave_mode ? "" : "XOR[18:16]");
2010 		if (interleave_mode)
2011 			idx = ((addr >> 6) ^ (addr >> 16)) & 7;
2012 		else
2013 			idx = (addr >> 6) & 7;
2014 		switch (sad_way) {
2015 		case 1:
2016 			idx = 0;
2017 			break;
2018 		case 2:
2019 			idx = idx & 1;
2020 			break;
2021 		case 4:
2022 			idx = idx & 3;
2023 			break;
2024 		case 8:
2025 			break;
2026 		default:
2027 			sprintf(msg, "Can't discover socket interleave");
2028 			return -EINVAL;
2029 		}
2030 		*socket = sad_interleave[idx];
2031 		edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
2032 			 idx, sad_way, *socket);
2033 	} else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
2034 		int bits, a7mode = A7MODE(dram_rule);
2035 
2036 		if (a7mode) {
2037 			/* A7 mode swaps P9 with P6 */
2038 			bits = GET_BITFIELD(addr, 7, 8) << 1;
2039 			bits |= GET_BITFIELD(addr, 9, 9);
2040 		} else
2041 			bits = GET_BITFIELD(addr, 6, 8);
2042 
2043 		if (interleave_mode == 0) {
2044 			/* interleave mode will XOR {8,7,6} with {18,17,16} */
2045 			idx = GET_BITFIELD(addr, 16, 18);
2046 			idx ^= bits;
2047 		} else
2048 			idx = bits;
2049 
2050 		pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
2051 		*socket = sad_pkg_socket(pkg);
2052 		sad_ha = sad_pkg_ha(pkg);
2053 		if (sad_ha)
2054 			ch_add = 4;
2055 
2056 		if (a7mode) {
2057 			/* MCChanShiftUpEnable */
2058 			pci_read_config_dword(pvt->pci_ha0,
2059 					      HASWELL_HASYSDEFEATURE2, &reg);
2060 			shiftup = GET_BITFIELD(reg, 22, 22);
2061 		}
2062 
2063 		edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n",
2064 			 idx, *socket, sad_ha, shiftup);
2065 	} else {
2066 		/* Ivy Bridge's SAD mode doesn't support XOR interleave mode */
2067 		idx = (addr >> 6) & 7;
2068 		pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
2069 		*socket = sad_pkg_socket(pkg);
2070 		sad_ha = sad_pkg_ha(pkg);
2071 		if (sad_ha)
2072 			ch_add = 4;
2073 		edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n",
2074 			 idx, *socket, sad_ha);
2075 	}
2076 
2077 	*ha = sad_ha;
2078 
2079 	/*
2080 	 * Move to the proper node structure, in order to access the
2081 	 * right PCI registers
2082 	 */
2083 	new_mci = get_mci_for_node_id(*socket);
2084 	if (!new_mci) {
2085 		sprintf(msg, "Struct for socket #%u wasn't initialized",
2086 			*socket);
2087 		return -EINVAL;
2088 	}
2089 	mci = new_mci;
2090 	pvt = mci->pvt_info;
2091 
2092 	/*
2093 	 * Step 2) Get memory channel
2094 	 */
2095 	prv = 0;
2096 	if (pvt->info.type == SANDY_BRIDGE)
2097 		pci_ha = pvt->pci_ha0;
2098 	else {
2099 		if (sad_ha)
2100 			pci_ha = pvt->pci_ha1;
2101 		else
2102 			pci_ha = pvt->pci_ha0;
2103 	}
2104 	for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
2105 		pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], &reg);
2106 		limit = TAD_LIMIT(reg);
2107 		if (limit <= prv) {
2108 			sprintf(msg, "Can't discover the memory channel");
2109 			return -EINVAL;
2110 		}
2111 		if  (addr <= limit)
2112 			break;
2113 		prv = limit;
2114 	}
2115 	if (n_tads == MAX_TAD) {
2116 		sprintf(msg, "Can't discover the memory channel");
2117 		return -EINVAL;
2118 	}
2119 
2120 	ch_way = TAD_CH(reg) + 1;
2121 	sck_way = 1 << TAD_SOCK(reg);
2122 
2123 	if (ch_way == 3)
2124 		idx = addr >> 6;
2125 	else
2126 		idx = (addr >> (6 + sck_way + shiftup)) & 0x3;
2127 	idx = idx % ch_way;
2128 
2129 	/*
2130 	 * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ???
2131 	 */
2132 	switch (idx) {
2133 	case 0:
2134 		base_ch = TAD_TGT0(reg);
2135 		break;
2136 	case 1:
2137 		base_ch = TAD_TGT1(reg);
2138 		break;
2139 	case 2:
2140 		base_ch = TAD_TGT2(reg);
2141 		break;
2142 	case 3:
2143 		base_ch = TAD_TGT3(reg);
2144 		break;
2145 	default:
2146 		sprintf(msg, "Can't discover the TAD target");
2147 		return -EINVAL;
2148 	}
2149 	*channel_mask = 1 << base_ch;
2150 
2151 	pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
2152 				tad_ch_nilv_offset[n_tads],
2153 				&tad_offset);
2154 
2155 	if (pvt->is_mirrored) {
2156 		*channel_mask |= 1 << ((base_ch + 2) % 4);
2157 		switch(ch_way) {
2158 		case 2:
2159 		case 4:
2160 			sck_xch = 1 << sck_way * (ch_way >> 1);
2161 			break;
2162 		default:
2163 			sprintf(msg, "Invalid mirror set. Can't decode addr");
2164 			return -EINVAL;
2165 		}
2166 	} else
2167 		sck_xch = (1 << sck_way) * ch_way;
2168 
2169 	if (pvt->is_lockstep)
2170 		*channel_mask |= 1 << ((base_ch + 1) % 4);
2171 
2172 	offset = TAD_OFFSET(tad_offset);
2173 
2174 	edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
2175 		 n_tads,
2176 		 addr,
2177 		 limit,
2178 		 sck_way,
2179 		 ch_way,
2180 		 offset,
2181 		 idx,
2182 		 base_ch,
2183 		 *channel_mask);
2184 
2185 	/* Calculate channel address */
2186 	/* Remove the TAD offset */
2187 
2188 	if (offset > addr) {
2189 		sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!",
2190 			offset, addr);
2191 		return -EINVAL;
2192 	}
2193 
2194 	ch_addr = addr - offset;
2195 	ch_addr >>= (6 + shiftup);
2196 	ch_addr /= ch_way * sck_way;
2197 	ch_addr <<= (6 + shiftup);
2198 	ch_addr |= addr & ((1 << (6 + shiftup)) - 1);
2199 
2200 	/*
2201 	 * Step 3) Decode rank
2202 	 */
2203 	for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) {
2204 		pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
2205 				      rir_way_limit[n_rir],
2206 				      &reg);
2207 
2208 		if (!IS_RIR_VALID(reg))
2209 			continue;
2210 
2211 		limit = pvt->info.rir_limit(reg);
2212 		gb = div_u64_rem(limit >> 20, 1024, &mb);
2213 		edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
2214 			 n_rir,
2215 			 gb, (mb*1000)/1024,
2216 			 limit,
2217 			 1 << RIR_WAY(reg));
2218 		if  (ch_addr <= limit)
2219 			break;
2220 	}
2221 	if (n_rir == MAX_RIR_RANGES) {
2222 		sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx",
2223 			ch_addr);
2224 		return -EINVAL;
2225 	}
2226 	rir_way = RIR_WAY(reg);
2227 
2228 	if (pvt->is_close_pg)
2229 		idx = (ch_addr >> 6);
2230 	else
2231 		idx = (ch_addr >> 13);	/* FIXME: Datasheet says to shift by 15 */
2232 	idx %= 1 << rir_way;
2233 
2234 	pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
2235 			      rir_offset[n_rir][idx],
2236 			      &reg);
2237 	*rank = RIR_RNK_TGT(reg);
2238 
2239 	edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
2240 		 n_rir,
2241 		 ch_addr,
2242 		 limit,
2243 		 rir_way,
2244 		 idx);
2245 
2246 	return 0;
2247 }
2248 
2249 /****************************************************************************
2250 	Device initialization routines: put/get, init/exit
2251  ****************************************************************************/
2252 
2253 /*
2254  *	sbridge_put_all_devices	'put' all the devices that we have
2255  *				reserved via 'get'
2256  */
2257 static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)
2258 {
2259 	int i;
2260 
2261 	edac_dbg(0, "\n");
2262 	for (i = 0; i < sbridge_dev->n_devs; i++) {
2263 		struct pci_dev *pdev = sbridge_dev->pdev[i];
2264 		if (!pdev)
2265 			continue;
2266 		edac_dbg(0, "Removing dev %02x:%02x.%d\n",
2267 			 pdev->bus->number,
2268 			 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
2269 		pci_dev_put(pdev);
2270 	}
2271 }
2272 
2273 static void sbridge_put_all_devices(void)
2274 {
2275 	struct sbridge_dev *sbridge_dev, *tmp;
2276 
2277 	list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) {
2278 		sbridge_put_devices(sbridge_dev);
2279 		free_sbridge_dev(sbridge_dev);
2280 	}
2281 }
2282 
2283 static int sbridge_get_onedevice(struct pci_dev **prev,
2284 				 u8 *num_mc,
2285 				 const struct pci_id_table *table,
2286 				 const unsigned devno,
2287 				 const int multi_bus)
2288 {
2289 	struct sbridge_dev *sbridge_dev;
2290 	const struct pci_id_descr *dev_descr = &table->descr[devno];
2291 	struct pci_dev *pdev = NULL;
2292 	u8 bus = 0;
2293 
2294 	sbridge_printk(KERN_DEBUG,
2295 		"Seeking for: PCI ID %04x:%04x\n",
2296 		PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2297 
2298 	pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
2299 			      dev_descr->dev_id, *prev);
2300 
2301 	if (!pdev) {
2302 		if (*prev) {
2303 			*prev = pdev;
2304 			return 0;
2305 		}
2306 
2307 		if (dev_descr->optional)
2308 			return 0;
2309 
2310 		/* if the HA wasn't found */
2311 		if (devno == 0)
2312 			return -ENODEV;
2313 
2314 		sbridge_printk(KERN_INFO,
2315 			"Device not found: %04x:%04x\n",
2316 			PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2317 
2318 		/* End of list, leave */
2319 		return -ENODEV;
2320 	}
2321 	bus = pdev->bus->number;
2322 
2323 	sbridge_dev = get_sbridge_dev(bus, multi_bus);
2324 	if (!sbridge_dev) {
2325 		sbridge_dev = alloc_sbridge_dev(bus, table);
2326 		if (!sbridge_dev) {
2327 			pci_dev_put(pdev);
2328 			return -ENOMEM;
2329 		}
2330 		(*num_mc)++;
2331 	}
2332 
2333 	if (sbridge_dev->pdev[devno]) {
2334 		sbridge_printk(KERN_ERR,
2335 			"Duplicated device for %04x:%04x\n",
2336 			PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2337 		pci_dev_put(pdev);
2338 		return -ENODEV;
2339 	}
2340 
2341 	sbridge_dev->pdev[devno] = pdev;
2342 
2343 	/* Be sure that the device is enabled */
2344 	if (unlikely(pci_enable_device(pdev) < 0)) {
2345 		sbridge_printk(KERN_ERR,
2346 			"Couldn't enable %04x:%04x\n",
2347 			PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2348 		return -ENODEV;
2349 	}
2350 
2351 	edac_dbg(0, "Detected %04x:%04x\n",
2352 		 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2353 
2354 	/*
2355 	 * As stated on drivers/pci/search.c, the reference count for
2356 	 * @from is always decremented if it is not %NULL. So, as we need
2357 	 * to get all devices up to null, we need to do a get for the device
2358 	 */
2359 	pci_dev_get(pdev);
2360 
2361 	*prev = pdev;
2362 
2363 	return 0;
2364 }
2365 
2366 /*
2367  * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's
2368  *			     devices we want to reference for this driver.
2369  * @num_mc: pointer to the memory controllers count, to be incremented in case
2370  *	    of success.
2371  * @table: model specific table
2372  * @allow_dups: allow for multiple devices to exist with the same device id
2373  *              (as implemented, this isn't expected to work correctly in the
2374  *              multi-socket case).
2375  * @multi_bus: don't assume devices on different buses belong to different
2376  *             memory controllers.
2377  *
2378  * returns 0 in case of success or error code
2379  */
2380 static int sbridge_get_all_devices_full(u8 *num_mc,
2381 					const struct pci_id_table *table,
2382 					int allow_dups,
2383 					int multi_bus)
2384 {
2385 	int i, rc;
2386 	struct pci_dev *pdev = NULL;
2387 
2388 	while (table && table->descr) {
2389 		for (i = 0; i < table->n_devs; i++) {
2390 			if (!allow_dups || i == 0 ||
2391 					table->descr[i].dev_id !=
2392 						table->descr[i-1].dev_id) {
2393 				pdev = NULL;
2394 			}
2395 			do {
2396 				rc = sbridge_get_onedevice(&pdev, num_mc,
2397 							   table, i, multi_bus);
2398 				if (rc < 0) {
2399 					if (i == 0) {
2400 						i = table->n_devs;
2401 						break;
2402 					}
2403 					sbridge_put_all_devices();
2404 					return -ENODEV;
2405 				}
2406 			} while (pdev && !allow_dups);
2407 		}
2408 		table++;
2409 	}
2410 
2411 	return 0;
2412 }
2413 
2414 #define sbridge_get_all_devices(num_mc, table) \
2415 		sbridge_get_all_devices_full(num_mc, table, 0, 0)
2416 #define sbridge_get_all_devices_knl(num_mc, table) \
2417 		sbridge_get_all_devices_full(num_mc, table, 1, 1)
2418 
2419 static int sbridge_mci_bind_devs(struct mem_ctl_info *mci,
2420 				 struct sbridge_dev *sbridge_dev)
2421 {
2422 	struct sbridge_pvt *pvt = mci->pvt_info;
2423 	struct pci_dev *pdev;
2424 	u8 saw_chan_mask = 0;
2425 	int i;
2426 
2427 	for (i = 0; i < sbridge_dev->n_devs; i++) {
2428 		pdev = sbridge_dev->pdev[i];
2429 		if (!pdev)
2430 			continue;
2431 
2432 		switch (pdev->device) {
2433 		case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0:
2434 			pvt->pci_sad0 = pdev;
2435 			break;
2436 		case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1:
2437 			pvt->pci_sad1 = pdev;
2438 			break;
2439 		case PCI_DEVICE_ID_INTEL_SBRIDGE_BR:
2440 			pvt->pci_br0 = pdev;
2441 			break;
2442 		case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:
2443 			pvt->pci_ha0 = pdev;
2444 			break;
2445 		case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA:
2446 			pvt->pci_ta = pdev;
2447 			break;
2448 		case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS:
2449 			pvt->pci_ras = pdev;
2450 			break;
2451 		case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0:
2452 		case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1:
2453 		case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2:
2454 		case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3:
2455 		{
2456 			int id = pdev->device - PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0;
2457 			pvt->pci_tad[id] = pdev;
2458 			saw_chan_mask |= 1 << id;
2459 		}
2460 			break;
2461 		case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO:
2462 			pvt->pci_ddrio = pdev;
2463 			break;
2464 		default:
2465 			goto error;
2466 		}
2467 
2468 		edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n",
2469 			 pdev->vendor, pdev->device,
2470 			 sbridge_dev->bus,
2471 			 pdev);
2472 	}
2473 
2474 	/* Check if everything were registered */
2475 	if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 ||
2476 	    !pvt-> pci_tad || !pvt->pci_ras  || !pvt->pci_ta)
2477 		goto enodev;
2478 
2479 	if (saw_chan_mask != 0x0f)
2480 		goto enodev;
2481 	return 0;
2482 
2483 enodev:
2484 	sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2485 	return -ENODEV;
2486 
2487 error:
2488 	sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n",
2489 		       PCI_VENDOR_ID_INTEL, pdev->device);
2490 	return -EINVAL;
2491 }
2492 
2493 static int ibridge_mci_bind_devs(struct mem_ctl_info *mci,
2494 				 struct sbridge_dev *sbridge_dev)
2495 {
2496 	struct sbridge_pvt *pvt = mci->pvt_info;
2497 	struct pci_dev *pdev;
2498 	u8 saw_chan_mask = 0;
2499 	int i;
2500 
2501 	for (i = 0; i < sbridge_dev->n_devs; i++) {
2502 		pdev = sbridge_dev->pdev[i];
2503 		if (!pdev)
2504 			continue;
2505 
2506 		switch (pdev->device) {
2507 		case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0:
2508 			pvt->pci_ha0 = pdev;
2509 			break;
2510 		case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
2511 			pvt->pci_ta = pdev;
2512 		case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS:
2513 			pvt->pci_ras = pdev;
2514 			break;
2515 		case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0:
2516 		case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1:
2517 		case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2:
2518 		case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3:
2519 		{
2520 			int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0;
2521 			pvt->pci_tad[id] = pdev;
2522 			saw_chan_mask |= 1 << id;
2523 		}
2524 			break;
2525 		case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0:
2526 			pvt->pci_ddrio = pdev;
2527 			break;
2528 		case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0:
2529 			pvt->pci_ddrio = pdev;
2530 			break;
2531 		case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD:
2532 			pvt->pci_sad0 = pdev;
2533 			break;
2534 		case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0:
2535 			pvt->pci_br0 = pdev;
2536 			break;
2537 		case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1:
2538 			pvt->pci_br1 = pdev;
2539 			break;
2540 		case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1:
2541 			pvt->pci_ha1 = pdev;
2542 			break;
2543 		case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0:
2544 		case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1:
2545 		case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2:
2546 		case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3:
2547 		{
2548 			int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 + 4;
2549 			pvt->pci_tad[id] = pdev;
2550 			saw_chan_mask |= 1 << id;
2551 		}
2552 			break;
2553 		default:
2554 			goto error;
2555 		}
2556 
2557 		edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2558 			 sbridge_dev->bus,
2559 			 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2560 			 pdev);
2561 	}
2562 
2563 	/* Check if everything were registered */
2564 	if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_br0 ||
2565 	    !pvt->pci_br1 || !pvt->pci_tad || !pvt->pci_ras  ||
2566 	    !pvt->pci_ta)
2567 		goto enodev;
2568 
2569 	if (saw_chan_mask != 0x0f && /* -EN */
2570 	    saw_chan_mask != 0x33 && /* -EP */
2571 	    saw_chan_mask != 0xff)   /* -EX */
2572 		goto enodev;
2573 	return 0;
2574 
2575 enodev:
2576 	sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2577 	return -ENODEV;
2578 
2579 error:
2580 	sbridge_printk(KERN_ERR,
2581 		       "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL,
2582 			pdev->device);
2583 	return -EINVAL;
2584 }
2585 
2586 static int haswell_mci_bind_devs(struct mem_ctl_info *mci,
2587 				 struct sbridge_dev *sbridge_dev)
2588 {
2589 	struct sbridge_pvt *pvt = mci->pvt_info;
2590 	struct pci_dev *pdev;
2591 	u8 saw_chan_mask = 0;
2592 	int i;
2593 
2594 	/* there's only one device per system; not tied to any bus */
2595 	if (pvt->info.pci_vtd == NULL)
2596 		/* result will be checked later */
2597 		pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
2598 						   PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC,
2599 						   NULL);
2600 
2601 	for (i = 0; i < sbridge_dev->n_devs; i++) {
2602 		pdev = sbridge_dev->pdev[i];
2603 		if (!pdev)
2604 			continue;
2605 
2606 		switch (pdev->device) {
2607 		case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0:
2608 			pvt->pci_sad0 = pdev;
2609 			break;
2610 		case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1:
2611 			pvt->pci_sad1 = pdev;
2612 			break;
2613 		case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
2614 			pvt->pci_ha0 = pdev;
2615 			break;
2616 		case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA:
2617 			pvt->pci_ta = pdev;
2618 			break;
2619 		case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL:
2620 			pvt->pci_ras = pdev;
2621 			break;
2622 		case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0:
2623 		case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1:
2624 		case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2:
2625 		case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3:
2626 		{
2627 			int id = pdev->device - PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0;
2628 
2629 			pvt->pci_tad[id] = pdev;
2630 			saw_chan_mask |= 1 << id;
2631 		}
2632 			break;
2633 		case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0:
2634 		case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1:
2635 		case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2:
2636 		case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3:
2637 		{
2638 			int id = pdev->device - PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 + 4;
2639 
2640 			pvt->pci_tad[id] = pdev;
2641 			saw_chan_mask |= 1 << id;
2642 		}
2643 			break;
2644 		case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0:
2645 		case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1:
2646 		case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2:
2647 		case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3:
2648 			if (!pvt->pci_ddrio)
2649 				pvt->pci_ddrio = pdev;
2650 			break;
2651 		case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1:
2652 			pvt->pci_ha1 = pdev;
2653 			break;
2654 		case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA:
2655 			pvt->pci_ha1_ta = pdev;
2656 			break;
2657 		default:
2658 			break;
2659 		}
2660 
2661 		edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2662 			 sbridge_dev->bus,
2663 			 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2664 			 pdev);
2665 	}
2666 
2667 	/* Check if everything were registered */
2668 	if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 ||
2669 	    !pvt->pci_ras  || !pvt->pci_ta || !pvt->info.pci_vtd)
2670 		goto enodev;
2671 
2672 	if (saw_chan_mask != 0x0f && /* -EN */
2673 	    saw_chan_mask != 0x33 && /* -EP */
2674 	    saw_chan_mask != 0xff)   /* -EX */
2675 		goto enodev;
2676 	return 0;
2677 
2678 enodev:
2679 	sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2680 	return -ENODEV;
2681 }
2682 
2683 static int broadwell_mci_bind_devs(struct mem_ctl_info *mci,
2684 				 struct sbridge_dev *sbridge_dev)
2685 {
2686 	struct sbridge_pvt *pvt = mci->pvt_info;
2687 	struct pci_dev *pdev;
2688 	u8 saw_chan_mask = 0;
2689 	int i;
2690 
2691 	/* there's only one device per system; not tied to any bus */
2692 	if (pvt->info.pci_vtd == NULL)
2693 		/* result will be checked later */
2694 		pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
2695 						   PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC,
2696 						   NULL);
2697 
2698 	for (i = 0; i < sbridge_dev->n_devs; i++) {
2699 		pdev = sbridge_dev->pdev[i];
2700 		if (!pdev)
2701 			continue;
2702 
2703 		switch (pdev->device) {
2704 		case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0:
2705 			pvt->pci_sad0 = pdev;
2706 			break;
2707 		case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1:
2708 			pvt->pci_sad1 = pdev;
2709 			break;
2710 		case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:
2711 			pvt->pci_ha0 = pdev;
2712 			break;
2713 		case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA:
2714 			pvt->pci_ta = pdev;
2715 			break;
2716 		case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL:
2717 			pvt->pci_ras = pdev;
2718 			break;
2719 		case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0:
2720 		case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1:
2721 		case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2:
2722 		case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3:
2723 		{
2724 			int id = pdev->device - PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0;
2725 			pvt->pci_tad[id] = pdev;
2726 			saw_chan_mask |= 1 << id;
2727 		}
2728 			break;
2729 		case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0:
2730 		case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1:
2731 		case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2:
2732 		case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3:
2733 		{
2734 			int id = pdev->device - PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 + 4;
2735 			pvt->pci_tad[id] = pdev;
2736 			saw_chan_mask |= 1 << id;
2737 		}
2738 			break;
2739 		case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0:
2740 			pvt->pci_ddrio = pdev;
2741 			break;
2742 		case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1:
2743 			pvt->pci_ha1 = pdev;
2744 			break;
2745 		case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA:
2746 			pvt->pci_ha1_ta = pdev;
2747 			break;
2748 		default:
2749 			break;
2750 		}
2751 
2752 		edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2753 			 sbridge_dev->bus,
2754 			 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2755 			 pdev);
2756 	}
2757 
2758 	/* Check if everything were registered */
2759 	if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 ||
2760 	    !pvt->pci_ras  || !pvt->pci_ta || !pvt->info.pci_vtd)
2761 		goto enodev;
2762 
2763 	if (saw_chan_mask != 0x0f && /* -EN */
2764 	    saw_chan_mask != 0x33 && /* -EP */
2765 	    saw_chan_mask != 0xff)   /* -EX */
2766 		goto enodev;
2767 	return 0;
2768 
2769 enodev:
2770 	sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2771 	return -ENODEV;
2772 }
2773 
2774 static int knl_mci_bind_devs(struct mem_ctl_info *mci,
2775 			struct sbridge_dev *sbridge_dev)
2776 {
2777 	struct sbridge_pvt *pvt = mci->pvt_info;
2778 	struct pci_dev *pdev;
2779 	int dev, func;
2780 
2781 	int i;
2782 	int devidx;
2783 
2784 	for (i = 0; i < sbridge_dev->n_devs; i++) {
2785 		pdev = sbridge_dev->pdev[i];
2786 		if (!pdev)
2787 			continue;
2788 
2789 		/* Extract PCI device and function. */
2790 		dev = (pdev->devfn >> 3) & 0x1f;
2791 		func = pdev->devfn & 0x7;
2792 
2793 		switch (pdev->device) {
2794 		case PCI_DEVICE_ID_INTEL_KNL_IMC_MC:
2795 			if (dev == 8)
2796 				pvt->knl.pci_mc0 = pdev;
2797 			else if (dev == 9)
2798 				pvt->knl.pci_mc1 = pdev;
2799 			else {
2800 				sbridge_printk(KERN_ERR,
2801 					"Memory controller in unexpected place! (dev %d, fn %d)\n",
2802 					dev, func);
2803 				continue;
2804 			}
2805 			break;
2806 
2807 		case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0:
2808 			pvt->pci_sad0 = pdev;
2809 			break;
2810 
2811 		case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1:
2812 			pvt->pci_sad1 = pdev;
2813 			break;
2814 
2815 		case PCI_DEVICE_ID_INTEL_KNL_IMC_CHA:
2816 			/* There are one of these per tile, and range from
2817 			 * 1.14.0 to 1.18.5.
2818 			 */
2819 			devidx = ((dev-14)*8)+func;
2820 
2821 			if (devidx < 0 || devidx >= KNL_MAX_CHAS) {
2822 				sbridge_printk(KERN_ERR,
2823 					"Caching and Home Agent in unexpected place! (dev %d, fn %d)\n",
2824 					dev, func);
2825 				continue;
2826 			}
2827 
2828 			WARN_ON(pvt->knl.pci_cha[devidx] != NULL);
2829 
2830 			pvt->knl.pci_cha[devidx] = pdev;
2831 			break;
2832 
2833 		case PCI_DEVICE_ID_INTEL_KNL_IMC_CHANNEL:
2834 			devidx = -1;
2835 
2836 			/*
2837 			 *  MC0 channels 0-2 are device 9 function 2-4,
2838 			 *  MC1 channels 3-5 are device 8 function 2-4.
2839 			 */
2840 
2841 			if (dev == 9)
2842 				devidx = func-2;
2843 			else if (dev == 8)
2844 				devidx = 3 + (func-2);
2845 
2846 			if (devidx < 0 || devidx >= KNL_MAX_CHANNELS) {
2847 				sbridge_printk(KERN_ERR,
2848 					"DRAM Channel Registers in unexpected place! (dev %d, fn %d)\n",
2849 					dev, func);
2850 				continue;
2851 			}
2852 
2853 			WARN_ON(pvt->knl.pci_channel[devidx] != NULL);
2854 			pvt->knl.pci_channel[devidx] = pdev;
2855 			break;
2856 
2857 		case PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM:
2858 			pvt->knl.pci_mc_info = pdev;
2859 			break;
2860 
2861 		case PCI_DEVICE_ID_INTEL_KNL_IMC_TA:
2862 			pvt->pci_ta = pdev;
2863 			break;
2864 
2865 		default:
2866 			sbridge_printk(KERN_ERR, "Unexpected device %d\n",
2867 				pdev->device);
2868 			break;
2869 		}
2870 	}
2871 
2872 	if (!pvt->knl.pci_mc0  || !pvt->knl.pci_mc1 ||
2873 	    !pvt->pci_sad0     || !pvt->pci_sad1    ||
2874 	    !pvt->pci_ta) {
2875 		goto enodev;
2876 	}
2877 
2878 	for (i = 0; i < KNL_MAX_CHANNELS; i++) {
2879 		if (!pvt->knl.pci_channel[i]) {
2880 			sbridge_printk(KERN_ERR, "Missing channel %d\n", i);
2881 			goto enodev;
2882 		}
2883 	}
2884 
2885 	for (i = 0; i < KNL_MAX_CHAS; i++) {
2886 		if (!pvt->knl.pci_cha[i]) {
2887 			sbridge_printk(KERN_ERR, "Missing CHA %d\n", i);
2888 			goto enodev;
2889 		}
2890 	}
2891 
2892 	return 0;
2893 
2894 enodev:
2895 	sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2896 	return -ENODEV;
2897 }
2898 
2899 /****************************************************************************
2900 			Error check routines
2901  ****************************************************************************/
2902 
2903 /*
2904  * While Sandy Bridge has error count registers, SMI BIOS read values from
2905  * and resets the counters. So, they are not reliable for the OS to read
2906  * from them. So, we have no option but to just trust on whatever MCE is
2907  * telling us about the errors.
2908  */
2909 static void sbridge_mce_output_error(struct mem_ctl_info *mci,
2910 				    const struct mce *m)
2911 {
2912 	struct mem_ctl_info *new_mci;
2913 	struct sbridge_pvt *pvt = mci->pvt_info;
2914 	enum hw_event_mc_err_type tp_event;
2915 	char *type, *optype, msg[256];
2916 	bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
2917 	bool overflow = GET_BITFIELD(m->status, 62, 62);
2918 	bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
2919 	bool recoverable;
2920 	u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
2921 	u32 mscod = GET_BITFIELD(m->status, 16, 31);
2922 	u32 errcode = GET_BITFIELD(m->status, 0, 15);
2923 	u32 channel = GET_BITFIELD(m->status, 0, 3);
2924 	u32 optypenum = GET_BITFIELD(m->status, 4, 6);
2925 	long channel_mask, first_channel;
2926 	u8  rank, socket, ha;
2927 	int rc, dimm;
2928 	char *area_type = NULL;
2929 
2930 	if (pvt->info.type != SANDY_BRIDGE)
2931 		recoverable = true;
2932 	else
2933 		recoverable = GET_BITFIELD(m->status, 56, 56);
2934 
2935 	if (uncorrected_error) {
2936 		if (ripv) {
2937 			type = "FATAL";
2938 			tp_event = HW_EVENT_ERR_FATAL;
2939 		} else {
2940 			type = "NON_FATAL";
2941 			tp_event = HW_EVENT_ERR_UNCORRECTED;
2942 		}
2943 	} else {
2944 		type = "CORRECTED";
2945 		tp_event = HW_EVENT_ERR_CORRECTED;
2946 	}
2947 
2948 	/*
2949 	 * According with Table 15-9 of the Intel Architecture spec vol 3A,
2950 	 * memory errors should fit in this mask:
2951 	 *	000f 0000 1mmm cccc (binary)
2952 	 * where:
2953 	 *	f = Correction Report Filtering Bit. If 1, subsequent errors
2954 	 *	    won't be shown
2955 	 *	mmm = error type
2956 	 *	cccc = channel
2957 	 * If the mask doesn't match, report an error to the parsing logic
2958 	 */
2959 	if (! ((errcode & 0xef80) == 0x80)) {
2960 		optype = "Can't parse: it is not a mem";
2961 	} else {
2962 		switch (optypenum) {
2963 		case 0:
2964 			optype = "generic undef request error";
2965 			break;
2966 		case 1:
2967 			optype = "memory read error";
2968 			break;
2969 		case 2:
2970 			optype = "memory write error";
2971 			break;
2972 		case 3:
2973 			optype = "addr/cmd error";
2974 			break;
2975 		case 4:
2976 			optype = "memory scrubbing error";
2977 			break;
2978 		default:
2979 			optype = "reserved";
2980 			break;
2981 		}
2982 	}
2983 
2984 	/* Only decode errors with an valid address (ADDRV) */
2985 	if (!GET_BITFIELD(m->status, 58, 58))
2986 		return;
2987 
2988 	if (pvt->info.type == KNIGHTS_LANDING) {
2989 		if (channel == 14) {
2990 			edac_dbg(0, "%s%s err_code:%04x:%04x EDRAM bank %d\n",
2991 				overflow ? " OVERFLOW" : "",
2992 				(uncorrected_error && recoverable)
2993 				? " recoverable" : "",
2994 				mscod, errcode,
2995 				m->bank);
2996 		} else {
2997 			char A = *("A");
2998 
2999 			channel = knl_channel_remap(channel);
3000 			channel_mask = 1 << channel;
3001 			snprintf(msg, sizeof(msg),
3002 				"%s%s err_code:%04x:%04x channel:%d (DIMM_%c)",
3003 				overflow ? " OVERFLOW" : "",
3004 				(uncorrected_error && recoverable)
3005 				? " recoverable" : " ",
3006 				mscod, errcode, channel, A + channel);
3007 			edac_mc_handle_error(tp_event, mci, core_err_cnt,
3008 				m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
3009 				channel, 0, -1,
3010 				optype, msg);
3011 		}
3012 		return;
3013 	} else {
3014 		rc = get_memory_error_data(mci, m->addr, &socket, &ha,
3015 				&channel_mask, &rank, &area_type, msg);
3016 	}
3017 
3018 	if (rc < 0)
3019 		goto err_parsing;
3020 	new_mci = get_mci_for_node_id(socket);
3021 	if (!new_mci) {
3022 		strcpy(msg, "Error: socket got corrupted!");
3023 		goto err_parsing;
3024 	}
3025 	mci = new_mci;
3026 	pvt = mci->pvt_info;
3027 
3028 	first_channel = find_first_bit(&channel_mask, NUM_CHANNELS);
3029 
3030 	if (rank < 4)
3031 		dimm = 0;
3032 	else if (rank < 8)
3033 		dimm = 1;
3034 	else
3035 		dimm = 2;
3036 
3037 
3038 	/*
3039 	 * FIXME: On some memory configurations (mirror, lockstep), the
3040 	 * Memory Controller can't point the error to a single DIMM. The
3041 	 * EDAC core should be handling the channel mask, in order to point
3042 	 * to the group of dimm's where the error may be happening.
3043 	 */
3044 	if (!pvt->is_lockstep && !pvt->is_mirrored && !pvt->is_close_pg)
3045 		channel = first_channel;
3046 
3047 	snprintf(msg, sizeof(msg),
3048 		 "%s%s area:%s err_code:%04x:%04x socket:%d ha:%d channel_mask:%ld rank:%d",
3049 		 overflow ? " OVERFLOW" : "",
3050 		 (uncorrected_error && recoverable) ? " recoverable" : "",
3051 		 area_type,
3052 		 mscod, errcode,
3053 		 socket, ha,
3054 		 channel_mask,
3055 		 rank);
3056 
3057 	edac_dbg(0, "%s\n", msg);
3058 
3059 	/* FIXME: need support for channel mask */
3060 
3061 	if (channel == CHANNEL_UNSPECIFIED)
3062 		channel = -1;
3063 
3064 	/* Call the helper to output message */
3065 	edac_mc_handle_error(tp_event, mci, core_err_cnt,
3066 			     m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
3067 			     4*ha+channel, dimm, -1,
3068 			     optype, msg);
3069 	return;
3070 err_parsing:
3071 	edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0,
3072 			     -1, -1, -1,
3073 			     msg, "");
3074 
3075 }
3076 
3077 /*
3078  *	sbridge_check_error	Retrieve and process errors reported by the
3079  *				hardware. Called by the Core module.
3080  */
3081 static void sbridge_check_error(struct mem_ctl_info *mci)
3082 {
3083 	struct sbridge_pvt *pvt = mci->pvt_info;
3084 	int i;
3085 	unsigned count = 0;
3086 	struct mce *m;
3087 
3088 	/*
3089 	 * MCE first step: Copy all mce errors into a temporary buffer
3090 	 * We use a double buffering here, to reduce the risk of
3091 	 * loosing an error.
3092 	 */
3093 	smp_rmb();
3094 	count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
3095 		% MCE_LOG_LEN;
3096 	if (!count)
3097 		return;
3098 
3099 	m = pvt->mce_outentry;
3100 	if (pvt->mce_in + count > MCE_LOG_LEN) {
3101 		unsigned l = MCE_LOG_LEN - pvt->mce_in;
3102 
3103 		memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
3104 		smp_wmb();
3105 		pvt->mce_in = 0;
3106 		count -= l;
3107 		m += l;
3108 	}
3109 	memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
3110 	smp_wmb();
3111 	pvt->mce_in += count;
3112 
3113 	smp_rmb();
3114 	if (pvt->mce_overrun) {
3115 		sbridge_printk(KERN_ERR, "Lost %d memory errors\n",
3116 			      pvt->mce_overrun);
3117 		smp_wmb();
3118 		pvt->mce_overrun = 0;
3119 	}
3120 
3121 	/*
3122 	 * MCE second step: parse errors and display
3123 	 */
3124 	for (i = 0; i < count; i++)
3125 		sbridge_mce_output_error(mci, &pvt->mce_outentry[i]);
3126 }
3127 
3128 /*
3129  * sbridge_mce_check_error	Replicates mcelog routine to get errors
3130  *				This routine simply queues mcelog errors, and
3131  *				return. The error itself should be handled later
3132  *				by sbridge_check_error.
3133  * WARNING: As this routine should be called at NMI time, extra care should
3134  * be taken to avoid deadlocks, and to be as fast as possible.
3135  */
3136 static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
3137 				   void *data)
3138 {
3139 	struct mce *mce = (struct mce *)data;
3140 	struct mem_ctl_info *mci;
3141 	struct sbridge_pvt *pvt;
3142 	char *type;
3143 
3144 	if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
3145 		return NOTIFY_DONE;
3146 
3147 	mci = get_mci_for_node_id(mce->socketid);
3148 	if (!mci)
3149 		return NOTIFY_BAD;
3150 	pvt = mci->pvt_info;
3151 
3152 	/*
3153 	 * Just let mcelog handle it if the error is
3154 	 * outside the memory controller. A memory error
3155 	 * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
3156 	 * bit 12 has an special meaning.
3157 	 */
3158 	if ((mce->status & 0xefff) >> 7 != 1)
3159 		return NOTIFY_DONE;
3160 
3161 	if (mce->mcgstatus & MCG_STATUS_MCIP)
3162 		type = "Exception";
3163 	else
3164 		type = "Event";
3165 
3166 	sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
3167 
3168 	sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx "
3169 			  "Bank %d: %016Lx\n", mce->extcpu, type,
3170 			  mce->mcgstatus, mce->bank, mce->status);
3171 	sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc);
3172 	sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr);
3173 	sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc);
3174 
3175 	sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET "
3176 			  "%u APIC %x\n", mce->cpuvendor, mce->cpuid,
3177 			  mce->time, mce->socketid, mce->apicid);
3178 
3179 	smp_rmb();
3180 	if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
3181 		smp_wmb();
3182 		pvt->mce_overrun++;
3183 		return NOTIFY_DONE;
3184 	}
3185 
3186 	/* Copy memory error at the ringbuffer */
3187 	memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
3188 	smp_wmb();
3189 	pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
3190 
3191 	/* Handle fatal errors immediately */
3192 	if (mce->mcgstatus & 1)
3193 		sbridge_check_error(mci);
3194 
3195 	/* Advice mcelog that the error were handled */
3196 	return NOTIFY_STOP;
3197 }
3198 
3199 static struct notifier_block sbridge_mce_dec = {
3200 	.notifier_call      = sbridge_mce_check_error,
3201 };
3202 
3203 /****************************************************************************
3204 			EDAC register/unregister logic
3205  ****************************************************************************/
3206 
3207 static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
3208 {
3209 	struct mem_ctl_info *mci = sbridge_dev->mci;
3210 	struct sbridge_pvt *pvt;
3211 
3212 	if (unlikely(!mci || !mci->pvt_info)) {
3213 		edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev);
3214 
3215 		sbridge_printk(KERN_ERR, "Couldn't find mci handler\n");
3216 		return;
3217 	}
3218 
3219 	pvt = mci->pvt_info;
3220 
3221 	edac_dbg(0, "MC: mci = %p, dev = %p\n",
3222 		 mci, &sbridge_dev->pdev[0]->dev);
3223 
3224 	/* Remove MC sysfs nodes */
3225 	edac_mc_del_mc(mci->pdev);
3226 
3227 	edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
3228 	kfree(mci->ctl_name);
3229 	edac_mc_free(mci);
3230 	sbridge_dev->mci = NULL;
3231 }
3232 
3233 static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
3234 {
3235 	struct mem_ctl_info *mci;
3236 	struct edac_mc_layer layers[2];
3237 	struct sbridge_pvt *pvt;
3238 	struct pci_dev *pdev = sbridge_dev->pdev[0];
3239 	int rc;
3240 
3241 	/* Check the number of active and not disabled channels */
3242 	rc = check_if_ecc_is_active(sbridge_dev->bus, type);
3243 	if (unlikely(rc < 0))
3244 		return rc;
3245 
3246 	/* allocate a new MC control structure */
3247 	layers[0].type = EDAC_MC_LAYER_CHANNEL;
3248 	layers[0].size = type == KNIGHTS_LANDING ?
3249 		KNL_MAX_CHANNELS : NUM_CHANNELS;
3250 	layers[0].is_virt_csrow = false;
3251 	layers[1].type = EDAC_MC_LAYER_SLOT;
3252 	layers[1].size = type == KNIGHTS_LANDING ? 1 : MAX_DIMMS;
3253 	layers[1].is_virt_csrow = true;
3254 	mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers,
3255 			    sizeof(*pvt));
3256 
3257 	if (unlikely(!mci))
3258 		return -ENOMEM;
3259 
3260 	edac_dbg(0, "MC: mci = %p, dev = %p\n",
3261 		 mci, &pdev->dev);
3262 
3263 	pvt = mci->pvt_info;
3264 	memset(pvt, 0, sizeof(*pvt));
3265 
3266 	/* Associate sbridge_dev and mci for future usage */
3267 	pvt->sbridge_dev = sbridge_dev;
3268 	sbridge_dev->mci = mci;
3269 
3270 	mci->mtype_cap = type == KNIGHTS_LANDING ?
3271 		MEM_FLAG_DDR4 : MEM_FLAG_DDR3;
3272 	mci->edac_ctl_cap = EDAC_FLAG_NONE;
3273 	mci->edac_cap = EDAC_FLAG_NONE;
3274 	mci->mod_name = "sbridge_edac.c";
3275 	mci->mod_ver = SBRIDGE_REVISION;
3276 	mci->dev_name = pci_name(pdev);
3277 	mci->ctl_page_to_phys = NULL;
3278 
3279 	/* Set the function pointer to an actual operation function */
3280 	mci->edac_check = sbridge_check_error;
3281 
3282 	pvt->info.type = type;
3283 	switch (type) {
3284 	case IVY_BRIDGE:
3285 		pvt->info.rankcfgr = IB_RANK_CFG_A;
3286 		pvt->info.get_tolm = ibridge_get_tolm;
3287 		pvt->info.get_tohm = ibridge_get_tohm;
3288 		pvt->info.dram_rule = ibridge_dram_rule;
3289 		pvt->info.get_memory_type = get_memory_type;
3290 		pvt->info.get_node_id = get_node_id;
3291 		pvt->info.rir_limit = rir_limit;
3292 		pvt->info.sad_limit = sad_limit;
3293 		pvt->info.interleave_mode = interleave_mode;
3294 		pvt->info.show_interleave_mode = show_interleave_mode;
3295 		pvt->info.dram_attr = dram_attr;
3296 		pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3297 		pvt->info.interleave_list = ibridge_interleave_list;
3298 		pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
3299 		pvt->info.interleave_pkg = ibridge_interleave_pkg;
3300 		pvt->info.get_width = ibridge_get_width;
3301 		mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge Socket#%d", mci->mc_idx);
3302 
3303 		/* Store pci devices at mci for faster access */
3304 		rc = ibridge_mci_bind_devs(mci, sbridge_dev);
3305 		if (unlikely(rc < 0))
3306 			goto fail0;
3307 		break;
3308 	case SANDY_BRIDGE:
3309 		pvt->info.rankcfgr = SB_RANK_CFG_A;
3310 		pvt->info.get_tolm = sbridge_get_tolm;
3311 		pvt->info.get_tohm = sbridge_get_tohm;
3312 		pvt->info.dram_rule = sbridge_dram_rule;
3313 		pvt->info.get_memory_type = get_memory_type;
3314 		pvt->info.get_node_id = get_node_id;
3315 		pvt->info.rir_limit = rir_limit;
3316 		pvt->info.sad_limit = sad_limit;
3317 		pvt->info.interleave_mode = interleave_mode;
3318 		pvt->info.show_interleave_mode = show_interleave_mode;
3319 		pvt->info.dram_attr = dram_attr;
3320 		pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule);
3321 		pvt->info.interleave_list = sbridge_interleave_list;
3322 		pvt->info.max_interleave = ARRAY_SIZE(sbridge_interleave_list);
3323 		pvt->info.interleave_pkg = sbridge_interleave_pkg;
3324 		pvt->info.get_width = sbridge_get_width;
3325 		mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx);
3326 
3327 		/* Store pci devices at mci for faster access */
3328 		rc = sbridge_mci_bind_devs(mci, sbridge_dev);
3329 		if (unlikely(rc < 0))
3330 			goto fail0;
3331 		break;
3332 	case HASWELL:
3333 		/* rankcfgr isn't used */
3334 		pvt->info.get_tolm = haswell_get_tolm;
3335 		pvt->info.get_tohm = haswell_get_tohm;
3336 		pvt->info.dram_rule = ibridge_dram_rule;
3337 		pvt->info.get_memory_type = haswell_get_memory_type;
3338 		pvt->info.get_node_id = haswell_get_node_id;
3339 		pvt->info.rir_limit = haswell_rir_limit;
3340 		pvt->info.sad_limit = sad_limit;
3341 		pvt->info.interleave_mode = interleave_mode;
3342 		pvt->info.show_interleave_mode = show_interleave_mode;
3343 		pvt->info.dram_attr = dram_attr;
3344 		pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3345 		pvt->info.interleave_list = ibridge_interleave_list;
3346 		pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
3347 		pvt->info.interleave_pkg = ibridge_interleave_pkg;
3348 		pvt->info.get_width = ibridge_get_width;
3349 		mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell Socket#%d", mci->mc_idx);
3350 
3351 		/* Store pci devices at mci for faster access */
3352 		rc = haswell_mci_bind_devs(mci, sbridge_dev);
3353 		if (unlikely(rc < 0))
3354 			goto fail0;
3355 		break;
3356 	case BROADWELL:
3357 		/* rankcfgr isn't used */
3358 		pvt->info.get_tolm = haswell_get_tolm;
3359 		pvt->info.get_tohm = haswell_get_tohm;
3360 		pvt->info.dram_rule = ibridge_dram_rule;
3361 		pvt->info.get_memory_type = haswell_get_memory_type;
3362 		pvt->info.get_node_id = haswell_get_node_id;
3363 		pvt->info.rir_limit = haswell_rir_limit;
3364 		pvt->info.sad_limit = sad_limit;
3365 		pvt->info.interleave_mode = interleave_mode;
3366 		pvt->info.show_interleave_mode = show_interleave_mode;
3367 		pvt->info.dram_attr = dram_attr;
3368 		pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3369 		pvt->info.interleave_list = ibridge_interleave_list;
3370 		pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
3371 		pvt->info.interleave_pkg = ibridge_interleave_pkg;
3372 		pvt->info.get_width = broadwell_get_width;
3373 		mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell Socket#%d", mci->mc_idx);
3374 
3375 		/* Store pci devices at mci for faster access */
3376 		rc = broadwell_mci_bind_devs(mci, sbridge_dev);
3377 		if (unlikely(rc < 0))
3378 			goto fail0;
3379 		break;
3380 	case KNIGHTS_LANDING:
3381 		/* pvt->info.rankcfgr == ??? */
3382 		pvt->info.get_tolm = knl_get_tolm;
3383 		pvt->info.get_tohm = knl_get_tohm;
3384 		pvt->info.dram_rule = knl_dram_rule;
3385 		pvt->info.get_memory_type = knl_get_memory_type;
3386 		pvt->info.get_node_id = knl_get_node_id;
3387 		pvt->info.rir_limit = NULL;
3388 		pvt->info.sad_limit = knl_sad_limit;
3389 		pvt->info.interleave_mode = knl_interleave_mode;
3390 		pvt->info.show_interleave_mode = knl_show_interleave_mode;
3391 		pvt->info.dram_attr = dram_attr_knl;
3392 		pvt->info.max_sad = ARRAY_SIZE(knl_dram_rule);
3393 		pvt->info.interleave_list = knl_interleave_list;
3394 		pvt->info.max_interleave = ARRAY_SIZE(knl_interleave_list);
3395 		pvt->info.interleave_pkg = ibridge_interleave_pkg;
3396 		pvt->info.get_width = knl_get_width;
3397 		mci->ctl_name = kasprintf(GFP_KERNEL,
3398 			"Knights Landing Socket#%d", mci->mc_idx);
3399 
3400 		rc = knl_mci_bind_devs(mci, sbridge_dev);
3401 		if (unlikely(rc < 0))
3402 			goto fail0;
3403 		break;
3404 	}
3405 
3406 	/* Get dimm basic config and the memory layout */
3407 	get_dimm_config(mci);
3408 	get_memory_layout(mci);
3409 
3410 	/* record ptr to the generic device */
3411 	mci->pdev = &pdev->dev;
3412 
3413 	/* add this new MC control structure to EDAC's list of MCs */
3414 	if (unlikely(edac_mc_add_mc(mci))) {
3415 		edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
3416 		rc = -EINVAL;
3417 		goto fail0;
3418 	}
3419 
3420 	return 0;
3421 
3422 fail0:
3423 	kfree(mci->ctl_name);
3424 	edac_mc_free(mci);
3425 	sbridge_dev->mci = NULL;
3426 	return rc;
3427 }
3428 
3429 /*
3430  *	sbridge_probe	Probe for ONE instance of device to see if it is
3431  *			present.
3432  *	return:
3433  *		0 for FOUND a device
3434  *		< 0 for error code
3435  */
3436 
3437 static int sbridge_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3438 {
3439 	int rc = -ENODEV;
3440 	u8 mc, num_mc = 0;
3441 	struct sbridge_dev *sbridge_dev;
3442 	enum type type = SANDY_BRIDGE;
3443 
3444 	/* get the pci devices we want to reserve for our use */
3445 	mutex_lock(&sbridge_edac_lock);
3446 
3447 	/*
3448 	 * All memory controllers are allocated at the first pass.
3449 	 */
3450 	if (unlikely(probed >= 1)) {
3451 		mutex_unlock(&sbridge_edac_lock);
3452 		return -ENODEV;
3453 	}
3454 	probed++;
3455 
3456 	switch (pdev->device) {
3457 	case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
3458 		rc = sbridge_get_all_devices(&num_mc,
3459 					pci_dev_descr_ibridge_table);
3460 		type = IVY_BRIDGE;
3461 		break;
3462 	case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:
3463 		rc = sbridge_get_all_devices(&num_mc,
3464 					pci_dev_descr_sbridge_table);
3465 		type = SANDY_BRIDGE;
3466 		break;
3467 	case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
3468 		rc = sbridge_get_all_devices(&num_mc,
3469 					pci_dev_descr_haswell_table);
3470 		type = HASWELL;
3471 		break;
3472 	case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:
3473 		rc = sbridge_get_all_devices(&num_mc,
3474 					pci_dev_descr_broadwell_table);
3475 		type = BROADWELL;
3476 	    break;
3477 	case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0:
3478 		rc = sbridge_get_all_devices_knl(&num_mc,
3479 					pci_dev_descr_knl_table);
3480 		type = KNIGHTS_LANDING;
3481 		break;
3482 	}
3483 	if (unlikely(rc < 0)) {
3484 		edac_dbg(0, "couldn't get all devices for 0x%x\n", pdev->device);
3485 		goto fail0;
3486 	}
3487 
3488 	mc = 0;
3489 
3490 	list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
3491 		edac_dbg(0, "Registering MC#%d (%d of %d)\n",
3492 			 mc, mc + 1, num_mc);
3493 
3494 		sbridge_dev->mc = mc++;
3495 		rc = sbridge_register_mci(sbridge_dev, type);
3496 		if (unlikely(rc < 0))
3497 			goto fail1;
3498 	}
3499 
3500 	sbridge_printk(KERN_INFO, "%s\n", SBRIDGE_REVISION);
3501 
3502 	mutex_unlock(&sbridge_edac_lock);
3503 	return 0;
3504 
3505 fail1:
3506 	list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
3507 		sbridge_unregister_mci(sbridge_dev);
3508 
3509 	sbridge_put_all_devices();
3510 fail0:
3511 	mutex_unlock(&sbridge_edac_lock);
3512 	return rc;
3513 }
3514 
3515 /*
3516  *	sbridge_remove	destructor for one instance of device
3517  *
3518  */
3519 static void sbridge_remove(struct pci_dev *pdev)
3520 {
3521 	struct sbridge_dev *sbridge_dev;
3522 
3523 	edac_dbg(0, "\n");
3524 
3525 	/*
3526 	 * we have a trouble here: pdev value for removal will be wrong, since
3527 	 * it will point to the X58 register used to detect that the machine
3528 	 * is a Nehalem or upper design. However, due to the way several PCI
3529 	 * devices are grouped together to provide MC functionality, we need
3530 	 * to use a different method for releasing the devices
3531 	 */
3532 
3533 	mutex_lock(&sbridge_edac_lock);
3534 
3535 	if (unlikely(!probed)) {
3536 		mutex_unlock(&sbridge_edac_lock);
3537 		return;
3538 	}
3539 
3540 	list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
3541 		sbridge_unregister_mci(sbridge_dev);
3542 
3543 	/* Release PCI resources */
3544 	sbridge_put_all_devices();
3545 
3546 	probed--;
3547 
3548 	mutex_unlock(&sbridge_edac_lock);
3549 }
3550 
3551 MODULE_DEVICE_TABLE(pci, sbridge_pci_tbl);
3552 
3553 /*
3554  *	sbridge_driver	pci_driver structure for this module
3555  *
3556  */
3557 static struct pci_driver sbridge_driver = {
3558 	.name     = "sbridge_edac",
3559 	.probe    = sbridge_probe,
3560 	.remove   = sbridge_remove,
3561 	.id_table = sbridge_pci_tbl,
3562 };
3563 
3564 /*
3565  *	sbridge_init		Module entry function
3566  *			Try to initialize this module for its devices
3567  */
3568 static int __init sbridge_init(void)
3569 {
3570 	int pci_rc;
3571 
3572 	edac_dbg(2, "\n");
3573 
3574 	/* Ensure that the OPSTATE is set correctly for POLL or NMI */
3575 	opstate_init();
3576 
3577 	pci_rc = pci_register_driver(&sbridge_driver);
3578 	if (pci_rc >= 0) {
3579 		mce_register_decode_chain(&sbridge_mce_dec);
3580 		if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
3581 			sbridge_printk(KERN_WARNING, "Loading driver, error reporting disabled.\n");
3582 		return 0;
3583 	}
3584 
3585 	sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n",
3586 		      pci_rc);
3587 
3588 	return pci_rc;
3589 }
3590 
3591 /*
3592  *	sbridge_exit()	Module exit function
3593  *			Unregister the driver
3594  */
3595 static void __exit sbridge_exit(void)
3596 {
3597 	edac_dbg(2, "\n");
3598 	pci_unregister_driver(&sbridge_driver);
3599 	mce_unregister_decode_chain(&sbridge_mce_dec);
3600 }
3601 
3602 module_init(sbridge_init);
3603 module_exit(sbridge_exit);
3604 
3605 module_param(edac_op_state, int, 0444);
3606 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
3607 
3608 MODULE_LICENSE("GPL");
3609 MODULE_AUTHOR("Mauro Carvalho Chehab");
3610 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
3611 MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - "
3612 		   SBRIDGE_REVISION);
3613