1 /* 2 * Copyright (c) 2008 Nuovation System Designs, LLC 3 * Grant Erickson <gerickson@nuovations.com> 4 * 5 * This file defines processor mnemonics for accessing and managing 6 * the IBM DDR1/DDR2 ECC controller found in the 405EX[r], 440SP, 7 * 440SPe, 460EX, 460GT and 460SX. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; version 2 of the 12 * License. 13 * 14 */ 15 16 #ifndef __PPC4XX_EDAC_H 17 #define __PPC4XX_EDAC_H 18 19 #include <linux/types.h> 20 21 /* 22 * Macro for generating register field mnemonics 23 */ 24 #define PPC_REG_BITS 32 25 #define PPC_REG_VAL(bit, val) ((val) << ((PPC_REG_BITS - 1) - (bit))) 26 #define PPC_REG_DECODE(bit, val) ((val) >> ((PPC_REG_BITS - 1) - (bit))) 27 28 /* 29 * IBM 4xx DDR1/DDR2 SDRAM memory controller registers (at least those 30 * relevant to ECC) 31 */ 32 #define SDRAM_BESR 0x00 /* Error status (read/clear) */ 33 #define SDRAM_BESRT 0x01 /* Error statuss (test/set) */ 34 #define SDRAM_BEARL 0x02 /* Error address low */ 35 #define SDRAM_BEARH 0x03 /* Error address high */ 36 #define SDRAM_WMIRQ 0x06 /* Write master (read/clear) */ 37 #define SDRAM_WMIRQT 0x07 /* Write master (test/set) */ 38 #define SDRAM_MCOPT1 0x20 /* Controller options 1 */ 39 #define SDRAM_MBXCF_BASE 0x40 /* Bank n configuration base */ 40 #define SDRAM_MBXCF(n) (SDRAM_MBXCF_BASE + (4 * (n))) 41 #define SDRAM_MB0CF SDRAM_MBXCF(0) 42 #define SDRAM_MB1CF SDRAM_MBXCF(1) 43 #define SDRAM_MB2CF SDRAM_MBXCF(2) 44 #define SDRAM_MB3CF SDRAM_MBXCF(3) 45 #define SDRAM_ECCCR 0x98 /* ECC error status */ 46 #define SDRAM_ECCES SDRAM_ECCCR 47 48 /* 49 * PLB Master IDs 50 */ 51 #define SDRAM_PLB_M0ID_FIRST 0 52 #define SDRAM_PLB_M0ID_ICU SDRAM_PLB_M0ID_FIRST 53 #define SDRAM_PLB_M0ID_PCIE0 1 54 #define SDRAM_PLB_M0ID_PCIE1 2 55 #define SDRAM_PLB_M0ID_DMA 3 56 #define SDRAM_PLB_M0ID_DCU 4 57 #define SDRAM_PLB_M0ID_OPB 5 58 #define SDRAM_PLB_M0ID_MAL 6 59 #define SDRAM_PLB_M0ID_SEC 7 60 #define SDRAM_PLB_M0ID_AHB 8 61 #define SDRAM_PLB_M0ID_LAST SDRAM_PLB_M0ID_AHB 62 #define SDRAM_PLB_M0ID_COUNT (SDRAM_PLB_M0ID_LAST - \ 63 SDRAM_PLB_M0ID_FIRST + 1) 64 65 /* 66 * Memory Controller Bus Error Status Register 67 */ 68 #define SDRAM_BESR_MASK PPC_REG_VAL(7, 0xFF) 69 #define SDRAM_BESR_M0ID_MASK PPC_REG_VAL(3, 0xF) 70 #define SDRAM_BESR_M0ID_DECODE(n) PPC_REG_DECODE(3, n) 71 #define SDRAM_BESR_M0ID_ICU PPC_REG_VAL(3, SDRAM_PLB_M0ID_ICU) 72 #define SDRAM_BESR_M0ID_PCIE0 PPC_REG_VAL(3, SDRAM_PLB_M0ID_PCIE0) 73 #define SDRAM_BESR_M0ID_PCIE1 PPC_REG_VAL(3, SDRAM_PLB_M0ID_PCIE1) 74 #define SDRAM_BESR_M0ID_DMA PPC_REG_VAL(3, SDRAM_PLB_M0ID_DMA) 75 #define SDRAM_BESR_M0ID_DCU PPC_REG_VAL(3, SDRAM_PLB_M0ID_DCU) 76 #define SDRAM_BESR_M0ID_OPB PPC_REG_VAL(3, SDRAM_PLB_M0ID_OPB) 77 #define SDRAM_BESR_M0ID_MAL PPC_REG_VAL(3, SDRAM_PLB_M0ID_MAL) 78 #define SDRAM_BESR_M0ID_SEC PPC_REG_VAL(3, SDRAM_PLB_M0ID_SEC) 79 #define SDRAM_BESR_M0ID_AHB PPC_REG_VAL(3, SDRAM_PLB_M0ID_AHB) 80 #define SDRAM_BESR_M0ET_MASK PPC_REG_VAL(6, 0x7) 81 #define SDRAM_BESR_M0ET_NONE PPC_REG_VAL(6, 0) 82 #define SDRAM_BESR_M0ET_ECC PPC_REG_VAL(6, 1) 83 #define SDRAM_BESR_M0RW_MASK PPC_REG_VAL(7, 1) 84 #define SDRAM_BESR_M0RW_WRITE PPC_REG_VAL(7, 0) 85 #define SDRAM_BESR_M0RW_READ PPC_REG_VAL(7, 1) 86 87 /* 88 * Memory Controller PLB Write Master Interrupt Register 89 */ 90 #define SDRAM_WMIRQ_MASK PPC_REG_VAL(8, 0x1FF) 91 #define SDRAM_WMIRQ_ENCODE(id) PPC_REG_VAL((id % \ 92 SDRAM_PLB_M0ID_COUNT), 1) 93 #define SDRAM_WMIRQ_ICU PPC_REG_VAL(SDRAM_PLB_M0ID_ICU, 1) 94 #define SDRAM_WMIRQ_PCIE0 PPC_REG_VAL(SDRAM_PLB_M0ID_PCIE0, 1) 95 #define SDRAM_WMIRQ_PCIE1 PPC_REG_VAL(SDRAM_PLB_M0ID_PCIE1, 1) 96 #define SDRAM_WMIRQ_DMA PPC_REG_VAL(SDRAM_PLB_M0ID_DMA, 1) 97 #define SDRAM_WMIRQ_DCU PPC_REG_VAL(SDRAM_PLB_M0ID_DCU, 1) 98 #define SDRAM_WMIRQ_OPB PPC_REG_VAL(SDRAM_PLB_M0ID_OPB, 1) 99 #define SDRAM_WMIRQ_MAL PPC_REG_VAL(SDRAM_PLB_M0ID_MAL, 1) 100 #define SDRAM_WMIRQ_SEC PPC_REG_VAL(SDRAM_PLB_M0ID_SEC, 1) 101 #define SDRAM_WMIRQ_AHB PPC_REG_VAL(SDRAM_PLB_M0ID_AHB, 1) 102 103 /* 104 * Memory Controller Options 1 Register 105 */ 106 #define SDRAM_MCOPT1_MCHK_MASK PPC_REG_VAL(3, 0x3) /* ECC mask */ 107 #define SDRAM_MCOPT1_MCHK_NON PPC_REG_VAL(3, 0x0) /* No ECC gen */ 108 #define SDRAM_MCOPT1_MCHK_GEN PPC_REG_VAL(3, 0x2) /* ECC gen */ 109 #define SDRAM_MCOPT1_MCHK_CHK PPC_REG_VAL(3, 0x1) /* ECC gen and chk */ 110 #define SDRAM_MCOPT1_MCHK_CHK_REP PPC_REG_VAL(3, 0x3) /* ECC gen/chk/rpt */ 111 #define SDRAM_MCOPT1_MCHK_DECODE(n) ((((u32)(n)) >> 28) & 0x3) 112 #define SDRAM_MCOPT1_RDEN_MASK PPC_REG_VAL(4, 0x1) /* Rgstrd DIMM mask */ 113 #define SDRAM_MCOPT1_RDEN PPC_REG_VAL(4, 0x1) /* Rgstrd DIMM enbl */ 114 #define SDRAM_MCOPT1_WDTH_MASK PPC_REG_VAL(7, 0x1) /* Width mask */ 115 #define SDRAM_MCOPT1_WDTH_32 PPC_REG_VAL(7, 0x0) /* 32 bits */ 116 #define SDRAM_MCOPT1_WDTH_16 PPC_REG_VAL(7, 0x1) /* 16 bits */ 117 #define SDRAM_MCOPT1_DDR_TYPE_MASK PPC_REG_VAL(11, 0x1) /* DDR type mask */ 118 #define SDRAM_MCOPT1_DDR1_TYPE PPC_REG_VAL(11, 0x0) /* DDR1 type */ 119 #define SDRAM_MCOPT1_DDR2_TYPE PPC_REG_VAL(11, 0x1) /* DDR2 type */ 120 121 /* 122 * Memory Bank 0 - n Configuration Register 123 */ 124 #define SDRAM_MBCF_BA_MASK PPC_REG_VAL(12, 0x1FFF) 125 #define SDRAM_MBCF_SZ_MASK PPC_REG_VAL(19, 0xF) 126 #define SDRAM_MBCF_SZ_DECODE(mbxcf) PPC_REG_DECODE(19, mbxcf) 127 #define SDRAM_MBCF_SZ_4MB PPC_REG_VAL(19, 0x0) 128 #define SDRAM_MBCF_SZ_8MB PPC_REG_VAL(19, 0x1) 129 #define SDRAM_MBCF_SZ_16MB PPC_REG_VAL(19, 0x2) 130 #define SDRAM_MBCF_SZ_32MB PPC_REG_VAL(19, 0x3) 131 #define SDRAM_MBCF_SZ_64MB PPC_REG_VAL(19, 0x4) 132 #define SDRAM_MBCF_SZ_128MB PPC_REG_VAL(19, 0x5) 133 #define SDRAM_MBCF_SZ_256MB PPC_REG_VAL(19, 0x6) 134 #define SDRAM_MBCF_SZ_512MB PPC_REG_VAL(19, 0x7) 135 #define SDRAM_MBCF_SZ_1GB PPC_REG_VAL(19, 0x8) 136 #define SDRAM_MBCF_SZ_2GB PPC_REG_VAL(19, 0x9) 137 #define SDRAM_MBCF_SZ_4GB PPC_REG_VAL(19, 0xA) 138 #define SDRAM_MBCF_SZ_8GB PPC_REG_VAL(19, 0xB) 139 #define SDRAM_MBCF_AM_MASK PPC_REG_VAL(23, 0xF) 140 #define SDRAM_MBCF_AM_MODE0 PPC_REG_VAL(23, 0x0) 141 #define SDRAM_MBCF_AM_MODE1 PPC_REG_VAL(23, 0x1) 142 #define SDRAM_MBCF_AM_MODE2 PPC_REG_VAL(23, 0x2) 143 #define SDRAM_MBCF_AM_MODE3 PPC_REG_VAL(23, 0x3) 144 #define SDRAM_MBCF_AM_MODE4 PPC_REG_VAL(23, 0x4) 145 #define SDRAM_MBCF_AM_MODE5 PPC_REG_VAL(23, 0x5) 146 #define SDRAM_MBCF_AM_MODE6 PPC_REG_VAL(23, 0x6) 147 #define SDRAM_MBCF_AM_MODE7 PPC_REG_VAL(23, 0x7) 148 #define SDRAM_MBCF_AM_MODE8 PPC_REG_VAL(23, 0x8) 149 #define SDRAM_MBCF_AM_MODE9 PPC_REG_VAL(23, 0x9) 150 #define SDRAM_MBCF_BE_MASK PPC_REG_VAL(31, 0x1) 151 #define SDRAM_MBCF_BE_DISABLE PPC_REG_VAL(31, 0x0) 152 #define SDRAM_MBCF_BE_ENABLE PPC_REG_VAL(31, 0x1) 153 154 /* 155 * ECC Error Status 156 */ 157 #define SDRAM_ECCES_MASK PPC_REG_VAL(21, 0x3FFFFF) 158 #define SDRAM_ECCES_BNCE_MASK PPC_REG_VAL(15, 0xFFFF) 159 #define SDRAM_ECCES_BNCE_ENCODE(lane) PPC_REG_VAL(((lane) & 0xF), 1) 160 #define SDRAM_ECCES_CKBER_MASK PPC_REG_VAL(17, 0x3) 161 #define SDRAM_ECCES_CKBER_NONE PPC_REG_VAL(17, 0) 162 #define SDRAM_ECCES_CKBER_16_ECC_0_3 PPC_REG_VAL(17, 2) 163 #define SDRAM_ECCES_CKBER_32_ECC_0_3 PPC_REG_VAL(17, 1) 164 #define SDRAM_ECCES_CKBER_32_ECC_4_8 PPC_REG_VAL(17, 2) 165 #define SDRAM_ECCES_CKBER_32_ECC_0_8 PPC_REG_VAL(17, 3) 166 #define SDRAM_ECCES_CE PPC_REG_VAL(18, 1) 167 #define SDRAM_ECCES_UE PPC_REG_VAL(19, 1) 168 #define SDRAM_ECCES_BKNER_MASK PPC_REG_VAL(21, 0x3) 169 #define SDRAM_ECCES_BK0ER PPC_REG_VAL(20, 1) 170 #define SDRAM_ECCES_BK1ER PPC_REG_VAL(21, 1) 171 172 #endif /* __PPC4XX_EDAC_H */ 173