1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2022 Nuvoton Technology Corporation 3 4 #include <linux/debugfs.h> 5 #include <linux/iopoll.h> 6 #include <linux/of_device.h> 7 #include <linux/regmap.h> 8 #include "edac_module.h" 9 10 #define EDAC_MOD_NAME "npcm-edac" 11 #define EDAC_MSG_SIZE 256 12 13 /* chip serials */ 14 #define NPCM7XX_CHIP BIT(0) 15 #define NPCM8XX_CHIP BIT(1) 16 17 /* syndrome values */ 18 #define UE_SYNDROME 0x03 19 20 /* error injection */ 21 #define ERROR_TYPE_CORRECTABLE 0 22 #define ERROR_TYPE_UNCORRECTABLE 1 23 #define ERROR_LOCATION_DATA 0 24 #define ERROR_LOCATION_CHECKCODE 1 25 #define ERROR_BIT_DATA_MAX 63 26 #define ERROR_BIT_CHECKCODE_MAX 7 27 28 static char data_synd[] = { 29 0xf4, 0xf1, 0xec, 0xea, 0xe9, 0xe6, 0xe5, 0xe3, 30 0xdc, 0xda, 0xd9, 0xd6, 0xd5, 0xd3, 0xce, 0xcb, 31 0xb5, 0xb0, 0xad, 0xab, 0xa8, 0xa7, 0xa4, 0xa2, 32 0x9d, 0x9b, 0x98, 0x97, 0x94, 0x92, 0x8f, 0x8a, 33 0x75, 0x70, 0x6d, 0x6b, 0x68, 0x67, 0x64, 0x62, 34 0x5e, 0x5b, 0x58, 0x57, 0x54, 0x52, 0x4f, 0x4a, 35 0x34, 0x31, 0x2c, 0x2a, 0x29, 0x26, 0x25, 0x23, 36 0x1c, 0x1a, 0x19, 0x16, 0x15, 0x13, 0x0e, 0x0b 37 }; 38 39 static struct regmap *npcm_regmap; 40 41 struct npcm_platform_data { 42 /* chip serials */ 43 int chip; 44 45 /* memory controller registers */ 46 u32 ctl_ecc_en; 47 u32 ctl_int_status; 48 u32 ctl_int_ack; 49 u32 ctl_int_mask_master; 50 u32 ctl_int_mask_ecc; 51 u32 ctl_ce_addr_l; 52 u32 ctl_ce_addr_h; 53 u32 ctl_ce_data_l; 54 u32 ctl_ce_data_h; 55 u32 ctl_ce_synd; 56 u32 ctl_ue_addr_l; 57 u32 ctl_ue_addr_h; 58 u32 ctl_ue_data_l; 59 u32 ctl_ue_data_h; 60 u32 ctl_ue_synd; 61 u32 ctl_source_id; 62 u32 ctl_controller_busy; 63 u32 ctl_xor_check_bits; 64 65 /* masks and shifts */ 66 u32 ecc_en_mask; 67 u32 int_status_ce_mask; 68 u32 int_status_ue_mask; 69 u32 int_ack_ce_mask; 70 u32 int_ack_ue_mask; 71 u32 int_mask_master_non_ecc_mask; 72 u32 int_mask_master_global_mask; 73 u32 int_mask_ecc_non_event_mask; 74 u32 ce_addr_h_mask; 75 u32 ce_synd_mask; 76 u32 ce_synd_shift; 77 u32 ue_addr_h_mask; 78 u32 ue_synd_mask; 79 u32 ue_synd_shift; 80 u32 source_id_ce_mask; 81 u32 source_id_ce_shift; 82 u32 source_id_ue_mask; 83 u32 source_id_ue_shift; 84 u32 controller_busy_mask; 85 u32 xor_check_bits_mask; 86 u32 xor_check_bits_shift; 87 u32 writeback_en_mask; 88 u32 fwc_mask; 89 }; 90 91 struct priv_data { 92 void __iomem *reg; 93 char message[EDAC_MSG_SIZE]; 94 const struct npcm_platform_data *pdata; 95 96 /* error injection */ 97 struct dentry *debugfs; 98 u8 error_type; 99 u8 location; 100 u8 bit; 101 }; 102 103 static void handle_ce(struct mem_ctl_info *mci) 104 { 105 struct priv_data *priv = mci->pvt_info; 106 const struct npcm_platform_data *pdata; 107 u32 val_h = 0, val_l, id, synd; 108 u64 addr = 0, data = 0; 109 110 pdata = priv->pdata; 111 regmap_read(npcm_regmap, pdata->ctl_ce_addr_l, &val_l); 112 if (pdata->chip == NPCM8XX_CHIP) { 113 regmap_read(npcm_regmap, pdata->ctl_ce_addr_h, &val_h); 114 val_h &= pdata->ce_addr_h_mask; 115 } 116 addr = ((addr | val_h) << 32) | val_l; 117 118 regmap_read(npcm_regmap, pdata->ctl_ce_data_l, &val_l); 119 if (pdata->chip == NPCM8XX_CHIP) 120 regmap_read(npcm_regmap, pdata->ctl_ce_data_h, &val_h); 121 data = ((data | val_h) << 32) | val_l; 122 123 regmap_read(npcm_regmap, pdata->ctl_source_id, &id); 124 id = (id & pdata->source_id_ce_mask) >> pdata->source_id_ce_shift; 125 126 regmap_read(npcm_regmap, pdata->ctl_ce_synd, &synd); 127 synd = (synd & pdata->ce_synd_mask) >> pdata->ce_synd_shift; 128 129 snprintf(priv->message, EDAC_MSG_SIZE, 130 "addr = 0x%llx, data = 0x%llx, id = 0x%x", addr, data, id); 131 132 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, addr >> PAGE_SHIFT, 133 addr & ~PAGE_MASK, synd, 0, 0, -1, priv->message, ""); 134 } 135 136 static void handle_ue(struct mem_ctl_info *mci) 137 { 138 struct priv_data *priv = mci->pvt_info; 139 const struct npcm_platform_data *pdata; 140 u32 val_h = 0, val_l, id, synd; 141 u64 addr = 0, data = 0; 142 143 pdata = priv->pdata; 144 regmap_read(npcm_regmap, pdata->ctl_ue_addr_l, &val_l); 145 if (pdata->chip == NPCM8XX_CHIP) { 146 regmap_read(npcm_regmap, pdata->ctl_ue_addr_h, &val_h); 147 val_h &= pdata->ue_addr_h_mask; 148 } 149 addr = ((addr | val_h) << 32) | val_l; 150 151 regmap_read(npcm_regmap, pdata->ctl_ue_data_l, &val_l); 152 if (pdata->chip == NPCM8XX_CHIP) 153 regmap_read(npcm_regmap, pdata->ctl_ue_data_h, &val_h); 154 data = ((data | val_h) << 32) | val_l; 155 156 regmap_read(npcm_regmap, pdata->ctl_source_id, &id); 157 id = (id & pdata->source_id_ue_mask) >> pdata->source_id_ue_shift; 158 159 regmap_read(npcm_regmap, pdata->ctl_ue_synd, &synd); 160 synd = (synd & pdata->ue_synd_mask) >> pdata->ue_synd_shift; 161 162 snprintf(priv->message, EDAC_MSG_SIZE, 163 "addr = 0x%llx, data = 0x%llx, id = 0x%x", addr, data, id); 164 165 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, addr >> PAGE_SHIFT, 166 addr & ~PAGE_MASK, synd, 0, 0, -1, priv->message, ""); 167 } 168 169 static irqreturn_t edac_ecc_isr(int irq, void *dev_id) 170 { 171 const struct npcm_platform_data *pdata; 172 struct mem_ctl_info *mci = dev_id; 173 u32 status; 174 175 pdata = ((struct priv_data *)mci->pvt_info)->pdata; 176 regmap_read(npcm_regmap, pdata->ctl_int_status, &status); 177 if (status & pdata->int_status_ce_mask) { 178 handle_ce(mci); 179 180 /* acknowledge the CE interrupt */ 181 regmap_write(npcm_regmap, pdata->ctl_int_ack, 182 pdata->int_ack_ce_mask); 183 return IRQ_HANDLED; 184 } else if (status & pdata->int_status_ue_mask) { 185 handle_ue(mci); 186 187 /* acknowledge the UE interrupt */ 188 regmap_write(npcm_regmap, pdata->ctl_int_ack, 189 pdata->int_ack_ue_mask); 190 return IRQ_HANDLED; 191 } 192 193 WARN_ON_ONCE(1); 194 return IRQ_NONE; 195 } 196 197 static ssize_t force_ecc_error(struct file *file, const char __user *data, 198 size_t count, loff_t *ppos) 199 { 200 struct device *dev = file->private_data; 201 struct mem_ctl_info *mci = to_mci(dev); 202 struct priv_data *priv = mci->pvt_info; 203 const struct npcm_platform_data *pdata; 204 u32 val, syndrome; 205 int ret; 206 207 pdata = priv->pdata; 208 edac_printk(KERN_INFO, EDAC_MOD_NAME, 209 "force an ECC error, type = %d, location = %d, bit = %d\n", 210 priv->error_type, priv->location, priv->bit); 211 212 /* ensure no pending writes */ 213 ret = regmap_read_poll_timeout(npcm_regmap, pdata->ctl_controller_busy, 214 val, !(val & pdata->controller_busy_mask), 215 1000, 10000); 216 if (ret) { 217 edac_printk(KERN_INFO, EDAC_MOD_NAME, 218 "wait pending writes timeout\n"); 219 return count; 220 } 221 222 regmap_read(npcm_regmap, pdata->ctl_xor_check_bits, &val); 223 val &= ~pdata->xor_check_bits_mask; 224 225 /* write syndrome to XOR_CHECK_BITS */ 226 if (priv->error_type == ERROR_TYPE_CORRECTABLE) { 227 if (priv->location == ERROR_LOCATION_DATA && 228 priv->bit > ERROR_BIT_DATA_MAX) { 229 edac_printk(KERN_INFO, EDAC_MOD_NAME, 230 "data bit should not exceed %d (%d)\n", 231 ERROR_BIT_DATA_MAX, priv->bit); 232 return count; 233 } 234 235 if (priv->location == ERROR_LOCATION_CHECKCODE && 236 priv->bit > ERROR_BIT_CHECKCODE_MAX) { 237 edac_printk(KERN_INFO, EDAC_MOD_NAME, 238 "checkcode bit should not exceed %d (%d)\n", 239 ERROR_BIT_CHECKCODE_MAX, priv->bit); 240 return count; 241 } 242 243 syndrome = priv->location ? 1 << priv->bit 244 : data_synd[priv->bit]; 245 246 regmap_write(npcm_regmap, pdata->ctl_xor_check_bits, 247 val | (syndrome << pdata->xor_check_bits_shift) | 248 pdata->writeback_en_mask); 249 } else if (priv->error_type == ERROR_TYPE_UNCORRECTABLE) { 250 regmap_write(npcm_regmap, pdata->ctl_xor_check_bits, 251 val | (UE_SYNDROME << pdata->xor_check_bits_shift)); 252 } 253 254 /* force write check */ 255 regmap_update_bits(npcm_regmap, pdata->ctl_xor_check_bits, 256 pdata->fwc_mask, pdata->fwc_mask); 257 258 return count; 259 } 260 261 static const struct file_operations force_ecc_error_fops = { 262 .open = simple_open, 263 .write = force_ecc_error, 264 .llseek = generic_file_llseek, 265 }; 266 267 /* 268 * Setup debugfs for error injection. 269 * 270 * Nodes: 271 * error_type - 0: CE, 1: UE 272 * location - 0: data, 1: checkcode 273 * bit - 0 ~ 63 for data and 0 ~ 7 for checkcode 274 * force_ecc_error - trigger 275 * 276 * Examples: 277 * 1. Inject a correctable error (CE) at checkcode bit 7. 278 * ~# echo 0 > /sys/kernel/debug/edac/npcm-edac/error_type 279 * ~# echo 1 > /sys/kernel/debug/edac/npcm-edac/location 280 * ~# echo 7 > /sys/kernel/debug/edac/npcm-edac/bit 281 * ~# echo 1 > /sys/kernel/debug/edac/npcm-edac/force_ecc_error 282 * 283 * 2. Inject an uncorrectable error (UE). 284 * ~# echo 1 > /sys/kernel/debug/edac/npcm-edac/error_type 285 * ~# echo 1 > /sys/kernel/debug/edac/npcm-edac/force_ecc_error 286 */ 287 static void setup_debugfs(struct mem_ctl_info *mci) 288 { 289 struct priv_data *priv = mci->pvt_info; 290 291 priv->debugfs = edac_debugfs_create_dir(mci->mod_name); 292 if (!priv->debugfs) 293 return; 294 295 edac_debugfs_create_x8("error_type", 0644, priv->debugfs, &priv->error_type); 296 edac_debugfs_create_x8("location", 0644, priv->debugfs, &priv->location); 297 edac_debugfs_create_x8("bit", 0644, priv->debugfs, &priv->bit); 298 edac_debugfs_create_file("force_ecc_error", 0200, priv->debugfs, 299 &mci->dev, &force_ecc_error_fops); 300 } 301 302 static int setup_irq(struct mem_ctl_info *mci, struct platform_device *pdev) 303 { 304 const struct npcm_platform_data *pdata; 305 int ret, irq; 306 307 pdata = ((struct priv_data *)mci->pvt_info)->pdata; 308 irq = platform_get_irq(pdev, 0); 309 if (irq < 0) { 310 edac_printk(KERN_ERR, EDAC_MOD_NAME, "IRQ not defined in DTS\n"); 311 return irq; 312 } 313 314 ret = devm_request_irq(&pdev->dev, irq, edac_ecc_isr, 0, 315 dev_name(&pdev->dev), mci); 316 if (ret < 0) { 317 edac_printk(KERN_ERR, EDAC_MOD_NAME, "failed to request IRQ\n"); 318 return ret; 319 } 320 321 /* enable the functional group of ECC and mask the others */ 322 regmap_write(npcm_regmap, pdata->ctl_int_mask_master, 323 pdata->int_mask_master_non_ecc_mask); 324 325 if (pdata->chip == NPCM8XX_CHIP) 326 regmap_write(npcm_regmap, pdata->ctl_int_mask_ecc, 327 pdata->int_mask_ecc_non_event_mask); 328 329 return 0; 330 } 331 332 static const struct regmap_config npcm_regmap_cfg = { 333 .reg_bits = 32, 334 .reg_stride = 4, 335 .val_bits = 32, 336 }; 337 338 static int edac_probe(struct platform_device *pdev) 339 { 340 const struct npcm_platform_data *pdata; 341 struct device *dev = &pdev->dev; 342 struct edac_mc_layer layers[1]; 343 struct mem_ctl_info *mci; 344 struct priv_data *priv; 345 void __iomem *reg; 346 u32 val; 347 int rc; 348 349 reg = devm_platform_ioremap_resource(pdev, 0); 350 if (IS_ERR(reg)) 351 return PTR_ERR(reg); 352 353 npcm_regmap = devm_regmap_init_mmio(dev, reg, &npcm_regmap_cfg); 354 if (IS_ERR(npcm_regmap)) 355 return PTR_ERR(npcm_regmap); 356 357 pdata = of_device_get_match_data(dev); 358 if (!pdata) 359 return -EINVAL; 360 361 /* bail out if ECC is not enabled */ 362 regmap_read(npcm_regmap, pdata->ctl_ecc_en, &val); 363 if (!(val & pdata->ecc_en_mask)) { 364 edac_printk(KERN_ERR, EDAC_MOD_NAME, "ECC is not enabled\n"); 365 return -EPERM; 366 } 367 368 edac_op_state = EDAC_OPSTATE_INT; 369 370 layers[0].type = EDAC_MC_LAYER_ALL_MEM; 371 layers[0].size = 1; 372 373 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 374 sizeof(struct priv_data)); 375 if (!mci) 376 return -ENOMEM; 377 378 mci->pdev = &pdev->dev; 379 priv = mci->pvt_info; 380 priv->reg = reg; 381 priv->pdata = pdata; 382 platform_set_drvdata(pdev, mci); 383 384 mci->mtype_cap = MEM_FLAG_DDR4; 385 mci->edac_ctl_cap = EDAC_FLAG_SECDED; 386 mci->scrub_cap = SCRUB_FLAG_HW_SRC; 387 mci->scrub_mode = SCRUB_HW_SRC; 388 mci->edac_cap = EDAC_FLAG_SECDED; 389 mci->ctl_name = "npcm_ddr_controller"; 390 mci->dev_name = dev_name(&pdev->dev); 391 mci->mod_name = EDAC_MOD_NAME; 392 mci->ctl_page_to_phys = NULL; 393 394 rc = setup_irq(mci, pdev); 395 if (rc) 396 goto free_edac_mc; 397 398 rc = edac_mc_add_mc(mci); 399 if (rc) 400 goto free_edac_mc; 401 402 if (IS_ENABLED(CONFIG_EDAC_DEBUG) && pdata->chip == NPCM8XX_CHIP) 403 setup_debugfs(mci); 404 405 return rc; 406 407 free_edac_mc: 408 edac_mc_free(mci); 409 return rc; 410 } 411 412 static int edac_remove(struct platform_device *pdev) 413 { 414 struct mem_ctl_info *mci = platform_get_drvdata(pdev); 415 struct priv_data *priv = mci->pvt_info; 416 const struct npcm_platform_data *pdata; 417 418 pdata = priv->pdata; 419 if (IS_ENABLED(CONFIG_EDAC_DEBUG) && pdata->chip == NPCM8XX_CHIP) 420 edac_debugfs_remove_recursive(priv->debugfs); 421 422 edac_mc_del_mc(&pdev->dev); 423 edac_mc_free(mci); 424 425 regmap_write(npcm_regmap, pdata->ctl_int_mask_master, 426 pdata->int_mask_master_global_mask); 427 regmap_update_bits(npcm_regmap, pdata->ctl_ecc_en, pdata->ecc_en_mask, 0); 428 429 return 0; 430 } 431 432 static const struct npcm_platform_data npcm750_edac = { 433 .chip = NPCM7XX_CHIP, 434 435 /* memory controller registers */ 436 .ctl_ecc_en = 0x174, 437 .ctl_int_status = 0x1d0, 438 .ctl_int_ack = 0x1d4, 439 .ctl_int_mask_master = 0x1d8, 440 .ctl_ce_addr_l = 0x188, 441 .ctl_ce_data_l = 0x190, 442 .ctl_ce_synd = 0x18c, 443 .ctl_ue_addr_l = 0x17c, 444 .ctl_ue_data_l = 0x184, 445 .ctl_ue_synd = 0x180, 446 .ctl_source_id = 0x194, 447 448 /* masks and shifts */ 449 .ecc_en_mask = BIT(24), 450 .int_status_ce_mask = GENMASK(4, 3), 451 .int_status_ue_mask = GENMASK(6, 5), 452 .int_ack_ce_mask = GENMASK(4, 3), 453 .int_ack_ue_mask = GENMASK(6, 5), 454 .int_mask_master_non_ecc_mask = GENMASK(30, 7) | GENMASK(2, 0), 455 .int_mask_master_global_mask = BIT(31), 456 .ce_synd_mask = GENMASK(6, 0), 457 .ce_synd_shift = 0, 458 .ue_synd_mask = GENMASK(6, 0), 459 .ue_synd_shift = 0, 460 .source_id_ce_mask = GENMASK(29, 16), 461 .source_id_ce_shift = 16, 462 .source_id_ue_mask = GENMASK(13, 0), 463 .source_id_ue_shift = 0, 464 }; 465 466 static const struct npcm_platform_data npcm845_edac = { 467 .chip = NPCM8XX_CHIP, 468 469 /* memory controller registers */ 470 .ctl_ecc_en = 0x16c, 471 .ctl_int_status = 0x228, 472 .ctl_int_ack = 0x244, 473 .ctl_int_mask_master = 0x220, 474 .ctl_int_mask_ecc = 0x260, 475 .ctl_ce_addr_l = 0x18c, 476 .ctl_ce_addr_h = 0x190, 477 .ctl_ce_data_l = 0x194, 478 .ctl_ce_data_h = 0x198, 479 .ctl_ce_synd = 0x190, 480 .ctl_ue_addr_l = 0x17c, 481 .ctl_ue_addr_h = 0x180, 482 .ctl_ue_data_l = 0x184, 483 .ctl_ue_data_h = 0x188, 484 .ctl_ue_synd = 0x180, 485 .ctl_source_id = 0x19c, 486 .ctl_controller_busy = 0x20c, 487 .ctl_xor_check_bits = 0x174, 488 489 /* masks and shifts */ 490 .ecc_en_mask = GENMASK(17, 16), 491 .int_status_ce_mask = GENMASK(1, 0), 492 .int_status_ue_mask = GENMASK(3, 2), 493 .int_ack_ce_mask = GENMASK(1, 0), 494 .int_ack_ue_mask = GENMASK(3, 2), 495 .int_mask_master_non_ecc_mask = GENMASK(30, 3) | GENMASK(1, 0), 496 .int_mask_master_global_mask = BIT(31), 497 .int_mask_ecc_non_event_mask = GENMASK(8, 4), 498 .ce_addr_h_mask = GENMASK(1, 0), 499 .ce_synd_mask = GENMASK(15, 8), 500 .ce_synd_shift = 8, 501 .ue_addr_h_mask = GENMASK(1, 0), 502 .ue_synd_mask = GENMASK(15, 8), 503 .ue_synd_shift = 8, 504 .source_id_ce_mask = GENMASK(29, 16), 505 .source_id_ce_shift = 16, 506 .source_id_ue_mask = GENMASK(13, 0), 507 .source_id_ue_shift = 0, 508 .controller_busy_mask = BIT(0), 509 .xor_check_bits_mask = GENMASK(23, 16), 510 .xor_check_bits_shift = 16, 511 .writeback_en_mask = BIT(24), 512 .fwc_mask = BIT(8), 513 }; 514 515 static const struct of_device_id npcm_edac_of_match[] = { 516 { 517 .compatible = "nuvoton,npcm750-memory-controller", 518 .data = &npcm750_edac 519 }, 520 { 521 .compatible = "nuvoton,npcm845-memory-controller", 522 .data = &npcm845_edac 523 }, 524 {}, 525 }; 526 527 MODULE_DEVICE_TABLE(of, npcm_edac_of_match); 528 529 static struct platform_driver npcm_edac_driver = { 530 .driver = { 531 .name = "npcm-edac", 532 .of_match_table = npcm_edac_of_match, 533 }, 534 .probe = edac_probe, 535 .remove = edac_remove, 536 }; 537 538 module_platform_driver(npcm_edac_driver); 539 540 MODULE_AUTHOR("Medad CChien <medadyoung@gmail.com>"); 541 MODULE_AUTHOR("Marvin Lin <kflin@nuvoton.com>"); 542 MODULE_DESCRIPTION("Nuvoton NPCM EDAC Driver"); 543 MODULE_LICENSE("GPL"); 544