1 /* 2 * Freescale MPC85xx Memory Controller kenel module 3 * 4 * Parts Copyrighted (c) 2013 by Freescale Semiconductor, Inc. 5 * 6 * Author: Dave Jiang <djiang@mvista.com> 7 * 8 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under 9 * the terms of the GNU General Public License version 2. This program 10 * is licensed "as is" without any warranty of any kind, whether express 11 * or implied. 12 * 13 */ 14 #include <linux/module.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/ctype.h> 18 #include <linux/io.h> 19 #include <linux/mod_devicetable.h> 20 #include <linux/edac.h> 21 #include <linux/smp.h> 22 #include <linux/gfp.h> 23 24 #include <linux/of_platform.h> 25 #include <linux/of_device.h> 26 #include "edac_module.h" 27 #include "edac_core.h" 28 #include "mpc85xx_edac.h" 29 30 static int edac_dev_idx; 31 #ifdef CONFIG_PCI 32 static int edac_pci_idx; 33 #endif 34 static int edac_mc_idx; 35 36 static u32 orig_ddr_err_disable; 37 static u32 orig_ddr_err_sbe; 38 39 /* 40 * PCI Err defines 41 */ 42 #ifdef CONFIG_PCI 43 static u32 orig_pci_err_cap_dr; 44 static u32 orig_pci_err_en; 45 #endif 46 47 static u32 orig_l2_err_disable; 48 #ifdef CONFIG_FSL_SOC_BOOKE 49 static u32 orig_hid1[2]; 50 #endif 51 52 /************************ MC SYSFS parts ***********************************/ 53 54 #define to_mci(k) container_of(k, struct mem_ctl_info, dev) 55 56 static ssize_t mpc85xx_mc_inject_data_hi_show(struct device *dev, 57 struct device_attribute *mattr, 58 char *data) 59 { 60 struct mem_ctl_info *mci = to_mci(dev); 61 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 62 return sprintf(data, "0x%08x", 63 in_be32(pdata->mc_vbase + 64 MPC85XX_MC_DATA_ERR_INJECT_HI)); 65 } 66 67 static ssize_t mpc85xx_mc_inject_data_lo_show(struct device *dev, 68 struct device_attribute *mattr, 69 char *data) 70 { 71 struct mem_ctl_info *mci = to_mci(dev); 72 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 73 return sprintf(data, "0x%08x", 74 in_be32(pdata->mc_vbase + 75 MPC85XX_MC_DATA_ERR_INJECT_LO)); 76 } 77 78 static ssize_t mpc85xx_mc_inject_ctrl_show(struct device *dev, 79 struct device_attribute *mattr, 80 char *data) 81 { 82 struct mem_ctl_info *mci = to_mci(dev); 83 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 84 return sprintf(data, "0x%08x", 85 in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT)); 86 } 87 88 static ssize_t mpc85xx_mc_inject_data_hi_store(struct device *dev, 89 struct device_attribute *mattr, 90 const char *data, size_t count) 91 { 92 struct mem_ctl_info *mci = to_mci(dev); 93 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 94 if (isdigit(*data)) { 95 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI, 96 simple_strtoul(data, NULL, 0)); 97 return count; 98 } 99 return 0; 100 } 101 102 static ssize_t mpc85xx_mc_inject_data_lo_store(struct device *dev, 103 struct device_attribute *mattr, 104 const char *data, size_t count) 105 { 106 struct mem_ctl_info *mci = to_mci(dev); 107 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 108 if (isdigit(*data)) { 109 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO, 110 simple_strtoul(data, NULL, 0)); 111 return count; 112 } 113 return 0; 114 } 115 116 static ssize_t mpc85xx_mc_inject_ctrl_store(struct device *dev, 117 struct device_attribute *mattr, 118 const char *data, size_t count) 119 { 120 struct mem_ctl_info *mci = to_mci(dev); 121 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 122 if (isdigit(*data)) { 123 out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT, 124 simple_strtoul(data, NULL, 0)); 125 return count; 126 } 127 return 0; 128 } 129 130 DEVICE_ATTR(inject_data_hi, S_IRUGO | S_IWUSR, 131 mpc85xx_mc_inject_data_hi_show, mpc85xx_mc_inject_data_hi_store); 132 DEVICE_ATTR(inject_data_lo, S_IRUGO | S_IWUSR, 133 mpc85xx_mc_inject_data_lo_show, mpc85xx_mc_inject_data_lo_store); 134 DEVICE_ATTR(inject_ctrl, S_IRUGO | S_IWUSR, 135 mpc85xx_mc_inject_ctrl_show, mpc85xx_mc_inject_ctrl_store); 136 137 static int mpc85xx_create_sysfs_attributes(struct mem_ctl_info *mci) 138 { 139 int rc; 140 141 rc = device_create_file(&mci->dev, &dev_attr_inject_data_hi); 142 if (rc < 0) 143 return rc; 144 rc = device_create_file(&mci->dev, &dev_attr_inject_data_lo); 145 if (rc < 0) 146 return rc; 147 rc = device_create_file(&mci->dev, &dev_attr_inject_ctrl); 148 if (rc < 0) 149 return rc; 150 151 return 0; 152 } 153 154 static void mpc85xx_remove_sysfs_attributes(struct mem_ctl_info *mci) 155 { 156 device_remove_file(&mci->dev, &dev_attr_inject_data_hi); 157 device_remove_file(&mci->dev, &dev_attr_inject_data_lo); 158 device_remove_file(&mci->dev, &dev_attr_inject_ctrl); 159 } 160 161 /**************************** PCI Err device ***************************/ 162 #ifdef CONFIG_PCI 163 164 static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci) 165 { 166 struct mpc85xx_pci_pdata *pdata = pci->pvt_info; 167 u32 err_detect; 168 169 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); 170 171 /* master aborts can happen during PCI config cycles */ 172 if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) { 173 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); 174 return; 175 } 176 177 printk(KERN_ERR "PCI error(s) detected\n"); 178 printk(KERN_ERR "PCI/X ERR_DR register: %#08x\n", err_detect); 179 180 printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x\n", 181 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB)); 182 printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x\n", 183 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR)); 184 printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x\n", 185 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR)); 186 printk(KERN_ERR "PCI/X ERR_DL register: %#08x\n", 187 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL)); 188 printk(KERN_ERR "PCI/X ERR_DH register: %#08x\n", 189 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH)); 190 191 /* clear error bits */ 192 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); 193 194 if (err_detect & PCI_EDE_PERR_MASK) 195 edac_pci_handle_pe(pci, pci->ctl_name); 196 197 if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK) 198 edac_pci_handle_npe(pci, pci->ctl_name); 199 } 200 201 static void mpc85xx_pcie_check(struct edac_pci_ctl_info *pci) 202 { 203 struct mpc85xx_pci_pdata *pdata = pci->pvt_info; 204 u32 err_detect; 205 206 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); 207 208 pr_err("PCIe error(s) detected\n"); 209 pr_err("PCIe ERR_DR register: 0x%08x\n", err_detect); 210 pr_err("PCIe ERR_CAP_STAT register: 0x%08x\n", 211 in_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR)); 212 pr_err("PCIe ERR_CAP_R0 register: 0x%08x\n", 213 in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R0)); 214 pr_err("PCIe ERR_CAP_R1 register: 0x%08x\n", 215 in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R1)); 216 pr_err("PCIe ERR_CAP_R2 register: 0x%08x\n", 217 in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R2)); 218 pr_err("PCIe ERR_CAP_R3 register: 0x%08x\n", 219 in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R3)); 220 221 /* clear error bits */ 222 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); 223 } 224 225 static int mpc85xx_pcie_find_capability(struct device_node *np) 226 { 227 struct pci_controller *hose; 228 229 if (!np) 230 return -EINVAL; 231 232 hose = pci_find_hose_for_OF_device(np); 233 234 return early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP); 235 } 236 237 static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id) 238 { 239 struct edac_pci_ctl_info *pci = dev_id; 240 struct mpc85xx_pci_pdata *pdata = pci->pvt_info; 241 u32 err_detect; 242 243 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); 244 245 if (!err_detect) 246 return IRQ_NONE; 247 248 if (pdata->is_pcie) 249 mpc85xx_pcie_check(pci); 250 else 251 mpc85xx_pci_check(pci); 252 253 return IRQ_HANDLED; 254 } 255 256 int mpc85xx_pci_err_probe(struct platform_device *op) 257 { 258 struct edac_pci_ctl_info *pci; 259 struct mpc85xx_pci_pdata *pdata; 260 struct resource r; 261 int res = 0; 262 263 if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL)) 264 return -ENOMEM; 265 266 pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err"); 267 if (!pci) 268 return -ENOMEM; 269 270 /* make sure error reporting method is sane */ 271 switch (edac_op_state) { 272 case EDAC_OPSTATE_POLL: 273 case EDAC_OPSTATE_INT: 274 break; 275 default: 276 edac_op_state = EDAC_OPSTATE_INT; 277 break; 278 } 279 280 pdata = pci->pvt_info; 281 pdata->name = "mpc85xx_pci_err"; 282 pdata->irq = NO_IRQ; 283 284 if (mpc85xx_pcie_find_capability(op->dev.of_node) > 0) 285 pdata->is_pcie = true; 286 287 dev_set_drvdata(&op->dev, pci); 288 pci->dev = &op->dev; 289 pci->mod_name = EDAC_MOD_STR; 290 pci->ctl_name = pdata->name; 291 pci->dev_name = dev_name(&op->dev); 292 293 if (edac_op_state == EDAC_OPSTATE_POLL) { 294 if (pdata->is_pcie) 295 pci->edac_check = mpc85xx_pcie_check; 296 else 297 pci->edac_check = mpc85xx_pci_check; 298 } 299 300 pdata->edac_idx = edac_pci_idx++; 301 302 res = of_address_to_resource(op->dev.of_node, 0, &r); 303 if (res) { 304 printk(KERN_ERR "%s: Unable to get resource for " 305 "PCI err regs\n", __func__); 306 goto err; 307 } 308 309 /* we only need the error registers */ 310 r.start += 0xe00; 311 312 if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r), 313 pdata->name)) { 314 printk(KERN_ERR "%s: Error while requesting mem region\n", 315 __func__); 316 res = -EBUSY; 317 goto err; 318 } 319 320 pdata->pci_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r)); 321 if (!pdata->pci_vbase) { 322 printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__); 323 res = -ENOMEM; 324 goto err; 325 } 326 327 if (pdata->is_pcie) { 328 orig_pci_err_cap_dr = 329 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR); 330 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, ~0); 331 orig_pci_err_en = 332 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN); 333 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, 0); 334 } else { 335 orig_pci_err_cap_dr = 336 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR); 337 338 /* PCI master abort is expected during config cycles */ 339 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40); 340 341 orig_pci_err_en = 342 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN); 343 344 /* disable master abort reporting */ 345 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40); 346 } 347 348 /* clear error bits */ 349 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0); 350 351 if (edac_pci_add_device(pci, pdata->edac_idx) > 0) { 352 edac_dbg(3, "failed edac_pci_add_device()\n"); 353 goto err; 354 } 355 356 if (edac_op_state == EDAC_OPSTATE_INT) { 357 pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0); 358 res = devm_request_irq(&op->dev, pdata->irq, 359 mpc85xx_pci_isr, 360 IRQF_SHARED, 361 "[EDAC] PCI err", pci); 362 if (res < 0) { 363 printk(KERN_ERR 364 "%s: Unable to request irq %d for " 365 "MPC85xx PCI err\n", __func__, pdata->irq); 366 irq_dispose_mapping(pdata->irq); 367 res = -ENODEV; 368 goto err2; 369 } 370 371 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for PCI Err\n", 372 pdata->irq); 373 } 374 375 if (pdata->is_pcie) { 376 /* 377 * Enable all PCIe error interrupt & error detect except invalid 378 * PEX_CONFIG_ADDR/PEX_CONFIG_DATA access interrupt generation 379 * enable bit and invalid PEX_CONFIG_ADDR/PEX_CONFIG_DATA access 380 * detection enable bit. Because PCIe bus code to initialize and 381 * configure these PCIe devices on booting will use some invalid 382 * PEX_CONFIG_ADDR/PEX_CONFIG_DATA, edac driver prints the much 383 * notice information. So disable this detect to fix ugly print. 384 */ 385 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0 386 & ~PEX_ERR_ICCAIE_EN_BIT); 387 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, 0 388 | PEX_ERR_ICCAD_DISR_BIT); 389 } 390 391 devres_remove_group(&op->dev, mpc85xx_pci_err_probe); 392 edac_dbg(3, "success\n"); 393 printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n"); 394 395 return 0; 396 397 err2: 398 edac_pci_del_device(&op->dev); 399 err: 400 edac_pci_free_ctl_info(pci); 401 devres_release_group(&op->dev, mpc85xx_pci_err_probe); 402 return res; 403 } 404 EXPORT_SYMBOL(mpc85xx_pci_err_probe); 405 406 #endif /* CONFIG_PCI */ 407 408 /**************************** L2 Err device ***************************/ 409 410 /************************ L2 SYSFS parts ***********************************/ 411 412 static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info 413 *edac_dev, char *data) 414 { 415 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 416 return sprintf(data, "0x%08x", 417 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI)); 418 } 419 420 static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info 421 *edac_dev, char *data) 422 { 423 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 424 return sprintf(data, "0x%08x", 425 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO)); 426 } 427 428 static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info 429 *edac_dev, char *data) 430 { 431 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 432 return sprintf(data, "0x%08x", 433 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL)); 434 } 435 436 static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info 437 *edac_dev, const char *data, 438 size_t count) 439 { 440 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 441 if (isdigit(*data)) { 442 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI, 443 simple_strtoul(data, NULL, 0)); 444 return count; 445 } 446 return 0; 447 } 448 449 static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info 450 *edac_dev, const char *data, 451 size_t count) 452 { 453 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 454 if (isdigit(*data)) { 455 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO, 456 simple_strtoul(data, NULL, 0)); 457 return count; 458 } 459 return 0; 460 } 461 462 static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info 463 *edac_dev, const char *data, 464 size_t count) 465 { 466 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 467 if (isdigit(*data)) { 468 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL, 469 simple_strtoul(data, NULL, 0)); 470 return count; 471 } 472 return 0; 473 } 474 475 static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = { 476 { 477 .attr = { 478 .name = "inject_data_hi", 479 .mode = (S_IRUGO | S_IWUSR) 480 }, 481 .show = mpc85xx_l2_inject_data_hi_show, 482 .store = mpc85xx_l2_inject_data_hi_store}, 483 { 484 .attr = { 485 .name = "inject_data_lo", 486 .mode = (S_IRUGO | S_IWUSR) 487 }, 488 .show = mpc85xx_l2_inject_data_lo_show, 489 .store = mpc85xx_l2_inject_data_lo_store}, 490 { 491 .attr = { 492 .name = "inject_ctrl", 493 .mode = (S_IRUGO | S_IWUSR) 494 }, 495 .show = mpc85xx_l2_inject_ctrl_show, 496 .store = mpc85xx_l2_inject_ctrl_store}, 497 498 /* End of list */ 499 { 500 .attr = {.name = NULL} 501 } 502 }; 503 504 static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info 505 *edac_dev) 506 { 507 edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes; 508 } 509 510 /***************************** L2 ops ***********************************/ 511 512 static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev) 513 { 514 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 515 u32 err_detect; 516 517 err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET); 518 519 if (!(err_detect & L2_EDE_MASK)) 520 return; 521 522 printk(KERN_ERR "ECC Error in CPU L2 cache\n"); 523 printk(KERN_ERR "L2 Error Detect Register: 0x%08x\n", err_detect); 524 printk(KERN_ERR "L2 Error Capture Data High Register: 0x%08x\n", 525 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI)); 526 printk(KERN_ERR "L2 Error Capture Data Lo Register: 0x%08x\n", 527 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO)); 528 printk(KERN_ERR "L2 Error Syndrome Register: 0x%08x\n", 529 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC)); 530 printk(KERN_ERR "L2 Error Attributes Capture Register: 0x%08x\n", 531 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR)); 532 printk(KERN_ERR "L2 Error Address Capture Register: 0x%08x\n", 533 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR)); 534 535 /* clear error detect register */ 536 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect); 537 538 if (err_detect & L2_EDE_CE_MASK) 539 edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name); 540 541 if (err_detect & L2_EDE_UE_MASK) 542 edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name); 543 } 544 545 static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id) 546 { 547 struct edac_device_ctl_info *edac_dev = dev_id; 548 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 549 u32 err_detect; 550 551 err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET); 552 553 if (!(err_detect & L2_EDE_MASK)) 554 return IRQ_NONE; 555 556 mpc85xx_l2_check(edac_dev); 557 558 return IRQ_HANDLED; 559 } 560 561 static int mpc85xx_l2_err_probe(struct platform_device *op) 562 { 563 struct edac_device_ctl_info *edac_dev; 564 struct mpc85xx_l2_pdata *pdata; 565 struct resource r; 566 int res; 567 568 if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL)) 569 return -ENOMEM; 570 571 edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata), 572 "cpu", 1, "L", 1, 2, NULL, 0, 573 edac_dev_idx); 574 if (!edac_dev) { 575 devres_release_group(&op->dev, mpc85xx_l2_err_probe); 576 return -ENOMEM; 577 } 578 579 pdata = edac_dev->pvt_info; 580 pdata->name = "mpc85xx_l2_err"; 581 pdata->irq = NO_IRQ; 582 edac_dev->dev = &op->dev; 583 dev_set_drvdata(edac_dev->dev, edac_dev); 584 edac_dev->ctl_name = pdata->name; 585 edac_dev->dev_name = pdata->name; 586 587 res = of_address_to_resource(op->dev.of_node, 0, &r); 588 if (res) { 589 printk(KERN_ERR "%s: Unable to get resource for " 590 "L2 err regs\n", __func__); 591 goto err; 592 } 593 594 /* we only need the error registers */ 595 r.start += 0xe00; 596 597 if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r), 598 pdata->name)) { 599 printk(KERN_ERR "%s: Error while requesting mem region\n", 600 __func__); 601 res = -EBUSY; 602 goto err; 603 } 604 605 pdata->l2_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r)); 606 if (!pdata->l2_vbase) { 607 printk(KERN_ERR "%s: Unable to setup L2 err regs\n", __func__); 608 res = -ENOMEM; 609 goto err; 610 } 611 612 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0); 613 614 orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS); 615 616 /* clear the err_dis */ 617 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0); 618 619 edac_dev->mod_name = EDAC_MOD_STR; 620 621 if (edac_op_state == EDAC_OPSTATE_POLL) 622 edac_dev->edac_check = mpc85xx_l2_check; 623 624 mpc85xx_set_l2_sysfs_attributes(edac_dev); 625 626 pdata->edac_idx = edac_dev_idx++; 627 628 if (edac_device_add_device(edac_dev) > 0) { 629 edac_dbg(3, "failed edac_device_add_device()\n"); 630 goto err; 631 } 632 633 if (edac_op_state == EDAC_OPSTATE_INT) { 634 pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0); 635 res = devm_request_irq(&op->dev, pdata->irq, 636 mpc85xx_l2_isr, IRQF_SHARED, 637 "[EDAC] L2 err", edac_dev); 638 if (res < 0) { 639 printk(KERN_ERR 640 "%s: Unable to request irq %d for " 641 "MPC85xx L2 err\n", __func__, pdata->irq); 642 irq_dispose_mapping(pdata->irq); 643 res = -ENODEV; 644 goto err2; 645 } 646 647 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for L2 Err\n", 648 pdata->irq); 649 650 edac_dev->op_state = OP_RUNNING_INTERRUPT; 651 652 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK); 653 } 654 655 devres_remove_group(&op->dev, mpc85xx_l2_err_probe); 656 657 edac_dbg(3, "success\n"); 658 printk(KERN_INFO EDAC_MOD_STR " L2 err registered\n"); 659 660 return 0; 661 662 err2: 663 edac_device_del_device(&op->dev); 664 err: 665 devres_release_group(&op->dev, mpc85xx_l2_err_probe); 666 edac_device_free_ctl_info(edac_dev); 667 return res; 668 } 669 670 static int mpc85xx_l2_err_remove(struct platform_device *op) 671 { 672 struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev); 673 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 674 675 edac_dbg(0, "\n"); 676 677 if (edac_op_state == EDAC_OPSTATE_INT) { 678 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0); 679 irq_dispose_mapping(pdata->irq); 680 } 681 682 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable); 683 edac_device_del_device(&op->dev); 684 edac_device_free_ctl_info(edac_dev); 685 return 0; 686 } 687 688 static struct of_device_id mpc85xx_l2_err_of_match[] = { 689 /* deprecate the fsl,85.. forms in the future, 2.6.30? */ 690 { .compatible = "fsl,8540-l2-cache-controller", }, 691 { .compatible = "fsl,8541-l2-cache-controller", }, 692 { .compatible = "fsl,8544-l2-cache-controller", }, 693 { .compatible = "fsl,8548-l2-cache-controller", }, 694 { .compatible = "fsl,8555-l2-cache-controller", }, 695 { .compatible = "fsl,8568-l2-cache-controller", }, 696 { .compatible = "fsl,mpc8536-l2-cache-controller", }, 697 { .compatible = "fsl,mpc8540-l2-cache-controller", }, 698 { .compatible = "fsl,mpc8541-l2-cache-controller", }, 699 { .compatible = "fsl,mpc8544-l2-cache-controller", }, 700 { .compatible = "fsl,mpc8548-l2-cache-controller", }, 701 { .compatible = "fsl,mpc8555-l2-cache-controller", }, 702 { .compatible = "fsl,mpc8560-l2-cache-controller", }, 703 { .compatible = "fsl,mpc8568-l2-cache-controller", }, 704 { .compatible = "fsl,mpc8569-l2-cache-controller", }, 705 { .compatible = "fsl,mpc8572-l2-cache-controller", }, 706 { .compatible = "fsl,p1020-l2-cache-controller", }, 707 { .compatible = "fsl,p1021-l2-cache-controller", }, 708 { .compatible = "fsl,p2020-l2-cache-controller", }, 709 {}, 710 }; 711 MODULE_DEVICE_TABLE(of, mpc85xx_l2_err_of_match); 712 713 static struct platform_driver mpc85xx_l2_err_driver = { 714 .probe = mpc85xx_l2_err_probe, 715 .remove = mpc85xx_l2_err_remove, 716 .driver = { 717 .name = "mpc85xx_l2_err", 718 .owner = THIS_MODULE, 719 .of_match_table = mpc85xx_l2_err_of_match, 720 }, 721 }; 722 723 /**************************** MC Err device ***************************/ 724 725 /* 726 * Taken from table 8-55 in the MPC8641 User's Manual and/or 9-61 in the 727 * MPC8572 User's Manual. Each line represents a syndrome bit column as a 728 * 64-bit value, but split into an upper and lower 32-bit chunk. The labels 729 * below correspond to Freescale's manuals. 730 */ 731 static unsigned int ecc_table[16] = { 732 /* MSB LSB */ 733 /* [0:31] [32:63] */ 734 0xf00fe11e, 0xc33c0ff7, /* Syndrome bit 7 */ 735 0x00ff00ff, 0x00fff0ff, 736 0x0f0f0f0f, 0x0f0fff00, 737 0x11113333, 0x7777000f, 738 0x22224444, 0x8888222f, 739 0x44448888, 0xffff4441, 740 0x8888ffff, 0x11118882, 741 0xffff1111, 0x22221114, /* Syndrome bit 0 */ 742 }; 743 744 /* 745 * Calculate the correct ECC value for a 64-bit value specified by high:low 746 */ 747 static u8 calculate_ecc(u32 high, u32 low) 748 { 749 u32 mask_low; 750 u32 mask_high; 751 int bit_cnt; 752 u8 ecc = 0; 753 int i; 754 int j; 755 756 for (i = 0; i < 8; i++) { 757 mask_high = ecc_table[i * 2]; 758 mask_low = ecc_table[i * 2 + 1]; 759 bit_cnt = 0; 760 761 for (j = 0; j < 32; j++) { 762 if ((mask_high >> j) & 1) 763 bit_cnt ^= (high >> j) & 1; 764 if ((mask_low >> j) & 1) 765 bit_cnt ^= (low >> j) & 1; 766 } 767 768 ecc |= bit_cnt << i; 769 } 770 771 return ecc; 772 } 773 774 /* 775 * Create the syndrome code which is generated if the data line specified by 776 * 'bit' failed. Eg generate an 8-bit codes seen in Table 8-55 in the MPC8641 777 * User's Manual and 9-61 in the MPC8572 User's Manual. 778 */ 779 static u8 syndrome_from_bit(unsigned int bit) { 780 int i; 781 u8 syndrome = 0; 782 783 /* 784 * Cycle through the upper or lower 32-bit portion of each value in 785 * ecc_table depending on if 'bit' is in the upper or lower half of 786 * 64-bit data. 787 */ 788 for (i = bit < 32; i < 16; i += 2) 789 syndrome |= ((ecc_table[i] >> (bit % 32)) & 1) << (i / 2); 790 791 return syndrome; 792 } 793 794 /* 795 * Decode data and ecc syndrome to determine what went wrong 796 * Note: This can only decode single-bit errors 797 */ 798 static void sbe_ecc_decode(u32 cap_high, u32 cap_low, u32 cap_ecc, 799 int *bad_data_bit, int *bad_ecc_bit) 800 { 801 int i; 802 u8 syndrome; 803 804 *bad_data_bit = -1; 805 *bad_ecc_bit = -1; 806 807 /* 808 * Calculate the ECC of the captured data and XOR it with the captured 809 * ECC to find an ECC syndrome value we can search for 810 */ 811 syndrome = calculate_ecc(cap_high, cap_low) ^ cap_ecc; 812 813 /* Check if a data line is stuck... */ 814 for (i = 0; i < 64; i++) { 815 if (syndrome == syndrome_from_bit(i)) { 816 *bad_data_bit = i; 817 return; 818 } 819 } 820 821 /* If data is correct, check ECC bits for errors... */ 822 for (i = 0; i < 8; i++) { 823 if ((syndrome >> i) & 0x1) { 824 *bad_ecc_bit = i; 825 return; 826 } 827 } 828 } 829 830 static void mpc85xx_mc_check(struct mem_ctl_info *mci) 831 { 832 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 833 struct csrow_info *csrow; 834 u32 bus_width; 835 u32 err_detect; 836 u32 syndrome; 837 u32 err_addr; 838 u32 pfn; 839 int row_index; 840 u32 cap_high; 841 u32 cap_low; 842 int bad_data_bit; 843 int bad_ecc_bit; 844 845 err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT); 846 if (!err_detect) 847 return; 848 849 mpc85xx_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n", 850 err_detect); 851 852 /* no more processing if not ECC bit errors */ 853 if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) { 854 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect); 855 return; 856 } 857 858 syndrome = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ECC); 859 860 /* Mask off appropriate bits of syndrome based on bus width */ 861 bus_width = (in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG) & 862 DSC_DBW_MASK) ? 32 : 64; 863 if (bus_width == 64) 864 syndrome &= 0xff; 865 else 866 syndrome &= 0xffff; 867 868 err_addr = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ADDRESS); 869 pfn = err_addr >> PAGE_SHIFT; 870 871 for (row_index = 0; row_index < mci->nr_csrows; row_index++) { 872 csrow = mci->csrows[row_index]; 873 if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page)) 874 break; 875 } 876 877 cap_high = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_HI); 878 cap_low = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_LO); 879 880 /* 881 * Analyze single-bit errors on 64-bit wide buses 882 * TODO: Add support for 32-bit wide buses 883 */ 884 if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) { 885 sbe_ecc_decode(cap_high, cap_low, syndrome, 886 &bad_data_bit, &bad_ecc_bit); 887 888 if (bad_data_bit != -1) 889 mpc85xx_mc_printk(mci, KERN_ERR, 890 "Faulty Data bit: %d\n", bad_data_bit); 891 if (bad_ecc_bit != -1) 892 mpc85xx_mc_printk(mci, KERN_ERR, 893 "Faulty ECC bit: %d\n", bad_ecc_bit); 894 895 mpc85xx_mc_printk(mci, KERN_ERR, 896 "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n", 897 cap_high ^ (1 << (bad_data_bit - 32)), 898 cap_low ^ (1 << bad_data_bit), 899 syndrome ^ (1 << bad_ecc_bit)); 900 } 901 902 mpc85xx_mc_printk(mci, KERN_ERR, 903 "Captured Data / ECC:\t%#8.8x_%08x / %#2.2x\n", 904 cap_high, cap_low, syndrome); 905 mpc85xx_mc_printk(mci, KERN_ERR, "Err addr: %#8.8x\n", err_addr); 906 mpc85xx_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn); 907 908 /* we are out of range */ 909 if (row_index == mci->nr_csrows) 910 mpc85xx_mc_printk(mci, KERN_ERR, "PFN out of range!\n"); 911 912 if (err_detect & DDR_EDE_SBE) 913 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 914 pfn, err_addr & ~PAGE_MASK, syndrome, 915 row_index, 0, -1, 916 mci->ctl_name, ""); 917 918 if (err_detect & DDR_EDE_MBE) 919 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 920 pfn, err_addr & ~PAGE_MASK, syndrome, 921 row_index, 0, -1, 922 mci->ctl_name, ""); 923 924 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect); 925 } 926 927 static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id) 928 { 929 struct mem_ctl_info *mci = dev_id; 930 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 931 u32 err_detect; 932 933 err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT); 934 if (!err_detect) 935 return IRQ_NONE; 936 937 mpc85xx_mc_check(mci); 938 939 return IRQ_HANDLED; 940 } 941 942 static void mpc85xx_init_csrows(struct mem_ctl_info *mci) 943 { 944 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 945 struct csrow_info *csrow; 946 struct dimm_info *dimm; 947 u32 sdram_ctl; 948 u32 sdtype; 949 enum mem_type mtype; 950 u32 cs_bnds; 951 int index; 952 953 sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG); 954 955 sdtype = sdram_ctl & DSC_SDTYPE_MASK; 956 if (sdram_ctl & DSC_RD_EN) { 957 switch (sdtype) { 958 case DSC_SDTYPE_DDR: 959 mtype = MEM_RDDR; 960 break; 961 case DSC_SDTYPE_DDR2: 962 mtype = MEM_RDDR2; 963 break; 964 case DSC_SDTYPE_DDR3: 965 mtype = MEM_RDDR3; 966 break; 967 default: 968 mtype = MEM_UNKNOWN; 969 break; 970 } 971 } else { 972 switch (sdtype) { 973 case DSC_SDTYPE_DDR: 974 mtype = MEM_DDR; 975 break; 976 case DSC_SDTYPE_DDR2: 977 mtype = MEM_DDR2; 978 break; 979 case DSC_SDTYPE_DDR3: 980 mtype = MEM_DDR3; 981 break; 982 default: 983 mtype = MEM_UNKNOWN; 984 break; 985 } 986 } 987 988 for (index = 0; index < mci->nr_csrows; index++) { 989 u32 start; 990 u32 end; 991 992 csrow = mci->csrows[index]; 993 dimm = csrow->channels[0]->dimm; 994 995 cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 + 996 (index * MPC85XX_MC_CS_BNDS_OFS)); 997 998 start = (cs_bnds & 0xffff0000) >> 16; 999 end = (cs_bnds & 0x0000ffff); 1000 1001 if (start == end) 1002 continue; /* not populated */ 1003 1004 start <<= (24 - PAGE_SHIFT); 1005 end <<= (24 - PAGE_SHIFT); 1006 end |= (1 << (24 - PAGE_SHIFT)) - 1; 1007 1008 csrow->first_page = start; 1009 csrow->last_page = end; 1010 1011 dimm->nr_pages = end + 1 - start; 1012 dimm->grain = 8; 1013 dimm->mtype = mtype; 1014 dimm->dtype = DEV_UNKNOWN; 1015 if (sdram_ctl & DSC_X32_EN) 1016 dimm->dtype = DEV_X32; 1017 dimm->edac_mode = EDAC_SECDED; 1018 } 1019 } 1020 1021 static int mpc85xx_mc_err_probe(struct platform_device *op) 1022 { 1023 struct mem_ctl_info *mci; 1024 struct edac_mc_layer layers[2]; 1025 struct mpc85xx_mc_pdata *pdata; 1026 struct resource r; 1027 u32 sdram_ctl; 1028 int res; 1029 1030 if (!devres_open_group(&op->dev, mpc85xx_mc_err_probe, GFP_KERNEL)) 1031 return -ENOMEM; 1032 1033 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 1034 layers[0].size = 4; 1035 layers[0].is_virt_csrow = true; 1036 layers[1].type = EDAC_MC_LAYER_CHANNEL; 1037 layers[1].size = 1; 1038 layers[1].is_virt_csrow = false; 1039 mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers, 1040 sizeof(*pdata)); 1041 if (!mci) { 1042 devres_release_group(&op->dev, mpc85xx_mc_err_probe); 1043 return -ENOMEM; 1044 } 1045 1046 pdata = mci->pvt_info; 1047 pdata->name = "mpc85xx_mc_err"; 1048 pdata->irq = NO_IRQ; 1049 mci->pdev = &op->dev; 1050 pdata->edac_idx = edac_mc_idx++; 1051 dev_set_drvdata(mci->pdev, mci); 1052 mci->ctl_name = pdata->name; 1053 mci->dev_name = pdata->name; 1054 1055 res = of_address_to_resource(op->dev.of_node, 0, &r); 1056 if (res) { 1057 printk(KERN_ERR "%s: Unable to get resource for MC err regs\n", 1058 __func__); 1059 goto err; 1060 } 1061 1062 if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r), 1063 pdata->name)) { 1064 printk(KERN_ERR "%s: Error while requesting mem region\n", 1065 __func__); 1066 res = -EBUSY; 1067 goto err; 1068 } 1069 1070 pdata->mc_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r)); 1071 if (!pdata->mc_vbase) { 1072 printk(KERN_ERR "%s: Unable to setup MC err regs\n", __func__); 1073 res = -ENOMEM; 1074 goto err; 1075 } 1076 1077 sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG); 1078 if (!(sdram_ctl & DSC_ECC_EN)) { 1079 /* no ECC */ 1080 printk(KERN_WARNING "%s: No ECC DIMMs discovered\n", __func__); 1081 res = -ENODEV; 1082 goto err; 1083 } 1084 1085 edac_dbg(3, "init mci\n"); 1086 mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 | 1087 MEM_FLAG_DDR | MEM_FLAG_DDR2; 1088 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; 1089 mci->edac_cap = EDAC_FLAG_SECDED; 1090 mci->mod_name = EDAC_MOD_STR; 1091 mci->mod_ver = MPC85XX_REVISION; 1092 1093 if (edac_op_state == EDAC_OPSTATE_POLL) 1094 mci->edac_check = mpc85xx_mc_check; 1095 1096 mci->ctl_page_to_phys = NULL; 1097 1098 mci->scrub_mode = SCRUB_SW_SRC; 1099 1100 mpc85xx_init_csrows(mci); 1101 1102 /* store the original error disable bits */ 1103 orig_ddr_err_disable = 1104 in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE); 1105 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 0); 1106 1107 /* clear all error bits */ 1108 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0); 1109 1110 if (edac_mc_add_mc(mci)) { 1111 edac_dbg(3, "failed edac_mc_add_mc()\n"); 1112 goto err; 1113 } 1114 1115 if (mpc85xx_create_sysfs_attributes(mci)) { 1116 edac_mc_del_mc(mci->pdev); 1117 edac_dbg(3, "failed edac_mc_add_mc()\n"); 1118 goto err; 1119 } 1120 1121 if (edac_op_state == EDAC_OPSTATE_INT) { 1122 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 1123 DDR_EIE_MBEE | DDR_EIE_SBEE); 1124 1125 /* store the original error management threshold */ 1126 orig_ddr_err_sbe = in_be32(pdata->mc_vbase + 1127 MPC85XX_MC_ERR_SBE) & 0xff0000; 1128 1129 /* set threshold to 1 error per interrupt */ 1130 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, 0x10000); 1131 1132 /* register interrupts */ 1133 pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0); 1134 res = devm_request_irq(&op->dev, pdata->irq, 1135 mpc85xx_mc_isr, 1136 IRQF_SHARED, 1137 "[EDAC] MC err", mci); 1138 if (res < 0) { 1139 printk(KERN_ERR "%s: Unable to request irq %d for " 1140 "MPC85xx DRAM ERR\n", __func__, pdata->irq); 1141 irq_dispose_mapping(pdata->irq); 1142 res = -ENODEV; 1143 goto err2; 1144 } 1145 1146 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for MC\n", 1147 pdata->irq); 1148 } 1149 1150 devres_remove_group(&op->dev, mpc85xx_mc_err_probe); 1151 edac_dbg(3, "success\n"); 1152 printk(KERN_INFO EDAC_MOD_STR " MC err registered\n"); 1153 1154 return 0; 1155 1156 err2: 1157 edac_mc_del_mc(&op->dev); 1158 err: 1159 devres_release_group(&op->dev, mpc85xx_mc_err_probe); 1160 edac_mc_free(mci); 1161 return res; 1162 } 1163 1164 static int mpc85xx_mc_err_remove(struct platform_device *op) 1165 { 1166 struct mem_ctl_info *mci = dev_get_drvdata(&op->dev); 1167 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 1168 1169 edac_dbg(0, "\n"); 1170 1171 if (edac_op_state == EDAC_OPSTATE_INT) { 1172 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0); 1173 irq_dispose_mapping(pdata->irq); 1174 } 1175 1176 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 1177 orig_ddr_err_disable); 1178 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, orig_ddr_err_sbe); 1179 1180 mpc85xx_remove_sysfs_attributes(mci); 1181 edac_mc_del_mc(&op->dev); 1182 edac_mc_free(mci); 1183 return 0; 1184 } 1185 1186 static struct of_device_id mpc85xx_mc_err_of_match[] = { 1187 /* deprecate the fsl,85.. forms in the future, 2.6.30? */ 1188 { .compatible = "fsl,8540-memory-controller", }, 1189 { .compatible = "fsl,8541-memory-controller", }, 1190 { .compatible = "fsl,8544-memory-controller", }, 1191 { .compatible = "fsl,8548-memory-controller", }, 1192 { .compatible = "fsl,8555-memory-controller", }, 1193 { .compatible = "fsl,8568-memory-controller", }, 1194 { .compatible = "fsl,mpc8536-memory-controller", }, 1195 { .compatible = "fsl,mpc8540-memory-controller", }, 1196 { .compatible = "fsl,mpc8541-memory-controller", }, 1197 { .compatible = "fsl,mpc8544-memory-controller", }, 1198 { .compatible = "fsl,mpc8548-memory-controller", }, 1199 { .compatible = "fsl,mpc8555-memory-controller", }, 1200 { .compatible = "fsl,mpc8560-memory-controller", }, 1201 { .compatible = "fsl,mpc8568-memory-controller", }, 1202 { .compatible = "fsl,mpc8569-memory-controller", }, 1203 { .compatible = "fsl,mpc8572-memory-controller", }, 1204 { .compatible = "fsl,mpc8349-memory-controller", }, 1205 { .compatible = "fsl,p1020-memory-controller", }, 1206 { .compatible = "fsl,p1021-memory-controller", }, 1207 { .compatible = "fsl,p2020-memory-controller", }, 1208 { .compatible = "fsl,qoriq-memory-controller", }, 1209 {}, 1210 }; 1211 MODULE_DEVICE_TABLE(of, mpc85xx_mc_err_of_match); 1212 1213 static struct platform_driver mpc85xx_mc_err_driver = { 1214 .probe = mpc85xx_mc_err_probe, 1215 .remove = mpc85xx_mc_err_remove, 1216 .driver = { 1217 .name = "mpc85xx_mc_err", 1218 .owner = THIS_MODULE, 1219 .of_match_table = mpc85xx_mc_err_of_match, 1220 }, 1221 }; 1222 1223 #ifdef CONFIG_FSL_SOC_BOOKE 1224 static void __init mpc85xx_mc_clear_rfxe(void *data) 1225 { 1226 orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1); 1227 mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~HID1_RFXE)); 1228 } 1229 #endif 1230 1231 static int __init mpc85xx_mc_init(void) 1232 { 1233 int res = 0; 1234 u32 pvr = 0; 1235 1236 printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, " 1237 "(C) 2006 Montavista Software\n"); 1238 1239 /* make sure error reporting method is sane */ 1240 switch (edac_op_state) { 1241 case EDAC_OPSTATE_POLL: 1242 case EDAC_OPSTATE_INT: 1243 break; 1244 default: 1245 edac_op_state = EDAC_OPSTATE_INT; 1246 break; 1247 } 1248 1249 res = platform_driver_register(&mpc85xx_mc_err_driver); 1250 if (res) 1251 printk(KERN_WARNING EDAC_MOD_STR "MC fails to register\n"); 1252 1253 res = platform_driver_register(&mpc85xx_l2_err_driver); 1254 if (res) 1255 printk(KERN_WARNING EDAC_MOD_STR "L2 fails to register\n"); 1256 1257 #ifdef CONFIG_FSL_SOC_BOOKE 1258 pvr = mfspr(SPRN_PVR); 1259 1260 if ((PVR_VER(pvr) == PVR_VER_E500V1) || 1261 (PVR_VER(pvr) == PVR_VER_E500V2)) { 1262 /* 1263 * need to clear HID1[RFXE] to disable machine check int 1264 * so we can catch it 1265 */ 1266 if (edac_op_state == EDAC_OPSTATE_INT) 1267 on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0); 1268 } 1269 #endif 1270 1271 return 0; 1272 } 1273 1274 module_init(mpc85xx_mc_init); 1275 1276 #ifdef CONFIG_FSL_SOC_BOOKE 1277 static void __exit mpc85xx_mc_restore_hid1(void *data) 1278 { 1279 mtspr(SPRN_HID1, orig_hid1[smp_processor_id()]); 1280 } 1281 #endif 1282 1283 static void __exit mpc85xx_mc_exit(void) 1284 { 1285 #ifdef CONFIG_FSL_SOC_BOOKE 1286 u32 pvr = mfspr(SPRN_PVR); 1287 1288 if ((PVR_VER(pvr) == PVR_VER_E500V1) || 1289 (PVR_VER(pvr) == PVR_VER_E500V2)) { 1290 on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0); 1291 } 1292 #endif 1293 platform_driver_unregister(&mpc85xx_l2_err_driver); 1294 platform_driver_unregister(&mpc85xx_mc_err_driver); 1295 } 1296 1297 module_exit(mpc85xx_mc_exit); 1298 1299 MODULE_LICENSE("GPL"); 1300 MODULE_AUTHOR("Montavista Software, Inc."); 1301 module_param(edac_op_state, int, 0444); 1302 MODULE_PARM_DESC(edac_op_state, 1303 "EDAC Error Reporting state: 0=Poll, 2=Interrupt"); 1304