1 /* 2 * Freescale MPC85xx Memory Controller kenel module 3 * 4 * Author: Dave Jiang <djiang@mvista.com> 5 * 6 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under 7 * the terms of the GNU General Public License version 2. This program 8 * is licensed "as is" without any warranty of any kind, whether express 9 * or implied. 10 * 11 */ 12 #include <linux/module.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/ctype.h> 16 #include <linux/io.h> 17 #include <linux/mod_devicetable.h> 18 #include <linux/edac.h> 19 #include <linux/smp.h> 20 #include <linux/gfp.h> 21 22 #include <linux/of_platform.h> 23 #include <linux/of_device.h> 24 #include "edac_module.h" 25 #include "edac_core.h" 26 #include "mpc85xx_edac.h" 27 28 static int edac_dev_idx; 29 #ifdef CONFIG_PCI 30 static int edac_pci_idx; 31 #endif 32 static int edac_mc_idx; 33 34 static u32 orig_ddr_err_disable; 35 static u32 orig_ddr_err_sbe; 36 37 /* 38 * PCI Err defines 39 */ 40 #ifdef CONFIG_PCI 41 static u32 orig_pci_err_cap_dr; 42 static u32 orig_pci_err_en; 43 #endif 44 45 static u32 orig_l2_err_disable; 46 #ifdef CONFIG_FSL_SOC_BOOKE 47 static u32 orig_hid1[2]; 48 #endif 49 50 /************************ MC SYSFS parts ***********************************/ 51 52 #define to_mci(k) container_of(k, struct mem_ctl_info, dev) 53 54 static ssize_t mpc85xx_mc_inject_data_hi_show(struct device *dev, 55 struct device_attribute *mattr, 56 char *data) 57 { 58 struct mem_ctl_info *mci = to_mci(dev); 59 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 60 return sprintf(data, "0x%08x", 61 in_be32(pdata->mc_vbase + 62 MPC85XX_MC_DATA_ERR_INJECT_HI)); 63 } 64 65 static ssize_t mpc85xx_mc_inject_data_lo_show(struct device *dev, 66 struct device_attribute *mattr, 67 char *data) 68 { 69 struct mem_ctl_info *mci = to_mci(dev); 70 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 71 return sprintf(data, "0x%08x", 72 in_be32(pdata->mc_vbase + 73 MPC85XX_MC_DATA_ERR_INJECT_LO)); 74 } 75 76 static ssize_t mpc85xx_mc_inject_ctrl_show(struct device *dev, 77 struct device_attribute *mattr, 78 char *data) 79 { 80 struct mem_ctl_info *mci = to_mci(dev); 81 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 82 return sprintf(data, "0x%08x", 83 in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT)); 84 } 85 86 static ssize_t mpc85xx_mc_inject_data_hi_store(struct device *dev, 87 struct device_attribute *mattr, 88 const char *data, size_t count) 89 { 90 struct mem_ctl_info *mci = to_mci(dev); 91 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 92 if (isdigit(*data)) { 93 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI, 94 simple_strtoul(data, NULL, 0)); 95 return count; 96 } 97 return 0; 98 } 99 100 static ssize_t mpc85xx_mc_inject_data_lo_store(struct device *dev, 101 struct device_attribute *mattr, 102 const char *data, size_t count) 103 { 104 struct mem_ctl_info *mci = to_mci(dev); 105 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 106 if (isdigit(*data)) { 107 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO, 108 simple_strtoul(data, NULL, 0)); 109 return count; 110 } 111 return 0; 112 } 113 114 static ssize_t mpc85xx_mc_inject_ctrl_store(struct device *dev, 115 struct device_attribute *mattr, 116 const char *data, size_t count) 117 { 118 struct mem_ctl_info *mci = to_mci(dev); 119 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 120 if (isdigit(*data)) { 121 out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT, 122 simple_strtoul(data, NULL, 0)); 123 return count; 124 } 125 return 0; 126 } 127 128 DEVICE_ATTR(inject_data_hi, S_IRUGO | S_IWUSR, 129 mpc85xx_mc_inject_data_hi_show, mpc85xx_mc_inject_data_hi_store); 130 DEVICE_ATTR(inject_data_lo, S_IRUGO | S_IWUSR, 131 mpc85xx_mc_inject_data_lo_show, mpc85xx_mc_inject_data_lo_store); 132 DEVICE_ATTR(inject_ctrl, S_IRUGO | S_IWUSR, 133 mpc85xx_mc_inject_ctrl_show, mpc85xx_mc_inject_ctrl_store); 134 135 static int mpc85xx_create_sysfs_attributes(struct mem_ctl_info *mci) 136 { 137 int rc; 138 139 rc = device_create_file(&mci->dev, &dev_attr_inject_data_hi); 140 if (rc < 0) 141 return rc; 142 rc = device_create_file(&mci->dev, &dev_attr_inject_data_lo); 143 if (rc < 0) 144 return rc; 145 rc = device_create_file(&mci->dev, &dev_attr_inject_ctrl); 146 if (rc < 0) 147 return rc; 148 149 return 0; 150 } 151 152 static void mpc85xx_remove_sysfs_attributes(struct mem_ctl_info *mci) 153 { 154 device_remove_file(&mci->dev, &dev_attr_inject_data_hi); 155 device_remove_file(&mci->dev, &dev_attr_inject_data_lo); 156 device_remove_file(&mci->dev, &dev_attr_inject_ctrl); 157 } 158 159 /**************************** PCI Err device ***************************/ 160 #ifdef CONFIG_PCI 161 162 static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci) 163 { 164 struct mpc85xx_pci_pdata *pdata = pci->pvt_info; 165 u32 err_detect; 166 167 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); 168 169 /* master aborts can happen during PCI config cycles */ 170 if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) { 171 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); 172 return; 173 } 174 175 printk(KERN_ERR "PCI error(s) detected\n"); 176 printk(KERN_ERR "PCI/X ERR_DR register: %#08x\n", err_detect); 177 178 printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x\n", 179 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB)); 180 printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x\n", 181 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR)); 182 printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x\n", 183 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR)); 184 printk(KERN_ERR "PCI/X ERR_DL register: %#08x\n", 185 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL)); 186 printk(KERN_ERR "PCI/X ERR_DH register: %#08x\n", 187 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH)); 188 189 /* clear error bits */ 190 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); 191 192 if (err_detect & PCI_EDE_PERR_MASK) 193 edac_pci_handle_pe(pci, pci->ctl_name); 194 195 if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK) 196 edac_pci_handle_npe(pci, pci->ctl_name); 197 } 198 199 static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id) 200 { 201 struct edac_pci_ctl_info *pci = dev_id; 202 struct mpc85xx_pci_pdata *pdata = pci->pvt_info; 203 u32 err_detect; 204 205 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); 206 207 if (!err_detect) 208 return IRQ_NONE; 209 210 mpc85xx_pci_check(pci); 211 212 return IRQ_HANDLED; 213 } 214 215 int mpc85xx_pci_err_probe(struct platform_device *op) 216 { 217 struct edac_pci_ctl_info *pci; 218 struct mpc85xx_pci_pdata *pdata; 219 struct resource r; 220 int res = 0; 221 222 if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL)) 223 return -ENOMEM; 224 225 pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err"); 226 if (!pci) 227 return -ENOMEM; 228 229 /* make sure error reporting method is sane */ 230 switch (edac_op_state) { 231 case EDAC_OPSTATE_POLL: 232 case EDAC_OPSTATE_INT: 233 break; 234 default: 235 edac_op_state = EDAC_OPSTATE_INT; 236 break; 237 } 238 239 pdata = pci->pvt_info; 240 pdata->name = "mpc85xx_pci_err"; 241 pdata->irq = NO_IRQ; 242 dev_set_drvdata(&op->dev, pci); 243 pci->dev = &op->dev; 244 pci->mod_name = EDAC_MOD_STR; 245 pci->ctl_name = pdata->name; 246 pci->dev_name = dev_name(&op->dev); 247 248 if (edac_op_state == EDAC_OPSTATE_POLL) 249 pci->edac_check = mpc85xx_pci_check; 250 251 pdata->edac_idx = edac_pci_idx++; 252 253 res = of_address_to_resource(op->dev.of_node, 0, &r); 254 if (res) { 255 printk(KERN_ERR "%s: Unable to get resource for " 256 "PCI err regs\n", __func__); 257 goto err; 258 } 259 260 /* we only need the error registers */ 261 r.start += 0xe00; 262 263 if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r), 264 pdata->name)) { 265 printk(KERN_ERR "%s: Error while requesting mem region\n", 266 __func__); 267 res = -EBUSY; 268 goto err; 269 } 270 271 pdata->pci_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r)); 272 if (!pdata->pci_vbase) { 273 printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__); 274 res = -ENOMEM; 275 goto err; 276 } 277 278 orig_pci_err_cap_dr = 279 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR); 280 281 /* PCI master abort is expected during config cycles */ 282 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40); 283 284 orig_pci_err_en = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN); 285 286 /* disable master abort reporting */ 287 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40); 288 289 /* clear error bits */ 290 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0); 291 292 if (edac_pci_add_device(pci, pdata->edac_idx) > 0) { 293 edac_dbg(3, "failed edac_pci_add_device()\n"); 294 goto err; 295 } 296 297 if (edac_op_state == EDAC_OPSTATE_INT) { 298 pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0); 299 res = devm_request_irq(&op->dev, pdata->irq, 300 mpc85xx_pci_isr, IRQF_DISABLED, 301 "[EDAC] PCI err", pci); 302 if (res < 0) { 303 printk(KERN_ERR 304 "%s: Unable to request irq %d for " 305 "MPC85xx PCI err\n", __func__, pdata->irq); 306 irq_dispose_mapping(pdata->irq); 307 res = -ENODEV; 308 goto err2; 309 } 310 311 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for PCI Err\n", 312 pdata->irq); 313 } 314 315 devres_remove_group(&op->dev, mpc85xx_pci_err_probe); 316 edac_dbg(3, "success\n"); 317 printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n"); 318 319 return 0; 320 321 err2: 322 edac_pci_del_device(&op->dev); 323 err: 324 edac_pci_free_ctl_info(pci); 325 devres_release_group(&op->dev, mpc85xx_pci_err_probe); 326 return res; 327 } 328 EXPORT_SYMBOL(mpc85xx_pci_err_probe); 329 330 #endif /* CONFIG_PCI */ 331 332 /**************************** L2 Err device ***************************/ 333 334 /************************ L2 SYSFS parts ***********************************/ 335 336 static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info 337 *edac_dev, char *data) 338 { 339 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 340 return sprintf(data, "0x%08x", 341 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI)); 342 } 343 344 static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info 345 *edac_dev, char *data) 346 { 347 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 348 return sprintf(data, "0x%08x", 349 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO)); 350 } 351 352 static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info 353 *edac_dev, char *data) 354 { 355 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 356 return sprintf(data, "0x%08x", 357 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL)); 358 } 359 360 static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info 361 *edac_dev, const char *data, 362 size_t count) 363 { 364 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 365 if (isdigit(*data)) { 366 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI, 367 simple_strtoul(data, NULL, 0)); 368 return count; 369 } 370 return 0; 371 } 372 373 static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info 374 *edac_dev, const char *data, 375 size_t count) 376 { 377 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 378 if (isdigit(*data)) { 379 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO, 380 simple_strtoul(data, NULL, 0)); 381 return count; 382 } 383 return 0; 384 } 385 386 static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info 387 *edac_dev, const char *data, 388 size_t count) 389 { 390 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 391 if (isdigit(*data)) { 392 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL, 393 simple_strtoul(data, NULL, 0)); 394 return count; 395 } 396 return 0; 397 } 398 399 static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = { 400 { 401 .attr = { 402 .name = "inject_data_hi", 403 .mode = (S_IRUGO | S_IWUSR) 404 }, 405 .show = mpc85xx_l2_inject_data_hi_show, 406 .store = mpc85xx_l2_inject_data_hi_store}, 407 { 408 .attr = { 409 .name = "inject_data_lo", 410 .mode = (S_IRUGO | S_IWUSR) 411 }, 412 .show = mpc85xx_l2_inject_data_lo_show, 413 .store = mpc85xx_l2_inject_data_lo_store}, 414 { 415 .attr = { 416 .name = "inject_ctrl", 417 .mode = (S_IRUGO | S_IWUSR) 418 }, 419 .show = mpc85xx_l2_inject_ctrl_show, 420 .store = mpc85xx_l2_inject_ctrl_store}, 421 422 /* End of list */ 423 { 424 .attr = {.name = NULL} 425 } 426 }; 427 428 static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info 429 *edac_dev) 430 { 431 edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes; 432 } 433 434 /***************************** L2 ops ***********************************/ 435 436 static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev) 437 { 438 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 439 u32 err_detect; 440 441 err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET); 442 443 if (!(err_detect & L2_EDE_MASK)) 444 return; 445 446 printk(KERN_ERR "ECC Error in CPU L2 cache\n"); 447 printk(KERN_ERR "L2 Error Detect Register: 0x%08x\n", err_detect); 448 printk(KERN_ERR "L2 Error Capture Data High Register: 0x%08x\n", 449 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI)); 450 printk(KERN_ERR "L2 Error Capture Data Lo Register: 0x%08x\n", 451 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO)); 452 printk(KERN_ERR "L2 Error Syndrome Register: 0x%08x\n", 453 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC)); 454 printk(KERN_ERR "L2 Error Attributes Capture Register: 0x%08x\n", 455 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR)); 456 printk(KERN_ERR "L2 Error Address Capture Register: 0x%08x\n", 457 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR)); 458 459 /* clear error detect register */ 460 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect); 461 462 if (err_detect & L2_EDE_CE_MASK) 463 edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name); 464 465 if (err_detect & L2_EDE_UE_MASK) 466 edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name); 467 } 468 469 static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id) 470 { 471 struct edac_device_ctl_info *edac_dev = dev_id; 472 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 473 u32 err_detect; 474 475 err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET); 476 477 if (!(err_detect & L2_EDE_MASK)) 478 return IRQ_NONE; 479 480 mpc85xx_l2_check(edac_dev); 481 482 return IRQ_HANDLED; 483 } 484 485 static int mpc85xx_l2_err_probe(struct platform_device *op) 486 { 487 struct edac_device_ctl_info *edac_dev; 488 struct mpc85xx_l2_pdata *pdata; 489 struct resource r; 490 int res; 491 492 if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL)) 493 return -ENOMEM; 494 495 edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata), 496 "cpu", 1, "L", 1, 2, NULL, 0, 497 edac_dev_idx); 498 if (!edac_dev) { 499 devres_release_group(&op->dev, mpc85xx_l2_err_probe); 500 return -ENOMEM; 501 } 502 503 pdata = edac_dev->pvt_info; 504 pdata->name = "mpc85xx_l2_err"; 505 pdata->irq = NO_IRQ; 506 edac_dev->dev = &op->dev; 507 dev_set_drvdata(edac_dev->dev, edac_dev); 508 edac_dev->ctl_name = pdata->name; 509 edac_dev->dev_name = pdata->name; 510 511 res = of_address_to_resource(op->dev.of_node, 0, &r); 512 if (res) { 513 printk(KERN_ERR "%s: Unable to get resource for " 514 "L2 err regs\n", __func__); 515 goto err; 516 } 517 518 /* we only need the error registers */ 519 r.start += 0xe00; 520 521 if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r), 522 pdata->name)) { 523 printk(KERN_ERR "%s: Error while requesting mem region\n", 524 __func__); 525 res = -EBUSY; 526 goto err; 527 } 528 529 pdata->l2_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r)); 530 if (!pdata->l2_vbase) { 531 printk(KERN_ERR "%s: Unable to setup L2 err regs\n", __func__); 532 res = -ENOMEM; 533 goto err; 534 } 535 536 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0); 537 538 orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS); 539 540 /* clear the err_dis */ 541 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0); 542 543 edac_dev->mod_name = EDAC_MOD_STR; 544 545 if (edac_op_state == EDAC_OPSTATE_POLL) 546 edac_dev->edac_check = mpc85xx_l2_check; 547 548 mpc85xx_set_l2_sysfs_attributes(edac_dev); 549 550 pdata->edac_idx = edac_dev_idx++; 551 552 if (edac_device_add_device(edac_dev) > 0) { 553 edac_dbg(3, "failed edac_device_add_device()\n"); 554 goto err; 555 } 556 557 if (edac_op_state == EDAC_OPSTATE_INT) { 558 pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0); 559 res = devm_request_irq(&op->dev, pdata->irq, 560 mpc85xx_l2_isr, IRQF_DISABLED, 561 "[EDAC] L2 err", edac_dev); 562 if (res < 0) { 563 printk(KERN_ERR 564 "%s: Unable to request irq %d for " 565 "MPC85xx L2 err\n", __func__, pdata->irq); 566 irq_dispose_mapping(pdata->irq); 567 res = -ENODEV; 568 goto err2; 569 } 570 571 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for L2 Err\n", 572 pdata->irq); 573 574 edac_dev->op_state = OP_RUNNING_INTERRUPT; 575 576 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK); 577 } 578 579 devres_remove_group(&op->dev, mpc85xx_l2_err_probe); 580 581 edac_dbg(3, "success\n"); 582 printk(KERN_INFO EDAC_MOD_STR " L2 err registered\n"); 583 584 return 0; 585 586 err2: 587 edac_device_del_device(&op->dev); 588 err: 589 devres_release_group(&op->dev, mpc85xx_l2_err_probe); 590 edac_device_free_ctl_info(edac_dev); 591 return res; 592 } 593 594 static int mpc85xx_l2_err_remove(struct platform_device *op) 595 { 596 struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev); 597 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 598 599 edac_dbg(0, "\n"); 600 601 if (edac_op_state == EDAC_OPSTATE_INT) { 602 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0); 603 irq_dispose_mapping(pdata->irq); 604 } 605 606 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable); 607 edac_device_del_device(&op->dev); 608 edac_device_free_ctl_info(edac_dev); 609 return 0; 610 } 611 612 static struct of_device_id mpc85xx_l2_err_of_match[] = { 613 /* deprecate the fsl,85.. forms in the future, 2.6.30? */ 614 { .compatible = "fsl,8540-l2-cache-controller", }, 615 { .compatible = "fsl,8541-l2-cache-controller", }, 616 { .compatible = "fsl,8544-l2-cache-controller", }, 617 { .compatible = "fsl,8548-l2-cache-controller", }, 618 { .compatible = "fsl,8555-l2-cache-controller", }, 619 { .compatible = "fsl,8568-l2-cache-controller", }, 620 { .compatible = "fsl,mpc8536-l2-cache-controller", }, 621 { .compatible = "fsl,mpc8540-l2-cache-controller", }, 622 { .compatible = "fsl,mpc8541-l2-cache-controller", }, 623 { .compatible = "fsl,mpc8544-l2-cache-controller", }, 624 { .compatible = "fsl,mpc8548-l2-cache-controller", }, 625 { .compatible = "fsl,mpc8555-l2-cache-controller", }, 626 { .compatible = "fsl,mpc8560-l2-cache-controller", }, 627 { .compatible = "fsl,mpc8568-l2-cache-controller", }, 628 { .compatible = "fsl,mpc8569-l2-cache-controller", }, 629 { .compatible = "fsl,mpc8572-l2-cache-controller", }, 630 { .compatible = "fsl,p1020-l2-cache-controller", }, 631 { .compatible = "fsl,p1021-l2-cache-controller", }, 632 { .compatible = "fsl,p2020-l2-cache-controller", }, 633 {}, 634 }; 635 MODULE_DEVICE_TABLE(of, mpc85xx_l2_err_of_match); 636 637 static struct platform_driver mpc85xx_l2_err_driver = { 638 .probe = mpc85xx_l2_err_probe, 639 .remove = mpc85xx_l2_err_remove, 640 .driver = { 641 .name = "mpc85xx_l2_err", 642 .owner = THIS_MODULE, 643 .of_match_table = mpc85xx_l2_err_of_match, 644 }, 645 }; 646 647 /**************************** MC Err device ***************************/ 648 649 /* 650 * Taken from table 8-55 in the MPC8641 User's Manual and/or 9-61 in the 651 * MPC8572 User's Manual. Each line represents a syndrome bit column as a 652 * 64-bit value, but split into an upper and lower 32-bit chunk. The labels 653 * below correspond to Freescale's manuals. 654 */ 655 static unsigned int ecc_table[16] = { 656 /* MSB LSB */ 657 /* [0:31] [32:63] */ 658 0xf00fe11e, 0xc33c0ff7, /* Syndrome bit 7 */ 659 0x00ff00ff, 0x00fff0ff, 660 0x0f0f0f0f, 0x0f0fff00, 661 0x11113333, 0x7777000f, 662 0x22224444, 0x8888222f, 663 0x44448888, 0xffff4441, 664 0x8888ffff, 0x11118882, 665 0xffff1111, 0x22221114, /* Syndrome bit 0 */ 666 }; 667 668 /* 669 * Calculate the correct ECC value for a 64-bit value specified by high:low 670 */ 671 static u8 calculate_ecc(u32 high, u32 low) 672 { 673 u32 mask_low; 674 u32 mask_high; 675 int bit_cnt; 676 u8 ecc = 0; 677 int i; 678 int j; 679 680 for (i = 0; i < 8; i++) { 681 mask_high = ecc_table[i * 2]; 682 mask_low = ecc_table[i * 2 + 1]; 683 bit_cnt = 0; 684 685 for (j = 0; j < 32; j++) { 686 if ((mask_high >> j) & 1) 687 bit_cnt ^= (high >> j) & 1; 688 if ((mask_low >> j) & 1) 689 bit_cnt ^= (low >> j) & 1; 690 } 691 692 ecc |= bit_cnt << i; 693 } 694 695 return ecc; 696 } 697 698 /* 699 * Create the syndrome code which is generated if the data line specified by 700 * 'bit' failed. Eg generate an 8-bit codes seen in Table 8-55 in the MPC8641 701 * User's Manual and 9-61 in the MPC8572 User's Manual. 702 */ 703 static u8 syndrome_from_bit(unsigned int bit) { 704 int i; 705 u8 syndrome = 0; 706 707 /* 708 * Cycle through the upper or lower 32-bit portion of each value in 709 * ecc_table depending on if 'bit' is in the upper or lower half of 710 * 64-bit data. 711 */ 712 for (i = bit < 32; i < 16; i += 2) 713 syndrome |= ((ecc_table[i] >> (bit % 32)) & 1) << (i / 2); 714 715 return syndrome; 716 } 717 718 /* 719 * Decode data and ecc syndrome to determine what went wrong 720 * Note: This can only decode single-bit errors 721 */ 722 static void sbe_ecc_decode(u32 cap_high, u32 cap_low, u32 cap_ecc, 723 int *bad_data_bit, int *bad_ecc_bit) 724 { 725 int i; 726 u8 syndrome; 727 728 *bad_data_bit = -1; 729 *bad_ecc_bit = -1; 730 731 /* 732 * Calculate the ECC of the captured data and XOR it with the captured 733 * ECC to find an ECC syndrome value we can search for 734 */ 735 syndrome = calculate_ecc(cap_high, cap_low) ^ cap_ecc; 736 737 /* Check if a data line is stuck... */ 738 for (i = 0; i < 64; i++) { 739 if (syndrome == syndrome_from_bit(i)) { 740 *bad_data_bit = i; 741 return; 742 } 743 } 744 745 /* If data is correct, check ECC bits for errors... */ 746 for (i = 0; i < 8; i++) { 747 if ((syndrome >> i) & 0x1) { 748 *bad_ecc_bit = i; 749 return; 750 } 751 } 752 } 753 754 static void mpc85xx_mc_check(struct mem_ctl_info *mci) 755 { 756 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 757 struct csrow_info *csrow; 758 u32 bus_width; 759 u32 err_detect; 760 u32 syndrome; 761 u32 err_addr; 762 u32 pfn; 763 int row_index; 764 u32 cap_high; 765 u32 cap_low; 766 int bad_data_bit; 767 int bad_ecc_bit; 768 769 err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT); 770 if (!err_detect) 771 return; 772 773 mpc85xx_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n", 774 err_detect); 775 776 /* no more processing if not ECC bit errors */ 777 if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) { 778 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect); 779 return; 780 } 781 782 syndrome = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ECC); 783 784 /* Mask off appropriate bits of syndrome based on bus width */ 785 bus_width = (in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG) & 786 DSC_DBW_MASK) ? 32 : 64; 787 if (bus_width == 64) 788 syndrome &= 0xff; 789 else 790 syndrome &= 0xffff; 791 792 err_addr = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ADDRESS); 793 pfn = err_addr >> PAGE_SHIFT; 794 795 for (row_index = 0; row_index < mci->nr_csrows; row_index++) { 796 csrow = mci->csrows[row_index]; 797 if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page)) 798 break; 799 } 800 801 cap_high = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_HI); 802 cap_low = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_LO); 803 804 /* 805 * Analyze single-bit errors on 64-bit wide buses 806 * TODO: Add support for 32-bit wide buses 807 */ 808 if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) { 809 sbe_ecc_decode(cap_high, cap_low, syndrome, 810 &bad_data_bit, &bad_ecc_bit); 811 812 if (bad_data_bit != -1) 813 mpc85xx_mc_printk(mci, KERN_ERR, 814 "Faulty Data bit: %d\n", bad_data_bit); 815 if (bad_ecc_bit != -1) 816 mpc85xx_mc_printk(mci, KERN_ERR, 817 "Faulty ECC bit: %d\n", bad_ecc_bit); 818 819 mpc85xx_mc_printk(mci, KERN_ERR, 820 "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n", 821 cap_high ^ (1 << (bad_data_bit - 32)), 822 cap_low ^ (1 << bad_data_bit), 823 syndrome ^ (1 << bad_ecc_bit)); 824 } 825 826 mpc85xx_mc_printk(mci, KERN_ERR, 827 "Captured Data / ECC:\t%#8.8x_%08x / %#2.2x\n", 828 cap_high, cap_low, syndrome); 829 mpc85xx_mc_printk(mci, KERN_ERR, "Err addr: %#8.8x\n", err_addr); 830 mpc85xx_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn); 831 832 /* we are out of range */ 833 if (row_index == mci->nr_csrows) 834 mpc85xx_mc_printk(mci, KERN_ERR, "PFN out of range!\n"); 835 836 if (err_detect & DDR_EDE_SBE) 837 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 838 pfn, err_addr & ~PAGE_MASK, syndrome, 839 row_index, 0, -1, 840 mci->ctl_name, ""); 841 842 if (err_detect & DDR_EDE_MBE) 843 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 844 pfn, err_addr & ~PAGE_MASK, syndrome, 845 row_index, 0, -1, 846 mci->ctl_name, ""); 847 848 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect); 849 } 850 851 static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id) 852 { 853 struct mem_ctl_info *mci = dev_id; 854 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 855 u32 err_detect; 856 857 err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT); 858 if (!err_detect) 859 return IRQ_NONE; 860 861 mpc85xx_mc_check(mci); 862 863 return IRQ_HANDLED; 864 } 865 866 static void mpc85xx_init_csrows(struct mem_ctl_info *mci) 867 { 868 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 869 struct csrow_info *csrow; 870 struct dimm_info *dimm; 871 u32 sdram_ctl; 872 u32 sdtype; 873 enum mem_type mtype; 874 u32 cs_bnds; 875 int index; 876 877 sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG); 878 879 sdtype = sdram_ctl & DSC_SDTYPE_MASK; 880 if (sdram_ctl & DSC_RD_EN) { 881 switch (sdtype) { 882 case DSC_SDTYPE_DDR: 883 mtype = MEM_RDDR; 884 break; 885 case DSC_SDTYPE_DDR2: 886 mtype = MEM_RDDR2; 887 break; 888 case DSC_SDTYPE_DDR3: 889 mtype = MEM_RDDR3; 890 break; 891 default: 892 mtype = MEM_UNKNOWN; 893 break; 894 } 895 } else { 896 switch (sdtype) { 897 case DSC_SDTYPE_DDR: 898 mtype = MEM_DDR; 899 break; 900 case DSC_SDTYPE_DDR2: 901 mtype = MEM_DDR2; 902 break; 903 case DSC_SDTYPE_DDR3: 904 mtype = MEM_DDR3; 905 break; 906 default: 907 mtype = MEM_UNKNOWN; 908 break; 909 } 910 } 911 912 for (index = 0; index < mci->nr_csrows; index++) { 913 u32 start; 914 u32 end; 915 916 csrow = mci->csrows[index]; 917 dimm = csrow->channels[0]->dimm; 918 919 cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 + 920 (index * MPC85XX_MC_CS_BNDS_OFS)); 921 922 start = (cs_bnds & 0xffff0000) >> 16; 923 end = (cs_bnds & 0x0000ffff); 924 925 if (start == end) 926 continue; /* not populated */ 927 928 start <<= (24 - PAGE_SHIFT); 929 end <<= (24 - PAGE_SHIFT); 930 end |= (1 << (24 - PAGE_SHIFT)) - 1; 931 932 csrow->first_page = start; 933 csrow->last_page = end; 934 935 dimm->nr_pages = end + 1 - start; 936 dimm->grain = 8; 937 dimm->mtype = mtype; 938 dimm->dtype = DEV_UNKNOWN; 939 if (sdram_ctl & DSC_X32_EN) 940 dimm->dtype = DEV_X32; 941 dimm->edac_mode = EDAC_SECDED; 942 } 943 } 944 945 static int mpc85xx_mc_err_probe(struct platform_device *op) 946 { 947 struct mem_ctl_info *mci; 948 struct edac_mc_layer layers[2]; 949 struct mpc85xx_mc_pdata *pdata; 950 struct resource r; 951 u32 sdram_ctl; 952 int res; 953 954 if (!devres_open_group(&op->dev, mpc85xx_mc_err_probe, GFP_KERNEL)) 955 return -ENOMEM; 956 957 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 958 layers[0].size = 4; 959 layers[0].is_virt_csrow = true; 960 layers[1].type = EDAC_MC_LAYER_CHANNEL; 961 layers[1].size = 1; 962 layers[1].is_virt_csrow = false; 963 mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers, 964 sizeof(*pdata)); 965 if (!mci) { 966 devres_release_group(&op->dev, mpc85xx_mc_err_probe); 967 return -ENOMEM; 968 } 969 970 pdata = mci->pvt_info; 971 pdata->name = "mpc85xx_mc_err"; 972 pdata->irq = NO_IRQ; 973 mci->pdev = &op->dev; 974 pdata->edac_idx = edac_mc_idx++; 975 dev_set_drvdata(mci->pdev, mci); 976 mci->ctl_name = pdata->name; 977 mci->dev_name = pdata->name; 978 979 res = of_address_to_resource(op->dev.of_node, 0, &r); 980 if (res) { 981 printk(KERN_ERR "%s: Unable to get resource for MC err regs\n", 982 __func__); 983 goto err; 984 } 985 986 if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r), 987 pdata->name)) { 988 printk(KERN_ERR "%s: Error while requesting mem region\n", 989 __func__); 990 res = -EBUSY; 991 goto err; 992 } 993 994 pdata->mc_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r)); 995 if (!pdata->mc_vbase) { 996 printk(KERN_ERR "%s: Unable to setup MC err regs\n", __func__); 997 res = -ENOMEM; 998 goto err; 999 } 1000 1001 sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG); 1002 if (!(sdram_ctl & DSC_ECC_EN)) { 1003 /* no ECC */ 1004 printk(KERN_WARNING "%s: No ECC DIMMs discovered\n", __func__); 1005 res = -ENODEV; 1006 goto err; 1007 } 1008 1009 edac_dbg(3, "init mci\n"); 1010 mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 | 1011 MEM_FLAG_DDR | MEM_FLAG_DDR2; 1012 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; 1013 mci->edac_cap = EDAC_FLAG_SECDED; 1014 mci->mod_name = EDAC_MOD_STR; 1015 mci->mod_ver = MPC85XX_REVISION; 1016 1017 if (edac_op_state == EDAC_OPSTATE_POLL) 1018 mci->edac_check = mpc85xx_mc_check; 1019 1020 mci->ctl_page_to_phys = NULL; 1021 1022 mci->scrub_mode = SCRUB_SW_SRC; 1023 1024 mpc85xx_init_csrows(mci); 1025 1026 /* store the original error disable bits */ 1027 orig_ddr_err_disable = 1028 in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE); 1029 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 0); 1030 1031 /* clear all error bits */ 1032 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0); 1033 1034 if (edac_mc_add_mc(mci)) { 1035 edac_dbg(3, "failed edac_mc_add_mc()\n"); 1036 goto err; 1037 } 1038 1039 if (mpc85xx_create_sysfs_attributes(mci)) { 1040 edac_mc_del_mc(mci->pdev); 1041 edac_dbg(3, "failed edac_mc_add_mc()\n"); 1042 goto err; 1043 } 1044 1045 if (edac_op_state == EDAC_OPSTATE_INT) { 1046 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 1047 DDR_EIE_MBEE | DDR_EIE_SBEE); 1048 1049 /* store the original error management threshold */ 1050 orig_ddr_err_sbe = in_be32(pdata->mc_vbase + 1051 MPC85XX_MC_ERR_SBE) & 0xff0000; 1052 1053 /* set threshold to 1 error per interrupt */ 1054 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, 0x10000); 1055 1056 /* register interrupts */ 1057 pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0); 1058 res = devm_request_irq(&op->dev, pdata->irq, 1059 mpc85xx_mc_isr, 1060 IRQF_DISABLED | IRQF_SHARED, 1061 "[EDAC] MC err", mci); 1062 if (res < 0) { 1063 printk(KERN_ERR "%s: Unable to request irq %d for " 1064 "MPC85xx DRAM ERR\n", __func__, pdata->irq); 1065 irq_dispose_mapping(pdata->irq); 1066 res = -ENODEV; 1067 goto err2; 1068 } 1069 1070 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for MC\n", 1071 pdata->irq); 1072 } 1073 1074 devres_remove_group(&op->dev, mpc85xx_mc_err_probe); 1075 edac_dbg(3, "success\n"); 1076 printk(KERN_INFO EDAC_MOD_STR " MC err registered\n"); 1077 1078 return 0; 1079 1080 err2: 1081 edac_mc_del_mc(&op->dev); 1082 err: 1083 devres_release_group(&op->dev, mpc85xx_mc_err_probe); 1084 edac_mc_free(mci); 1085 return res; 1086 } 1087 1088 static int mpc85xx_mc_err_remove(struct platform_device *op) 1089 { 1090 struct mem_ctl_info *mci = dev_get_drvdata(&op->dev); 1091 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 1092 1093 edac_dbg(0, "\n"); 1094 1095 if (edac_op_state == EDAC_OPSTATE_INT) { 1096 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0); 1097 irq_dispose_mapping(pdata->irq); 1098 } 1099 1100 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 1101 orig_ddr_err_disable); 1102 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, orig_ddr_err_sbe); 1103 1104 mpc85xx_remove_sysfs_attributes(mci); 1105 edac_mc_del_mc(&op->dev); 1106 edac_mc_free(mci); 1107 return 0; 1108 } 1109 1110 static struct of_device_id mpc85xx_mc_err_of_match[] = { 1111 /* deprecate the fsl,85.. forms in the future, 2.6.30? */ 1112 { .compatible = "fsl,8540-memory-controller", }, 1113 { .compatible = "fsl,8541-memory-controller", }, 1114 { .compatible = "fsl,8544-memory-controller", }, 1115 { .compatible = "fsl,8548-memory-controller", }, 1116 { .compatible = "fsl,8555-memory-controller", }, 1117 { .compatible = "fsl,8568-memory-controller", }, 1118 { .compatible = "fsl,mpc8536-memory-controller", }, 1119 { .compatible = "fsl,mpc8540-memory-controller", }, 1120 { .compatible = "fsl,mpc8541-memory-controller", }, 1121 { .compatible = "fsl,mpc8544-memory-controller", }, 1122 { .compatible = "fsl,mpc8548-memory-controller", }, 1123 { .compatible = "fsl,mpc8555-memory-controller", }, 1124 { .compatible = "fsl,mpc8560-memory-controller", }, 1125 { .compatible = "fsl,mpc8568-memory-controller", }, 1126 { .compatible = "fsl,mpc8569-memory-controller", }, 1127 { .compatible = "fsl,mpc8572-memory-controller", }, 1128 { .compatible = "fsl,mpc8349-memory-controller", }, 1129 { .compatible = "fsl,p1020-memory-controller", }, 1130 { .compatible = "fsl,p1021-memory-controller", }, 1131 { .compatible = "fsl,p2020-memory-controller", }, 1132 { .compatible = "fsl,qoriq-memory-controller", }, 1133 {}, 1134 }; 1135 MODULE_DEVICE_TABLE(of, mpc85xx_mc_err_of_match); 1136 1137 static struct platform_driver mpc85xx_mc_err_driver = { 1138 .probe = mpc85xx_mc_err_probe, 1139 .remove = mpc85xx_mc_err_remove, 1140 .driver = { 1141 .name = "mpc85xx_mc_err", 1142 .owner = THIS_MODULE, 1143 .of_match_table = mpc85xx_mc_err_of_match, 1144 }, 1145 }; 1146 1147 #ifdef CONFIG_FSL_SOC_BOOKE 1148 static void __init mpc85xx_mc_clear_rfxe(void *data) 1149 { 1150 orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1); 1151 mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~HID1_RFXE)); 1152 } 1153 #endif 1154 1155 static int __init mpc85xx_mc_init(void) 1156 { 1157 int res = 0; 1158 u32 pvr = 0; 1159 1160 printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, " 1161 "(C) 2006 Montavista Software\n"); 1162 1163 /* make sure error reporting method is sane */ 1164 switch (edac_op_state) { 1165 case EDAC_OPSTATE_POLL: 1166 case EDAC_OPSTATE_INT: 1167 break; 1168 default: 1169 edac_op_state = EDAC_OPSTATE_INT; 1170 break; 1171 } 1172 1173 res = platform_driver_register(&mpc85xx_mc_err_driver); 1174 if (res) 1175 printk(KERN_WARNING EDAC_MOD_STR "MC fails to register\n"); 1176 1177 res = platform_driver_register(&mpc85xx_l2_err_driver); 1178 if (res) 1179 printk(KERN_WARNING EDAC_MOD_STR "L2 fails to register\n"); 1180 1181 #ifdef CONFIG_FSL_SOC_BOOKE 1182 pvr = mfspr(SPRN_PVR); 1183 1184 if ((PVR_VER(pvr) == PVR_VER_E500V1) || 1185 (PVR_VER(pvr) == PVR_VER_E500V2)) { 1186 /* 1187 * need to clear HID1[RFXE] to disable machine check int 1188 * so we can catch it 1189 */ 1190 if (edac_op_state == EDAC_OPSTATE_INT) 1191 on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0); 1192 } 1193 #endif 1194 1195 return 0; 1196 } 1197 1198 module_init(mpc85xx_mc_init); 1199 1200 #ifdef CONFIG_FSL_SOC_BOOKE 1201 static void __exit mpc85xx_mc_restore_hid1(void *data) 1202 { 1203 mtspr(SPRN_HID1, orig_hid1[smp_processor_id()]); 1204 } 1205 #endif 1206 1207 static void __exit mpc85xx_mc_exit(void) 1208 { 1209 #ifdef CONFIG_FSL_SOC_BOOKE 1210 u32 pvr = mfspr(SPRN_PVR); 1211 1212 if ((PVR_VER(pvr) == PVR_VER_E500V1) || 1213 (PVR_VER(pvr) == PVR_VER_E500V2)) { 1214 on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0); 1215 } 1216 #endif 1217 platform_driver_unregister(&mpc85xx_l2_err_driver); 1218 platform_driver_unregister(&mpc85xx_mc_err_driver); 1219 } 1220 1221 module_exit(mpc85xx_mc_exit); 1222 1223 MODULE_LICENSE("GPL"); 1224 MODULE_AUTHOR("Montavista Software, Inc."); 1225 module_param(edac_op_state, int, 0444); 1226 MODULE_PARM_DESC(edac_op_state, 1227 "EDAC Error Reporting state: 0=Poll, 2=Interrupt"); 1228