1 /* 2 * Freescale MPC85xx Memory Controller kenel module 3 * 4 * Author: Dave Jiang <djiang@mvista.com> 5 * 6 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under 7 * the terms of the GNU General Public License version 2. This program 8 * is licensed "as is" without any warranty of any kind, whether express 9 * or implied. 10 * 11 */ 12 #include <linux/module.h> 13 #include <linux/init.h> 14 #include <linux/slab.h> 15 #include <linux/interrupt.h> 16 #include <linux/ctype.h> 17 #include <linux/io.h> 18 #include <linux/mod_devicetable.h> 19 #include <linux/edac.h> 20 #include <linux/smp.h> 21 22 #include <linux/of_platform.h> 23 #include <linux/of_device.h> 24 #include "edac_module.h" 25 #include "edac_core.h" 26 #include "mpc85xx_edac.h" 27 28 static int edac_dev_idx; 29 #ifdef CONFIG_PCI 30 static int edac_pci_idx; 31 #endif 32 static int edac_mc_idx; 33 34 static u32 orig_ddr_err_disable; 35 static u32 orig_ddr_err_sbe; 36 37 /* 38 * PCI Err defines 39 */ 40 #ifdef CONFIG_PCI 41 static u32 orig_pci_err_cap_dr; 42 static u32 orig_pci_err_en; 43 #endif 44 45 static u32 orig_l2_err_disable; 46 #ifdef CONFIG_MPC85xx 47 static u32 orig_hid1[2]; 48 #endif 49 50 /************************ MC SYSFS parts ***********************************/ 51 52 static ssize_t mpc85xx_mc_inject_data_hi_show(struct mem_ctl_info *mci, 53 char *data) 54 { 55 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 56 return sprintf(data, "0x%08x", 57 in_be32(pdata->mc_vbase + 58 MPC85XX_MC_DATA_ERR_INJECT_HI)); 59 } 60 61 static ssize_t mpc85xx_mc_inject_data_lo_show(struct mem_ctl_info *mci, 62 char *data) 63 { 64 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 65 return sprintf(data, "0x%08x", 66 in_be32(pdata->mc_vbase + 67 MPC85XX_MC_DATA_ERR_INJECT_LO)); 68 } 69 70 static ssize_t mpc85xx_mc_inject_ctrl_show(struct mem_ctl_info *mci, char *data) 71 { 72 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 73 return sprintf(data, "0x%08x", 74 in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT)); 75 } 76 77 static ssize_t mpc85xx_mc_inject_data_hi_store(struct mem_ctl_info *mci, 78 const char *data, size_t count) 79 { 80 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 81 if (isdigit(*data)) { 82 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI, 83 simple_strtoul(data, NULL, 0)); 84 return count; 85 } 86 return 0; 87 } 88 89 static ssize_t mpc85xx_mc_inject_data_lo_store(struct mem_ctl_info *mci, 90 const char *data, size_t count) 91 { 92 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 93 if (isdigit(*data)) { 94 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO, 95 simple_strtoul(data, NULL, 0)); 96 return count; 97 } 98 return 0; 99 } 100 101 static ssize_t mpc85xx_mc_inject_ctrl_store(struct mem_ctl_info *mci, 102 const char *data, size_t count) 103 { 104 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 105 if (isdigit(*data)) { 106 out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT, 107 simple_strtoul(data, NULL, 0)); 108 return count; 109 } 110 return 0; 111 } 112 113 static struct mcidev_sysfs_attribute mpc85xx_mc_sysfs_attributes[] = { 114 { 115 .attr = { 116 .name = "inject_data_hi", 117 .mode = (S_IRUGO | S_IWUSR) 118 }, 119 .show = mpc85xx_mc_inject_data_hi_show, 120 .store = mpc85xx_mc_inject_data_hi_store}, 121 { 122 .attr = { 123 .name = "inject_data_lo", 124 .mode = (S_IRUGO | S_IWUSR) 125 }, 126 .show = mpc85xx_mc_inject_data_lo_show, 127 .store = mpc85xx_mc_inject_data_lo_store}, 128 { 129 .attr = { 130 .name = "inject_ctrl", 131 .mode = (S_IRUGO | S_IWUSR) 132 }, 133 .show = mpc85xx_mc_inject_ctrl_show, 134 .store = mpc85xx_mc_inject_ctrl_store}, 135 136 /* End of list */ 137 { 138 .attr = {.name = NULL} 139 } 140 }; 141 142 static void mpc85xx_set_mc_sysfs_attributes(struct mem_ctl_info *mci) 143 { 144 mci->mc_driver_sysfs_attributes = mpc85xx_mc_sysfs_attributes; 145 } 146 147 /**************************** PCI Err device ***************************/ 148 #ifdef CONFIG_PCI 149 150 static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci) 151 { 152 struct mpc85xx_pci_pdata *pdata = pci->pvt_info; 153 u32 err_detect; 154 155 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); 156 157 /* master aborts can happen during PCI config cycles */ 158 if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) { 159 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); 160 return; 161 } 162 163 printk(KERN_ERR "PCI error(s) detected\n"); 164 printk(KERN_ERR "PCI/X ERR_DR register: %#08x\n", err_detect); 165 166 printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x\n", 167 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB)); 168 printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x\n", 169 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR)); 170 printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x\n", 171 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR)); 172 printk(KERN_ERR "PCI/X ERR_DL register: %#08x\n", 173 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL)); 174 printk(KERN_ERR "PCI/X ERR_DH register: %#08x\n", 175 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH)); 176 177 /* clear error bits */ 178 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); 179 180 if (err_detect & PCI_EDE_PERR_MASK) 181 edac_pci_handle_pe(pci, pci->ctl_name); 182 183 if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK) 184 edac_pci_handle_npe(pci, pci->ctl_name); 185 } 186 187 static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id) 188 { 189 struct edac_pci_ctl_info *pci = dev_id; 190 struct mpc85xx_pci_pdata *pdata = pci->pvt_info; 191 u32 err_detect; 192 193 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); 194 195 if (!err_detect) 196 return IRQ_NONE; 197 198 mpc85xx_pci_check(pci); 199 200 return IRQ_HANDLED; 201 } 202 203 static int __devinit mpc85xx_pci_err_probe(struct of_device *op, 204 const struct of_device_id *match) 205 { 206 struct edac_pci_ctl_info *pci; 207 struct mpc85xx_pci_pdata *pdata; 208 struct resource r; 209 int res = 0; 210 211 if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL)) 212 return -ENOMEM; 213 214 pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err"); 215 if (!pci) 216 return -ENOMEM; 217 218 pdata = pci->pvt_info; 219 pdata->name = "mpc85xx_pci_err"; 220 pdata->irq = NO_IRQ; 221 dev_set_drvdata(&op->dev, pci); 222 pci->dev = &op->dev; 223 pci->mod_name = EDAC_MOD_STR; 224 pci->ctl_name = pdata->name; 225 pci->dev_name = dev_name(&op->dev); 226 227 if (edac_op_state == EDAC_OPSTATE_POLL) 228 pci->edac_check = mpc85xx_pci_check; 229 230 pdata->edac_idx = edac_pci_idx++; 231 232 res = of_address_to_resource(op->node, 0, &r); 233 if (res) { 234 printk(KERN_ERR "%s: Unable to get resource for " 235 "PCI err regs\n", __func__); 236 goto err; 237 } 238 239 /* we only need the error registers */ 240 r.start += 0xe00; 241 242 if (!devm_request_mem_region(&op->dev, r.start, 243 r.end - r.start + 1, pdata->name)) { 244 printk(KERN_ERR "%s: Error while requesting mem region\n", 245 __func__); 246 res = -EBUSY; 247 goto err; 248 } 249 250 pdata->pci_vbase = devm_ioremap(&op->dev, r.start, 251 r.end - r.start + 1); 252 if (!pdata->pci_vbase) { 253 printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__); 254 res = -ENOMEM; 255 goto err; 256 } 257 258 orig_pci_err_cap_dr = 259 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR); 260 261 /* PCI master abort is expected during config cycles */ 262 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40); 263 264 orig_pci_err_en = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN); 265 266 /* disable master abort reporting */ 267 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40); 268 269 /* clear error bits */ 270 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0); 271 272 if (edac_pci_add_device(pci, pdata->edac_idx) > 0) { 273 debugf3("%s(): failed edac_pci_add_device()\n", __func__); 274 goto err; 275 } 276 277 if (edac_op_state == EDAC_OPSTATE_INT) { 278 pdata->irq = irq_of_parse_and_map(op->node, 0); 279 res = devm_request_irq(&op->dev, pdata->irq, 280 mpc85xx_pci_isr, IRQF_DISABLED, 281 "[EDAC] PCI err", pci); 282 if (res < 0) { 283 printk(KERN_ERR 284 "%s: Unable to requiest irq %d for " 285 "MPC85xx PCI err\n", __func__, pdata->irq); 286 irq_dispose_mapping(pdata->irq); 287 res = -ENODEV; 288 goto err2; 289 } 290 291 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for PCI Err\n", 292 pdata->irq); 293 } 294 295 devres_remove_group(&op->dev, mpc85xx_pci_err_probe); 296 debugf3("%s(): success\n", __func__); 297 printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n"); 298 299 return 0; 300 301 err2: 302 edac_pci_del_device(&op->dev); 303 err: 304 edac_pci_free_ctl_info(pci); 305 devres_release_group(&op->dev, mpc85xx_pci_err_probe); 306 return res; 307 } 308 309 static int mpc85xx_pci_err_remove(struct of_device *op) 310 { 311 struct edac_pci_ctl_info *pci = dev_get_drvdata(&op->dev); 312 struct mpc85xx_pci_pdata *pdata = pci->pvt_info; 313 314 debugf0("%s()\n", __func__); 315 316 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 317 orig_pci_err_cap_dr); 318 319 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, orig_pci_err_en); 320 321 edac_pci_del_device(pci->dev); 322 323 if (edac_op_state == EDAC_OPSTATE_INT) 324 irq_dispose_mapping(pdata->irq); 325 326 edac_pci_free_ctl_info(pci); 327 328 return 0; 329 } 330 331 static struct of_device_id mpc85xx_pci_err_of_match[] = { 332 { 333 .compatible = "fsl,mpc8540-pcix", 334 }, 335 { 336 .compatible = "fsl,mpc8540-pci", 337 }, 338 {}, 339 }; 340 341 static struct of_platform_driver mpc85xx_pci_err_driver = { 342 .owner = THIS_MODULE, 343 .name = "mpc85xx_pci_err", 344 .match_table = mpc85xx_pci_err_of_match, 345 .probe = mpc85xx_pci_err_probe, 346 .remove = __devexit_p(mpc85xx_pci_err_remove), 347 .driver = { 348 .name = "mpc85xx_pci_err", 349 .owner = THIS_MODULE, 350 }, 351 }; 352 353 #endif /* CONFIG_PCI */ 354 355 /**************************** L2 Err device ***************************/ 356 357 /************************ L2 SYSFS parts ***********************************/ 358 359 static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info 360 *edac_dev, char *data) 361 { 362 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 363 return sprintf(data, "0x%08x", 364 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI)); 365 } 366 367 static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info 368 *edac_dev, char *data) 369 { 370 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 371 return sprintf(data, "0x%08x", 372 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO)); 373 } 374 375 static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info 376 *edac_dev, char *data) 377 { 378 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 379 return sprintf(data, "0x%08x", 380 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL)); 381 } 382 383 static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info 384 *edac_dev, const char *data, 385 size_t count) 386 { 387 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 388 if (isdigit(*data)) { 389 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI, 390 simple_strtoul(data, NULL, 0)); 391 return count; 392 } 393 return 0; 394 } 395 396 static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info 397 *edac_dev, const char *data, 398 size_t count) 399 { 400 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 401 if (isdigit(*data)) { 402 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO, 403 simple_strtoul(data, NULL, 0)); 404 return count; 405 } 406 return 0; 407 } 408 409 static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info 410 *edac_dev, const char *data, 411 size_t count) 412 { 413 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 414 if (isdigit(*data)) { 415 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL, 416 simple_strtoul(data, NULL, 0)); 417 return count; 418 } 419 return 0; 420 } 421 422 static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = { 423 { 424 .attr = { 425 .name = "inject_data_hi", 426 .mode = (S_IRUGO | S_IWUSR) 427 }, 428 .show = mpc85xx_l2_inject_data_hi_show, 429 .store = mpc85xx_l2_inject_data_hi_store}, 430 { 431 .attr = { 432 .name = "inject_data_lo", 433 .mode = (S_IRUGO | S_IWUSR) 434 }, 435 .show = mpc85xx_l2_inject_data_lo_show, 436 .store = mpc85xx_l2_inject_data_lo_store}, 437 { 438 .attr = { 439 .name = "inject_ctrl", 440 .mode = (S_IRUGO | S_IWUSR) 441 }, 442 .show = mpc85xx_l2_inject_ctrl_show, 443 .store = mpc85xx_l2_inject_ctrl_store}, 444 445 /* End of list */ 446 { 447 .attr = {.name = NULL} 448 } 449 }; 450 451 static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info 452 *edac_dev) 453 { 454 edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes; 455 } 456 457 /***************************** L2 ops ***********************************/ 458 459 static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev) 460 { 461 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 462 u32 err_detect; 463 464 err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET); 465 466 if (!(err_detect & L2_EDE_MASK)) 467 return; 468 469 printk(KERN_ERR "ECC Error in CPU L2 cache\n"); 470 printk(KERN_ERR "L2 Error Detect Register: 0x%08x\n", err_detect); 471 printk(KERN_ERR "L2 Error Capture Data High Register: 0x%08x\n", 472 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI)); 473 printk(KERN_ERR "L2 Error Capture Data Lo Register: 0x%08x\n", 474 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO)); 475 printk(KERN_ERR "L2 Error Syndrome Register: 0x%08x\n", 476 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC)); 477 printk(KERN_ERR "L2 Error Attributes Capture Register: 0x%08x\n", 478 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR)); 479 printk(KERN_ERR "L2 Error Address Capture Register: 0x%08x\n", 480 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR)); 481 482 /* clear error detect register */ 483 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect); 484 485 if (err_detect & L2_EDE_CE_MASK) 486 edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name); 487 488 if (err_detect & L2_EDE_UE_MASK) 489 edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name); 490 } 491 492 static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id) 493 { 494 struct edac_device_ctl_info *edac_dev = dev_id; 495 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 496 u32 err_detect; 497 498 err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET); 499 500 if (!(err_detect & L2_EDE_MASK)) 501 return IRQ_NONE; 502 503 mpc85xx_l2_check(edac_dev); 504 505 return IRQ_HANDLED; 506 } 507 508 static int __devinit mpc85xx_l2_err_probe(struct of_device *op, 509 const struct of_device_id *match) 510 { 511 struct edac_device_ctl_info *edac_dev; 512 struct mpc85xx_l2_pdata *pdata; 513 struct resource r; 514 int res; 515 516 if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL)) 517 return -ENOMEM; 518 519 edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata), 520 "cpu", 1, "L", 1, 2, NULL, 0, 521 edac_dev_idx); 522 if (!edac_dev) { 523 devres_release_group(&op->dev, mpc85xx_l2_err_probe); 524 return -ENOMEM; 525 } 526 527 pdata = edac_dev->pvt_info; 528 pdata->name = "mpc85xx_l2_err"; 529 pdata->irq = NO_IRQ; 530 edac_dev->dev = &op->dev; 531 dev_set_drvdata(edac_dev->dev, edac_dev); 532 edac_dev->ctl_name = pdata->name; 533 edac_dev->dev_name = pdata->name; 534 535 res = of_address_to_resource(op->node, 0, &r); 536 if (res) { 537 printk(KERN_ERR "%s: Unable to get resource for " 538 "L2 err regs\n", __func__); 539 goto err; 540 } 541 542 /* we only need the error registers */ 543 r.start += 0xe00; 544 545 if (!devm_request_mem_region(&op->dev, r.start, 546 r.end - r.start + 1, pdata->name)) { 547 printk(KERN_ERR "%s: Error while requesting mem region\n", 548 __func__); 549 res = -EBUSY; 550 goto err; 551 } 552 553 pdata->l2_vbase = devm_ioremap(&op->dev, r.start, r.end - r.start + 1); 554 if (!pdata->l2_vbase) { 555 printk(KERN_ERR "%s: Unable to setup L2 err regs\n", __func__); 556 res = -ENOMEM; 557 goto err; 558 } 559 560 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0); 561 562 orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS); 563 564 /* clear the err_dis */ 565 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0); 566 567 edac_dev->mod_name = EDAC_MOD_STR; 568 569 if (edac_op_state == EDAC_OPSTATE_POLL) 570 edac_dev->edac_check = mpc85xx_l2_check; 571 572 mpc85xx_set_l2_sysfs_attributes(edac_dev); 573 574 pdata->edac_idx = edac_dev_idx++; 575 576 if (edac_device_add_device(edac_dev) > 0) { 577 debugf3("%s(): failed edac_device_add_device()\n", __func__); 578 goto err; 579 } 580 581 if (edac_op_state == EDAC_OPSTATE_INT) { 582 pdata->irq = irq_of_parse_and_map(op->node, 0); 583 res = devm_request_irq(&op->dev, pdata->irq, 584 mpc85xx_l2_isr, IRQF_DISABLED, 585 "[EDAC] L2 err", edac_dev); 586 if (res < 0) { 587 printk(KERN_ERR 588 "%s: Unable to requiest irq %d for " 589 "MPC85xx L2 err\n", __func__, pdata->irq); 590 irq_dispose_mapping(pdata->irq); 591 res = -ENODEV; 592 goto err2; 593 } 594 595 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for L2 Err\n", 596 pdata->irq); 597 598 edac_dev->op_state = OP_RUNNING_INTERRUPT; 599 600 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK); 601 } 602 603 devres_remove_group(&op->dev, mpc85xx_l2_err_probe); 604 605 debugf3("%s(): success\n", __func__); 606 printk(KERN_INFO EDAC_MOD_STR " L2 err registered\n"); 607 608 return 0; 609 610 err2: 611 edac_device_del_device(&op->dev); 612 err: 613 devres_release_group(&op->dev, mpc85xx_l2_err_probe); 614 edac_device_free_ctl_info(edac_dev); 615 return res; 616 } 617 618 static int mpc85xx_l2_err_remove(struct of_device *op) 619 { 620 struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev); 621 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 622 623 debugf0("%s()\n", __func__); 624 625 if (edac_op_state == EDAC_OPSTATE_INT) { 626 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0); 627 irq_dispose_mapping(pdata->irq); 628 } 629 630 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable); 631 edac_device_del_device(&op->dev); 632 edac_device_free_ctl_info(edac_dev); 633 return 0; 634 } 635 636 static struct of_device_id mpc85xx_l2_err_of_match[] = { 637 /* deprecate the fsl,85.. forms in the future, 2.6.30? */ 638 { .compatible = "fsl,8540-l2-cache-controller", }, 639 { .compatible = "fsl,8541-l2-cache-controller", }, 640 { .compatible = "fsl,8544-l2-cache-controller", }, 641 { .compatible = "fsl,8548-l2-cache-controller", }, 642 { .compatible = "fsl,8555-l2-cache-controller", }, 643 { .compatible = "fsl,8568-l2-cache-controller", }, 644 { .compatible = "fsl,mpc8536-l2-cache-controller", }, 645 { .compatible = "fsl,mpc8540-l2-cache-controller", }, 646 { .compatible = "fsl,mpc8541-l2-cache-controller", }, 647 { .compatible = "fsl,mpc8544-l2-cache-controller", }, 648 { .compatible = "fsl,mpc8548-l2-cache-controller", }, 649 { .compatible = "fsl,mpc8555-l2-cache-controller", }, 650 { .compatible = "fsl,mpc8560-l2-cache-controller", }, 651 { .compatible = "fsl,mpc8568-l2-cache-controller", }, 652 { .compatible = "fsl,mpc8572-l2-cache-controller", }, 653 { .compatible = "fsl,p2020-l2-cache-controller", }, 654 {}, 655 }; 656 657 static struct of_platform_driver mpc85xx_l2_err_driver = { 658 .owner = THIS_MODULE, 659 .name = "mpc85xx_l2_err", 660 .match_table = mpc85xx_l2_err_of_match, 661 .probe = mpc85xx_l2_err_probe, 662 .remove = mpc85xx_l2_err_remove, 663 .driver = { 664 .name = "mpc85xx_l2_err", 665 .owner = THIS_MODULE, 666 }, 667 }; 668 669 /**************************** MC Err device ***************************/ 670 671 static void mpc85xx_mc_check(struct mem_ctl_info *mci) 672 { 673 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 674 struct csrow_info *csrow; 675 u32 err_detect; 676 u32 syndrome; 677 u32 err_addr; 678 u32 pfn; 679 int row_index; 680 681 err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT); 682 if (!err_detect) 683 return; 684 685 mpc85xx_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n", 686 err_detect); 687 688 /* no more processing if not ECC bit errors */ 689 if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) { 690 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect); 691 return; 692 } 693 694 syndrome = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ECC); 695 err_addr = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ADDRESS); 696 pfn = err_addr >> PAGE_SHIFT; 697 698 for (row_index = 0; row_index < mci->nr_csrows; row_index++) { 699 csrow = &mci->csrows[row_index]; 700 if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page)) 701 break; 702 } 703 704 mpc85xx_mc_printk(mci, KERN_ERR, "Capture Data High: %#8.8x\n", 705 in_be32(pdata->mc_vbase + 706 MPC85XX_MC_CAPTURE_DATA_HI)); 707 mpc85xx_mc_printk(mci, KERN_ERR, "Capture Data Low: %#8.8x\n", 708 in_be32(pdata->mc_vbase + 709 MPC85XX_MC_CAPTURE_DATA_LO)); 710 mpc85xx_mc_printk(mci, KERN_ERR, "syndrome: %#8.8x\n", syndrome); 711 mpc85xx_mc_printk(mci, KERN_ERR, "err addr: %#8.8x\n", err_addr); 712 mpc85xx_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn); 713 714 /* we are out of range */ 715 if (row_index == mci->nr_csrows) 716 mpc85xx_mc_printk(mci, KERN_ERR, "PFN out of range!\n"); 717 718 if (err_detect & DDR_EDE_SBE) 719 edac_mc_handle_ce(mci, pfn, err_addr & PAGE_MASK, 720 syndrome, row_index, 0, mci->ctl_name); 721 722 if (err_detect & DDR_EDE_MBE) 723 edac_mc_handle_ue(mci, pfn, err_addr & PAGE_MASK, 724 row_index, mci->ctl_name); 725 726 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect); 727 } 728 729 static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id) 730 { 731 struct mem_ctl_info *mci = dev_id; 732 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 733 u32 err_detect; 734 735 err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT); 736 if (!err_detect) 737 return IRQ_NONE; 738 739 mpc85xx_mc_check(mci); 740 741 return IRQ_HANDLED; 742 } 743 744 static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci) 745 { 746 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 747 struct csrow_info *csrow; 748 u32 sdram_ctl; 749 u32 sdtype; 750 enum mem_type mtype; 751 u32 cs_bnds; 752 int index; 753 754 sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG); 755 756 sdtype = sdram_ctl & DSC_SDTYPE_MASK; 757 if (sdram_ctl & DSC_RD_EN) { 758 switch (sdtype) { 759 case DSC_SDTYPE_DDR: 760 mtype = MEM_RDDR; 761 break; 762 case DSC_SDTYPE_DDR2: 763 mtype = MEM_RDDR2; 764 break; 765 case DSC_SDTYPE_DDR3: 766 mtype = MEM_RDDR3; 767 break; 768 default: 769 mtype = MEM_UNKNOWN; 770 break; 771 } 772 } else { 773 switch (sdtype) { 774 case DSC_SDTYPE_DDR: 775 mtype = MEM_DDR; 776 break; 777 case DSC_SDTYPE_DDR2: 778 mtype = MEM_DDR2; 779 break; 780 case DSC_SDTYPE_DDR3: 781 mtype = MEM_DDR3; 782 break; 783 default: 784 mtype = MEM_UNKNOWN; 785 break; 786 } 787 } 788 789 for (index = 0; index < mci->nr_csrows; index++) { 790 u32 start; 791 u32 end; 792 793 csrow = &mci->csrows[index]; 794 cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 + 795 (index * MPC85XX_MC_CS_BNDS_OFS)); 796 797 start = (cs_bnds & 0xffff0000) >> 16; 798 end = (cs_bnds & 0x0000ffff); 799 800 if (start == end) 801 continue; /* not populated */ 802 803 start <<= (24 - PAGE_SHIFT); 804 end <<= (24 - PAGE_SHIFT); 805 end |= (1 << (24 - PAGE_SHIFT)) - 1; 806 807 csrow->first_page = start >> PAGE_SHIFT; 808 csrow->last_page = end >> PAGE_SHIFT; 809 csrow->nr_pages = end + 1 - start; 810 csrow->grain = 8; 811 csrow->mtype = mtype; 812 csrow->dtype = DEV_UNKNOWN; 813 if (sdram_ctl & DSC_X32_EN) 814 csrow->dtype = DEV_X32; 815 csrow->edac_mode = EDAC_SECDED; 816 } 817 } 818 819 static int __devinit mpc85xx_mc_err_probe(struct of_device *op, 820 const struct of_device_id *match) 821 { 822 struct mem_ctl_info *mci; 823 struct mpc85xx_mc_pdata *pdata; 824 struct resource r; 825 u32 sdram_ctl; 826 int res; 827 828 if (!devres_open_group(&op->dev, mpc85xx_mc_err_probe, GFP_KERNEL)) 829 return -ENOMEM; 830 831 mci = edac_mc_alloc(sizeof(*pdata), 4, 1, edac_mc_idx); 832 if (!mci) { 833 devres_release_group(&op->dev, mpc85xx_mc_err_probe); 834 return -ENOMEM; 835 } 836 837 pdata = mci->pvt_info; 838 pdata->name = "mpc85xx_mc_err"; 839 pdata->irq = NO_IRQ; 840 mci->dev = &op->dev; 841 pdata->edac_idx = edac_mc_idx++; 842 dev_set_drvdata(mci->dev, mci); 843 mci->ctl_name = pdata->name; 844 mci->dev_name = pdata->name; 845 846 res = of_address_to_resource(op->node, 0, &r); 847 if (res) { 848 printk(KERN_ERR "%s: Unable to get resource for MC err regs\n", 849 __func__); 850 goto err; 851 } 852 853 if (!devm_request_mem_region(&op->dev, r.start, 854 r.end - r.start + 1, pdata->name)) { 855 printk(KERN_ERR "%s: Error while requesting mem region\n", 856 __func__); 857 res = -EBUSY; 858 goto err; 859 } 860 861 pdata->mc_vbase = devm_ioremap(&op->dev, r.start, r.end - r.start + 1); 862 if (!pdata->mc_vbase) { 863 printk(KERN_ERR "%s: Unable to setup MC err regs\n", __func__); 864 res = -ENOMEM; 865 goto err; 866 } 867 868 sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG); 869 if (!(sdram_ctl & DSC_ECC_EN)) { 870 /* no ECC */ 871 printk(KERN_WARNING "%s: No ECC DIMMs discovered\n", __func__); 872 res = -ENODEV; 873 goto err; 874 } 875 876 debugf3("%s(): init mci\n", __func__); 877 mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 | 878 MEM_FLAG_DDR | MEM_FLAG_DDR2; 879 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; 880 mci->edac_cap = EDAC_FLAG_SECDED; 881 mci->mod_name = EDAC_MOD_STR; 882 mci->mod_ver = MPC85XX_REVISION; 883 884 if (edac_op_state == EDAC_OPSTATE_POLL) 885 mci->edac_check = mpc85xx_mc_check; 886 887 mci->ctl_page_to_phys = NULL; 888 889 mci->scrub_mode = SCRUB_SW_SRC; 890 891 mpc85xx_set_mc_sysfs_attributes(mci); 892 893 mpc85xx_init_csrows(mci); 894 895 #ifdef CONFIG_EDAC_DEBUG 896 edac_mc_register_mcidev_debug((struct attribute **)debug_attr); 897 #endif 898 899 /* store the original error disable bits */ 900 orig_ddr_err_disable = 901 in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE); 902 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 0); 903 904 /* clear all error bits */ 905 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0); 906 907 if (edac_mc_add_mc(mci)) { 908 debugf3("%s(): failed edac_mc_add_mc()\n", __func__); 909 goto err; 910 } 911 912 if (edac_op_state == EDAC_OPSTATE_INT) { 913 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 914 DDR_EIE_MBEE | DDR_EIE_SBEE); 915 916 /* store the original error management threshold */ 917 orig_ddr_err_sbe = in_be32(pdata->mc_vbase + 918 MPC85XX_MC_ERR_SBE) & 0xff0000; 919 920 /* set threshold to 1 error per interrupt */ 921 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, 0x10000); 922 923 /* register interrupts */ 924 pdata->irq = irq_of_parse_and_map(op->node, 0); 925 res = devm_request_irq(&op->dev, pdata->irq, 926 mpc85xx_mc_isr, 927 IRQF_DISABLED | IRQF_SHARED, 928 "[EDAC] MC err", mci); 929 if (res < 0) { 930 printk(KERN_ERR "%s: Unable to request irq %d for " 931 "MPC85xx DRAM ERR\n", __func__, pdata->irq); 932 irq_dispose_mapping(pdata->irq); 933 res = -ENODEV; 934 goto err2; 935 } 936 937 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for MC\n", 938 pdata->irq); 939 } 940 941 devres_remove_group(&op->dev, mpc85xx_mc_err_probe); 942 debugf3("%s(): success\n", __func__); 943 printk(KERN_INFO EDAC_MOD_STR " MC err registered\n"); 944 945 return 0; 946 947 err2: 948 edac_mc_del_mc(&op->dev); 949 err: 950 devres_release_group(&op->dev, mpc85xx_mc_err_probe); 951 edac_mc_free(mci); 952 return res; 953 } 954 955 static int mpc85xx_mc_err_remove(struct of_device *op) 956 { 957 struct mem_ctl_info *mci = dev_get_drvdata(&op->dev); 958 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 959 960 debugf0("%s()\n", __func__); 961 962 if (edac_op_state == EDAC_OPSTATE_INT) { 963 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0); 964 irq_dispose_mapping(pdata->irq); 965 } 966 967 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 968 orig_ddr_err_disable); 969 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, orig_ddr_err_sbe); 970 971 edac_mc_del_mc(&op->dev); 972 edac_mc_free(mci); 973 return 0; 974 } 975 976 static struct of_device_id mpc85xx_mc_err_of_match[] = { 977 /* deprecate the fsl,85.. forms in the future, 2.6.30? */ 978 { .compatible = "fsl,8540-memory-controller", }, 979 { .compatible = "fsl,8541-memory-controller", }, 980 { .compatible = "fsl,8544-memory-controller", }, 981 { .compatible = "fsl,8548-memory-controller", }, 982 { .compatible = "fsl,8555-memory-controller", }, 983 { .compatible = "fsl,8568-memory-controller", }, 984 { .compatible = "fsl,mpc8536-memory-controller", }, 985 { .compatible = "fsl,mpc8540-memory-controller", }, 986 { .compatible = "fsl,mpc8541-memory-controller", }, 987 { .compatible = "fsl,mpc8544-memory-controller", }, 988 { .compatible = "fsl,mpc8548-memory-controller", }, 989 { .compatible = "fsl,mpc8555-memory-controller", }, 990 { .compatible = "fsl,mpc8560-memory-controller", }, 991 { .compatible = "fsl,mpc8568-memory-controller", }, 992 { .compatible = "fsl,mpc8572-memory-controller", }, 993 { .compatible = "fsl,mpc8349-memory-controller", }, 994 { .compatible = "fsl,p2020-memory-controller", }, 995 {}, 996 }; 997 998 static struct of_platform_driver mpc85xx_mc_err_driver = { 999 .owner = THIS_MODULE, 1000 .name = "mpc85xx_mc_err", 1001 .match_table = mpc85xx_mc_err_of_match, 1002 .probe = mpc85xx_mc_err_probe, 1003 .remove = mpc85xx_mc_err_remove, 1004 .driver = { 1005 .name = "mpc85xx_mc_err", 1006 .owner = THIS_MODULE, 1007 }, 1008 }; 1009 1010 #ifdef CONFIG_MPC85xx 1011 static void __init mpc85xx_mc_clear_rfxe(void *data) 1012 { 1013 orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1); 1014 mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~0x20000)); 1015 } 1016 #endif 1017 1018 static int __init mpc85xx_mc_init(void) 1019 { 1020 int res = 0; 1021 1022 printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, " 1023 "(C) 2006 Montavista Software\n"); 1024 1025 /* make sure error reporting method is sane */ 1026 switch (edac_op_state) { 1027 case EDAC_OPSTATE_POLL: 1028 case EDAC_OPSTATE_INT: 1029 break; 1030 default: 1031 edac_op_state = EDAC_OPSTATE_INT; 1032 break; 1033 } 1034 1035 res = of_register_platform_driver(&mpc85xx_mc_err_driver); 1036 if (res) 1037 printk(KERN_WARNING EDAC_MOD_STR "MC fails to register\n"); 1038 1039 res = of_register_platform_driver(&mpc85xx_l2_err_driver); 1040 if (res) 1041 printk(KERN_WARNING EDAC_MOD_STR "L2 fails to register\n"); 1042 1043 #ifdef CONFIG_PCI 1044 res = of_register_platform_driver(&mpc85xx_pci_err_driver); 1045 if (res) 1046 printk(KERN_WARNING EDAC_MOD_STR "PCI fails to register\n"); 1047 #endif 1048 1049 #ifdef CONFIG_MPC85xx 1050 /* 1051 * need to clear HID1[RFXE] to disable machine check int 1052 * so we can catch it 1053 */ 1054 if (edac_op_state == EDAC_OPSTATE_INT) 1055 on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0); 1056 #endif 1057 1058 return 0; 1059 } 1060 1061 module_init(mpc85xx_mc_init); 1062 1063 #ifdef CONFIG_MPC85xx 1064 static void __exit mpc85xx_mc_restore_hid1(void *data) 1065 { 1066 mtspr(SPRN_HID1, orig_hid1[smp_processor_id()]); 1067 } 1068 #endif 1069 1070 static void __exit mpc85xx_mc_exit(void) 1071 { 1072 #ifdef CONFIG_MPC85xx 1073 on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0); 1074 #endif 1075 #ifdef CONFIG_PCI 1076 of_unregister_platform_driver(&mpc85xx_pci_err_driver); 1077 #endif 1078 of_unregister_platform_driver(&mpc85xx_l2_err_driver); 1079 of_unregister_platform_driver(&mpc85xx_mc_err_driver); 1080 } 1081 1082 module_exit(mpc85xx_mc_exit); 1083 1084 MODULE_LICENSE("GPL"); 1085 MODULE_AUTHOR("Montavista Software, Inc."); 1086 module_param(edac_op_state, int, 0444); 1087 MODULE_PARM_DESC(edac_op_state, 1088 "EDAC Error Reporting state: 0=Poll, 2=Interrupt"); 1089