1 /* 2 * Freescale MPC85xx Memory Controller kenel module 3 * 4 * Author: Dave Jiang <djiang@mvista.com> 5 * 6 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under 7 * the terms of the GNU General Public License version 2. This program 8 * is licensed "as is" without any warranty of any kind, whether express 9 * or implied. 10 * 11 */ 12 #include <linux/module.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/ctype.h> 16 #include <linux/io.h> 17 #include <linux/mod_devicetable.h> 18 #include <linux/edac.h> 19 #include <linux/smp.h> 20 #include <linux/gfp.h> 21 22 #include <linux/of_platform.h> 23 #include <linux/of_device.h> 24 #include "edac_module.h" 25 #include "edac_core.h" 26 #include "mpc85xx_edac.h" 27 28 static int edac_dev_idx; 29 #ifdef CONFIG_PCI 30 static int edac_pci_idx; 31 #endif 32 static int edac_mc_idx; 33 34 static u32 orig_ddr_err_disable; 35 static u32 orig_ddr_err_sbe; 36 37 /* 38 * PCI Err defines 39 */ 40 #ifdef CONFIG_PCI 41 static u32 orig_pci_err_cap_dr; 42 static u32 orig_pci_err_en; 43 #endif 44 45 static u32 orig_l2_err_disable; 46 #ifdef CONFIG_MPC85xx 47 static u32 orig_hid1[2]; 48 #endif 49 50 /************************ MC SYSFS parts ***********************************/ 51 52 static ssize_t mpc85xx_mc_inject_data_hi_show(struct mem_ctl_info *mci, 53 char *data) 54 { 55 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 56 return sprintf(data, "0x%08x", 57 in_be32(pdata->mc_vbase + 58 MPC85XX_MC_DATA_ERR_INJECT_HI)); 59 } 60 61 static ssize_t mpc85xx_mc_inject_data_lo_show(struct mem_ctl_info *mci, 62 char *data) 63 { 64 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 65 return sprintf(data, "0x%08x", 66 in_be32(pdata->mc_vbase + 67 MPC85XX_MC_DATA_ERR_INJECT_LO)); 68 } 69 70 static ssize_t mpc85xx_mc_inject_ctrl_show(struct mem_ctl_info *mci, char *data) 71 { 72 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 73 return sprintf(data, "0x%08x", 74 in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT)); 75 } 76 77 static ssize_t mpc85xx_mc_inject_data_hi_store(struct mem_ctl_info *mci, 78 const char *data, size_t count) 79 { 80 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 81 if (isdigit(*data)) { 82 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI, 83 simple_strtoul(data, NULL, 0)); 84 return count; 85 } 86 return 0; 87 } 88 89 static ssize_t mpc85xx_mc_inject_data_lo_store(struct mem_ctl_info *mci, 90 const char *data, size_t count) 91 { 92 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 93 if (isdigit(*data)) { 94 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO, 95 simple_strtoul(data, NULL, 0)); 96 return count; 97 } 98 return 0; 99 } 100 101 static ssize_t mpc85xx_mc_inject_ctrl_store(struct mem_ctl_info *mci, 102 const char *data, size_t count) 103 { 104 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 105 if (isdigit(*data)) { 106 out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT, 107 simple_strtoul(data, NULL, 0)); 108 return count; 109 } 110 return 0; 111 } 112 113 static struct mcidev_sysfs_attribute mpc85xx_mc_sysfs_attributes[] = { 114 { 115 .attr = { 116 .name = "inject_data_hi", 117 .mode = (S_IRUGO | S_IWUSR) 118 }, 119 .show = mpc85xx_mc_inject_data_hi_show, 120 .store = mpc85xx_mc_inject_data_hi_store}, 121 { 122 .attr = { 123 .name = "inject_data_lo", 124 .mode = (S_IRUGO | S_IWUSR) 125 }, 126 .show = mpc85xx_mc_inject_data_lo_show, 127 .store = mpc85xx_mc_inject_data_lo_store}, 128 { 129 .attr = { 130 .name = "inject_ctrl", 131 .mode = (S_IRUGO | S_IWUSR) 132 }, 133 .show = mpc85xx_mc_inject_ctrl_show, 134 .store = mpc85xx_mc_inject_ctrl_store}, 135 136 /* End of list */ 137 { 138 .attr = {.name = NULL} 139 } 140 }; 141 142 static void mpc85xx_set_mc_sysfs_attributes(struct mem_ctl_info *mci) 143 { 144 mci->mc_driver_sysfs_attributes = mpc85xx_mc_sysfs_attributes; 145 } 146 147 /**************************** PCI Err device ***************************/ 148 #ifdef CONFIG_PCI 149 150 static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci) 151 { 152 struct mpc85xx_pci_pdata *pdata = pci->pvt_info; 153 u32 err_detect; 154 155 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); 156 157 /* master aborts can happen during PCI config cycles */ 158 if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) { 159 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); 160 return; 161 } 162 163 printk(KERN_ERR "PCI error(s) detected\n"); 164 printk(KERN_ERR "PCI/X ERR_DR register: %#08x\n", err_detect); 165 166 printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x\n", 167 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB)); 168 printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x\n", 169 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR)); 170 printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x\n", 171 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR)); 172 printk(KERN_ERR "PCI/X ERR_DL register: %#08x\n", 173 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL)); 174 printk(KERN_ERR "PCI/X ERR_DH register: %#08x\n", 175 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH)); 176 177 /* clear error bits */ 178 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); 179 180 if (err_detect & PCI_EDE_PERR_MASK) 181 edac_pci_handle_pe(pci, pci->ctl_name); 182 183 if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK) 184 edac_pci_handle_npe(pci, pci->ctl_name); 185 } 186 187 static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id) 188 { 189 struct edac_pci_ctl_info *pci = dev_id; 190 struct mpc85xx_pci_pdata *pdata = pci->pvt_info; 191 u32 err_detect; 192 193 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); 194 195 if (!err_detect) 196 return IRQ_NONE; 197 198 mpc85xx_pci_check(pci); 199 200 return IRQ_HANDLED; 201 } 202 203 static int __devinit mpc85xx_pci_err_probe(struct of_device *op, 204 const struct of_device_id *match) 205 { 206 struct edac_pci_ctl_info *pci; 207 struct mpc85xx_pci_pdata *pdata; 208 struct resource r; 209 int res = 0; 210 211 if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL)) 212 return -ENOMEM; 213 214 pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err"); 215 if (!pci) 216 return -ENOMEM; 217 218 pdata = pci->pvt_info; 219 pdata->name = "mpc85xx_pci_err"; 220 pdata->irq = NO_IRQ; 221 dev_set_drvdata(&op->dev, pci); 222 pci->dev = &op->dev; 223 pci->mod_name = EDAC_MOD_STR; 224 pci->ctl_name = pdata->name; 225 pci->dev_name = dev_name(&op->dev); 226 227 if (edac_op_state == EDAC_OPSTATE_POLL) 228 pci->edac_check = mpc85xx_pci_check; 229 230 pdata->edac_idx = edac_pci_idx++; 231 232 res = of_address_to_resource(op->dev.of_node, 0, &r); 233 if (res) { 234 printk(KERN_ERR "%s: Unable to get resource for " 235 "PCI err regs\n", __func__); 236 goto err; 237 } 238 239 /* we only need the error registers */ 240 r.start += 0xe00; 241 242 if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r), 243 pdata->name)) { 244 printk(KERN_ERR "%s: Error while requesting mem region\n", 245 __func__); 246 res = -EBUSY; 247 goto err; 248 } 249 250 pdata->pci_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r)); 251 if (!pdata->pci_vbase) { 252 printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__); 253 res = -ENOMEM; 254 goto err; 255 } 256 257 orig_pci_err_cap_dr = 258 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR); 259 260 /* PCI master abort is expected during config cycles */ 261 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40); 262 263 orig_pci_err_en = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN); 264 265 /* disable master abort reporting */ 266 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40); 267 268 /* clear error bits */ 269 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0); 270 271 if (edac_pci_add_device(pci, pdata->edac_idx) > 0) { 272 debugf3("%s(): failed edac_pci_add_device()\n", __func__); 273 goto err; 274 } 275 276 if (edac_op_state == EDAC_OPSTATE_INT) { 277 pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0); 278 res = devm_request_irq(&op->dev, pdata->irq, 279 mpc85xx_pci_isr, IRQF_DISABLED, 280 "[EDAC] PCI err", pci); 281 if (res < 0) { 282 printk(KERN_ERR 283 "%s: Unable to requiest irq %d for " 284 "MPC85xx PCI err\n", __func__, pdata->irq); 285 irq_dispose_mapping(pdata->irq); 286 res = -ENODEV; 287 goto err2; 288 } 289 290 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for PCI Err\n", 291 pdata->irq); 292 } 293 294 devres_remove_group(&op->dev, mpc85xx_pci_err_probe); 295 debugf3("%s(): success\n", __func__); 296 printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n"); 297 298 return 0; 299 300 err2: 301 edac_pci_del_device(&op->dev); 302 err: 303 edac_pci_free_ctl_info(pci); 304 devres_release_group(&op->dev, mpc85xx_pci_err_probe); 305 return res; 306 } 307 308 static int mpc85xx_pci_err_remove(struct of_device *op) 309 { 310 struct edac_pci_ctl_info *pci = dev_get_drvdata(&op->dev); 311 struct mpc85xx_pci_pdata *pdata = pci->pvt_info; 312 313 debugf0("%s()\n", __func__); 314 315 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 316 orig_pci_err_cap_dr); 317 318 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, orig_pci_err_en); 319 320 edac_pci_del_device(pci->dev); 321 322 if (edac_op_state == EDAC_OPSTATE_INT) 323 irq_dispose_mapping(pdata->irq); 324 325 edac_pci_free_ctl_info(pci); 326 327 return 0; 328 } 329 330 static struct of_device_id mpc85xx_pci_err_of_match[] = { 331 { 332 .compatible = "fsl,mpc8540-pcix", 333 }, 334 { 335 .compatible = "fsl,mpc8540-pci", 336 }, 337 {}, 338 }; 339 340 static struct of_platform_driver mpc85xx_pci_err_driver = { 341 .probe = mpc85xx_pci_err_probe, 342 .remove = __devexit_p(mpc85xx_pci_err_remove), 343 .driver = { 344 .name = "mpc85xx_pci_err", 345 .owner = THIS_MODULE, 346 .of_match_table = mpc85xx_pci_err_of_match, 347 }, 348 }; 349 350 #endif /* CONFIG_PCI */ 351 352 /**************************** L2 Err device ***************************/ 353 354 /************************ L2 SYSFS parts ***********************************/ 355 356 static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info 357 *edac_dev, char *data) 358 { 359 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 360 return sprintf(data, "0x%08x", 361 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI)); 362 } 363 364 static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info 365 *edac_dev, char *data) 366 { 367 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 368 return sprintf(data, "0x%08x", 369 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO)); 370 } 371 372 static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info 373 *edac_dev, char *data) 374 { 375 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 376 return sprintf(data, "0x%08x", 377 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL)); 378 } 379 380 static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info 381 *edac_dev, const char *data, 382 size_t count) 383 { 384 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 385 if (isdigit(*data)) { 386 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI, 387 simple_strtoul(data, NULL, 0)); 388 return count; 389 } 390 return 0; 391 } 392 393 static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info 394 *edac_dev, const char *data, 395 size_t count) 396 { 397 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 398 if (isdigit(*data)) { 399 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO, 400 simple_strtoul(data, NULL, 0)); 401 return count; 402 } 403 return 0; 404 } 405 406 static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info 407 *edac_dev, const char *data, 408 size_t count) 409 { 410 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 411 if (isdigit(*data)) { 412 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL, 413 simple_strtoul(data, NULL, 0)); 414 return count; 415 } 416 return 0; 417 } 418 419 static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = { 420 { 421 .attr = { 422 .name = "inject_data_hi", 423 .mode = (S_IRUGO | S_IWUSR) 424 }, 425 .show = mpc85xx_l2_inject_data_hi_show, 426 .store = mpc85xx_l2_inject_data_hi_store}, 427 { 428 .attr = { 429 .name = "inject_data_lo", 430 .mode = (S_IRUGO | S_IWUSR) 431 }, 432 .show = mpc85xx_l2_inject_data_lo_show, 433 .store = mpc85xx_l2_inject_data_lo_store}, 434 { 435 .attr = { 436 .name = "inject_ctrl", 437 .mode = (S_IRUGO | S_IWUSR) 438 }, 439 .show = mpc85xx_l2_inject_ctrl_show, 440 .store = mpc85xx_l2_inject_ctrl_store}, 441 442 /* End of list */ 443 { 444 .attr = {.name = NULL} 445 } 446 }; 447 448 static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info 449 *edac_dev) 450 { 451 edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes; 452 } 453 454 /***************************** L2 ops ***********************************/ 455 456 static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev) 457 { 458 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 459 u32 err_detect; 460 461 err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET); 462 463 if (!(err_detect & L2_EDE_MASK)) 464 return; 465 466 printk(KERN_ERR "ECC Error in CPU L2 cache\n"); 467 printk(KERN_ERR "L2 Error Detect Register: 0x%08x\n", err_detect); 468 printk(KERN_ERR "L2 Error Capture Data High Register: 0x%08x\n", 469 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI)); 470 printk(KERN_ERR "L2 Error Capture Data Lo Register: 0x%08x\n", 471 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO)); 472 printk(KERN_ERR "L2 Error Syndrome Register: 0x%08x\n", 473 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC)); 474 printk(KERN_ERR "L2 Error Attributes Capture Register: 0x%08x\n", 475 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR)); 476 printk(KERN_ERR "L2 Error Address Capture Register: 0x%08x\n", 477 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR)); 478 479 /* clear error detect register */ 480 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect); 481 482 if (err_detect & L2_EDE_CE_MASK) 483 edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name); 484 485 if (err_detect & L2_EDE_UE_MASK) 486 edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name); 487 } 488 489 static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id) 490 { 491 struct edac_device_ctl_info *edac_dev = dev_id; 492 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 493 u32 err_detect; 494 495 err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET); 496 497 if (!(err_detect & L2_EDE_MASK)) 498 return IRQ_NONE; 499 500 mpc85xx_l2_check(edac_dev); 501 502 return IRQ_HANDLED; 503 } 504 505 static int __devinit mpc85xx_l2_err_probe(struct of_device *op, 506 const struct of_device_id *match) 507 { 508 struct edac_device_ctl_info *edac_dev; 509 struct mpc85xx_l2_pdata *pdata; 510 struct resource r; 511 int res; 512 513 if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL)) 514 return -ENOMEM; 515 516 edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata), 517 "cpu", 1, "L", 1, 2, NULL, 0, 518 edac_dev_idx); 519 if (!edac_dev) { 520 devres_release_group(&op->dev, mpc85xx_l2_err_probe); 521 return -ENOMEM; 522 } 523 524 pdata = edac_dev->pvt_info; 525 pdata->name = "mpc85xx_l2_err"; 526 pdata->irq = NO_IRQ; 527 edac_dev->dev = &op->dev; 528 dev_set_drvdata(edac_dev->dev, edac_dev); 529 edac_dev->ctl_name = pdata->name; 530 edac_dev->dev_name = pdata->name; 531 532 res = of_address_to_resource(op->dev.of_node, 0, &r); 533 if (res) { 534 printk(KERN_ERR "%s: Unable to get resource for " 535 "L2 err regs\n", __func__); 536 goto err; 537 } 538 539 /* we only need the error registers */ 540 r.start += 0xe00; 541 542 if (!devm_request_mem_region(&op->dev, r.start, 543 r.end - r.start + 1, pdata->name)) { 544 printk(KERN_ERR "%s: Error while requesting mem region\n", 545 __func__); 546 res = -EBUSY; 547 goto err; 548 } 549 550 pdata->l2_vbase = devm_ioremap(&op->dev, r.start, r.end - r.start + 1); 551 if (!pdata->l2_vbase) { 552 printk(KERN_ERR "%s: Unable to setup L2 err regs\n", __func__); 553 res = -ENOMEM; 554 goto err; 555 } 556 557 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0); 558 559 orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS); 560 561 /* clear the err_dis */ 562 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0); 563 564 edac_dev->mod_name = EDAC_MOD_STR; 565 566 if (edac_op_state == EDAC_OPSTATE_POLL) 567 edac_dev->edac_check = mpc85xx_l2_check; 568 569 mpc85xx_set_l2_sysfs_attributes(edac_dev); 570 571 pdata->edac_idx = edac_dev_idx++; 572 573 if (edac_device_add_device(edac_dev) > 0) { 574 debugf3("%s(): failed edac_device_add_device()\n", __func__); 575 goto err; 576 } 577 578 if (edac_op_state == EDAC_OPSTATE_INT) { 579 pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0); 580 res = devm_request_irq(&op->dev, pdata->irq, 581 mpc85xx_l2_isr, IRQF_DISABLED, 582 "[EDAC] L2 err", edac_dev); 583 if (res < 0) { 584 printk(KERN_ERR 585 "%s: Unable to requiest irq %d for " 586 "MPC85xx L2 err\n", __func__, pdata->irq); 587 irq_dispose_mapping(pdata->irq); 588 res = -ENODEV; 589 goto err2; 590 } 591 592 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for L2 Err\n", 593 pdata->irq); 594 595 edac_dev->op_state = OP_RUNNING_INTERRUPT; 596 597 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK); 598 } 599 600 devres_remove_group(&op->dev, mpc85xx_l2_err_probe); 601 602 debugf3("%s(): success\n", __func__); 603 printk(KERN_INFO EDAC_MOD_STR " L2 err registered\n"); 604 605 return 0; 606 607 err2: 608 edac_device_del_device(&op->dev); 609 err: 610 devres_release_group(&op->dev, mpc85xx_l2_err_probe); 611 edac_device_free_ctl_info(edac_dev); 612 return res; 613 } 614 615 static int mpc85xx_l2_err_remove(struct of_device *op) 616 { 617 struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev); 618 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 619 620 debugf0("%s()\n", __func__); 621 622 if (edac_op_state == EDAC_OPSTATE_INT) { 623 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0); 624 irq_dispose_mapping(pdata->irq); 625 } 626 627 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable); 628 edac_device_del_device(&op->dev); 629 edac_device_free_ctl_info(edac_dev); 630 return 0; 631 } 632 633 static struct of_device_id mpc85xx_l2_err_of_match[] = { 634 /* deprecate the fsl,85.. forms in the future, 2.6.30? */ 635 { .compatible = "fsl,8540-l2-cache-controller", }, 636 { .compatible = "fsl,8541-l2-cache-controller", }, 637 { .compatible = "fsl,8544-l2-cache-controller", }, 638 { .compatible = "fsl,8548-l2-cache-controller", }, 639 { .compatible = "fsl,8555-l2-cache-controller", }, 640 { .compatible = "fsl,8568-l2-cache-controller", }, 641 { .compatible = "fsl,mpc8536-l2-cache-controller", }, 642 { .compatible = "fsl,mpc8540-l2-cache-controller", }, 643 { .compatible = "fsl,mpc8541-l2-cache-controller", }, 644 { .compatible = "fsl,mpc8544-l2-cache-controller", }, 645 { .compatible = "fsl,mpc8548-l2-cache-controller", }, 646 { .compatible = "fsl,mpc8555-l2-cache-controller", }, 647 { .compatible = "fsl,mpc8560-l2-cache-controller", }, 648 { .compatible = "fsl,mpc8568-l2-cache-controller", }, 649 { .compatible = "fsl,mpc8572-l2-cache-controller", }, 650 { .compatible = "fsl,p2020-l2-cache-controller", }, 651 {}, 652 }; 653 654 static struct of_platform_driver mpc85xx_l2_err_driver = { 655 .probe = mpc85xx_l2_err_probe, 656 .remove = mpc85xx_l2_err_remove, 657 .driver = { 658 .name = "mpc85xx_l2_err", 659 .owner = THIS_MODULE, 660 .of_match_table = mpc85xx_l2_err_of_match, 661 }, 662 }; 663 664 /**************************** MC Err device ***************************/ 665 666 /* 667 * Taken from table 8-55 in the MPC8641 User's Manual and/or 9-61 in the 668 * MPC8572 User's Manual. Each line represents a syndrome bit column as a 669 * 64-bit value, but split into an upper and lower 32-bit chunk. The labels 670 * below correspond to Freescale's manuals. 671 */ 672 static unsigned int ecc_table[16] = { 673 /* MSB LSB */ 674 /* [0:31] [32:63] */ 675 0xf00fe11e, 0xc33c0ff7, /* Syndrome bit 7 */ 676 0x00ff00ff, 0x00fff0ff, 677 0x0f0f0f0f, 0x0f0fff00, 678 0x11113333, 0x7777000f, 679 0x22224444, 0x8888222f, 680 0x44448888, 0xffff4441, 681 0x8888ffff, 0x11118882, 682 0xffff1111, 0x22221114, /* Syndrome bit 0 */ 683 }; 684 685 /* 686 * Calculate the correct ECC value for a 64-bit value specified by high:low 687 */ 688 static u8 calculate_ecc(u32 high, u32 low) 689 { 690 u32 mask_low; 691 u32 mask_high; 692 int bit_cnt; 693 u8 ecc = 0; 694 int i; 695 int j; 696 697 for (i = 0; i < 8; i++) { 698 mask_high = ecc_table[i * 2]; 699 mask_low = ecc_table[i * 2 + 1]; 700 bit_cnt = 0; 701 702 for (j = 0; j < 32; j++) { 703 if ((mask_high >> j) & 1) 704 bit_cnt ^= (high >> j) & 1; 705 if ((mask_low >> j) & 1) 706 bit_cnt ^= (low >> j) & 1; 707 } 708 709 ecc |= bit_cnt << i; 710 } 711 712 return ecc; 713 } 714 715 /* 716 * Create the syndrome code which is generated if the data line specified by 717 * 'bit' failed. Eg generate an 8-bit codes seen in Table 8-55 in the MPC8641 718 * User's Manual and 9-61 in the MPC8572 User's Manual. 719 */ 720 static u8 syndrome_from_bit(unsigned int bit) { 721 int i; 722 u8 syndrome = 0; 723 724 /* 725 * Cycle through the upper or lower 32-bit portion of each value in 726 * ecc_table depending on if 'bit' is in the upper or lower half of 727 * 64-bit data. 728 */ 729 for (i = bit < 32; i < 16; i += 2) 730 syndrome |= ((ecc_table[i] >> (bit % 32)) & 1) << (i / 2); 731 732 return syndrome; 733 } 734 735 /* 736 * Decode data and ecc syndrome to determine what went wrong 737 * Note: This can only decode single-bit errors 738 */ 739 static void sbe_ecc_decode(u32 cap_high, u32 cap_low, u32 cap_ecc, 740 int *bad_data_bit, int *bad_ecc_bit) 741 { 742 int i; 743 u8 syndrome; 744 745 *bad_data_bit = -1; 746 *bad_ecc_bit = -1; 747 748 /* 749 * Calculate the ECC of the captured data and XOR it with the captured 750 * ECC to find an ECC syndrome value we can search for 751 */ 752 syndrome = calculate_ecc(cap_high, cap_low) ^ cap_ecc; 753 754 /* Check if a data line is stuck... */ 755 for (i = 0; i < 64; i++) { 756 if (syndrome == syndrome_from_bit(i)) { 757 *bad_data_bit = i; 758 return; 759 } 760 } 761 762 /* If data is correct, check ECC bits for errors... */ 763 for (i = 0; i < 8; i++) { 764 if ((syndrome >> i) & 0x1) { 765 *bad_ecc_bit = i; 766 return; 767 } 768 } 769 } 770 771 static void mpc85xx_mc_check(struct mem_ctl_info *mci) 772 { 773 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 774 struct csrow_info *csrow; 775 u32 bus_width; 776 u32 err_detect; 777 u32 syndrome; 778 u32 err_addr; 779 u32 pfn; 780 int row_index; 781 u32 cap_high; 782 u32 cap_low; 783 int bad_data_bit; 784 int bad_ecc_bit; 785 786 err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT); 787 if (!err_detect) 788 return; 789 790 mpc85xx_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n", 791 err_detect); 792 793 /* no more processing if not ECC bit errors */ 794 if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) { 795 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect); 796 return; 797 } 798 799 syndrome = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ECC); 800 801 /* Mask off appropriate bits of syndrome based on bus width */ 802 bus_width = (in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG) & 803 DSC_DBW_MASK) ? 32 : 64; 804 if (bus_width == 64) 805 syndrome &= 0xff; 806 else 807 syndrome &= 0xffff; 808 809 err_addr = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ADDRESS); 810 pfn = err_addr >> PAGE_SHIFT; 811 812 for (row_index = 0; row_index < mci->nr_csrows; row_index++) { 813 csrow = &mci->csrows[row_index]; 814 if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page)) 815 break; 816 } 817 818 cap_high = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_HI); 819 cap_low = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_LO); 820 821 /* 822 * Analyze single-bit errors on 64-bit wide buses 823 * TODO: Add support for 32-bit wide buses 824 */ 825 if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) { 826 sbe_ecc_decode(cap_high, cap_low, syndrome, 827 &bad_data_bit, &bad_ecc_bit); 828 829 if (bad_data_bit != -1) 830 mpc85xx_mc_printk(mci, KERN_ERR, 831 "Faulty Data bit: %d\n", bad_data_bit); 832 if (bad_ecc_bit != -1) 833 mpc85xx_mc_printk(mci, KERN_ERR, 834 "Faulty ECC bit: %d\n", bad_ecc_bit); 835 836 mpc85xx_mc_printk(mci, KERN_ERR, 837 "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n", 838 cap_high ^ (1 << (bad_data_bit - 32)), 839 cap_low ^ (1 << bad_data_bit), 840 syndrome ^ (1 << bad_ecc_bit)); 841 } 842 843 mpc85xx_mc_printk(mci, KERN_ERR, 844 "Captured Data / ECC:\t%#8.8x_%08x / %#2.2x\n", 845 cap_high, cap_low, syndrome); 846 mpc85xx_mc_printk(mci, KERN_ERR, "Err addr: %#8.8x\n", err_addr); 847 mpc85xx_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn); 848 849 /* we are out of range */ 850 if (row_index == mci->nr_csrows) 851 mpc85xx_mc_printk(mci, KERN_ERR, "PFN out of range!\n"); 852 853 if (err_detect & DDR_EDE_SBE) 854 edac_mc_handle_ce(mci, pfn, err_addr & PAGE_MASK, 855 syndrome, row_index, 0, mci->ctl_name); 856 857 if (err_detect & DDR_EDE_MBE) 858 edac_mc_handle_ue(mci, pfn, err_addr & PAGE_MASK, 859 row_index, mci->ctl_name); 860 861 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect); 862 } 863 864 static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id) 865 { 866 struct mem_ctl_info *mci = dev_id; 867 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 868 u32 err_detect; 869 870 err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT); 871 if (!err_detect) 872 return IRQ_NONE; 873 874 mpc85xx_mc_check(mci); 875 876 return IRQ_HANDLED; 877 } 878 879 static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci) 880 { 881 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 882 struct csrow_info *csrow; 883 u32 sdram_ctl; 884 u32 sdtype; 885 enum mem_type mtype; 886 u32 cs_bnds; 887 int index; 888 889 sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG); 890 891 sdtype = sdram_ctl & DSC_SDTYPE_MASK; 892 if (sdram_ctl & DSC_RD_EN) { 893 switch (sdtype) { 894 case DSC_SDTYPE_DDR: 895 mtype = MEM_RDDR; 896 break; 897 case DSC_SDTYPE_DDR2: 898 mtype = MEM_RDDR2; 899 break; 900 case DSC_SDTYPE_DDR3: 901 mtype = MEM_RDDR3; 902 break; 903 default: 904 mtype = MEM_UNKNOWN; 905 break; 906 } 907 } else { 908 switch (sdtype) { 909 case DSC_SDTYPE_DDR: 910 mtype = MEM_DDR; 911 break; 912 case DSC_SDTYPE_DDR2: 913 mtype = MEM_DDR2; 914 break; 915 case DSC_SDTYPE_DDR3: 916 mtype = MEM_DDR3; 917 break; 918 default: 919 mtype = MEM_UNKNOWN; 920 break; 921 } 922 } 923 924 for (index = 0; index < mci->nr_csrows; index++) { 925 u32 start; 926 u32 end; 927 928 csrow = &mci->csrows[index]; 929 cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 + 930 (index * MPC85XX_MC_CS_BNDS_OFS)); 931 932 start = (cs_bnds & 0xffff0000) >> 16; 933 end = (cs_bnds & 0x0000ffff); 934 935 if (start == end) 936 continue; /* not populated */ 937 938 start <<= (24 - PAGE_SHIFT); 939 end <<= (24 - PAGE_SHIFT); 940 end |= (1 << (24 - PAGE_SHIFT)) - 1; 941 942 csrow->first_page = start; 943 csrow->last_page = end; 944 csrow->nr_pages = end + 1 - start; 945 csrow->grain = 8; 946 csrow->mtype = mtype; 947 csrow->dtype = DEV_UNKNOWN; 948 if (sdram_ctl & DSC_X32_EN) 949 csrow->dtype = DEV_X32; 950 csrow->edac_mode = EDAC_SECDED; 951 } 952 } 953 954 static int __devinit mpc85xx_mc_err_probe(struct of_device *op, 955 const struct of_device_id *match) 956 { 957 struct mem_ctl_info *mci; 958 struct mpc85xx_mc_pdata *pdata; 959 struct resource r; 960 u32 sdram_ctl; 961 int res; 962 963 if (!devres_open_group(&op->dev, mpc85xx_mc_err_probe, GFP_KERNEL)) 964 return -ENOMEM; 965 966 mci = edac_mc_alloc(sizeof(*pdata), 4, 1, edac_mc_idx); 967 if (!mci) { 968 devres_release_group(&op->dev, mpc85xx_mc_err_probe); 969 return -ENOMEM; 970 } 971 972 pdata = mci->pvt_info; 973 pdata->name = "mpc85xx_mc_err"; 974 pdata->irq = NO_IRQ; 975 mci->dev = &op->dev; 976 pdata->edac_idx = edac_mc_idx++; 977 dev_set_drvdata(mci->dev, mci); 978 mci->ctl_name = pdata->name; 979 mci->dev_name = pdata->name; 980 981 res = of_address_to_resource(op->dev.of_node, 0, &r); 982 if (res) { 983 printk(KERN_ERR "%s: Unable to get resource for MC err regs\n", 984 __func__); 985 goto err; 986 } 987 988 if (!devm_request_mem_region(&op->dev, r.start, 989 r.end - r.start + 1, pdata->name)) { 990 printk(KERN_ERR "%s: Error while requesting mem region\n", 991 __func__); 992 res = -EBUSY; 993 goto err; 994 } 995 996 pdata->mc_vbase = devm_ioremap(&op->dev, r.start, r.end - r.start + 1); 997 if (!pdata->mc_vbase) { 998 printk(KERN_ERR "%s: Unable to setup MC err regs\n", __func__); 999 res = -ENOMEM; 1000 goto err; 1001 } 1002 1003 sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG); 1004 if (!(sdram_ctl & DSC_ECC_EN)) { 1005 /* no ECC */ 1006 printk(KERN_WARNING "%s: No ECC DIMMs discovered\n", __func__); 1007 res = -ENODEV; 1008 goto err; 1009 } 1010 1011 debugf3("%s(): init mci\n", __func__); 1012 mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 | 1013 MEM_FLAG_DDR | MEM_FLAG_DDR2; 1014 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; 1015 mci->edac_cap = EDAC_FLAG_SECDED; 1016 mci->mod_name = EDAC_MOD_STR; 1017 mci->mod_ver = MPC85XX_REVISION; 1018 1019 if (edac_op_state == EDAC_OPSTATE_POLL) 1020 mci->edac_check = mpc85xx_mc_check; 1021 1022 mci->ctl_page_to_phys = NULL; 1023 1024 mci->scrub_mode = SCRUB_SW_SRC; 1025 1026 mpc85xx_set_mc_sysfs_attributes(mci); 1027 1028 mpc85xx_init_csrows(mci); 1029 1030 /* store the original error disable bits */ 1031 orig_ddr_err_disable = 1032 in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE); 1033 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 0); 1034 1035 /* clear all error bits */ 1036 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0); 1037 1038 if (edac_mc_add_mc(mci)) { 1039 debugf3("%s(): failed edac_mc_add_mc()\n", __func__); 1040 goto err; 1041 } 1042 1043 if (edac_op_state == EDAC_OPSTATE_INT) { 1044 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 1045 DDR_EIE_MBEE | DDR_EIE_SBEE); 1046 1047 /* store the original error management threshold */ 1048 orig_ddr_err_sbe = in_be32(pdata->mc_vbase + 1049 MPC85XX_MC_ERR_SBE) & 0xff0000; 1050 1051 /* set threshold to 1 error per interrupt */ 1052 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, 0x10000); 1053 1054 /* register interrupts */ 1055 pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0); 1056 res = devm_request_irq(&op->dev, pdata->irq, 1057 mpc85xx_mc_isr, 1058 IRQF_DISABLED | IRQF_SHARED, 1059 "[EDAC] MC err", mci); 1060 if (res < 0) { 1061 printk(KERN_ERR "%s: Unable to request irq %d for " 1062 "MPC85xx DRAM ERR\n", __func__, pdata->irq); 1063 irq_dispose_mapping(pdata->irq); 1064 res = -ENODEV; 1065 goto err2; 1066 } 1067 1068 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for MC\n", 1069 pdata->irq); 1070 } 1071 1072 devres_remove_group(&op->dev, mpc85xx_mc_err_probe); 1073 debugf3("%s(): success\n", __func__); 1074 printk(KERN_INFO EDAC_MOD_STR " MC err registered\n"); 1075 1076 return 0; 1077 1078 err2: 1079 edac_mc_del_mc(&op->dev); 1080 err: 1081 devres_release_group(&op->dev, mpc85xx_mc_err_probe); 1082 edac_mc_free(mci); 1083 return res; 1084 } 1085 1086 static int mpc85xx_mc_err_remove(struct of_device *op) 1087 { 1088 struct mem_ctl_info *mci = dev_get_drvdata(&op->dev); 1089 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 1090 1091 debugf0("%s()\n", __func__); 1092 1093 if (edac_op_state == EDAC_OPSTATE_INT) { 1094 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0); 1095 irq_dispose_mapping(pdata->irq); 1096 } 1097 1098 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 1099 orig_ddr_err_disable); 1100 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, orig_ddr_err_sbe); 1101 1102 edac_mc_del_mc(&op->dev); 1103 edac_mc_free(mci); 1104 return 0; 1105 } 1106 1107 static struct of_device_id mpc85xx_mc_err_of_match[] = { 1108 /* deprecate the fsl,85.. forms in the future, 2.6.30? */ 1109 { .compatible = "fsl,8540-memory-controller", }, 1110 { .compatible = "fsl,8541-memory-controller", }, 1111 { .compatible = "fsl,8544-memory-controller", }, 1112 { .compatible = "fsl,8548-memory-controller", }, 1113 { .compatible = "fsl,8555-memory-controller", }, 1114 { .compatible = "fsl,8568-memory-controller", }, 1115 { .compatible = "fsl,mpc8536-memory-controller", }, 1116 { .compatible = "fsl,mpc8540-memory-controller", }, 1117 { .compatible = "fsl,mpc8541-memory-controller", }, 1118 { .compatible = "fsl,mpc8544-memory-controller", }, 1119 { .compatible = "fsl,mpc8548-memory-controller", }, 1120 { .compatible = "fsl,mpc8555-memory-controller", }, 1121 { .compatible = "fsl,mpc8560-memory-controller", }, 1122 { .compatible = "fsl,mpc8568-memory-controller", }, 1123 { .compatible = "fsl,mpc8572-memory-controller", }, 1124 { .compatible = "fsl,mpc8349-memory-controller", }, 1125 { .compatible = "fsl,p2020-memory-controller", }, 1126 {}, 1127 }; 1128 1129 static struct of_platform_driver mpc85xx_mc_err_driver = { 1130 .probe = mpc85xx_mc_err_probe, 1131 .remove = mpc85xx_mc_err_remove, 1132 .driver = { 1133 .name = "mpc85xx_mc_err", 1134 .owner = THIS_MODULE, 1135 .of_match_table = mpc85xx_mc_err_of_match, 1136 }, 1137 }; 1138 1139 #ifdef CONFIG_MPC85xx 1140 static void __init mpc85xx_mc_clear_rfxe(void *data) 1141 { 1142 orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1); 1143 mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~0x20000)); 1144 } 1145 #endif 1146 1147 static int __init mpc85xx_mc_init(void) 1148 { 1149 int res = 0; 1150 1151 printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, " 1152 "(C) 2006 Montavista Software\n"); 1153 1154 /* make sure error reporting method is sane */ 1155 switch (edac_op_state) { 1156 case EDAC_OPSTATE_POLL: 1157 case EDAC_OPSTATE_INT: 1158 break; 1159 default: 1160 edac_op_state = EDAC_OPSTATE_INT; 1161 break; 1162 } 1163 1164 res = of_register_platform_driver(&mpc85xx_mc_err_driver); 1165 if (res) 1166 printk(KERN_WARNING EDAC_MOD_STR "MC fails to register\n"); 1167 1168 res = of_register_platform_driver(&mpc85xx_l2_err_driver); 1169 if (res) 1170 printk(KERN_WARNING EDAC_MOD_STR "L2 fails to register\n"); 1171 1172 #ifdef CONFIG_PCI 1173 res = of_register_platform_driver(&mpc85xx_pci_err_driver); 1174 if (res) 1175 printk(KERN_WARNING EDAC_MOD_STR "PCI fails to register\n"); 1176 #endif 1177 1178 #ifdef CONFIG_MPC85xx 1179 /* 1180 * need to clear HID1[RFXE] to disable machine check int 1181 * so we can catch it 1182 */ 1183 if (edac_op_state == EDAC_OPSTATE_INT) 1184 on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0); 1185 #endif 1186 1187 return 0; 1188 } 1189 1190 module_init(mpc85xx_mc_init); 1191 1192 #ifdef CONFIG_MPC85xx 1193 static void __exit mpc85xx_mc_restore_hid1(void *data) 1194 { 1195 mtspr(SPRN_HID1, orig_hid1[smp_processor_id()]); 1196 } 1197 #endif 1198 1199 static void __exit mpc85xx_mc_exit(void) 1200 { 1201 #ifdef CONFIG_MPC85xx 1202 on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0); 1203 #endif 1204 #ifdef CONFIG_PCI 1205 of_unregister_platform_driver(&mpc85xx_pci_err_driver); 1206 #endif 1207 of_unregister_platform_driver(&mpc85xx_l2_err_driver); 1208 of_unregister_platform_driver(&mpc85xx_mc_err_driver); 1209 } 1210 1211 module_exit(mpc85xx_mc_exit); 1212 1213 MODULE_LICENSE("GPL"); 1214 MODULE_AUTHOR("Montavista Software, Inc."); 1215 module_param(edac_op_state, int, 0444); 1216 MODULE_PARM_DESC(edac_op_state, 1217 "EDAC Error Reporting state: 0=Poll, 2=Interrupt"); 1218