1 /*
2 * Freescale MPC85xx Memory Controller kernel module
3 *
4 * Parts Copyrighted (c) 2013 by Freescale Semiconductor, Inc.
5 *
6 * Author: Dave Jiang <djiang@mvista.com>
7 *
8 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 *
13 */
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/ctype.h>
18 #include <linux/io.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/edac.h>
21 #include <linux/smp.h>
22 #include <linux/gfp.h>
23 #include <linux/fsl/edac.h>
24
25 #include <linux/of.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include "edac_module.h"
29 #include "mpc85xx_edac.h"
30 #include "fsl_ddr_edac.h"
31
32 static int edac_dev_idx;
33 #ifdef CONFIG_PCI
34 static int edac_pci_idx;
35 #endif
36
37 /*
38 * PCI Err defines
39 */
40 #ifdef CONFIG_PCI
41 static u32 orig_pci_err_cap_dr;
42 static u32 orig_pci_err_en;
43 #endif
44
45 static u32 orig_l2_err_disable;
46
47 /**************************** PCI Err device ***************************/
48 #ifdef CONFIG_PCI
49
mpc85xx_pci_check(struct edac_pci_ctl_info * pci)50 static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci)
51 {
52 struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
53 u32 err_detect;
54
55 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
56
57 /* master aborts can happen during PCI config cycles */
58 if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) {
59 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
60 return;
61 }
62
63 pr_err("PCI error(s) detected\n");
64 pr_err("PCI/X ERR_DR register: %#08x\n", err_detect);
65
66 pr_err("PCI/X ERR_ATTRIB register: %#08x\n",
67 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB));
68 pr_err("PCI/X ERR_ADDR register: %#08x\n",
69 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR));
70 pr_err("PCI/X ERR_EXT_ADDR register: %#08x\n",
71 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR));
72 pr_err("PCI/X ERR_DL register: %#08x\n",
73 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL));
74 pr_err("PCI/X ERR_DH register: %#08x\n",
75 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH));
76
77 /* clear error bits */
78 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
79
80 if (err_detect & PCI_EDE_PERR_MASK)
81 edac_pci_handle_pe(pci, pci->ctl_name);
82
83 if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK)
84 edac_pci_handle_npe(pci, pci->ctl_name);
85 }
86
mpc85xx_pcie_check(struct edac_pci_ctl_info * pci)87 static void mpc85xx_pcie_check(struct edac_pci_ctl_info *pci)
88 {
89 struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
90 u32 err_detect, err_cap_stat;
91
92 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
93 err_cap_stat = in_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR);
94
95 pr_err("PCIe error(s) detected\n");
96 pr_err("PCIe ERR_DR register: 0x%08x\n", err_detect);
97 pr_err("PCIe ERR_CAP_STAT register: 0x%08x\n", err_cap_stat);
98 pr_err("PCIe ERR_CAP_R0 register: 0x%08x\n",
99 in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R0));
100 pr_err("PCIe ERR_CAP_R1 register: 0x%08x\n",
101 in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R1));
102 pr_err("PCIe ERR_CAP_R2 register: 0x%08x\n",
103 in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R2));
104 pr_err("PCIe ERR_CAP_R3 register: 0x%08x\n",
105 in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R3));
106
107 /* clear error bits */
108 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
109
110 /* reset error capture */
111 out_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR, err_cap_stat | 0x1);
112 }
113
mpc85xx_pcie_find_capability(struct device_node * np)114 static int mpc85xx_pcie_find_capability(struct device_node *np)
115 {
116 struct pci_controller *hose;
117
118 if (!np)
119 return -EINVAL;
120
121 hose = pci_find_hose_for_OF_device(np);
122
123 return early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
124 }
125
mpc85xx_pci_isr(int irq,void * dev_id)126 static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id)
127 {
128 struct edac_pci_ctl_info *pci = dev_id;
129 struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
130 u32 err_detect;
131
132 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
133
134 if (!err_detect)
135 return IRQ_NONE;
136
137 if (pdata->is_pcie)
138 mpc85xx_pcie_check(pci);
139 else
140 mpc85xx_pci_check(pci);
141
142 return IRQ_HANDLED;
143 }
144
mpc85xx_pci_err_probe(struct platform_device * op)145 static int mpc85xx_pci_err_probe(struct platform_device *op)
146 {
147 struct edac_pci_ctl_info *pci;
148 struct mpc85xx_pci_pdata *pdata;
149 struct mpc85xx_edac_pci_plat_data *plat_data;
150 struct device_node *of_node;
151 struct resource r;
152 int res = 0;
153
154 if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL))
155 return -ENOMEM;
156
157 pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err");
158 if (!pci)
159 return -ENOMEM;
160
161 /* make sure error reporting method is sane */
162 switch (edac_op_state) {
163 case EDAC_OPSTATE_POLL:
164 case EDAC_OPSTATE_INT:
165 break;
166 default:
167 edac_op_state = EDAC_OPSTATE_INT;
168 break;
169 }
170
171 pdata = pci->pvt_info;
172 pdata->name = "mpc85xx_pci_err";
173
174 plat_data = op->dev.platform_data;
175 if (!plat_data) {
176 dev_err(&op->dev, "no platform data");
177 res = -ENXIO;
178 goto err;
179 }
180 of_node = plat_data->of_node;
181
182 if (mpc85xx_pcie_find_capability(of_node) > 0)
183 pdata->is_pcie = true;
184
185 dev_set_drvdata(&op->dev, pci);
186 pci->dev = &op->dev;
187 pci->mod_name = EDAC_MOD_STR;
188 pci->ctl_name = pdata->name;
189 pci->dev_name = dev_name(&op->dev);
190
191 if (edac_op_state == EDAC_OPSTATE_POLL) {
192 if (pdata->is_pcie)
193 pci->edac_check = mpc85xx_pcie_check;
194 else
195 pci->edac_check = mpc85xx_pci_check;
196 }
197
198 pdata->edac_idx = edac_pci_idx++;
199
200 res = of_address_to_resource(of_node, 0, &r);
201 if (res) {
202 pr_err("%s: Unable to get resource for PCI err regs\n", __func__);
203 goto err;
204 }
205
206 /* we only need the error registers */
207 r.start += 0xe00;
208
209 if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
210 pdata->name)) {
211 pr_err("%s: Error while requesting mem region\n", __func__);
212 res = -EBUSY;
213 goto err;
214 }
215
216 pdata->pci_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
217 if (!pdata->pci_vbase) {
218 pr_err("%s: Unable to setup PCI err regs\n", __func__);
219 res = -ENOMEM;
220 goto err;
221 }
222
223 if (pdata->is_pcie) {
224 orig_pci_err_cap_dr =
225 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR);
226 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, ~0);
227 orig_pci_err_en =
228 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
229 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, 0);
230 } else {
231 orig_pci_err_cap_dr =
232 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR);
233
234 /* PCI master abort is expected during config cycles */
235 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40);
236
237 orig_pci_err_en =
238 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
239
240 /* disable master abort reporting */
241 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40);
242 }
243
244 /* clear error bits */
245 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0);
246
247 /* reset error capture */
248 out_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR, 0x1);
249
250 if (edac_pci_add_device(pci, pdata->edac_idx) > 0) {
251 edac_dbg(3, "failed edac_pci_add_device()\n");
252 goto err;
253 }
254
255 if (edac_op_state == EDAC_OPSTATE_INT) {
256 pdata->irq = irq_of_parse_and_map(of_node, 0);
257 res = devm_request_irq(&op->dev, pdata->irq,
258 mpc85xx_pci_isr,
259 IRQF_SHARED,
260 "[EDAC] PCI err", pci);
261 if (res < 0) {
262 pr_err("%s: Unable to request irq %d for MPC85xx PCI err\n",
263 __func__, pdata->irq);
264 irq_dispose_mapping(pdata->irq);
265 res = -ENODEV;
266 goto err2;
267 }
268
269 pr_info(EDAC_MOD_STR " acquired irq %d for PCI Err\n",
270 pdata->irq);
271 }
272
273 if (pdata->is_pcie) {
274 /*
275 * Enable all PCIe error interrupt & error detect except invalid
276 * PEX_CONFIG_ADDR/PEX_CONFIG_DATA access interrupt generation
277 * enable bit and invalid PEX_CONFIG_ADDR/PEX_CONFIG_DATA access
278 * detection enable bit. Because PCIe bus code to initialize and
279 * configure these PCIe devices on booting will use some invalid
280 * PEX_CONFIG_ADDR/PEX_CONFIG_DATA, edac driver prints the much
281 * notice information. So disable this detect to fix ugly print.
282 */
283 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0
284 & ~PEX_ERR_ICCAIE_EN_BIT);
285 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, 0
286 | PEX_ERR_ICCAD_DISR_BIT);
287 }
288
289 devres_remove_group(&op->dev, mpc85xx_pci_err_probe);
290 edac_dbg(3, "success\n");
291 pr_info(EDAC_MOD_STR " PCI err registered\n");
292
293 return 0;
294
295 err2:
296 edac_pci_del_device(&op->dev);
297 err:
298 edac_pci_free_ctl_info(pci);
299 devres_release_group(&op->dev, mpc85xx_pci_err_probe);
300 return res;
301 }
302
mpc85xx_pci_err_remove(struct platform_device * op)303 static int mpc85xx_pci_err_remove(struct platform_device *op)
304 {
305 struct edac_pci_ctl_info *pci = dev_get_drvdata(&op->dev);
306 struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
307
308 edac_dbg(0, "\n");
309
310 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, orig_pci_err_cap_dr);
311 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, orig_pci_err_en);
312
313 edac_pci_del_device(&op->dev);
314 edac_pci_free_ctl_info(pci);
315
316 return 0;
317 }
318
319 static const struct platform_device_id mpc85xx_pci_err_match[] = {
320 {
321 .name = "mpc85xx-pci-edac"
322 },
323 {}
324 };
325
326 static struct platform_driver mpc85xx_pci_err_driver = {
327 .probe = mpc85xx_pci_err_probe,
328 .remove = mpc85xx_pci_err_remove,
329 .id_table = mpc85xx_pci_err_match,
330 .driver = {
331 .name = "mpc85xx_pci_err",
332 .suppress_bind_attrs = true,
333 },
334 };
335 #endif /* CONFIG_PCI */
336
337 /**************************** L2 Err device ***************************/
338
339 /************************ L2 SYSFS parts ***********************************/
340
mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info * edac_dev,char * data)341 static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info
342 *edac_dev, char *data)
343 {
344 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
345 return sprintf(data, "0x%08x",
346 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI));
347 }
348
mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info * edac_dev,char * data)349 static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info
350 *edac_dev, char *data)
351 {
352 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
353 return sprintf(data, "0x%08x",
354 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO));
355 }
356
mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info * edac_dev,char * data)357 static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info
358 *edac_dev, char *data)
359 {
360 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
361 return sprintf(data, "0x%08x",
362 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL));
363 }
364
mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info * edac_dev,const char * data,size_t count)365 static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info
366 *edac_dev, const char *data,
367 size_t count)
368 {
369 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
370 if (isdigit(*data)) {
371 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI,
372 simple_strtoul(data, NULL, 0));
373 return count;
374 }
375 return 0;
376 }
377
mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info * edac_dev,const char * data,size_t count)378 static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info
379 *edac_dev, const char *data,
380 size_t count)
381 {
382 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
383 if (isdigit(*data)) {
384 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO,
385 simple_strtoul(data, NULL, 0));
386 return count;
387 }
388 return 0;
389 }
390
mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info * edac_dev,const char * data,size_t count)391 static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info
392 *edac_dev, const char *data,
393 size_t count)
394 {
395 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
396 if (isdigit(*data)) {
397 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL,
398 simple_strtoul(data, NULL, 0));
399 return count;
400 }
401 return 0;
402 }
403
404 static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = {
405 {
406 .attr = {
407 .name = "inject_data_hi",
408 .mode = (S_IRUGO | S_IWUSR)
409 },
410 .show = mpc85xx_l2_inject_data_hi_show,
411 .store = mpc85xx_l2_inject_data_hi_store},
412 {
413 .attr = {
414 .name = "inject_data_lo",
415 .mode = (S_IRUGO | S_IWUSR)
416 },
417 .show = mpc85xx_l2_inject_data_lo_show,
418 .store = mpc85xx_l2_inject_data_lo_store},
419 {
420 .attr = {
421 .name = "inject_ctrl",
422 .mode = (S_IRUGO | S_IWUSR)
423 },
424 .show = mpc85xx_l2_inject_ctrl_show,
425 .store = mpc85xx_l2_inject_ctrl_store},
426
427 /* End of list */
428 {
429 .attr = {.name = NULL}
430 }
431 };
432
mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info * edac_dev)433 static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info
434 *edac_dev)
435 {
436 edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes;
437 }
438
439 /***************************** L2 ops ***********************************/
440
mpc85xx_l2_check(struct edac_device_ctl_info * edac_dev)441 static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev)
442 {
443 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
444 u32 err_detect;
445
446 err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
447
448 if (!(err_detect & L2_EDE_MASK))
449 return;
450
451 pr_err("ECC Error in CPU L2 cache\n");
452 pr_err("L2 Error Detect Register: 0x%08x\n", err_detect);
453 pr_err("L2 Error Capture Data High Register: 0x%08x\n",
454 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI));
455 pr_err("L2 Error Capture Data Lo Register: 0x%08x\n",
456 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO));
457 pr_err("L2 Error Syndrome Register: 0x%08x\n",
458 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC));
459 pr_err("L2 Error Attributes Capture Register: 0x%08x\n",
460 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR));
461 pr_err("L2 Error Address Capture Register: 0x%08x\n",
462 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR));
463
464 /* clear error detect register */
465 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect);
466
467 if (err_detect & L2_EDE_CE_MASK)
468 edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name);
469
470 if (err_detect & L2_EDE_UE_MASK)
471 edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
472 }
473
mpc85xx_l2_isr(int irq,void * dev_id)474 static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id)
475 {
476 struct edac_device_ctl_info *edac_dev = dev_id;
477 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
478 u32 err_detect;
479
480 err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
481
482 if (!(err_detect & L2_EDE_MASK))
483 return IRQ_NONE;
484
485 mpc85xx_l2_check(edac_dev);
486
487 return IRQ_HANDLED;
488 }
489
mpc85xx_l2_err_probe(struct platform_device * op)490 static int mpc85xx_l2_err_probe(struct platform_device *op)
491 {
492 struct edac_device_ctl_info *edac_dev;
493 struct mpc85xx_l2_pdata *pdata;
494 struct resource r;
495 int res;
496
497 if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL))
498 return -ENOMEM;
499
500 edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata),
501 "cpu", 1, "L", 1, 2, NULL, 0,
502 edac_dev_idx);
503 if (!edac_dev) {
504 devres_release_group(&op->dev, mpc85xx_l2_err_probe);
505 return -ENOMEM;
506 }
507
508 pdata = edac_dev->pvt_info;
509 pdata->name = "mpc85xx_l2_err";
510 edac_dev->dev = &op->dev;
511 dev_set_drvdata(edac_dev->dev, edac_dev);
512 edac_dev->ctl_name = pdata->name;
513 edac_dev->dev_name = pdata->name;
514
515 res = of_address_to_resource(op->dev.of_node, 0, &r);
516 if (res) {
517 pr_err("%s: Unable to get resource for L2 err regs\n", __func__);
518 goto err;
519 }
520
521 /* we only need the error registers */
522 r.start += 0xe00;
523
524 if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
525 pdata->name)) {
526 pr_err("%s: Error while requesting mem region\n", __func__);
527 res = -EBUSY;
528 goto err;
529 }
530
531 pdata->l2_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
532 if (!pdata->l2_vbase) {
533 pr_err("%s: Unable to setup L2 err regs\n", __func__);
534 res = -ENOMEM;
535 goto err;
536 }
537
538 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0);
539
540 orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS);
541
542 /* clear the err_dis */
543 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0);
544
545 edac_dev->mod_name = EDAC_MOD_STR;
546
547 if (edac_op_state == EDAC_OPSTATE_POLL)
548 edac_dev->edac_check = mpc85xx_l2_check;
549
550 mpc85xx_set_l2_sysfs_attributes(edac_dev);
551
552 pdata->edac_idx = edac_dev_idx++;
553
554 if (edac_device_add_device(edac_dev) > 0) {
555 edac_dbg(3, "failed edac_device_add_device()\n");
556 goto err;
557 }
558
559 if (edac_op_state == EDAC_OPSTATE_INT) {
560 pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
561 res = devm_request_irq(&op->dev, pdata->irq,
562 mpc85xx_l2_isr, IRQF_SHARED,
563 "[EDAC] L2 err", edac_dev);
564 if (res < 0) {
565 pr_err("%s: Unable to request irq %d for MPC85xx L2 err\n",
566 __func__, pdata->irq);
567 irq_dispose_mapping(pdata->irq);
568 res = -ENODEV;
569 goto err2;
570 }
571
572 pr_info(EDAC_MOD_STR " acquired irq %d for L2 Err\n", pdata->irq);
573
574 edac_dev->op_state = OP_RUNNING_INTERRUPT;
575
576 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK);
577 }
578
579 devres_remove_group(&op->dev, mpc85xx_l2_err_probe);
580
581 edac_dbg(3, "success\n");
582 pr_info(EDAC_MOD_STR " L2 err registered\n");
583
584 return 0;
585
586 err2:
587 edac_device_del_device(&op->dev);
588 err:
589 devres_release_group(&op->dev, mpc85xx_l2_err_probe);
590 edac_device_free_ctl_info(edac_dev);
591 return res;
592 }
593
mpc85xx_l2_err_remove(struct platform_device * op)594 static int mpc85xx_l2_err_remove(struct platform_device *op)
595 {
596 struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev);
597 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
598
599 edac_dbg(0, "\n");
600
601 if (edac_op_state == EDAC_OPSTATE_INT) {
602 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0);
603 irq_dispose_mapping(pdata->irq);
604 }
605
606 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable);
607 edac_device_del_device(&op->dev);
608 edac_device_free_ctl_info(edac_dev);
609 return 0;
610 }
611
612 static const struct of_device_id mpc85xx_l2_err_of_match[] = {
613 { .compatible = "fsl,mpc8536-l2-cache-controller", },
614 { .compatible = "fsl,mpc8540-l2-cache-controller", },
615 { .compatible = "fsl,mpc8541-l2-cache-controller", },
616 { .compatible = "fsl,mpc8544-l2-cache-controller", },
617 { .compatible = "fsl,mpc8548-l2-cache-controller", },
618 { .compatible = "fsl,mpc8555-l2-cache-controller", },
619 { .compatible = "fsl,mpc8560-l2-cache-controller", },
620 { .compatible = "fsl,mpc8568-l2-cache-controller", },
621 { .compatible = "fsl,mpc8569-l2-cache-controller", },
622 { .compatible = "fsl,mpc8572-l2-cache-controller", },
623 { .compatible = "fsl,p1020-l2-cache-controller", },
624 { .compatible = "fsl,p1021-l2-cache-controller", },
625 { .compatible = "fsl,p2020-l2-cache-controller", },
626 { .compatible = "fsl,t2080-l2-cache-controller", },
627 {},
628 };
629 MODULE_DEVICE_TABLE(of, mpc85xx_l2_err_of_match);
630
631 static struct platform_driver mpc85xx_l2_err_driver = {
632 .probe = mpc85xx_l2_err_probe,
633 .remove = mpc85xx_l2_err_remove,
634 .driver = {
635 .name = "mpc85xx_l2_err",
636 .of_match_table = mpc85xx_l2_err_of_match,
637 },
638 };
639
640 static const struct of_device_id mpc85xx_mc_err_of_match[] = {
641 { .compatible = "fsl,mpc8536-memory-controller", },
642 { .compatible = "fsl,mpc8540-memory-controller", },
643 { .compatible = "fsl,mpc8541-memory-controller", },
644 { .compatible = "fsl,mpc8544-memory-controller", },
645 { .compatible = "fsl,mpc8548-memory-controller", },
646 { .compatible = "fsl,mpc8555-memory-controller", },
647 { .compatible = "fsl,mpc8560-memory-controller", },
648 { .compatible = "fsl,mpc8568-memory-controller", },
649 { .compatible = "fsl,mpc8569-memory-controller", },
650 { .compatible = "fsl,mpc8572-memory-controller", },
651 { .compatible = "fsl,mpc8349-memory-controller", },
652 { .compatible = "fsl,p1020-memory-controller", },
653 { .compatible = "fsl,p1021-memory-controller", },
654 { .compatible = "fsl,p2020-memory-controller", },
655 { .compatible = "fsl,qoriq-memory-controller", },
656 {},
657 };
658 MODULE_DEVICE_TABLE(of, mpc85xx_mc_err_of_match);
659
660 static struct platform_driver mpc85xx_mc_err_driver = {
661 .probe = fsl_mc_err_probe,
662 .remove = fsl_mc_err_remove,
663 .driver = {
664 .name = "mpc85xx_mc_err",
665 .of_match_table = mpc85xx_mc_err_of_match,
666 },
667 };
668
669 static struct platform_driver * const drivers[] = {
670 &mpc85xx_mc_err_driver,
671 &mpc85xx_l2_err_driver,
672 #ifdef CONFIG_PCI
673 &mpc85xx_pci_err_driver,
674 #endif
675 };
676
mpc85xx_mc_init(void)677 static int __init mpc85xx_mc_init(void)
678 {
679 int res = 0;
680 u32 __maybe_unused pvr = 0;
681
682 pr_info("Freescale(R) MPC85xx EDAC driver, (C) 2006 Montavista Software\n");
683
684 /* make sure error reporting method is sane */
685 switch (edac_op_state) {
686 case EDAC_OPSTATE_POLL:
687 case EDAC_OPSTATE_INT:
688 break;
689 default:
690 edac_op_state = EDAC_OPSTATE_INT;
691 break;
692 }
693
694 res = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
695 if (res)
696 pr_warn(EDAC_MOD_STR "drivers fail to register\n");
697
698 return 0;
699 }
700
701 module_init(mpc85xx_mc_init);
702
mpc85xx_mc_exit(void)703 static void __exit mpc85xx_mc_exit(void)
704 {
705 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
706 }
707
708 module_exit(mpc85xx_mc_exit);
709
710 MODULE_LICENSE("GPL");
711 MODULE_AUTHOR("Montavista Software, Inc.");
712 module_param(edac_op_state, int, 0444);
713 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll, 2=Interrupt");
714