1 #ifndef _EDAC_MCE_AMD_H 2 #define _EDAC_MCE_AMD_H 3 4 #include <linux/notifier.h> 5 6 #include <asm/mce.h> 7 8 #define BIT_64(n) (U64_C(1) << (n)) 9 10 #define ERROR_CODE(x) ((x) & 0xffff) 11 #define EXT_ERROR_CODE(x) (((x) >> 16) & 0x1f) 12 13 #define LOW_SYNDROME(x) (((x) >> 15) & 0xff) 14 #define HIGH_SYNDROME(x) (((x) >> 24) & 0xff) 15 16 #define TLB_ERROR(x) (((x) & 0xFFF0) == 0x0010) 17 #define MEM_ERROR(x) (((x) & 0xFF00) == 0x0100) 18 #define BUS_ERROR(x) (((x) & 0xF800) == 0x0800) 19 20 #define TT(x) (((x) >> 2) & 0x3) 21 #define TT_MSG(x) tt_msgs[TT(x)] 22 #define II(x) (((x) >> 2) & 0x3) 23 #define II_MSG(x) ii_msgs[II(x)] 24 #define LL(x) (((x) >> 0) & 0x3) 25 #define LL_MSG(x) ll_msgs[LL(x)] 26 #define TO(x) (((x) >> 8) & 0x1) 27 #define TO_MSG(x) to_msgs[TO(x)] 28 #define PP(x) (((x) >> 9) & 0x3) 29 #define PP_MSG(x) pp_msgs[PP(x)] 30 31 #define RRRR(x) (((x) >> 4) & 0xf) 32 #define RRRR_MSG(x) ((RRRR(x) < 9) ? rrrr_msgs[RRRR(x)] : "Wrong R4!") 33 34 #define K8_NBSH 0x4C 35 36 #define K8_NBSH_VALID_BIT BIT(31) 37 #define K8_NBSH_OVERFLOW BIT(30) 38 #define K8_NBSH_UC_ERR BIT(29) 39 #define K8_NBSH_ERR_EN BIT(28) 40 #define K8_NBSH_MISCV BIT(27) 41 #define K8_NBSH_VALID_ERROR_ADDR BIT(26) 42 #define K8_NBSH_PCC BIT(25) 43 #define K8_NBSH_ERR_CPU_VAL BIT(24) 44 #define K8_NBSH_CECC BIT(14) 45 #define K8_NBSH_UECC BIT(13) 46 #define K8_NBSH_ERR_SCRUBER BIT(8) 47 48 enum tt_ids { 49 TT_INSTR = 0, 50 TT_DATA, 51 TT_GEN, 52 TT_RESV, 53 }; 54 55 enum ll_ids { 56 LL_RESV = 0, 57 LL_L1, 58 LL_L2, 59 LL_LG, 60 }; 61 62 enum ii_ids { 63 II_MEM = 0, 64 II_RESV, 65 II_IO, 66 II_GEN, 67 }; 68 69 enum rrrr_ids { 70 R4_GEN = 0, 71 R4_RD, 72 R4_WR, 73 R4_DRD, 74 R4_DWR, 75 R4_IRD, 76 R4_PREF, 77 R4_EVICT, 78 R4_SNOOP, 79 }; 80 81 extern const char *tt_msgs[]; 82 extern const char *ll_msgs[]; 83 extern const char *rrrr_msgs[]; 84 extern const char *pp_msgs[]; 85 extern const char *to_msgs[]; 86 extern const char *ii_msgs[]; 87 88 /* 89 * relevant NB regs 90 */ 91 struct err_regs { 92 u32 nbcfg; 93 u32 nbsh; 94 u32 nbsl; 95 u32 nbeah; 96 u32 nbeal; 97 }; 98 99 /* 100 * per-family decoder ops 101 */ 102 struct amd_decoder_ops { 103 bool (*dc_mce)(u16); 104 bool (*ic_mce)(u16); 105 bool (*nb_mce)(u16, u8); 106 }; 107 108 void amd_report_gart_errors(bool); 109 void amd_register_ecc_decoder(void (*f)(int, struct mce *, u32)); 110 void amd_unregister_ecc_decoder(void (*f)(int, struct mce *, u32)); 111 void amd_decode_nb_mce(int, struct mce *, u32); 112 int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data); 113 114 #endif /* _EDAC_MCE_AMD_H */ 115