1 #include <linux/module.h> 2 #include <linux/slab.h> 3 4 #include <asm/cpu.h> 5 6 #include "mce_amd.h" 7 8 static struct amd_decoder_ops *fam_ops; 9 10 static u8 xec_mask = 0xf; 11 12 static bool report_gart_errors; 13 static void (*decode_dram_ecc)(int node_id, struct mce *m); 14 15 void amd_report_gart_errors(bool v) 16 { 17 report_gart_errors = v; 18 } 19 EXPORT_SYMBOL_GPL(amd_report_gart_errors); 20 21 void amd_register_ecc_decoder(void (*f)(int, struct mce *)) 22 { 23 decode_dram_ecc = f; 24 } 25 EXPORT_SYMBOL_GPL(amd_register_ecc_decoder); 26 27 void amd_unregister_ecc_decoder(void (*f)(int, struct mce *)) 28 { 29 if (decode_dram_ecc) { 30 WARN_ON(decode_dram_ecc != f); 31 32 decode_dram_ecc = NULL; 33 } 34 } 35 EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder); 36 37 /* 38 * string representation for the different MCA reported error types, see F3x48 39 * or MSR0000_0411. 40 */ 41 42 /* transaction type */ 43 static const char * const tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" }; 44 45 /* cache level */ 46 static const char * const ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" }; 47 48 /* memory transaction type */ 49 static const char * const rrrr_msgs[] = { 50 "GEN", "RD", "WR", "DRD", "DWR", "IRD", "PRF", "EV", "SNP" 51 }; 52 53 /* participating processor */ 54 const char * const pp_msgs[] = { "SRC", "RES", "OBS", "GEN" }; 55 EXPORT_SYMBOL_GPL(pp_msgs); 56 57 /* request timeout */ 58 static const char * const to_msgs[] = { "no timeout", "timed out" }; 59 60 /* memory or i/o */ 61 static const char * const ii_msgs[] = { "MEM", "RESV", "IO", "GEN" }; 62 63 /* internal error type */ 64 static const char * const uu_msgs[] = { "RESV", "RESV", "HWA", "RESV" }; 65 66 static const char * const f15h_mc1_mce_desc[] = { 67 "UC during a demand linefill from L2", 68 "Parity error during data load from IC", 69 "Parity error for IC valid bit", 70 "Main tag parity error", 71 "Parity error in prediction queue", 72 "PFB data/address parity error", 73 "Parity error in the branch status reg", 74 "PFB promotion address error", 75 "Tag error during probe/victimization", 76 "Parity error for IC probe tag valid bit", 77 "PFB non-cacheable bit parity error", 78 "PFB valid bit parity error", /* xec = 0xd */ 79 "Microcode Patch Buffer", /* xec = 010 */ 80 "uop queue", 81 "insn buffer", 82 "predecode buffer", 83 "fetch address FIFO", 84 "dispatch uop queue" 85 }; 86 87 static const char * const f15h_mc2_mce_desc[] = { 88 "Fill ECC error on data fills", /* xec = 0x4 */ 89 "Fill parity error on insn fills", 90 "Prefetcher request FIFO parity error", 91 "PRQ address parity error", 92 "PRQ data parity error", 93 "WCC Tag ECC error", 94 "WCC Data ECC error", 95 "WCB Data parity error", 96 "VB Data ECC or parity error", 97 "L2 Tag ECC error", /* xec = 0x10 */ 98 "Hard L2 Tag ECC error", 99 "Multiple hits on L2 tag", 100 "XAB parity error", 101 "PRB address parity error" 102 }; 103 104 static const char * const mc4_mce_desc[] = { 105 "DRAM ECC error detected on the NB", 106 "CRC error detected on HT link", 107 "Link-defined sync error packets detected on HT link", 108 "HT Master abort", 109 "HT Target abort", 110 "Invalid GART PTE entry during GART table walk", 111 "Unsupported atomic RMW received from an IO link", 112 "Watchdog timeout due to lack of progress", 113 "DRAM ECC error detected on the NB", 114 "SVM DMA Exclusion Vector error", 115 "HT data error detected on link", 116 "Protocol error (link, L3, probe filter)", 117 "NB internal arrays parity error", 118 "DRAM addr/ctl signals parity error", 119 "IO link transmission error", 120 "L3 data cache ECC error", /* xec = 0x1c */ 121 "L3 cache tag error", 122 "L3 LRU parity bits error", 123 "ECC Error in the Probe Filter directory" 124 }; 125 126 static const char * const mc5_mce_desc[] = { 127 "CPU Watchdog timer expire", 128 "Wakeup array dest tag", 129 "AG payload array", 130 "EX payload array", 131 "IDRF array", 132 "Retire dispatch queue", 133 "Mapper checkpoint array", 134 "Physical register file EX0 port", 135 "Physical register file EX1 port", 136 "Physical register file AG0 port", 137 "Physical register file AG1 port", 138 "Flag register file", 139 "DE error occurred", 140 "Retire status queue" 141 }; 142 143 static const char * const mc6_mce_desc[] = { 144 "Hardware Assertion", 145 "Free List", 146 "Physical Register File", 147 "Retire Queue", 148 "Scheduler table", 149 "Status Register File", 150 }; 151 152 /* Scalable MCA error strings */ 153 static const char * const smca_ls_mce_desc[] = { 154 "Load queue parity error", 155 "Store queue parity error", 156 "Miss address buffer payload parity error", 157 "Level 1 TLB parity error", 158 "DC Tag error type 5", 159 "DC Tag error type 6", 160 "DC Tag error type 1", 161 "Internal error type 1", 162 "Internal error type 2", 163 "System Read Data Error Thread 0", 164 "System Read Data Error Thread 1", 165 "DC Tag error type 2", 166 "DC Data error type 1 and poison consumption", 167 "DC Data error type 2", 168 "DC Data error type 3", 169 "DC Tag error type 4", 170 "Level 2 TLB parity error", 171 "PDC parity error", 172 "DC Tag error type 3", 173 "DC Tag error type 5", 174 "L2 Fill Data error", 175 }; 176 177 static const char * const smca_if_mce_desc[] = { 178 "Op Cache Microtag Probe Port Parity Error", 179 "IC Microtag or Full Tag Multi-hit Error", 180 "IC Full Tag Parity Error", 181 "IC Data Array Parity Error", 182 "Decoupling Queue PhysAddr Parity Error", 183 "L0 ITLB Parity Error", 184 "L1 ITLB Parity Error", 185 "L2 ITLB Parity Error", 186 "BPQ Thread 0 Snoop Parity Error", 187 "BPQ Thread 1 Snoop Parity Error", 188 "L1 BTB Multi-Match Error", 189 "L2 BTB Multi-Match Error", 190 "L2 Cache Response Poison Error", 191 "System Read Data Error", 192 }; 193 194 static const char * const smca_l2_mce_desc[] = { 195 "L2M Tag Multiple-Way-Hit error", 196 "L2M Tag or State Array ECC Error", 197 "L2M Data Array ECC Error", 198 "Hardware Assert Error", 199 }; 200 201 static const char * const smca_de_mce_desc[] = { 202 "Micro-op cache tag parity error", 203 "Micro-op cache data parity error", 204 "Instruction buffer parity error", 205 "Micro-op queue parity error", 206 "Instruction dispatch queue parity error", 207 "Fetch address FIFO parity error", 208 "Patch RAM data parity error", 209 "Patch RAM sequencer parity error", 210 "Micro-op buffer parity error" 211 }; 212 213 static const char * const smca_ex_mce_desc[] = { 214 "Watchdog Timeout error", 215 "Physical register file parity error", 216 "Flag register file parity error", 217 "Immediate displacement register file parity error", 218 "Address generator payload parity error", 219 "EX payload parity error", 220 "Checkpoint queue parity error", 221 "Retire dispatch queue parity error", 222 "Retire status queue parity error", 223 "Scheduling queue parity error", 224 "Branch buffer queue parity error", 225 "Hardware Assertion error", 226 }; 227 228 static const char * const smca_fp_mce_desc[] = { 229 "Physical register file (PRF) parity error", 230 "Freelist (FL) parity error", 231 "Schedule queue parity error", 232 "NSQ parity error", 233 "Retire queue (RQ) parity error", 234 "Status register file (SRF) parity error", 235 "Hardware assertion", 236 }; 237 238 static const char * const smca_l3_mce_desc[] = { 239 "Shadow Tag Macro ECC Error", 240 "Shadow Tag Macro Multi-way-hit Error", 241 "L3M Tag ECC Error", 242 "L3M Tag Multi-way-hit Error", 243 "L3M Data ECC Error", 244 "SDP Parity Error or SystemReadDataError from XI", 245 "L3 Victim Queue Parity Error", 246 "L3 Hardware Assertion", 247 }; 248 249 static const char * const smca_cs_mce_desc[] = { 250 "Illegal Request", 251 "Address Violation", 252 "Security Violation", 253 "Illegal Response", 254 "Unexpected Response", 255 "Request or Probe Parity Error", 256 "Read Response Parity Error", 257 "Atomic Request Parity Error", 258 "Probe Filter ECC Error", 259 }; 260 261 static const char * const smca_cs2_mce_desc[] = { 262 "Illegal Request", 263 "Address Violation", 264 "Security Violation", 265 "Illegal Response", 266 "Unexpected Response", 267 "Request or Probe Parity Error", 268 "Read Response Parity Error", 269 "Atomic Request Parity Error", 270 "SDP read response had no match in the CS queue", 271 "Probe Filter Protocol Error", 272 "Probe Filter ECC Error", 273 "SDP read response had an unexpected RETRY error", 274 "Counter overflow error", 275 "Counter underflow error", 276 }; 277 278 static const char * const smca_pie_mce_desc[] = { 279 "Hardware Assert", 280 "Register security violation", 281 "Link Error", 282 "Poison data consumption", 283 "A deferred error was detected in the DF" 284 }; 285 286 static const char * const smca_umc_mce_desc[] = { 287 "DRAM ECC error", 288 "Data poison error", 289 "SDP parity error", 290 "Advanced peripheral bus error", 291 "Address/Command parity error", 292 "Write data CRC error", 293 "DCQ SRAM ECC error", 294 "AES SRAM ECC error", 295 }; 296 297 static const char * const smca_pb_mce_desc[] = { 298 "An ECC error in the Parameter Block RAM array", 299 }; 300 301 static const char * const smca_psp_mce_desc[] = { 302 "An ECC or parity error in a PSP RAM instance", 303 }; 304 305 static const char * const smca_psp2_mce_desc[] = { 306 "High SRAM ECC or parity error", 307 "Low SRAM ECC or parity error", 308 "Instruction Cache Bank 0 ECC or parity error", 309 "Instruction Cache Bank 1 ECC or parity error", 310 "Instruction Tag Ram 0 parity error", 311 "Instruction Tag Ram 1 parity error", 312 "Data Cache Bank 0 ECC or parity error", 313 "Data Cache Bank 1 ECC or parity error", 314 "Data Cache Bank 2 ECC or parity error", 315 "Data Cache Bank 3 ECC or parity error", 316 "Data Tag Bank 0 parity error", 317 "Data Tag Bank 1 parity error", 318 "Data Tag Bank 2 parity error", 319 "Data Tag Bank 3 parity error", 320 "Dirty Data Ram parity error", 321 "TLB Bank 0 parity error", 322 "TLB Bank 1 parity error", 323 "System Hub Read Buffer ECC or parity error", 324 }; 325 326 static const char * const smca_smu_mce_desc[] = { 327 "An ECC or parity error in an SMU RAM instance", 328 }; 329 330 static const char * const smca_smu2_mce_desc[] = { 331 "High SRAM ECC or parity error", 332 "Low SRAM ECC or parity error", 333 "Data Cache Bank A ECC or parity error", 334 "Data Cache Bank B ECC or parity error", 335 "Data Tag Cache Bank A ECC or parity error", 336 "Data Tag Cache Bank B ECC or parity error", 337 "Instruction Cache Bank A ECC or parity error", 338 "Instruction Cache Bank B ECC or parity error", 339 "Instruction Tag Cache Bank A ECC or parity error", 340 "Instruction Tag Cache Bank B ECC or parity error", 341 "System Hub Read Buffer ECC or parity error", 342 }; 343 344 static const char * const smca_mp5_mce_desc[] = { 345 "High SRAM ECC or parity error", 346 "Low SRAM ECC or parity error", 347 "Data Cache Bank A ECC or parity error", 348 "Data Cache Bank B ECC or parity error", 349 "Data Tag Cache Bank A ECC or parity error", 350 "Data Tag Cache Bank B ECC or parity error", 351 "Instruction Cache Bank A ECC or parity error", 352 "Instruction Cache Bank B ECC or parity error", 353 "Instruction Tag Cache Bank A ECC or parity error", 354 "Instruction Tag Cache Bank B ECC or parity error", 355 }; 356 357 static const char * const smca_nbio_mce_desc[] = { 358 "ECC or Parity error", 359 "PCIE error", 360 "SDP ErrEvent error", 361 "SDP Egress Poison Error", 362 "IOHC Internal Poison Error", 363 }; 364 365 static const char * const smca_pcie_mce_desc[] = { 366 "CCIX PER Message logging", 367 "CCIX Read Response with Status: Non-Data Error", 368 "CCIX Write Response with Status: Non-Data Error", 369 "CCIX Read Response with Status: Data Error", 370 "CCIX Non-okay write response with data error", 371 }; 372 373 struct smca_mce_desc { 374 const char * const *descs; 375 unsigned int num_descs; 376 }; 377 378 static struct smca_mce_desc smca_mce_descs[] = { 379 [SMCA_LS] = { smca_ls_mce_desc, ARRAY_SIZE(smca_ls_mce_desc) }, 380 [SMCA_IF] = { smca_if_mce_desc, ARRAY_SIZE(smca_if_mce_desc) }, 381 [SMCA_L2_CACHE] = { smca_l2_mce_desc, ARRAY_SIZE(smca_l2_mce_desc) }, 382 [SMCA_DE] = { smca_de_mce_desc, ARRAY_SIZE(smca_de_mce_desc) }, 383 [SMCA_EX] = { smca_ex_mce_desc, ARRAY_SIZE(smca_ex_mce_desc) }, 384 [SMCA_FP] = { smca_fp_mce_desc, ARRAY_SIZE(smca_fp_mce_desc) }, 385 [SMCA_L3_CACHE] = { smca_l3_mce_desc, ARRAY_SIZE(smca_l3_mce_desc) }, 386 [SMCA_CS] = { smca_cs_mce_desc, ARRAY_SIZE(smca_cs_mce_desc) }, 387 [SMCA_CS_V2] = { smca_cs2_mce_desc, ARRAY_SIZE(smca_cs2_mce_desc) }, 388 [SMCA_PIE] = { smca_pie_mce_desc, ARRAY_SIZE(smca_pie_mce_desc) }, 389 [SMCA_UMC] = { smca_umc_mce_desc, ARRAY_SIZE(smca_umc_mce_desc) }, 390 [SMCA_PB] = { smca_pb_mce_desc, ARRAY_SIZE(smca_pb_mce_desc) }, 391 [SMCA_PSP] = { smca_psp_mce_desc, ARRAY_SIZE(smca_psp_mce_desc) }, 392 [SMCA_PSP_V2] = { smca_psp2_mce_desc, ARRAY_SIZE(smca_psp2_mce_desc) }, 393 [SMCA_SMU] = { smca_smu_mce_desc, ARRAY_SIZE(smca_smu_mce_desc) }, 394 [SMCA_SMU_V2] = { smca_smu2_mce_desc, ARRAY_SIZE(smca_smu2_mce_desc) }, 395 [SMCA_MP5] = { smca_mp5_mce_desc, ARRAY_SIZE(smca_mp5_mce_desc) }, 396 [SMCA_NBIO] = { smca_nbio_mce_desc, ARRAY_SIZE(smca_nbio_mce_desc) }, 397 [SMCA_PCIE] = { smca_pcie_mce_desc, ARRAY_SIZE(smca_pcie_mce_desc) }, 398 }; 399 400 static bool f12h_mc0_mce(u16 ec, u8 xec) 401 { 402 bool ret = false; 403 404 if (MEM_ERROR(ec)) { 405 u8 ll = LL(ec); 406 ret = true; 407 408 if (ll == LL_L2) 409 pr_cont("during L1 linefill from L2.\n"); 410 else if (ll == LL_L1) 411 pr_cont("Data/Tag %s error.\n", R4_MSG(ec)); 412 else 413 ret = false; 414 } 415 return ret; 416 } 417 418 static bool f10h_mc0_mce(u16 ec, u8 xec) 419 { 420 if (R4(ec) == R4_GEN && LL(ec) == LL_L1) { 421 pr_cont("during data scrub.\n"); 422 return true; 423 } 424 return f12h_mc0_mce(ec, xec); 425 } 426 427 static bool k8_mc0_mce(u16 ec, u8 xec) 428 { 429 if (BUS_ERROR(ec)) { 430 pr_cont("during system linefill.\n"); 431 return true; 432 } 433 434 return f10h_mc0_mce(ec, xec); 435 } 436 437 static bool cat_mc0_mce(u16 ec, u8 xec) 438 { 439 u8 r4 = R4(ec); 440 bool ret = true; 441 442 if (MEM_ERROR(ec)) { 443 444 if (TT(ec) != TT_DATA || LL(ec) != LL_L1) 445 return false; 446 447 switch (r4) { 448 case R4_DRD: 449 case R4_DWR: 450 pr_cont("Data/Tag parity error due to %s.\n", 451 (r4 == R4_DRD ? "load/hw prf" : "store")); 452 break; 453 case R4_EVICT: 454 pr_cont("Copyback parity error on a tag miss.\n"); 455 break; 456 case R4_SNOOP: 457 pr_cont("Tag parity error during snoop.\n"); 458 break; 459 default: 460 ret = false; 461 } 462 } else if (BUS_ERROR(ec)) { 463 464 if ((II(ec) != II_MEM && II(ec) != II_IO) || LL(ec) != LL_LG) 465 return false; 466 467 pr_cont("System read data error on a "); 468 469 switch (r4) { 470 case R4_RD: 471 pr_cont("TLB reload.\n"); 472 break; 473 case R4_DWR: 474 pr_cont("store.\n"); 475 break; 476 case R4_DRD: 477 pr_cont("load.\n"); 478 break; 479 default: 480 ret = false; 481 } 482 } else { 483 ret = false; 484 } 485 486 return ret; 487 } 488 489 static bool f15h_mc0_mce(u16 ec, u8 xec) 490 { 491 bool ret = true; 492 493 if (MEM_ERROR(ec)) { 494 495 switch (xec) { 496 case 0x0: 497 pr_cont("Data Array access error.\n"); 498 break; 499 500 case 0x1: 501 pr_cont("UC error during a linefill from L2/NB.\n"); 502 break; 503 504 case 0x2: 505 case 0x11: 506 pr_cont("STQ access error.\n"); 507 break; 508 509 case 0x3: 510 pr_cont("SCB access error.\n"); 511 break; 512 513 case 0x10: 514 pr_cont("Tag error.\n"); 515 break; 516 517 case 0x12: 518 pr_cont("LDQ access error.\n"); 519 break; 520 521 default: 522 ret = false; 523 } 524 } else if (BUS_ERROR(ec)) { 525 526 if (!xec) 527 pr_cont("System Read Data Error.\n"); 528 else 529 pr_cont(" Internal error condition type %d.\n", xec); 530 } else if (INT_ERROR(ec)) { 531 if (xec <= 0x1f) 532 pr_cont("Hardware Assert.\n"); 533 else 534 ret = false; 535 536 } else 537 ret = false; 538 539 return ret; 540 } 541 542 static void decode_mc0_mce(struct mce *m) 543 { 544 u16 ec = EC(m->status); 545 u8 xec = XEC(m->status, xec_mask); 546 547 pr_emerg(HW_ERR "MC0 Error: "); 548 549 /* TLB error signatures are the same across families */ 550 if (TLB_ERROR(ec)) { 551 if (TT(ec) == TT_DATA) { 552 pr_cont("%s TLB %s.\n", LL_MSG(ec), 553 ((xec == 2) ? "locked miss" 554 : (xec ? "multimatch" : "parity"))); 555 return; 556 } 557 } else if (fam_ops->mc0_mce(ec, xec)) 558 ; 559 else 560 pr_emerg(HW_ERR "Corrupted MC0 MCE info?\n"); 561 } 562 563 static bool k8_mc1_mce(u16 ec, u8 xec) 564 { 565 u8 ll = LL(ec); 566 bool ret = true; 567 568 if (!MEM_ERROR(ec)) 569 return false; 570 571 if (ll == 0x2) 572 pr_cont("during a linefill from L2.\n"); 573 else if (ll == 0x1) { 574 switch (R4(ec)) { 575 case R4_IRD: 576 pr_cont("Parity error during data load.\n"); 577 break; 578 579 case R4_EVICT: 580 pr_cont("Copyback Parity/Victim error.\n"); 581 break; 582 583 case R4_SNOOP: 584 pr_cont("Tag Snoop error.\n"); 585 break; 586 587 default: 588 ret = false; 589 break; 590 } 591 } else 592 ret = false; 593 594 return ret; 595 } 596 597 static bool cat_mc1_mce(u16 ec, u8 xec) 598 { 599 u8 r4 = R4(ec); 600 bool ret = true; 601 602 if (!MEM_ERROR(ec)) 603 return false; 604 605 if (TT(ec) != TT_INSTR) 606 return false; 607 608 if (r4 == R4_IRD) 609 pr_cont("Data/tag array parity error for a tag hit.\n"); 610 else if (r4 == R4_SNOOP) 611 pr_cont("Tag error during snoop/victimization.\n"); 612 else if (xec == 0x0) 613 pr_cont("Tag parity error from victim castout.\n"); 614 else if (xec == 0x2) 615 pr_cont("Microcode patch RAM parity error.\n"); 616 else 617 ret = false; 618 619 return ret; 620 } 621 622 static bool f15h_mc1_mce(u16 ec, u8 xec) 623 { 624 bool ret = true; 625 626 if (!MEM_ERROR(ec)) 627 return false; 628 629 switch (xec) { 630 case 0x0 ... 0xa: 631 pr_cont("%s.\n", f15h_mc1_mce_desc[xec]); 632 break; 633 634 case 0xd: 635 pr_cont("%s.\n", f15h_mc1_mce_desc[xec-2]); 636 break; 637 638 case 0x10: 639 pr_cont("%s.\n", f15h_mc1_mce_desc[xec-4]); 640 break; 641 642 case 0x11 ... 0x15: 643 pr_cont("Decoder %s parity error.\n", f15h_mc1_mce_desc[xec-4]); 644 break; 645 646 default: 647 ret = false; 648 } 649 return ret; 650 } 651 652 static void decode_mc1_mce(struct mce *m) 653 { 654 u16 ec = EC(m->status); 655 u8 xec = XEC(m->status, xec_mask); 656 657 pr_emerg(HW_ERR "MC1 Error: "); 658 659 if (TLB_ERROR(ec)) 660 pr_cont("%s TLB %s.\n", LL_MSG(ec), 661 (xec ? "multimatch" : "parity error")); 662 else if (BUS_ERROR(ec)) { 663 bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT_64(58))); 664 665 pr_cont("during %s.\n", (k8 ? "system linefill" : "NB data read")); 666 } else if (INT_ERROR(ec)) { 667 if (xec <= 0x3f) 668 pr_cont("Hardware Assert.\n"); 669 else 670 goto wrong_mc1_mce; 671 } else if (fam_ops->mc1_mce(ec, xec)) 672 ; 673 else 674 goto wrong_mc1_mce; 675 676 return; 677 678 wrong_mc1_mce: 679 pr_emerg(HW_ERR "Corrupted MC1 MCE info?\n"); 680 } 681 682 static bool k8_mc2_mce(u16 ec, u8 xec) 683 { 684 bool ret = true; 685 686 if (xec == 0x1) 687 pr_cont(" in the write data buffers.\n"); 688 else if (xec == 0x3) 689 pr_cont(" in the victim data buffers.\n"); 690 else if (xec == 0x2 && MEM_ERROR(ec)) 691 pr_cont(": %s error in the L2 cache tags.\n", R4_MSG(ec)); 692 else if (xec == 0x0) { 693 if (TLB_ERROR(ec)) 694 pr_cont("%s error in a Page Descriptor Cache or Guest TLB.\n", 695 TT_MSG(ec)); 696 else if (BUS_ERROR(ec)) 697 pr_cont(": %s/ECC error in data read from NB: %s.\n", 698 R4_MSG(ec), PP_MSG(ec)); 699 else if (MEM_ERROR(ec)) { 700 u8 r4 = R4(ec); 701 702 if (r4 >= 0x7) 703 pr_cont(": %s error during data copyback.\n", 704 R4_MSG(ec)); 705 else if (r4 <= 0x1) 706 pr_cont(": %s parity/ECC error during data " 707 "access from L2.\n", R4_MSG(ec)); 708 else 709 ret = false; 710 } else 711 ret = false; 712 } else 713 ret = false; 714 715 return ret; 716 } 717 718 static bool f15h_mc2_mce(u16 ec, u8 xec) 719 { 720 bool ret = true; 721 722 if (TLB_ERROR(ec)) { 723 if (xec == 0x0) 724 pr_cont("Data parity TLB read error.\n"); 725 else if (xec == 0x1) 726 pr_cont("Poison data provided for TLB fill.\n"); 727 else 728 ret = false; 729 } else if (BUS_ERROR(ec)) { 730 if (xec > 2) 731 ret = false; 732 733 pr_cont("Error during attempted NB data read.\n"); 734 } else if (MEM_ERROR(ec)) { 735 switch (xec) { 736 case 0x4 ... 0xc: 737 pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x4]); 738 break; 739 740 case 0x10 ... 0x14: 741 pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x7]); 742 break; 743 744 default: 745 ret = false; 746 } 747 } else if (INT_ERROR(ec)) { 748 if (xec <= 0x3f) 749 pr_cont("Hardware Assert.\n"); 750 else 751 ret = false; 752 } 753 754 return ret; 755 } 756 757 static bool f16h_mc2_mce(u16 ec, u8 xec) 758 { 759 u8 r4 = R4(ec); 760 761 if (!MEM_ERROR(ec)) 762 return false; 763 764 switch (xec) { 765 case 0x04 ... 0x05: 766 pr_cont("%cBUFF parity error.\n", (r4 == R4_RD) ? 'I' : 'O'); 767 break; 768 769 case 0x09 ... 0x0b: 770 case 0x0d ... 0x0f: 771 pr_cont("ECC error in L2 tag (%s).\n", 772 ((r4 == R4_GEN) ? "BankReq" : 773 ((r4 == R4_SNOOP) ? "Prb" : "Fill"))); 774 break; 775 776 case 0x10 ... 0x19: 777 case 0x1b: 778 pr_cont("ECC error in L2 data array (%s).\n", 779 (((r4 == R4_RD) && !(xec & 0x3)) ? "Hit" : 780 ((r4 == R4_GEN) ? "Attr" : 781 ((r4 == R4_EVICT) ? "Vict" : "Fill")))); 782 break; 783 784 case 0x1c ... 0x1d: 785 case 0x1f: 786 pr_cont("Parity error in L2 attribute bits (%s).\n", 787 ((r4 == R4_RD) ? "Hit" : 788 ((r4 == R4_GEN) ? "Attr" : "Fill"))); 789 break; 790 791 default: 792 return false; 793 } 794 795 return true; 796 } 797 798 static void decode_mc2_mce(struct mce *m) 799 { 800 u16 ec = EC(m->status); 801 u8 xec = XEC(m->status, xec_mask); 802 803 pr_emerg(HW_ERR "MC2 Error: "); 804 805 if (!fam_ops->mc2_mce(ec, xec)) 806 pr_cont(HW_ERR "Corrupted MC2 MCE info?\n"); 807 } 808 809 static void decode_mc3_mce(struct mce *m) 810 { 811 u16 ec = EC(m->status); 812 u8 xec = XEC(m->status, xec_mask); 813 814 if (boot_cpu_data.x86 >= 0x14) { 815 pr_emerg("You shouldn't be seeing MC3 MCE on this cpu family," 816 " please report on LKML.\n"); 817 return; 818 } 819 820 pr_emerg(HW_ERR "MC3 Error"); 821 822 if (xec == 0x0) { 823 u8 r4 = R4(ec); 824 825 if (!BUS_ERROR(ec) || (r4 != R4_DRD && r4 != R4_DWR)) 826 goto wrong_mc3_mce; 827 828 pr_cont(" during %s.\n", R4_MSG(ec)); 829 } else 830 goto wrong_mc3_mce; 831 832 return; 833 834 wrong_mc3_mce: 835 pr_emerg(HW_ERR "Corrupted MC3 MCE info?\n"); 836 } 837 838 static void decode_mc4_mce(struct mce *m) 839 { 840 unsigned int fam = x86_family(m->cpuid); 841 int node_id = amd_get_nb_id(m->extcpu); 842 u16 ec = EC(m->status); 843 u8 xec = XEC(m->status, 0x1f); 844 u8 offset = 0; 845 846 pr_emerg(HW_ERR "MC4 Error (node %d): ", node_id); 847 848 switch (xec) { 849 case 0x0 ... 0xe: 850 851 /* special handling for DRAM ECCs */ 852 if (xec == 0x0 || xec == 0x8) { 853 /* no ECCs on F11h */ 854 if (fam == 0x11) 855 goto wrong_mc4_mce; 856 857 pr_cont("%s.\n", mc4_mce_desc[xec]); 858 859 if (decode_dram_ecc) 860 decode_dram_ecc(node_id, m); 861 return; 862 } 863 break; 864 865 case 0xf: 866 if (TLB_ERROR(ec)) 867 pr_cont("GART Table Walk data error.\n"); 868 else if (BUS_ERROR(ec)) 869 pr_cont("DMA Exclusion Vector Table Walk error.\n"); 870 else 871 goto wrong_mc4_mce; 872 return; 873 874 case 0x19: 875 if (fam == 0x15 || fam == 0x16) 876 pr_cont("Compute Unit Data Error.\n"); 877 else 878 goto wrong_mc4_mce; 879 return; 880 881 case 0x1c ... 0x1f: 882 offset = 13; 883 break; 884 885 default: 886 goto wrong_mc4_mce; 887 } 888 889 pr_cont("%s.\n", mc4_mce_desc[xec - offset]); 890 return; 891 892 wrong_mc4_mce: 893 pr_emerg(HW_ERR "Corrupted MC4 MCE info?\n"); 894 } 895 896 static void decode_mc5_mce(struct mce *m) 897 { 898 unsigned int fam = x86_family(m->cpuid); 899 u16 ec = EC(m->status); 900 u8 xec = XEC(m->status, xec_mask); 901 902 if (fam == 0xf || fam == 0x11) 903 goto wrong_mc5_mce; 904 905 pr_emerg(HW_ERR "MC5 Error: "); 906 907 if (INT_ERROR(ec)) { 908 if (xec <= 0x1f) { 909 pr_cont("Hardware Assert.\n"); 910 return; 911 } else 912 goto wrong_mc5_mce; 913 } 914 915 if (xec == 0x0 || xec == 0xc) 916 pr_cont("%s.\n", mc5_mce_desc[xec]); 917 else if (xec <= 0xd) 918 pr_cont("%s parity error.\n", mc5_mce_desc[xec]); 919 else 920 goto wrong_mc5_mce; 921 922 return; 923 924 wrong_mc5_mce: 925 pr_emerg(HW_ERR "Corrupted MC5 MCE info?\n"); 926 } 927 928 static void decode_mc6_mce(struct mce *m) 929 { 930 u8 xec = XEC(m->status, xec_mask); 931 932 pr_emerg(HW_ERR "MC6 Error: "); 933 934 if (xec > 0x5) 935 goto wrong_mc6_mce; 936 937 pr_cont("%s parity error.\n", mc6_mce_desc[xec]); 938 return; 939 940 wrong_mc6_mce: 941 pr_emerg(HW_ERR "Corrupted MC6 MCE info?\n"); 942 } 943 944 /* Decode errors according to Scalable MCA specification */ 945 static void decode_smca_error(struct mce *m) 946 { 947 struct smca_hwid *hwid; 948 enum smca_bank_types bank_type; 949 const char *ip_name; 950 u8 xec = XEC(m->status, xec_mask); 951 952 if (m->bank >= ARRAY_SIZE(smca_banks)) 953 return; 954 955 hwid = smca_banks[m->bank].hwid; 956 if (!hwid) 957 return; 958 959 bank_type = hwid->bank_type; 960 961 if (bank_type == SMCA_RESERVED) { 962 pr_emerg(HW_ERR "Bank %d is reserved.\n", m->bank); 963 return; 964 } 965 966 ip_name = smca_get_long_name(bank_type); 967 968 pr_emerg(HW_ERR "%s Ext. Error Code: %d", ip_name, xec); 969 970 /* Only print the decode of valid error codes */ 971 if (xec < smca_mce_descs[bank_type].num_descs && 972 (hwid->xec_bitmap & BIT_ULL(xec))) { 973 pr_cont(", %s.\n", smca_mce_descs[bank_type].descs[xec]); 974 } 975 976 if (bank_type == SMCA_UMC && xec == 0 && decode_dram_ecc) 977 decode_dram_ecc(cpu_to_node(m->extcpu), m); 978 } 979 980 static inline void amd_decode_err_code(u16 ec) 981 { 982 if (INT_ERROR(ec)) { 983 pr_emerg(HW_ERR "internal: %s\n", UU_MSG(ec)); 984 return; 985 } 986 987 pr_emerg(HW_ERR "cache level: %s", LL_MSG(ec)); 988 989 if (BUS_ERROR(ec)) 990 pr_cont(", mem/io: %s", II_MSG(ec)); 991 else 992 pr_cont(", tx: %s", TT_MSG(ec)); 993 994 if (MEM_ERROR(ec) || BUS_ERROR(ec)) { 995 pr_cont(", mem-tx: %s", R4_MSG(ec)); 996 997 if (BUS_ERROR(ec)) 998 pr_cont(", part-proc: %s (%s)", PP_MSG(ec), TO_MSG(ec)); 999 } 1000 1001 pr_cont("\n"); 1002 } 1003 1004 /* 1005 * Filter out unwanted MCE signatures here. 1006 */ 1007 static bool amd_filter_mce(struct mce *m) 1008 { 1009 /* 1010 * NB GART TLB error reporting is disabled by default. 1011 */ 1012 if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5 && !report_gart_errors) 1013 return true; 1014 1015 return false; 1016 } 1017 1018 static const char *decode_error_status(struct mce *m) 1019 { 1020 if (m->status & MCI_STATUS_UC) { 1021 if (m->status & MCI_STATUS_PCC) 1022 return "System Fatal error."; 1023 if (m->mcgstatus & MCG_STATUS_RIPV) 1024 return "Uncorrected, software restartable error."; 1025 return "Uncorrected, software containable error."; 1026 } 1027 1028 if (m->status & MCI_STATUS_DEFERRED) 1029 return "Deferred error, no action required."; 1030 1031 return "Corrected error, no action required."; 1032 } 1033 1034 static int 1035 amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data) 1036 { 1037 struct mce *m = (struct mce *)data; 1038 unsigned int fam = x86_family(m->cpuid); 1039 int ecc; 1040 1041 if (amd_filter_mce(m)) 1042 return NOTIFY_STOP; 1043 1044 pr_emerg(HW_ERR "%s\n", decode_error_status(m)); 1045 1046 pr_emerg(HW_ERR "CPU:%d (%x:%x:%x) MC%d_STATUS[%s|%s|%s|%s|%s", 1047 m->extcpu, 1048 fam, x86_model(m->cpuid), x86_stepping(m->cpuid), 1049 m->bank, 1050 ((m->status & MCI_STATUS_OVER) ? "Over" : "-"), 1051 ((m->status & MCI_STATUS_UC) ? "UE" : 1052 (m->status & MCI_STATUS_DEFERRED) ? "-" : "CE"), 1053 ((m->status & MCI_STATUS_MISCV) ? "MiscV" : "-"), 1054 ((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-"), 1055 ((m->status & MCI_STATUS_PCC) ? "PCC" : "-")); 1056 1057 if (boot_cpu_has(X86_FEATURE_SMCA)) { 1058 u32 low, high; 1059 u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank); 1060 1061 if (!rdmsr_safe(addr, &low, &high) && 1062 (low & MCI_CONFIG_MCAX)) 1063 pr_cont("|%s", ((m->status & MCI_STATUS_TCC) ? "TCC" : "-")); 1064 1065 pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? "SyndV" : "-")); 1066 } 1067 1068 /* do the two bits[14:13] together */ 1069 ecc = (m->status >> 45) & 0x3; 1070 if (ecc) 1071 pr_cont("|%sECC", ((ecc == 2) ? "C" : "U")); 1072 1073 if (fam >= 0x15) { 1074 pr_cont("|%s", (m->status & MCI_STATUS_DEFERRED ? "Deferred" : "-")); 1075 1076 /* F15h, bank4, bit 43 is part of McaStatSubCache. */ 1077 if (fam != 0x15 || m->bank != 4) 1078 pr_cont("|%s", (m->status & MCI_STATUS_POISON ? "Poison" : "-")); 1079 } 1080 1081 if (fam >= 0x17) 1082 pr_cont("|%s", (m->status & MCI_STATUS_SCRUB ? "Scrub" : "-")); 1083 1084 pr_cont("]: 0x%016llx\n", m->status); 1085 1086 if (m->status & MCI_STATUS_ADDRV) 1087 pr_emerg(HW_ERR "Error Addr: 0x%016llx\n", m->addr); 1088 1089 if (boot_cpu_has(X86_FEATURE_SMCA)) { 1090 pr_emerg(HW_ERR "IPID: 0x%016llx", m->ipid); 1091 1092 if (m->status & MCI_STATUS_SYNDV) 1093 pr_cont(", Syndrome: 0x%016llx", m->synd); 1094 1095 pr_cont("\n"); 1096 1097 decode_smca_error(m); 1098 goto err_code; 1099 } 1100 1101 if (m->tsc) 1102 pr_emerg(HW_ERR "TSC: %llu\n", m->tsc); 1103 1104 if (!fam_ops) 1105 goto err_code; 1106 1107 switch (m->bank) { 1108 case 0: 1109 decode_mc0_mce(m); 1110 break; 1111 1112 case 1: 1113 decode_mc1_mce(m); 1114 break; 1115 1116 case 2: 1117 decode_mc2_mce(m); 1118 break; 1119 1120 case 3: 1121 decode_mc3_mce(m); 1122 break; 1123 1124 case 4: 1125 decode_mc4_mce(m); 1126 break; 1127 1128 case 5: 1129 decode_mc5_mce(m); 1130 break; 1131 1132 case 6: 1133 decode_mc6_mce(m); 1134 break; 1135 1136 default: 1137 break; 1138 } 1139 1140 err_code: 1141 amd_decode_err_code(m->status & 0xffff); 1142 1143 return NOTIFY_STOP; 1144 } 1145 1146 static struct notifier_block amd_mce_dec_nb = { 1147 .notifier_call = amd_decode_mce, 1148 .priority = MCE_PRIO_EDAC, 1149 }; 1150 1151 static int __init mce_amd_init(void) 1152 { 1153 struct cpuinfo_x86 *c = &boot_cpu_data; 1154 1155 if (c->x86_vendor != X86_VENDOR_AMD && 1156 c->x86_vendor != X86_VENDOR_HYGON) 1157 return -ENODEV; 1158 1159 fam_ops = kzalloc(sizeof(struct amd_decoder_ops), GFP_KERNEL); 1160 if (!fam_ops) 1161 return -ENOMEM; 1162 1163 switch (c->x86) { 1164 case 0xf: 1165 fam_ops->mc0_mce = k8_mc0_mce; 1166 fam_ops->mc1_mce = k8_mc1_mce; 1167 fam_ops->mc2_mce = k8_mc2_mce; 1168 break; 1169 1170 case 0x10: 1171 fam_ops->mc0_mce = f10h_mc0_mce; 1172 fam_ops->mc1_mce = k8_mc1_mce; 1173 fam_ops->mc2_mce = k8_mc2_mce; 1174 break; 1175 1176 case 0x11: 1177 fam_ops->mc0_mce = k8_mc0_mce; 1178 fam_ops->mc1_mce = k8_mc1_mce; 1179 fam_ops->mc2_mce = k8_mc2_mce; 1180 break; 1181 1182 case 0x12: 1183 fam_ops->mc0_mce = f12h_mc0_mce; 1184 fam_ops->mc1_mce = k8_mc1_mce; 1185 fam_ops->mc2_mce = k8_mc2_mce; 1186 break; 1187 1188 case 0x14: 1189 fam_ops->mc0_mce = cat_mc0_mce; 1190 fam_ops->mc1_mce = cat_mc1_mce; 1191 fam_ops->mc2_mce = k8_mc2_mce; 1192 break; 1193 1194 case 0x15: 1195 xec_mask = c->x86_model == 0x60 ? 0x3f : 0x1f; 1196 1197 fam_ops->mc0_mce = f15h_mc0_mce; 1198 fam_ops->mc1_mce = f15h_mc1_mce; 1199 fam_ops->mc2_mce = f15h_mc2_mce; 1200 break; 1201 1202 case 0x16: 1203 xec_mask = 0x1f; 1204 fam_ops->mc0_mce = cat_mc0_mce; 1205 fam_ops->mc1_mce = cat_mc1_mce; 1206 fam_ops->mc2_mce = f16h_mc2_mce; 1207 break; 1208 1209 case 0x17: 1210 case 0x18: 1211 xec_mask = 0x3f; 1212 if (!boot_cpu_has(X86_FEATURE_SMCA)) { 1213 printk(KERN_WARNING "Decoding supported only on Scalable MCA processors.\n"); 1214 goto err_out; 1215 } 1216 break; 1217 1218 default: 1219 printk(KERN_WARNING "Huh? What family is it: 0x%x?!\n", c->x86); 1220 goto err_out; 1221 } 1222 1223 pr_info("MCE: In-kernel MCE decoding enabled.\n"); 1224 1225 mce_register_decode_chain(&amd_mce_dec_nb); 1226 1227 return 0; 1228 1229 err_out: 1230 kfree(fam_ops); 1231 fam_ops = NULL; 1232 return -EINVAL; 1233 } 1234 early_initcall(mce_amd_init); 1235 1236 #ifdef MODULE 1237 static void __exit mce_amd_exit(void) 1238 { 1239 mce_unregister_decode_chain(&amd_mce_dec_nb); 1240 kfree(fam_ops); 1241 } 1242 1243 MODULE_DESCRIPTION("AMD MCE decoder"); 1244 MODULE_ALIAS("edac-mce-amd"); 1245 MODULE_LICENSE("GPL"); 1246 module_exit(mce_amd_exit); 1247 #endif 1248