1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Intel E3-1200 4 * Copyright (C) 2014 Jason Baron <jbaron@akamai.com> 5 * 6 * Support for the E3-1200 processor family. Heavily based on previous 7 * Intel EDAC drivers. 8 * 9 * Since the DRAM controller is on the cpu chip, we can use its PCI device 10 * id to identify these processors. 11 * 12 * PCI DRAM controller device ids (Taken from The PCI ID Repository - http://pci-ids.ucw.cz/) 13 * 14 * 0108: Xeon E3-1200 Processor Family DRAM Controller 15 * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller 16 * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller 17 * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller 18 * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller 19 * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller 20 * 0c08: Xeon E3-1200 v3 Processor DRAM Controller 21 * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers 22 * 5918: Xeon E3-1200 Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers 23 * 24 * Based on Intel specification: 25 * http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf 26 * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html 27 * http://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html 28 * 29 * According to the above datasheet (p.16): 30 * " 31 * 6. Software must not access B0/D0/F0 32-bit memory-mapped registers with 32 * requests that cross a DW boundary. 33 * " 34 * 35 * Thus, we make use of the explicit: lo_hi_readq(), which breaks the readq into 36 * 2 readl() calls. This restriction may be lifted in subsequent chip releases, 37 * but lo_hi_readq() ensures that we are safe across all e3-1200 processors. 38 */ 39 40 #include <linux/module.h> 41 #include <linux/init.h> 42 #include <linux/pci.h> 43 #include <linux/pci_ids.h> 44 #include <linux/edac.h> 45 46 #include <linux/io-64-nonatomic-lo-hi.h> 47 #include "edac_module.h" 48 49 #define EDAC_MOD_STR "ie31200_edac" 50 51 #define ie31200_printk(level, fmt, arg...) \ 52 edac_printk(level, "ie31200", fmt, ##arg) 53 54 #define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108 55 #define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c 56 #define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150 57 #define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158 58 #define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c 59 #define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04 60 #define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08 61 #define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x1918 62 #define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x5918 63 64 #define IE31200_DIMMS 4 65 #define IE31200_RANKS 8 66 #define IE31200_RANKS_PER_CHANNEL 4 67 #define IE31200_DIMMS_PER_CHANNEL 2 68 #define IE31200_CHANNELS 2 69 70 /* Intel IE31200 register addresses - device 0 function 0 - DRAM Controller */ 71 #define IE31200_MCHBAR_LOW 0x48 72 #define IE31200_MCHBAR_HIGH 0x4c 73 #define IE31200_MCHBAR_MASK GENMASK_ULL(38, 15) 74 #define IE31200_MMR_WINDOW_SIZE BIT(15) 75 76 /* 77 * Error Status Register (16b) 78 * 79 * 15 reserved 80 * 14 Isochronous TBWRR Run Behind FIFO Full 81 * (ITCV) 82 * 13 Isochronous TBWRR Run Behind FIFO Put 83 * (ITSTV) 84 * 12 reserved 85 * 11 MCH Thermal Sensor Event 86 * for SMI/SCI/SERR (GTSE) 87 * 10 reserved 88 * 9 LOCK to non-DRAM Memory Flag (LCKF) 89 * 8 reserved 90 * 7 DRAM Throttle Flag (DTF) 91 * 6:2 reserved 92 * 1 Multi-bit DRAM ECC Error Flag (DMERR) 93 * 0 Single-bit DRAM ECC Error Flag (DSERR) 94 */ 95 #define IE31200_ERRSTS 0xc8 96 #define IE31200_ERRSTS_UE BIT(1) 97 #define IE31200_ERRSTS_CE BIT(0) 98 #define IE31200_ERRSTS_BITS (IE31200_ERRSTS_UE | IE31200_ERRSTS_CE) 99 100 /* 101 * Channel 0 ECC Error Log (64b) 102 * 103 * 63:48 Error Column Address (ERRCOL) 104 * 47:32 Error Row Address (ERRROW) 105 * 31:29 Error Bank Address (ERRBANK) 106 * 28:27 Error Rank Address (ERRRANK) 107 * 26:24 reserved 108 * 23:16 Error Syndrome (ERRSYND) 109 * 15: 2 reserved 110 * 1 Multiple Bit Error Status (MERRSTS) 111 * 0 Correctable Error Status (CERRSTS) 112 */ 113 114 #define IE31200_C0ECCERRLOG 0x40c8 115 #define IE31200_C1ECCERRLOG 0x44c8 116 #define IE31200_C0ECCERRLOG_SKL 0x4048 117 #define IE31200_C1ECCERRLOG_SKL 0x4448 118 #define IE31200_ECCERRLOG_CE BIT(0) 119 #define IE31200_ECCERRLOG_UE BIT(1) 120 #define IE31200_ECCERRLOG_RANK_BITS GENMASK_ULL(28, 27) 121 #define IE31200_ECCERRLOG_RANK_SHIFT 27 122 #define IE31200_ECCERRLOG_SYNDROME_BITS GENMASK_ULL(23, 16) 123 #define IE31200_ECCERRLOG_SYNDROME_SHIFT 16 124 125 #define IE31200_ECCERRLOG_SYNDROME(log) \ 126 ((log & IE31200_ECCERRLOG_SYNDROME_BITS) >> \ 127 IE31200_ECCERRLOG_SYNDROME_SHIFT) 128 129 #define IE31200_CAPID0 0xe4 130 #define IE31200_CAPID0_PDCD BIT(4) 131 #define IE31200_CAPID0_DDPCD BIT(6) 132 #define IE31200_CAPID0_ECC BIT(1) 133 134 #define IE31200_MAD_DIMM_0_OFFSET 0x5004 135 #define IE31200_MAD_DIMM_0_OFFSET_SKL 0x500C 136 #define IE31200_MAD_DIMM_SIZE GENMASK_ULL(7, 0) 137 #define IE31200_MAD_DIMM_A_RANK BIT(17) 138 #define IE31200_MAD_DIMM_A_RANK_SHIFT 17 139 #define IE31200_MAD_DIMM_A_RANK_SKL BIT(10) 140 #define IE31200_MAD_DIMM_A_RANK_SKL_SHIFT 10 141 #define IE31200_MAD_DIMM_A_WIDTH BIT(19) 142 #define IE31200_MAD_DIMM_A_WIDTH_SHIFT 19 143 #define IE31200_MAD_DIMM_A_WIDTH_SKL GENMASK_ULL(9, 8) 144 #define IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT 8 145 146 /* Skylake reports 1GB increments, everything else is 256MB */ 147 #define IE31200_PAGES(n, skl) \ 148 (n << (28 + (2 * skl) - PAGE_SHIFT)) 149 150 static int nr_channels; 151 152 struct ie31200_priv { 153 void __iomem *window; 154 void __iomem *c0errlog; 155 void __iomem *c1errlog; 156 }; 157 158 enum ie31200_chips { 159 IE31200 = 0, 160 }; 161 162 struct ie31200_dev_info { 163 const char *ctl_name; 164 }; 165 166 struct ie31200_error_info { 167 u16 errsts; 168 u16 errsts2; 169 u64 eccerrlog[IE31200_CHANNELS]; 170 }; 171 172 static const struct ie31200_dev_info ie31200_devs[] = { 173 [IE31200] = { 174 .ctl_name = "IE31200" 175 }, 176 }; 177 178 struct dimm_data { 179 u8 size; /* in multiples of 256MB, except Skylake is 1GB */ 180 u8 dual_rank : 1, 181 x16_width : 2; /* 0 means x8 width */ 182 }; 183 184 static int how_many_channels(struct pci_dev *pdev) 185 { 186 int n_channels; 187 unsigned char capid0_2b; /* 2nd byte of CAPID0 */ 188 189 pci_read_config_byte(pdev, IE31200_CAPID0 + 1, &capid0_2b); 190 191 /* check PDCD: Dual Channel Disable */ 192 if (capid0_2b & IE31200_CAPID0_PDCD) { 193 edac_dbg(0, "In single channel mode\n"); 194 n_channels = 1; 195 } else { 196 edac_dbg(0, "In dual channel mode\n"); 197 n_channels = 2; 198 } 199 200 /* check DDPCD - check if both channels are filled */ 201 if (capid0_2b & IE31200_CAPID0_DDPCD) 202 edac_dbg(0, "2 DIMMS per channel disabled\n"); 203 else 204 edac_dbg(0, "2 DIMMS per channel enabled\n"); 205 206 return n_channels; 207 } 208 209 static bool ecc_capable(struct pci_dev *pdev) 210 { 211 unsigned char capid0_4b; /* 4th byte of CAPID0 */ 212 213 pci_read_config_byte(pdev, IE31200_CAPID0 + 3, &capid0_4b); 214 if (capid0_4b & IE31200_CAPID0_ECC) 215 return false; 216 return true; 217 } 218 219 static int eccerrlog_row(u64 log) 220 { 221 return ((log & IE31200_ECCERRLOG_RANK_BITS) >> 222 IE31200_ECCERRLOG_RANK_SHIFT); 223 } 224 225 static void ie31200_clear_error_info(struct mem_ctl_info *mci) 226 { 227 /* 228 * Clear any error bits. 229 * (Yes, we really clear bits by writing 1 to them.) 230 */ 231 pci_write_bits16(to_pci_dev(mci->pdev), IE31200_ERRSTS, 232 IE31200_ERRSTS_BITS, IE31200_ERRSTS_BITS); 233 } 234 235 static void ie31200_get_and_clear_error_info(struct mem_ctl_info *mci, 236 struct ie31200_error_info *info) 237 { 238 struct pci_dev *pdev; 239 struct ie31200_priv *priv = mci->pvt_info; 240 241 pdev = to_pci_dev(mci->pdev); 242 243 /* 244 * This is a mess because there is no atomic way to read all the 245 * registers at once and the registers can transition from CE being 246 * overwritten by UE. 247 */ 248 pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts); 249 if (!(info->errsts & IE31200_ERRSTS_BITS)) 250 return; 251 252 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog); 253 if (nr_channels == 2) 254 info->eccerrlog[1] = lo_hi_readq(priv->c1errlog); 255 256 pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts2); 257 258 /* 259 * If the error is the same for both reads then the first set 260 * of reads is valid. If there is a change then there is a CE 261 * with no info and the second set of reads is valid and 262 * should be UE info. 263 */ 264 if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) { 265 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog); 266 if (nr_channels == 2) 267 info->eccerrlog[1] = 268 lo_hi_readq(priv->c1errlog); 269 } 270 271 ie31200_clear_error_info(mci); 272 } 273 274 static void ie31200_process_error_info(struct mem_ctl_info *mci, 275 struct ie31200_error_info *info) 276 { 277 int channel; 278 u64 log; 279 280 if (!(info->errsts & IE31200_ERRSTS_BITS)) 281 return; 282 283 if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) { 284 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, 285 -1, -1, -1, "UE overwrote CE", ""); 286 info->errsts = info->errsts2; 287 } 288 289 for (channel = 0; channel < nr_channels; channel++) { 290 log = info->eccerrlog[channel]; 291 if (log & IE31200_ECCERRLOG_UE) { 292 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 293 0, 0, 0, 294 eccerrlog_row(log), 295 channel, -1, 296 "ie31200 UE", ""); 297 } else if (log & IE31200_ECCERRLOG_CE) { 298 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 299 0, 0, 300 IE31200_ECCERRLOG_SYNDROME(log), 301 eccerrlog_row(log), 302 channel, -1, 303 "ie31200 CE", ""); 304 } 305 } 306 } 307 308 static void ie31200_check(struct mem_ctl_info *mci) 309 { 310 struct ie31200_error_info info; 311 312 edac_dbg(1, "MC%d\n", mci->mc_idx); 313 ie31200_get_and_clear_error_info(mci, &info); 314 ie31200_process_error_info(mci, &info); 315 } 316 317 static void __iomem *ie31200_map_mchbar(struct pci_dev *pdev) 318 { 319 union { 320 u64 mchbar; 321 struct { 322 u32 mchbar_low; 323 u32 mchbar_high; 324 }; 325 } u; 326 void __iomem *window; 327 328 pci_read_config_dword(pdev, IE31200_MCHBAR_LOW, &u.mchbar_low); 329 pci_read_config_dword(pdev, IE31200_MCHBAR_HIGH, &u.mchbar_high); 330 u.mchbar &= IE31200_MCHBAR_MASK; 331 332 if (u.mchbar != (resource_size_t)u.mchbar) { 333 ie31200_printk(KERN_ERR, "mmio space beyond accessible range (0x%llx)\n", 334 (unsigned long long)u.mchbar); 335 return NULL; 336 } 337 338 window = ioremap_nocache(u.mchbar, IE31200_MMR_WINDOW_SIZE); 339 if (!window) 340 ie31200_printk(KERN_ERR, "Cannot map mmio space at 0x%llx\n", 341 (unsigned long long)u.mchbar); 342 343 return window; 344 } 345 346 static void __skl_populate_dimm_info(struct dimm_data *dd, u32 addr_decode, 347 int chan) 348 { 349 dd->size = (addr_decode >> (chan << 4)) & IE31200_MAD_DIMM_SIZE; 350 dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK_SKL << (chan << 4))) ? 1 : 0; 351 dd->x16_width = ((addr_decode & (IE31200_MAD_DIMM_A_WIDTH_SKL << (chan << 4))) >> 352 (IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT + (chan << 4))); 353 } 354 355 static void __populate_dimm_info(struct dimm_data *dd, u32 addr_decode, 356 int chan) 357 { 358 dd->size = (addr_decode >> (chan << 3)) & IE31200_MAD_DIMM_SIZE; 359 dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK << chan)) ? 1 : 0; 360 dd->x16_width = (addr_decode & (IE31200_MAD_DIMM_A_WIDTH << chan)) ? 1 : 0; 361 } 362 363 static void populate_dimm_info(struct dimm_data *dd, u32 addr_decode, int chan, 364 bool skl) 365 { 366 if (skl) 367 __skl_populate_dimm_info(dd, addr_decode, chan); 368 else 369 __populate_dimm_info(dd, addr_decode, chan); 370 } 371 372 373 static int ie31200_probe1(struct pci_dev *pdev, int dev_idx) 374 { 375 int i, j, ret; 376 struct mem_ctl_info *mci = NULL; 377 struct edac_mc_layer layers[2]; 378 struct dimm_data dimm_info[IE31200_CHANNELS][IE31200_DIMMS_PER_CHANNEL]; 379 void __iomem *window; 380 struct ie31200_priv *priv; 381 u32 addr_decode, mad_offset; 382 383 /* 384 * Kaby Lake seems to work like Skylake. Please re-visit this logic 385 * when adding new CPU support. 386 */ 387 bool skl = (pdev->device >= PCI_DEVICE_ID_INTEL_IE31200_HB_8); 388 389 edac_dbg(0, "MC:\n"); 390 391 if (!ecc_capable(pdev)) { 392 ie31200_printk(KERN_INFO, "No ECC support\n"); 393 return -ENODEV; 394 } 395 396 nr_channels = how_many_channels(pdev); 397 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 398 layers[0].size = IE31200_DIMMS; 399 layers[0].is_virt_csrow = true; 400 layers[1].type = EDAC_MC_LAYER_CHANNEL; 401 layers[1].size = nr_channels; 402 layers[1].is_virt_csrow = false; 403 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 404 sizeof(struct ie31200_priv)); 405 if (!mci) 406 return -ENOMEM; 407 408 window = ie31200_map_mchbar(pdev); 409 if (!window) { 410 ret = -ENODEV; 411 goto fail_free; 412 } 413 414 edac_dbg(3, "MC: init mci\n"); 415 mci->pdev = &pdev->dev; 416 if (skl) 417 mci->mtype_cap = MEM_FLAG_DDR4; 418 else 419 mci->mtype_cap = MEM_FLAG_DDR3; 420 mci->edac_ctl_cap = EDAC_FLAG_SECDED; 421 mci->edac_cap = EDAC_FLAG_SECDED; 422 mci->mod_name = EDAC_MOD_STR; 423 mci->ctl_name = ie31200_devs[dev_idx].ctl_name; 424 mci->dev_name = pci_name(pdev); 425 mci->edac_check = ie31200_check; 426 mci->ctl_page_to_phys = NULL; 427 priv = mci->pvt_info; 428 priv->window = window; 429 if (skl) { 430 priv->c0errlog = window + IE31200_C0ECCERRLOG_SKL; 431 priv->c1errlog = window + IE31200_C1ECCERRLOG_SKL; 432 mad_offset = IE31200_MAD_DIMM_0_OFFSET_SKL; 433 } else { 434 priv->c0errlog = window + IE31200_C0ECCERRLOG; 435 priv->c1errlog = window + IE31200_C1ECCERRLOG; 436 mad_offset = IE31200_MAD_DIMM_0_OFFSET; 437 } 438 439 /* populate DIMM info */ 440 for (i = 0; i < IE31200_CHANNELS; i++) { 441 addr_decode = readl(window + mad_offset + 442 (i * 4)); 443 edac_dbg(0, "addr_decode: 0x%x\n", addr_decode); 444 for (j = 0; j < IE31200_DIMMS_PER_CHANNEL; j++) { 445 populate_dimm_info(&dimm_info[i][j], addr_decode, j, 446 skl); 447 edac_dbg(0, "size: 0x%x, rank: %d, width: %d\n", 448 dimm_info[i][j].size, 449 dimm_info[i][j].dual_rank, 450 dimm_info[i][j].x16_width); 451 } 452 } 453 454 /* 455 * The dram rank boundary (DRB) reg values are boundary addresses 456 * for each DRAM rank with a granularity of 64MB. DRB regs are 457 * cumulative; the last one will contain the total memory 458 * contained in all ranks. 459 */ 460 for (i = 0; i < IE31200_DIMMS_PER_CHANNEL; i++) { 461 for (j = 0; j < IE31200_CHANNELS; j++) { 462 struct dimm_info *dimm; 463 unsigned long nr_pages; 464 465 nr_pages = IE31200_PAGES(dimm_info[j][i].size, skl); 466 if (nr_pages == 0) 467 continue; 468 469 if (dimm_info[j][i].dual_rank) { 470 nr_pages = nr_pages / 2; 471 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, 472 mci->n_layers, (i * 2) + 1, 473 j, 0); 474 dimm->nr_pages = nr_pages; 475 edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages); 476 dimm->grain = 8; /* just a guess */ 477 if (skl) 478 dimm->mtype = MEM_DDR4; 479 else 480 dimm->mtype = MEM_DDR3; 481 dimm->dtype = DEV_UNKNOWN; 482 dimm->edac_mode = EDAC_UNKNOWN; 483 } 484 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, 485 mci->n_layers, i * 2, j, 0); 486 dimm->nr_pages = nr_pages; 487 edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages); 488 dimm->grain = 8; /* same guess */ 489 if (skl) 490 dimm->mtype = MEM_DDR4; 491 else 492 dimm->mtype = MEM_DDR3; 493 dimm->dtype = DEV_UNKNOWN; 494 dimm->edac_mode = EDAC_UNKNOWN; 495 } 496 } 497 498 ie31200_clear_error_info(mci); 499 500 if (edac_mc_add_mc(mci)) { 501 edac_dbg(3, "MC: failed edac_mc_add_mc()\n"); 502 ret = -ENODEV; 503 goto fail_unmap; 504 } 505 506 /* get this far and it's successful */ 507 edac_dbg(3, "MC: success\n"); 508 return 0; 509 510 fail_unmap: 511 iounmap(window); 512 513 fail_free: 514 edac_mc_free(mci); 515 516 return ret; 517 } 518 519 static int ie31200_init_one(struct pci_dev *pdev, 520 const struct pci_device_id *ent) 521 { 522 edac_dbg(0, "MC:\n"); 523 524 if (pci_enable_device(pdev) < 0) 525 return -EIO; 526 527 return ie31200_probe1(pdev, ent->driver_data); 528 } 529 530 static void ie31200_remove_one(struct pci_dev *pdev) 531 { 532 struct mem_ctl_info *mci; 533 struct ie31200_priv *priv; 534 535 edac_dbg(0, "\n"); 536 mci = edac_mc_del_mc(&pdev->dev); 537 if (!mci) 538 return; 539 priv = mci->pvt_info; 540 iounmap(priv->window); 541 edac_mc_free(mci); 542 } 543 544 static const struct pci_device_id ie31200_pci_tbl[] = { 545 { 546 PCI_VEND_DEV(INTEL, IE31200_HB_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 547 IE31200}, 548 { 549 PCI_VEND_DEV(INTEL, IE31200_HB_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 550 IE31200}, 551 { 552 PCI_VEND_DEV(INTEL, IE31200_HB_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 553 IE31200}, 554 { 555 PCI_VEND_DEV(INTEL, IE31200_HB_4), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 556 IE31200}, 557 { 558 PCI_VEND_DEV(INTEL, IE31200_HB_5), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 559 IE31200}, 560 { 561 PCI_VEND_DEV(INTEL, IE31200_HB_6), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 562 IE31200}, 563 { 564 PCI_VEND_DEV(INTEL, IE31200_HB_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 565 IE31200}, 566 { 567 PCI_VEND_DEV(INTEL, IE31200_HB_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 568 IE31200}, 569 { 570 PCI_VEND_DEV(INTEL, IE31200_HB_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 571 IE31200}, 572 { 573 0, 574 } /* 0 terminated list. */ 575 }; 576 MODULE_DEVICE_TABLE(pci, ie31200_pci_tbl); 577 578 static struct pci_driver ie31200_driver = { 579 .name = EDAC_MOD_STR, 580 .probe = ie31200_init_one, 581 .remove = ie31200_remove_one, 582 .id_table = ie31200_pci_tbl, 583 }; 584 585 static int __init ie31200_init(void) 586 { 587 edac_dbg(3, "MC:\n"); 588 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 589 opstate_init(); 590 591 return pci_register_driver(&ie31200_driver); 592 } 593 594 static void __exit ie31200_exit(void) 595 { 596 edac_dbg(3, "MC:\n"); 597 pci_unregister_driver(&ie31200_driver); 598 } 599 600 module_init(ie31200_init); 601 module_exit(ie31200_exit); 602 603 MODULE_LICENSE("GPL"); 604 MODULE_AUTHOR("Jason Baron <jbaron@akamai.com>"); 605 MODULE_DESCRIPTION("MC support for Intel Processor E31200 memory hub controllers"); 606