1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Intel E3-1200 4 * Copyright (C) 2014 Jason Baron <jbaron@akamai.com> 5 * 6 * Support for the E3-1200 processor family. Heavily based on previous 7 * Intel EDAC drivers. 8 * 9 * Since the DRAM controller is on the cpu chip, we can use its PCI device 10 * id to identify these processors. 11 * 12 * PCI DRAM controller device ids (Taken from The PCI ID Repository - http://pci-ids.ucw.cz/) 13 * 14 * 0108: Xeon E3-1200 Processor Family DRAM Controller 15 * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller 16 * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller 17 * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller 18 * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller 19 * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller 20 * 0c08: Xeon E3-1200 v3 Processor DRAM Controller 21 * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers 22 * 5918: Xeon E3-1200 Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers 23 * 3e..: 8th/9th Gen Core Processor Host Bridge/DRAM Registers 24 * 25 * Based on Intel specification: 26 * http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf 27 * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html 28 * http://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html 29 * https://www.intel.com/content/www/us/en/products/docs/processors/core/8th-gen-core-family-datasheet-vol-2.html 30 * 31 * According to the above datasheet (p.16): 32 * " 33 * 6. Software must not access B0/D0/F0 32-bit memory-mapped registers with 34 * requests that cross a DW boundary. 35 * " 36 * 37 * Thus, we make use of the explicit: lo_hi_readq(), which breaks the readq into 38 * 2 readl() calls. This restriction may be lifted in subsequent chip releases, 39 * but lo_hi_readq() ensures that we are safe across all e3-1200 processors. 40 */ 41 42 #include <linux/module.h> 43 #include <linux/init.h> 44 #include <linux/pci.h> 45 #include <linux/pci_ids.h> 46 #include <linux/edac.h> 47 48 #include <linux/io-64-nonatomic-lo-hi.h> 49 #include "edac_module.h" 50 51 #define EDAC_MOD_STR "ie31200_edac" 52 53 #define ie31200_printk(level, fmt, arg...) \ 54 edac_printk(level, "ie31200", fmt, ##arg) 55 56 #define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108 57 #define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c 58 #define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150 59 #define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158 60 #define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c 61 #define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04 62 #define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08 63 #define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x1918 64 #define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x5918 65 66 /* Coffee Lake-S */ 67 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK 0x3e00 68 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_1 0x3e0f 69 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_2 0x3e18 70 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_3 0x3e1f 71 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_4 0x3e30 72 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_5 0x3e31 73 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_6 0x3e32 74 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_7 0x3e33 75 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_8 0x3ec2 76 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_9 0x3ec6 77 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_10 0x3eca 78 79 /* Test if HB is for Skylake or later. */ 80 #define DEVICE_ID_SKYLAKE_OR_LATER(did) \ 81 (((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_8) || \ 82 ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_9) || \ 83 (((did) & PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK) == \ 84 PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK)) 85 86 #define IE31200_DIMMS 4 87 #define IE31200_RANKS 8 88 #define IE31200_RANKS_PER_CHANNEL 4 89 #define IE31200_DIMMS_PER_CHANNEL 2 90 #define IE31200_CHANNELS 2 91 92 /* Intel IE31200 register addresses - device 0 function 0 - DRAM Controller */ 93 #define IE31200_MCHBAR_LOW 0x48 94 #define IE31200_MCHBAR_HIGH 0x4c 95 #define IE31200_MCHBAR_MASK GENMASK_ULL(38, 15) 96 #define IE31200_MMR_WINDOW_SIZE BIT(15) 97 98 /* 99 * Error Status Register (16b) 100 * 101 * 15 reserved 102 * 14 Isochronous TBWRR Run Behind FIFO Full 103 * (ITCV) 104 * 13 Isochronous TBWRR Run Behind FIFO Put 105 * (ITSTV) 106 * 12 reserved 107 * 11 MCH Thermal Sensor Event 108 * for SMI/SCI/SERR (GTSE) 109 * 10 reserved 110 * 9 LOCK to non-DRAM Memory Flag (LCKF) 111 * 8 reserved 112 * 7 DRAM Throttle Flag (DTF) 113 * 6:2 reserved 114 * 1 Multi-bit DRAM ECC Error Flag (DMERR) 115 * 0 Single-bit DRAM ECC Error Flag (DSERR) 116 */ 117 #define IE31200_ERRSTS 0xc8 118 #define IE31200_ERRSTS_UE BIT(1) 119 #define IE31200_ERRSTS_CE BIT(0) 120 #define IE31200_ERRSTS_BITS (IE31200_ERRSTS_UE | IE31200_ERRSTS_CE) 121 122 /* 123 * Channel 0 ECC Error Log (64b) 124 * 125 * 63:48 Error Column Address (ERRCOL) 126 * 47:32 Error Row Address (ERRROW) 127 * 31:29 Error Bank Address (ERRBANK) 128 * 28:27 Error Rank Address (ERRRANK) 129 * 26:24 reserved 130 * 23:16 Error Syndrome (ERRSYND) 131 * 15: 2 reserved 132 * 1 Multiple Bit Error Status (MERRSTS) 133 * 0 Correctable Error Status (CERRSTS) 134 */ 135 136 #define IE31200_C0ECCERRLOG 0x40c8 137 #define IE31200_C1ECCERRLOG 0x44c8 138 #define IE31200_C0ECCERRLOG_SKL 0x4048 139 #define IE31200_C1ECCERRLOG_SKL 0x4448 140 #define IE31200_ECCERRLOG_CE BIT(0) 141 #define IE31200_ECCERRLOG_UE BIT(1) 142 #define IE31200_ECCERRLOG_RANK_BITS GENMASK_ULL(28, 27) 143 #define IE31200_ECCERRLOG_RANK_SHIFT 27 144 #define IE31200_ECCERRLOG_SYNDROME_BITS GENMASK_ULL(23, 16) 145 #define IE31200_ECCERRLOG_SYNDROME_SHIFT 16 146 147 #define IE31200_ECCERRLOG_SYNDROME(log) \ 148 ((log & IE31200_ECCERRLOG_SYNDROME_BITS) >> \ 149 IE31200_ECCERRLOG_SYNDROME_SHIFT) 150 151 #define IE31200_CAPID0 0xe4 152 #define IE31200_CAPID0_PDCD BIT(4) 153 #define IE31200_CAPID0_DDPCD BIT(6) 154 #define IE31200_CAPID0_ECC BIT(1) 155 156 #define IE31200_MAD_DIMM_0_OFFSET 0x5004 157 #define IE31200_MAD_DIMM_0_OFFSET_SKL 0x500C 158 #define IE31200_MAD_DIMM_SIZE GENMASK_ULL(7, 0) 159 #define IE31200_MAD_DIMM_A_RANK BIT(17) 160 #define IE31200_MAD_DIMM_A_RANK_SHIFT 17 161 #define IE31200_MAD_DIMM_A_RANK_SKL BIT(10) 162 #define IE31200_MAD_DIMM_A_RANK_SKL_SHIFT 10 163 #define IE31200_MAD_DIMM_A_WIDTH BIT(19) 164 #define IE31200_MAD_DIMM_A_WIDTH_SHIFT 19 165 #define IE31200_MAD_DIMM_A_WIDTH_SKL GENMASK_ULL(9, 8) 166 #define IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT 8 167 168 /* Skylake reports 1GB increments, everything else is 256MB */ 169 #define IE31200_PAGES(n, skl) \ 170 (n << (28 + (2 * skl) - PAGE_SHIFT)) 171 172 static int nr_channels; 173 174 struct ie31200_priv { 175 void __iomem *window; 176 void __iomem *c0errlog; 177 void __iomem *c1errlog; 178 }; 179 180 enum ie31200_chips { 181 IE31200 = 0, 182 }; 183 184 struct ie31200_dev_info { 185 const char *ctl_name; 186 }; 187 188 struct ie31200_error_info { 189 u16 errsts; 190 u16 errsts2; 191 u64 eccerrlog[IE31200_CHANNELS]; 192 }; 193 194 static const struct ie31200_dev_info ie31200_devs[] = { 195 [IE31200] = { 196 .ctl_name = "IE31200" 197 }, 198 }; 199 200 struct dimm_data { 201 u8 size; /* in multiples of 256MB, except Skylake is 1GB */ 202 u8 dual_rank : 1, 203 x16_width : 2; /* 0 means x8 width */ 204 }; 205 206 static int how_many_channels(struct pci_dev *pdev) 207 { 208 int n_channels; 209 unsigned char capid0_2b; /* 2nd byte of CAPID0 */ 210 211 pci_read_config_byte(pdev, IE31200_CAPID0 + 1, &capid0_2b); 212 213 /* check PDCD: Dual Channel Disable */ 214 if (capid0_2b & IE31200_CAPID0_PDCD) { 215 edac_dbg(0, "In single channel mode\n"); 216 n_channels = 1; 217 } else { 218 edac_dbg(0, "In dual channel mode\n"); 219 n_channels = 2; 220 } 221 222 /* check DDPCD - check if both channels are filled */ 223 if (capid0_2b & IE31200_CAPID0_DDPCD) 224 edac_dbg(0, "2 DIMMS per channel disabled\n"); 225 else 226 edac_dbg(0, "2 DIMMS per channel enabled\n"); 227 228 return n_channels; 229 } 230 231 static bool ecc_capable(struct pci_dev *pdev) 232 { 233 unsigned char capid0_4b; /* 4th byte of CAPID0 */ 234 235 pci_read_config_byte(pdev, IE31200_CAPID0 + 3, &capid0_4b); 236 if (capid0_4b & IE31200_CAPID0_ECC) 237 return false; 238 return true; 239 } 240 241 static int eccerrlog_row(u64 log) 242 { 243 return ((log & IE31200_ECCERRLOG_RANK_BITS) >> 244 IE31200_ECCERRLOG_RANK_SHIFT); 245 } 246 247 static void ie31200_clear_error_info(struct mem_ctl_info *mci) 248 { 249 /* 250 * Clear any error bits. 251 * (Yes, we really clear bits by writing 1 to them.) 252 */ 253 pci_write_bits16(to_pci_dev(mci->pdev), IE31200_ERRSTS, 254 IE31200_ERRSTS_BITS, IE31200_ERRSTS_BITS); 255 } 256 257 static void ie31200_get_and_clear_error_info(struct mem_ctl_info *mci, 258 struct ie31200_error_info *info) 259 { 260 struct pci_dev *pdev; 261 struct ie31200_priv *priv = mci->pvt_info; 262 263 pdev = to_pci_dev(mci->pdev); 264 265 /* 266 * This is a mess because there is no atomic way to read all the 267 * registers at once and the registers can transition from CE being 268 * overwritten by UE. 269 */ 270 pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts); 271 if (!(info->errsts & IE31200_ERRSTS_BITS)) 272 return; 273 274 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog); 275 if (nr_channels == 2) 276 info->eccerrlog[1] = lo_hi_readq(priv->c1errlog); 277 278 pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts2); 279 280 /* 281 * If the error is the same for both reads then the first set 282 * of reads is valid. If there is a change then there is a CE 283 * with no info and the second set of reads is valid and 284 * should be UE info. 285 */ 286 if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) { 287 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog); 288 if (nr_channels == 2) 289 info->eccerrlog[1] = 290 lo_hi_readq(priv->c1errlog); 291 } 292 293 ie31200_clear_error_info(mci); 294 } 295 296 static void ie31200_process_error_info(struct mem_ctl_info *mci, 297 struct ie31200_error_info *info) 298 { 299 int channel; 300 u64 log; 301 302 if (!(info->errsts & IE31200_ERRSTS_BITS)) 303 return; 304 305 if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) { 306 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, 307 -1, -1, -1, "UE overwrote CE", ""); 308 info->errsts = info->errsts2; 309 } 310 311 for (channel = 0; channel < nr_channels; channel++) { 312 log = info->eccerrlog[channel]; 313 if (log & IE31200_ECCERRLOG_UE) { 314 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 315 0, 0, 0, 316 eccerrlog_row(log), 317 channel, -1, 318 "ie31200 UE", ""); 319 } else if (log & IE31200_ECCERRLOG_CE) { 320 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 321 0, 0, 322 IE31200_ECCERRLOG_SYNDROME(log), 323 eccerrlog_row(log), 324 channel, -1, 325 "ie31200 CE", ""); 326 } 327 } 328 } 329 330 static void ie31200_check(struct mem_ctl_info *mci) 331 { 332 struct ie31200_error_info info; 333 334 edac_dbg(1, "MC%d\n", mci->mc_idx); 335 ie31200_get_and_clear_error_info(mci, &info); 336 ie31200_process_error_info(mci, &info); 337 } 338 339 static void __iomem *ie31200_map_mchbar(struct pci_dev *pdev) 340 { 341 union { 342 u64 mchbar; 343 struct { 344 u32 mchbar_low; 345 u32 mchbar_high; 346 }; 347 } u; 348 void __iomem *window; 349 350 pci_read_config_dword(pdev, IE31200_MCHBAR_LOW, &u.mchbar_low); 351 pci_read_config_dword(pdev, IE31200_MCHBAR_HIGH, &u.mchbar_high); 352 u.mchbar &= IE31200_MCHBAR_MASK; 353 354 if (u.mchbar != (resource_size_t)u.mchbar) { 355 ie31200_printk(KERN_ERR, "mmio space beyond accessible range (0x%llx)\n", 356 (unsigned long long)u.mchbar); 357 return NULL; 358 } 359 360 window = ioremap(u.mchbar, IE31200_MMR_WINDOW_SIZE); 361 if (!window) 362 ie31200_printk(KERN_ERR, "Cannot map mmio space at 0x%llx\n", 363 (unsigned long long)u.mchbar); 364 365 return window; 366 } 367 368 static void __skl_populate_dimm_info(struct dimm_data *dd, u32 addr_decode, 369 int chan) 370 { 371 dd->size = (addr_decode >> (chan << 4)) & IE31200_MAD_DIMM_SIZE; 372 dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK_SKL << (chan << 4))) ? 1 : 0; 373 dd->x16_width = ((addr_decode & (IE31200_MAD_DIMM_A_WIDTH_SKL << (chan << 4))) >> 374 (IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT + (chan << 4))); 375 } 376 377 static void __populate_dimm_info(struct dimm_data *dd, u32 addr_decode, 378 int chan) 379 { 380 dd->size = (addr_decode >> (chan << 3)) & IE31200_MAD_DIMM_SIZE; 381 dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK << chan)) ? 1 : 0; 382 dd->x16_width = (addr_decode & (IE31200_MAD_DIMM_A_WIDTH << chan)) ? 1 : 0; 383 } 384 385 static void populate_dimm_info(struct dimm_data *dd, u32 addr_decode, int chan, 386 bool skl) 387 { 388 if (skl) 389 __skl_populate_dimm_info(dd, addr_decode, chan); 390 else 391 __populate_dimm_info(dd, addr_decode, chan); 392 } 393 394 395 static int ie31200_probe1(struct pci_dev *pdev, int dev_idx) 396 { 397 int i, j, ret; 398 struct mem_ctl_info *mci = NULL; 399 struct edac_mc_layer layers[2]; 400 struct dimm_data dimm_info[IE31200_CHANNELS][IE31200_DIMMS_PER_CHANNEL]; 401 void __iomem *window; 402 struct ie31200_priv *priv; 403 u32 addr_decode, mad_offset; 404 405 /* 406 * Kaby Lake, Coffee Lake seem to work like Skylake. Please re-visit 407 * this logic when adding new CPU support. 408 */ 409 bool skl = DEVICE_ID_SKYLAKE_OR_LATER(pdev->device); 410 411 edac_dbg(0, "MC:\n"); 412 413 if (!ecc_capable(pdev)) { 414 ie31200_printk(KERN_INFO, "No ECC support\n"); 415 return -ENODEV; 416 } 417 418 nr_channels = how_many_channels(pdev); 419 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 420 layers[0].size = IE31200_DIMMS; 421 layers[0].is_virt_csrow = true; 422 layers[1].type = EDAC_MC_LAYER_CHANNEL; 423 layers[1].size = nr_channels; 424 layers[1].is_virt_csrow = false; 425 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 426 sizeof(struct ie31200_priv)); 427 if (!mci) 428 return -ENOMEM; 429 430 window = ie31200_map_mchbar(pdev); 431 if (!window) { 432 ret = -ENODEV; 433 goto fail_free; 434 } 435 436 edac_dbg(3, "MC: init mci\n"); 437 mci->pdev = &pdev->dev; 438 if (skl) 439 mci->mtype_cap = MEM_FLAG_DDR4; 440 else 441 mci->mtype_cap = MEM_FLAG_DDR3; 442 mci->edac_ctl_cap = EDAC_FLAG_SECDED; 443 mci->edac_cap = EDAC_FLAG_SECDED; 444 mci->mod_name = EDAC_MOD_STR; 445 mci->ctl_name = ie31200_devs[dev_idx].ctl_name; 446 mci->dev_name = pci_name(pdev); 447 mci->edac_check = ie31200_check; 448 mci->ctl_page_to_phys = NULL; 449 priv = mci->pvt_info; 450 priv->window = window; 451 if (skl) { 452 priv->c0errlog = window + IE31200_C0ECCERRLOG_SKL; 453 priv->c1errlog = window + IE31200_C1ECCERRLOG_SKL; 454 mad_offset = IE31200_MAD_DIMM_0_OFFSET_SKL; 455 } else { 456 priv->c0errlog = window + IE31200_C0ECCERRLOG; 457 priv->c1errlog = window + IE31200_C1ECCERRLOG; 458 mad_offset = IE31200_MAD_DIMM_0_OFFSET; 459 } 460 461 /* populate DIMM info */ 462 for (i = 0; i < IE31200_CHANNELS; i++) { 463 addr_decode = readl(window + mad_offset + 464 (i * 4)); 465 edac_dbg(0, "addr_decode: 0x%x\n", addr_decode); 466 for (j = 0; j < IE31200_DIMMS_PER_CHANNEL; j++) { 467 populate_dimm_info(&dimm_info[i][j], addr_decode, j, 468 skl); 469 edac_dbg(0, "size: 0x%x, rank: %d, width: %d\n", 470 dimm_info[i][j].size, 471 dimm_info[i][j].dual_rank, 472 dimm_info[i][j].x16_width); 473 } 474 } 475 476 /* 477 * The dram rank boundary (DRB) reg values are boundary addresses 478 * for each DRAM rank with a granularity of 64MB. DRB regs are 479 * cumulative; the last one will contain the total memory 480 * contained in all ranks. 481 */ 482 for (i = 0; i < IE31200_DIMMS_PER_CHANNEL; i++) { 483 for (j = 0; j < IE31200_CHANNELS; j++) { 484 struct dimm_info *dimm; 485 unsigned long nr_pages; 486 487 nr_pages = IE31200_PAGES(dimm_info[j][i].size, skl); 488 if (nr_pages == 0) 489 continue; 490 491 if (dimm_info[j][i].dual_rank) { 492 nr_pages = nr_pages / 2; 493 dimm = edac_get_dimm(mci, (i * 2) + 1, j, 0); 494 dimm->nr_pages = nr_pages; 495 edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages); 496 dimm->grain = 8; /* just a guess */ 497 if (skl) 498 dimm->mtype = MEM_DDR4; 499 else 500 dimm->mtype = MEM_DDR3; 501 dimm->dtype = DEV_UNKNOWN; 502 dimm->edac_mode = EDAC_UNKNOWN; 503 } 504 dimm = edac_get_dimm(mci, i * 2, j, 0); 505 dimm->nr_pages = nr_pages; 506 edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages); 507 dimm->grain = 8; /* same guess */ 508 if (skl) 509 dimm->mtype = MEM_DDR4; 510 else 511 dimm->mtype = MEM_DDR3; 512 dimm->dtype = DEV_UNKNOWN; 513 dimm->edac_mode = EDAC_UNKNOWN; 514 } 515 } 516 517 ie31200_clear_error_info(mci); 518 519 if (edac_mc_add_mc(mci)) { 520 edac_dbg(3, "MC: failed edac_mc_add_mc()\n"); 521 ret = -ENODEV; 522 goto fail_unmap; 523 } 524 525 /* get this far and it's successful */ 526 edac_dbg(3, "MC: success\n"); 527 return 0; 528 529 fail_unmap: 530 iounmap(window); 531 532 fail_free: 533 edac_mc_free(mci); 534 535 return ret; 536 } 537 538 static int ie31200_init_one(struct pci_dev *pdev, 539 const struct pci_device_id *ent) 540 { 541 edac_dbg(0, "MC:\n"); 542 543 if (pci_enable_device(pdev) < 0) 544 return -EIO; 545 546 return ie31200_probe1(pdev, ent->driver_data); 547 } 548 549 static void ie31200_remove_one(struct pci_dev *pdev) 550 { 551 struct mem_ctl_info *mci; 552 struct ie31200_priv *priv; 553 554 edac_dbg(0, "\n"); 555 mci = edac_mc_del_mc(&pdev->dev); 556 if (!mci) 557 return; 558 priv = mci->pvt_info; 559 iounmap(priv->window); 560 edac_mc_free(mci); 561 } 562 563 static const struct pci_device_id ie31200_pci_tbl[] = { 564 { PCI_VEND_DEV(INTEL, IE31200_HB_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 565 { PCI_VEND_DEV(INTEL, IE31200_HB_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 566 { PCI_VEND_DEV(INTEL, IE31200_HB_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 567 { PCI_VEND_DEV(INTEL, IE31200_HB_4), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 568 { PCI_VEND_DEV(INTEL, IE31200_HB_5), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 569 { PCI_VEND_DEV(INTEL, IE31200_HB_6), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 570 { PCI_VEND_DEV(INTEL, IE31200_HB_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 571 { PCI_VEND_DEV(INTEL, IE31200_HB_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 572 { PCI_VEND_DEV(INTEL, IE31200_HB_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 573 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 574 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 575 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 576 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_4), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 577 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_5), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 578 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_6), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 579 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 580 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 581 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 582 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_10), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 583 { 0, } /* 0 terminated list. */ 584 }; 585 MODULE_DEVICE_TABLE(pci, ie31200_pci_tbl); 586 587 static struct pci_driver ie31200_driver = { 588 .name = EDAC_MOD_STR, 589 .probe = ie31200_init_one, 590 .remove = ie31200_remove_one, 591 .id_table = ie31200_pci_tbl, 592 }; 593 594 static int __init ie31200_init(void) 595 { 596 edac_dbg(3, "MC:\n"); 597 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 598 opstate_init(); 599 600 return pci_register_driver(&ie31200_driver); 601 } 602 603 static void __exit ie31200_exit(void) 604 { 605 edac_dbg(3, "MC:\n"); 606 pci_unregister_driver(&ie31200_driver); 607 } 608 609 module_init(ie31200_init); 610 module_exit(ie31200_exit); 611 612 MODULE_LICENSE("GPL"); 613 MODULE_AUTHOR("Jason Baron <jbaron@akamai.com>"); 614 MODULE_DESCRIPTION("MC support for Intel Processor E31200 memory hub controllers"); 615