1 /* 2 * Intel 5100 Memory Controllers kernel module 3 * 4 * This file may be distributed under the terms of the 5 * GNU General Public License. 6 * 7 * This module is based on the following document: 8 * 9 * Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet 10 * http://download.intel.com/design/chipsets/datashts/318378.pdf 11 * 12 * The intel 5100 has two independent channels. EDAC core currently 13 * can not reflect this configuration so instead the chip-select 14 * rows for each respective channel are laid out one after another, 15 * the first half belonging to channel 0, the second half belonging 16 * to channel 1. 17 * 18 * This driver is for DDR2 DIMMs, and it uses chip select to select among the 19 * several ranks. However, instead of showing memories as ranks, it outputs 20 * them as DIMM's. An internal table creates the association between ranks 21 * and DIMM's. 22 */ 23 #include <linux/module.h> 24 #include <linux/init.h> 25 #include <linux/pci.h> 26 #include <linux/pci_ids.h> 27 #include <linux/edac.h> 28 #include <linux/delay.h> 29 #include <linux/mmzone.h> 30 #include <linux/debugfs.h> 31 32 #include "edac_core.h" 33 #include "edac_module.h" 34 35 /* register addresses */ 36 37 /* device 16, func 1 */ 38 #define I5100_MC 0x40 /* Memory Control Register */ 39 #define I5100_MC_SCRBEN_MASK (1 << 7) 40 #define I5100_MC_SCRBDONE_MASK (1 << 4) 41 #define I5100_MS 0x44 /* Memory Status Register */ 42 #define I5100_SPDDATA 0x48 /* Serial Presence Detect Status Reg */ 43 #define I5100_SPDCMD 0x4c /* Serial Presence Detect Command Reg */ 44 #define I5100_TOLM 0x6c /* Top of Low Memory */ 45 #define I5100_MIR0 0x80 /* Memory Interleave Range 0 */ 46 #define I5100_MIR1 0x84 /* Memory Interleave Range 1 */ 47 #define I5100_AMIR_0 0x8c /* Adjusted Memory Interleave Range 0 */ 48 #define I5100_AMIR_1 0x90 /* Adjusted Memory Interleave Range 1 */ 49 #define I5100_FERR_NF_MEM 0xa0 /* MC First Non Fatal Errors */ 50 #define I5100_FERR_NF_MEM_M16ERR_MASK (1 << 16) 51 #define I5100_FERR_NF_MEM_M15ERR_MASK (1 << 15) 52 #define I5100_FERR_NF_MEM_M14ERR_MASK (1 << 14) 53 #define I5100_FERR_NF_MEM_M12ERR_MASK (1 << 12) 54 #define I5100_FERR_NF_MEM_M11ERR_MASK (1 << 11) 55 #define I5100_FERR_NF_MEM_M10ERR_MASK (1 << 10) 56 #define I5100_FERR_NF_MEM_M6ERR_MASK (1 << 6) 57 #define I5100_FERR_NF_MEM_M5ERR_MASK (1 << 5) 58 #define I5100_FERR_NF_MEM_M4ERR_MASK (1 << 4) 59 #define I5100_FERR_NF_MEM_M1ERR_MASK (1 << 1) 60 #define I5100_FERR_NF_MEM_ANY_MASK \ 61 (I5100_FERR_NF_MEM_M16ERR_MASK | \ 62 I5100_FERR_NF_MEM_M15ERR_MASK | \ 63 I5100_FERR_NF_MEM_M14ERR_MASK | \ 64 I5100_FERR_NF_MEM_M12ERR_MASK | \ 65 I5100_FERR_NF_MEM_M11ERR_MASK | \ 66 I5100_FERR_NF_MEM_M10ERR_MASK | \ 67 I5100_FERR_NF_MEM_M6ERR_MASK | \ 68 I5100_FERR_NF_MEM_M5ERR_MASK | \ 69 I5100_FERR_NF_MEM_M4ERR_MASK | \ 70 I5100_FERR_NF_MEM_M1ERR_MASK) 71 #define I5100_NERR_NF_MEM 0xa4 /* MC Next Non-Fatal Errors */ 72 #define I5100_EMASK_MEM 0xa8 /* MC Error Mask Register */ 73 #define I5100_MEM0EINJMSK0 0x200 /* Injection Mask0 Register Channel 0 */ 74 #define I5100_MEM1EINJMSK0 0x208 /* Injection Mask0 Register Channel 1 */ 75 #define I5100_MEMXEINJMSK0_EINJEN (1 << 27) 76 #define I5100_MEM0EINJMSK1 0x204 /* Injection Mask1 Register Channel 0 */ 77 #define I5100_MEM1EINJMSK1 0x206 /* Injection Mask1 Register Channel 1 */ 78 79 /* Device 19, Function 0 */ 80 #define I5100_DINJ0 0x9a 81 82 /* device 21 and 22, func 0 */ 83 #define I5100_MTR_0 0x154 /* Memory Technology Registers 0-3 */ 84 #define I5100_DMIR 0x15c /* DIMM Interleave Range */ 85 #define I5100_VALIDLOG 0x18c /* Valid Log Markers */ 86 #define I5100_NRECMEMA 0x190 /* Non-Recoverable Memory Error Log Reg A */ 87 #define I5100_NRECMEMB 0x194 /* Non-Recoverable Memory Error Log Reg B */ 88 #define I5100_REDMEMA 0x198 /* Recoverable Memory Data Error Log Reg A */ 89 #define I5100_REDMEMB 0x19c /* Recoverable Memory Data Error Log Reg B */ 90 #define I5100_RECMEMA 0x1a0 /* Recoverable Memory Error Log Reg A */ 91 #define I5100_RECMEMB 0x1a4 /* Recoverable Memory Error Log Reg B */ 92 #define I5100_MTR_4 0x1b0 /* Memory Technology Registers 4,5 */ 93 94 /* bit field accessors */ 95 96 static inline u32 i5100_mc_scrben(u32 mc) 97 { 98 return mc >> 7 & 1; 99 } 100 101 static inline u32 i5100_mc_errdeten(u32 mc) 102 { 103 return mc >> 5 & 1; 104 } 105 106 static inline u32 i5100_mc_scrbdone(u32 mc) 107 { 108 return mc >> 4 & 1; 109 } 110 111 static inline u16 i5100_spddata_rdo(u16 a) 112 { 113 return a >> 15 & 1; 114 } 115 116 static inline u16 i5100_spddata_sbe(u16 a) 117 { 118 return a >> 13 & 1; 119 } 120 121 static inline u16 i5100_spddata_busy(u16 a) 122 { 123 return a >> 12 & 1; 124 } 125 126 static inline u16 i5100_spddata_data(u16 a) 127 { 128 return a & ((1 << 8) - 1); 129 } 130 131 static inline u32 i5100_spdcmd_create(u32 dti, u32 ckovrd, u32 sa, u32 ba, 132 u32 data, u32 cmd) 133 { 134 return ((dti & ((1 << 4) - 1)) << 28) | 135 ((ckovrd & 1) << 27) | 136 ((sa & ((1 << 3) - 1)) << 24) | 137 ((ba & ((1 << 8) - 1)) << 16) | 138 ((data & ((1 << 8) - 1)) << 8) | 139 (cmd & 1); 140 } 141 142 static inline u16 i5100_tolm_tolm(u16 a) 143 { 144 return a >> 12 & ((1 << 4) - 1); 145 } 146 147 static inline u16 i5100_mir_limit(u16 a) 148 { 149 return a >> 4 & ((1 << 12) - 1); 150 } 151 152 static inline u16 i5100_mir_way1(u16 a) 153 { 154 return a >> 1 & 1; 155 } 156 157 static inline u16 i5100_mir_way0(u16 a) 158 { 159 return a & 1; 160 } 161 162 static inline u32 i5100_ferr_nf_mem_chan_indx(u32 a) 163 { 164 return a >> 28 & 1; 165 } 166 167 static inline u32 i5100_ferr_nf_mem_any(u32 a) 168 { 169 return a & I5100_FERR_NF_MEM_ANY_MASK; 170 } 171 172 static inline u32 i5100_nerr_nf_mem_any(u32 a) 173 { 174 return i5100_ferr_nf_mem_any(a); 175 } 176 177 static inline u32 i5100_dmir_limit(u32 a) 178 { 179 return a >> 16 & ((1 << 11) - 1); 180 } 181 182 static inline u32 i5100_dmir_rank(u32 a, u32 i) 183 { 184 return a >> (4 * i) & ((1 << 2) - 1); 185 } 186 187 static inline u16 i5100_mtr_present(u16 a) 188 { 189 return a >> 10 & 1; 190 } 191 192 static inline u16 i5100_mtr_ethrottle(u16 a) 193 { 194 return a >> 9 & 1; 195 } 196 197 static inline u16 i5100_mtr_width(u16 a) 198 { 199 return a >> 8 & 1; 200 } 201 202 static inline u16 i5100_mtr_numbank(u16 a) 203 { 204 return a >> 6 & 1; 205 } 206 207 static inline u16 i5100_mtr_numrow(u16 a) 208 { 209 return a >> 2 & ((1 << 2) - 1); 210 } 211 212 static inline u16 i5100_mtr_numcol(u16 a) 213 { 214 return a & ((1 << 2) - 1); 215 } 216 217 218 static inline u32 i5100_validlog_redmemvalid(u32 a) 219 { 220 return a >> 2 & 1; 221 } 222 223 static inline u32 i5100_validlog_recmemvalid(u32 a) 224 { 225 return a >> 1 & 1; 226 } 227 228 static inline u32 i5100_validlog_nrecmemvalid(u32 a) 229 { 230 return a & 1; 231 } 232 233 static inline u32 i5100_nrecmema_merr(u32 a) 234 { 235 return a >> 15 & ((1 << 5) - 1); 236 } 237 238 static inline u32 i5100_nrecmema_bank(u32 a) 239 { 240 return a >> 12 & ((1 << 3) - 1); 241 } 242 243 static inline u32 i5100_nrecmema_rank(u32 a) 244 { 245 return a >> 8 & ((1 << 3) - 1); 246 } 247 248 static inline u32 i5100_nrecmema_dm_buf_id(u32 a) 249 { 250 return a & ((1 << 8) - 1); 251 } 252 253 static inline u32 i5100_nrecmemb_cas(u32 a) 254 { 255 return a >> 16 & ((1 << 13) - 1); 256 } 257 258 static inline u32 i5100_nrecmemb_ras(u32 a) 259 { 260 return a & ((1 << 16) - 1); 261 } 262 263 static inline u32 i5100_redmemb_ecc_locator(u32 a) 264 { 265 return a & ((1 << 18) - 1); 266 } 267 268 static inline u32 i5100_recmema_merr(u32 a) 269 { 270 return i5100_nrecmema_merr(a); 271 } 272 273 static inline u32 i5100_recmema_bank(u32 a) 274 { 275 return i5100_nrecmema_bank(a); 276 } 277 278 static inline u32 i5100_recmema_rank(u32 a) 279 { 280 return i5100_nrecmema_rank(a); 281 } 282 283 static inline u32 i5100_recmemb_cas(u32 a) 284 { 285 return i5100_nrecmemb_cas(a); 286 } 287 288 static inline u32 i5100_recmemb_ras(u32 a) 289 { 290 return i5100_nrecmemb_ras(a); 291 } 292 293 /* some generic limits */ 294 #define I5100_MAX_RANKS_PER_CHAN 6 295 #define I5100_CHANNELS 2 296 #define I5100_MAX_RANKS_PER_DIMM 4 297 #define I5100_DIMM_ADDR_LINES (6 - 3) /* 64 bits / 8 bits per byte */ 298 #define I5100_MAX_DIMM_SLOTS_PER_CHAN 4 299 #define I5100_MAX_RANK_INTERLEAVE 4 300 #define I5100_MAX_DMIRS 5 301 #define I5100_SCRUB_REFRESH_RATE (5 * 60 * HZ) 302 303 struct i5100_priv { 304 /* ranks on each dimm -- 0 maps to not present -- obtained via SPD */ 305 int dimm_numrank[I5100_CHANNELS][I5100_MAX_DIMM_SLOTS_PER_CHAN]; 306 307 /* 308 * mainboard chip select map -- maps i5100 chip selects to 309 * DIMM slot chip selects. In the case of only 4 ranks per 310 * channel, the mapping is fairly obvious but not unique. 311 * we map -1 -> NC and assume both channels use the same 312 * map... 313 * 314 */ 315 int dimm_csmap[I5100_MAX_DIMM_SLOTS_PER_CHAN][I5100_MAX_RANKS_PER_DIMM]; 316 317 /* memory interleave range */ 318 struct { 319 u64 limit; 320 unsigned way[2]; 321 } mir[I5100_CHANNELS]; 322 323 /* adjusted memory interleave range register */ 324 unsigned amir[I5100_CHANNELS]; 325 326 /* dimm interleave range */ 327 struct { 328 unsigned rank[I5100_MAX_RANK_INTERLEAVE]; 329 u64 limit; 330 } dmir[I5100_CHANNELS][I5100_MAX_DMIRS]; 331 332 /* memory technology registers... */ 333 struct { 334 unsigned present; /* 0 or 1 */ 335 unsigned ethrottle; /* 0 or 1 */ 336 unsigned width; /* 4 or 8 bits */ 337 unsigned numbank; /* 2 or 3 lines */ 338 unsigned numrow; /* 13 .. 16 lines */ 339 unsigned numcol; /* 11 .. 12 lines */ 340 } mtr[I5100_CHANNELS][I5100_MAX_RANKS_PER_CHAN]; 341 342 u64 tolm; /* top of low memory in bytes */ 343 unsigned ranksperchan; /* number of ranks per channel */ 344 345 struct pci_dev *mc; /* device 16 func 1 */ 346 struct pci_dev *einj; /* device 19 func 0 */ 347 struct pci_dev *ch0mm; /* device 21 func 0 */ 348 struct pci_dev *ch1mm; /* device 22 func 0 */ 349 350 struct delayed_work i5100_scrubbing; 351 int scrub_enable; 352 353 /* Error injection */ 354 u8 inject_channel; 355 u8 inject_hlinesel; 356 u8 inject_deviceptr1; 357 u8 inject_deviceptr2; 358 u16 inject_eccmask1; 359 u16 inject_eccmask2; 360 361 struct dentry *debugfs; 362 }; 363 364 static struct dentry *i5100_debugfs; 365 366 /* map a rank/chan to a slot number on the mainboard */ 367 static int i5100_rank_to_slot(const struct mem_ctl_info *mci, 368 int chan, int rank) 369 { 370 const struct i5100_priv *priv = mci->pvt_info; 371 int i; 372 373 for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) { 374 int j; 375 const int numrank = priv->dimm_numrank[chan][i]; 376 377 for (j = 0; j < numrank; j++) 378 if (priv->dimm_csmap[i][j] == rank) 379 return i * 2 + chan; 380 } 381 382 return -1; 383 } 384 385 static const char *i5100_err_msg(unsigned err) 386 { 387 static const char *merrs[] = { 388 "unknown", /* 0 */ 389 "uncorrectable data ECC on replay", /* 1 */ 390 "unknown", /* 2 */ 391 "unknown", /* 3 */ 392 "aliased uncorrectable demand data ECC", /* 4 */ 393 "aliased uncorrectable spare-copy data ECC", /* 5 */ 394 "aliased uncorrectable patrol data ECC", /* 6 */ 395 "unknown", /* 7 */ 396 "unknown", /* 8 */ 397 "unknown", /* 9 */ 398 "non-aliased uncorrectable demand data ECC", /* 10 */ 399 "non-aliased uncorrectable spare-copy data ECC", /* 11 */ 400 "non-aliased uncorrectable patrol data ECC", /* 12 */ 401 "unknown", /* 13 */ 402 "correctable demand data ECC", /* 14 */ 403 "correctable spare-copy data ECC", /* 15 */ 404 "correctable patrol data ECC", /* 16 */ 405 "unknown", /* 17 */ 406 "SPD protocol error", /* 18 */ 407 "unknown", /* 19 */ 408 "spare copy initiated", /* 20 */ 409 "spare copy completed", /* 21 */ 410 }; 411 unsigned i; 412 413 for (i = 0; i < ARRAY_SIZE(merrs); i++) 414 if (1 << i & err) 415 return merrs[i]; 416 417 return "none"; 418 } 419 420 /* convert csrow index into a rank (per channel -- 0..5) */ 421 static int i5100_csrow_to_rank(const struct mem_ctl_info *mci, int csrow) 422 { 423 const struct i5100_priv *priv = mci->pvt_info; 424 425 return csrow % priv->ranksperchan; 426 } 427 428 /* convert csrow index into a channel (0..1) */ 429 static int i5100_csrow_to_chan(const struct mem_ctl_info *mci, int csrow) 430 { 431 const struct i5100_priv *priv = mci->pvt_info; 432 433 return csrow / priv->ranksperchan; 434 } 435 436 static void i5100_handle_ce(struct mem_ctl_info *mci, 437 int chan, 438 unsigned bank, 439 unsigned rank, 440 unsigned long syndrome, 441 unsigned cas, 442 unsigned ras, 443 const char *msg) 444 { 445 char detail[80]; 446 447 /* Form out message */ 448 snprintf(detail, sizeof(detail), 449 "bank %u, cas %u, ras %u\n", 450 bank, cas, ras); 451 452 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 453 0, 0, syndrome, 454 chan, rank, -1, 455 msg, detail); 456 } 457 458 static void i5100_handle_ue(struct mem_ctl_info *mci, 459 int chan, 460 unsigned bank, 461 unsigned rank, 462 unsigned long syndrome, 463 unsigned cas, 464 unsigned ras, 465 const char *msg) 466 { 467 char detail[80]; 468 469 /* Form out message */ 470 snprintf(detail, sizeof(detail), 471 "bank %u, cas %u, ras %u\n", 472 bank, cas, ras); 473 474 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 475 0, 0, syndrome, 476 chan, rank, -1, 477 msg, detail); 478 } 479 480 static void i5100_read_log(struct mem_ctl_info *mci, int chan, 481 u32 ferr, u32 nerr) 482 { 483 struct i5100_priv *priv = mci->pvt_info; 484 struct pci_dev *pdev = (chan) ? priv->ch1mm : priv->ch0mm; 485 u32 dw; 486 u32 dw2; 487 unsigned syndrome = 0; 488 unsigned ecc_loc = 0; 489 unsigned merr; 490 unsigned bank; 491 unsigned rank; 492 unsigned cas; 493 unsigned ras; 494 495 pci_read_config_dword(pdev, I5100_VALIDLOG, &dw); 496 497 if (i5100_validlog_redmemvalid(dw)) { 498 pci_read_config_dword(pdev, I5100_REDMEMA, &dw2); 499 syndrome = dw2; 500 pci_read_config_dword(pdev, I5100_REDMEMB, &dw2); 501 ecc_loc = i5100_redmemb_ecc_locator(dw2); 502 } 503 504 if (i5100_validlog_recmemvalid(dw)) { 505 const char *msg; 506 507 pci_read_config_dword(pdev, I5100_RECMEMA, &dw2); 508 merr = i5100_recmema_merr(dw2); 509 bank = i5100_recmema_bank(dw2); 510 rank = i5100_recmema_rank(dw2); 511 512 pci_read_config_dword(pdev, I5100_RECMEMB, &dw2); 513 cas = i5100_recmemb_cas(dw2); 514 ras = i5100_recmemb_ras(dw2); 515 516 /* FIXME: not really sure if this is what merr is... 517 */ 518 if (!merr) 519 msg = i5100_err_msg(ferr); 520 else 521 msg = i5100_err_msg(nerr); 522 523 i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg); 524 } 525 526 if (i5100_validlog_nrecmemvalid(dw)) { 527 const char *msg; 528 529 pci_read_config_dword(pdev, I5100_NRECMEMA, &dw2); 530 merr = i5100_nrecmema_merr(dw2); 531 bank = i5100_nrecmema_bank(dw2); 532 rank = i5100_nrecmema_rank(dw2); 533 534 pci_read_config_dword(pdev, I5100_NRECMEMB, &dw2); 535 cas = i5100_nrecmemb_cas(dw2); 536 ras = i5100_nrecmemb_ras(dw2); 537 538 /* FIXME: not really sure if this is what merr is... 539 */ 540 if (!merr) 541 msg = i5100_err_msg(ferr); 542 else 543 msg = i5100_err_msg(nerr); 544 545 i5100_handle_ue(mci, chan, bank, rank, syndrome, cas, ras, msg); 546 } 547 548 pci_write_config_dword(pdev, I5100_VALIDLOG, dw); 549 } 550 551 static void i5100_check_error(struct mem_ctl_info *mci) 552 { 553 struct i5100_priv *priv = mci->pvt_info; 554 u32 dw, dw2; 555 556 pci_read_config_dword(priv->mc, I5100_FERR_NF_MEM, &dw); 557 if (i5100_ferr_nf_mem_any(dw)) { 558 559 pci_read_config_dword(priv->mc, I5100_NERR_NF_MEM, &dw2); 560 561 i5100_read_log(mci, i5100_ferr_nf_mem_chan_indx(dw), 562 i5100_ferr_nf_mem_any(dw), 563 i5100_nerr_nf_mem_any(dw2)); 564 565 pci_write_config_dword(priv->mc, I5100_NERR_NF_MEM, dw2); 566 } 567 pci_write_config_dword(priv->mc, I5100_FERR_NF_MEM, dw); 568 } 569 570 /* The i5100 chipset will scrub the entire memory once, then 571 * set a done bit. Continuous scrubbing is achieved by enqueing 572 * delayed work to a workqueue, checking every few minutes if 573 * the scrubbing has completed and if so reinitiating it. 574 */ 575 576 static void i5100_refresh_scrubbing(struct work_struct *work) 577 { 578 struct delayed_work *i5100_scrubbing = to_delayed_work(work); 579 struct i5100_priv *priv = container_of(i5100_scrubbing, 580 struct i5100_priv, 581 i5100_scrubbing); 582 u32 dw; 583 584 pci_read_config_dword(priv->mc, I5100_MC, &dw); 585 586 if (priv->scrub_enable) { 587 588 pci_read_config_dword(priv->mc, I5100_MC, &dw); 589 590 if (i5100_mc_scrbdone(dw)) { 591 dw |= I5100_MC_SCRBEN_MASK; 592 pci_write_config_dword(priv->mc, I5100_MC, dw); 593 pci_read_config_dword(priv->mc, I5100_MC, &dw); 594 } 595 596 schedule_delayed_work(&(priv->i5100_scrubbing), 597 I5100_SCRUB_REFRESH_RATE); 598 } 599 } 600 /* 601 * The bandwidth is based on experimentation, feel free to refine it. 602 */ 603 static int i5100_set_scrub_rate(struct mem_ctl_info *mci, u32 bandwidth) 604 { 605 struct i5100_priv *priv = mci->pvt_info; 606 u32 dw; 607 608 pci_read_config_dword(priv->mc, I5100_MC, &dw); 609 if (bandwidth) { 610 priv->scrub_enable = 1; 611 dw |= I5100_MC_SCRBEN_MASK; 612 schedule_delayed_work(&(priv->i5100_scrubbing), 613 I5100_SCRUB_REFRESH_RATE); 614 } else { 615 priv->scrub_enable = 0; 616 dw &= ~I5100_MC_SCRBEN_MASK; 617 cancel_delayed_work(&(priv->i5100_scrubbing)); 618 } 619 pci_write_config_dword(priv->mc, I5100_MC, dw); 620 621 pci_read_config_dword(priv->mc, I5100_MC, &dw); 622 623 bandwidth = 5900000 * i5100_mc_scrben(dw); 624 625 return bandwidth; 626 } 627 628 static int i5100_get_scrub_rate(struct mem_ctl_info *mci) 629 { 630 struct i5100_priv *priv = mci->pvt_info; 631 u32 dw; 632 633 pci_read_config_dword(priv->mc, I5100_MC, &dw); 634 635 return 5900000 * i5100_mc_scrben(dw); 636 } 637 638 static struct pci_dev *pci_get_device_func(unsigned vendor, 639 unsigned device, 640 unsigned func) 641 { 642 struct pci_dev *ret = NULL; 643 644 while (1) { 645 ret = pci_get_device(vendor, device, ret); 646 647 if (!ret) 648 break; 649 650 if (PCI_FUNC(ret->devfn) == func) 651 break; 652 } 653 654 return ret; 655 } 656 657 static unsigned long i5100_npages(struct mem_ctl_info *mci, int csrow) 658 { 659 struct i5100_priv *priv = mci->pvt_info; 660 const unsigned chan_rank = i5100_csrow_to_rank(mci, csrow); 661 const unsigned chan = i5100_csrow_to_chan(mci, csrow); 662 unsigned addr_lines; 663 664 /* dimm present? */ 665 if (!priv->mtr[chan][chan_rank].present) 666 return 0ULL; 667 668 addr_lines = 669 I5100_DIMM_ADDR_LINES + 670 priv->mtr[chan][chan_rank].numcol + 671 priv->mtr[chan][chan_rank].numrow + 672 priv->mtr[chan][chan_rank].numbank; 673 674 return (unsigned long) 675 ((unsigned long long) (1ULL << addr_lines) / PAGE_SIZE); 676 } 677 678 static void i5100_init_mtr(struct mem_ctl_info *mci) 679 { 680 struct i5100_priv *priv = mci->pvt_info; 681 struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm }; 682 int i; 683 684 for (i = 0; i < I5100_CHANNELS; i++) { 685 int j; 686 struct pci_dev *pdev = mms[i]; 687 688 for (j = 0; j < I5100_MAX_RANKS_PER_CHAN; j++) { 689 const unsigned addr = 690 (j < 4) ? I5100_MTR_0 + j * 2 : 691 I5100_MTR_4 + (j - 4) * 2; 692 u16 w; 693 694 pci_read_config_word(pdev, addr, &w); 695 696 priv->mtr[i][j].present = i5100_mtr_present(w); 697 priv->mtr[i][j].ethrottle = i5100_mtr_ethrottle(w); 698 priv->mtr[i][j].width = 4 + 4 * i5100_mtr_width(w); 699 priv->mtr[i][j].numbank = 2 + i5100_mtr_numbank(w); 700 priv->mtr[i][j].numrow = 13 + i5100_mtr_numrow(w); 701 priv->mtr[i][j].numcol = 10 + i5100_mtr_numcol(w); 702 } 703 } 704 } 705 706 /* 707 * FIXME: make this into a real i2c adapter (so that dimm-decode 708 * will work)? 709 */ 710 static int i5100_read_spd_byte(const struct mem_ctl_info *mci, 711 u8 ch, u8 slot, u8 addr, u8 *byte) 712 { 713 struct i5100_priv *priv = mci->pvt_info; 714 u16 w; 715 unsigned long et; 716 717 pci_read_config_word(priv->mc, I5100_SPDDATA, &w); 718 if (i5100_spddata_busy(w)) 719 return -1; 720 721 pci_write_config_dword(priv->mc, I5100_SPDCMD, 722 i5100_spdcmd_create(0xa, 1, ch * 4 + slot, addr, 723 0, 0)); 724 725 /* wait up to 100ms */ 726 et = jiffies + HZ / 10; 727 udelay(100); 728 while (1) { 729 pci_read_config_word(priv->mc, I5100_SPDDATA, &w); 730 if (!i5100_spddata_busy(w)) 731 break; 732 udelay(100); 733 } 734 735 if (!i5100_spddata_rdo(w) || i5100_spddata_sbe(w)) 736 return -1; 737 738 *byte = i5100_spddata_data(w); 739 740 return 0; 741 } 742 743 /* 744 * fill dimm chip select map 745 * 746 * FIXME: 747 * o not the only way to may chip selects to dimm slots 748 * o investigate if there is some way to obtain this map from the bios 749 */ 750 static void i5100_init_dimm_csmap(struct mem_ctl_info *mci) 751 { 752 struct i5100_priv *priv = mci->pvt_info; 753 int i; 754 755 for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) { 756 int j; 757 758 for (j = 0; j < I5100_MAX_RANKS_PER_DIMM; j++) 759 priv->dimm_csmap[i][j] = -1; /* default NC */ 760 } 761 762 /* only 2 chip selects per slot... */ 763 if (priv->ranksperchan == 4) { 764 priv->dimm_csmap[0][0] = 0; 765 priv->dimm_csmap[0][1] = 3; 766 priv->dimm_csmap[1][0] = 1; 767 priv->dimm_csmap[1][1] = 2; 768 priv->dimm_csmap[2][0] = 2; 769 priv->dimm_csmap[3][0] = 3; 770 } else { 771 priv->dimm_csmap[0][0] = 0; 772 priv->dimm_csmap[0][1] = 1; 773 priv->dimm_csmap[1][0] = 2; 774 priv->dimm_csmap[1][1] = 3; 775 priv->dimm_csmap[2][0] = 4; 776 priv->dimm_csmap[2][1] = 5; 777 } 778 } 779 780 static void i5100_init_dimm_layout(struct pci_dev *pdev, 781 struct mem_ctl_info *mci) 782 { 783 struct i5100_priv *priv = mci->pvt_info; 784 int i; 785 786 for (i = 0; i < I5100_CHANNELS; i++) { 787 int j; 788 789 for (j = 0; j < I5100_MAX_DIMM_SLOTS_PER_CHAN; j++) { 790 u8 rank; 791 792 if (i5100_read_spd_byte(mci, i, j, 5, &rank) < 0) 793 priv->dimm_numrank[i][j] = 0; 794 else 795 priv->dimm_numrank[i][j] = (rank & 3) + 1; 796 } 797 } 798 799 i5100_init_dimm_csmap(mci); 800 } 801 802 static void i5100_init_interleaving(struct pci_dev *pdev, 803 struct mem_ctl_info *mci) 804 { 805 u16 w; 806 u32 dw; 807 struct i5100_priv *priv = mci->pvt_info; 808 struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm }; 809 int i; 810 811 pci_read_config_word(pdev, I5100_TOLM, &w); 812 priv->tolm = (u64) i5100_tolm_tolm(w) * 256 * 1024 * 1024; 813 814 pci_read_config_word(pdev, I5100_MIR0, &w); 815 priv->mir[0].limit = (u64) i5100_mir_limit(w) << 28; 816 priv->mir[0].way[1] = i5100_mir_way1(w); 817 priv->mir[0].way[0] = i5100_mir_way0(w); 818 819 pci_read_config_word(pdev, I5100_MIR1, &w); 820 priv->mir[1].limit = (u64) i5100_mir_limit(w) << 28; 821 priv->mir[1].way[1] = i5100_mir_way1(w); 822 priv->mir[1].way[0] = i5100_mir_way0(w); 823 824 pci_read_config_word(pdev, I5100_AMIR_0, &w); 825 priv->amir[0] = w; 826 pci_read_config_word(pdev, I5100_AMIR_1, &w); 827 priv->amir[1] = w; 828 829 for (i = 0; i < I5100_CHANNELS; i++) { 830 int j; 831 832 for (j = 0; j < 5; j++) { 833 int k; 834 835 pci_read_config_dword(mms[i], I5100_DMIR + j * 4, &dw); 836 837 priv->dmir[i][j].limit = 838 (u64) i5100_dmir_limit(dw) << 28; 839 for (k = 0; k < I5100_MAX_RANKS_PER_DIMM; k++) 840 priv->dmir[i][j].rank[k] = 841 i5100_dmir_rank(dw, k); 842 } 843 } 844 845 i5100_init_mtr(mci); 846 } 847 848 static void i5100_init_csrows(struct mem_ctl_info *mci) 849 { 850 int i; 851 struct i5100_priv *priv = mci->pvt_info; 852 853 for (i = 0; i < mci->tot_dimms; i++) { 854 struct dimm_info *dimm; 855 const unsigned long npages = i5100_npages(mci, i); 856 const unsigned chan = i5100_csrow_to_chan(mci, i); 857 const unsigned rank = i5100_csrow_to_rank(mci, i); 858 859 if (!npages) 860 continue; 861 862 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, 863 chan, rank, 0); 864 865 dimm->nr_pages = npages; 866 dimm->grain = 32; 867 dimm->dtype = (priv->mtr[chan][rank].width == 4) ? 868 DEV_X4 : DEV_X8; 869 dimm->mtype = MEM_RDDR2; 870 dimm->edac_mode = EDAC_SECDED; 871 snprintf(dimm->label, sizeof(dimm->label), "DIMM%u", 872 i5100_rank_to_slot(mci, chan, rank)); 873 874 edac_dbg(2, "dimm channel %d, rank %d, size %ld\n", 875 chan, rank, (long)PAGES_TO_MiB(npages)); 876 } 877 } 878 879 /**************************************************************************** 880 * Error injection routines 881 ****************************************************************************/ 882 883 static void i5100_do_inject(struct mem_ctl_info *mci) 884 { 885 struct i5100_priv *priv = mci->pvt_info; 886 u32 mask0; 887 u16 mask1; 888 889 /* MEM[1:0]EINJMSK0 890 * 31 - ADDRMATCHEN 891 * 29:28 - HLINESEL 892 * 00 Reserved 893 * 01 Lower half of cache line 894 * 10 Upper half of cache line 895 * 11 Both upper and lower parts of cache line 896 * 27 - EINJEN 897 * 25:19 - XORMASK1 for deviceptr1 898 * 9:5 - SEC2RAM for deviceptr2 899 * 4:0 - FIR2RAM for deviceptr1 900 */ 901 mask0 = ((priv->inject_hlinesel & 0x3) << 28) | 902 I5100_MEMXEINJMSK0_EINJEN | 903 ((priv->inject_eccmask1 & 0xffff) << 10) | 904 ((priv->inject_deviceptr2 & 0x1f) << 5) | 905 (priv->inject_deviceptr1 & 0x1f); 906 907 /* MEM[1:0]EINJMSK1 908 * 15:0 - XORMASK2 for deviceptr2 909 */ 910 mask1 = priv->inject_eccmask2; 911 912 if (priv->inject_channel == 0) { 913 pci_write_config_dword(priv->mc, I5100_MEM0EINJMSK0, mask0); 914 pci_write_config_word(priv->mc, I5100_MEM0EINJMSK1, mask1); 915 } else { 916 pci_write_config_dword(priv->mc, I5100_MEM1EINJMSK0, mask0); 917 pci_write_config_word(priv->mc, I5100_MEM1EINJMSK1, mask1); 918 } 919 920 /* Error Injection Response Function 921 * Intel 5100 Memory Controller Hub Chipset (318378) datasheet 922 * hints about this register but carry no data about them. All 923 * data regarding device 19 is based on experimentation and the 924 * Intel 7300 Chipset Memory Controller Hub (318082) datasheet 925 * which appears to be accurate for the i5100 in this area. 926 * 927 * The injection code don't work without setting this register. 928 * The register needs to be flipped off then on else the hardware 929 * will only preform the first injection. 930 * 931 * Stop condition bits 7:4 932 * 1010 - Stop after one injection 933 * 1011 - Never stop injecting faults 934 * 935 * Start condition bits 3:0 936 * 1010 - Never start 937 * 1011 - Start immediately 938 */ 939 pci_write_config_byte(priv->einj, I5100_DINJ0, 0xaa); 940 pci_write_config_byte(priv->einj, I5100_DINJ0, 0xab); 941 } 942 943 #define to_mci(k) container_of(k, struct mem_ctl_info, dev) 944 static ssize_t inject_enable_write(struct file *file, const char __user *data, 945 size_t count, loff_t *ppos) 946 { 947 struct device *dev = file->private_data; 948 struct mem_ctl_info *mci = to_mci(dev); 949 950 i5100_do_inject(mci); 951 952 return count; 953 } 954 955 static const struct file_operations i5100_inject_enable_fops = { 956 .open = simple_open, 957 .write = inject_enable_write, 958 .llseek = generic_file_llseek, 959 }; 960 961 static int i5100_setup_debugfs(struct mem_ctl_info *mci) 962 { 963 struct i5100_priv *priv = mci->pvt_info; 964 965 if (!i5100_debugfs) 966 return -ENODEV; 967 968 priv->debugfs = edac_debugfs_create_dir_at(mci->bus->name, i5100_debugfs); 969 970 if (!priv->debugfs) 971 return -ENOMEM; 972 973 edac_debugfs_create_x8("inject_channel", S_IRUGO | S_IWUSR, priv->debugfs, 974 &priv->inject_channel); 975 edac_debugfs_create_x8("inject_hlinesel", S_IRUGO | S_IWUSR, priv->debugfs, 976 &priv->inject_hlinesel); 977 edac_debugfs_create_x8("inject_deviceptr1", S_IRUGO | S_IWUSR, priv->debugfs, 978 &priv->inject_deviceptr1); 979 edac_debugfs_create_x8("inject_deviceptr2", S_IRUGO | S_IWUSR, priv->debugfs, 980 &priv->inject_deviceptr2); 981 edac_debugfs_create_x16("inject_eccmask1", S_IRUGO | S_IWUSR, priv->debugfs, 982 &priv->inject_eccmask1); 983 edac_debugfs_create_x16("inject_eccmask2", S_IRUGO | S_IWUSR, priv->debugfs, 984 &priv->inject_eccmask2); 985 edac_debugfs_create_file("inject_enable", S_IWUSR, priv->debugfs, 986 &mci->dev, &i5100_inject_enable_fops); 987 988 return 0; 989 990 } 991 992 static int i5100_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 993 { 994 int rc; 995 struct mem_ctl_info *mci; 996 struct edac_mc_layer layers[2]; 997 struct i5100_priv *priv; 998 struct pci_dev *ch0mm, *ch1mm, *einj; 999 int ret = 0; 1000 u32 dw; 1001 int ranksperch; 1002 1003 if (PCI_FUNC(pdev->devfn) != 1) 1004 return -ENODEV; 1005 1006 rc = pci_enable_device(pdev); 1007 if (rc < 0) { 1008 ret = rc; 1009 goto bail; 1010 } 1011 1012 /* ECC enabled? */ 1013 pci_read_config_dword(pdev, I5100_MC, &dw); 1014 if (!i5100_mc_errdeten(dw)) { 1015 printk(KERN_INFO "i5100_edac: ECC not enabled.\n"); 1016 ret = -ENODEV; 1017 goto bail_pdev; 1018 } 1019 1020 /* figure out how many ranks, from strapped state of 48GB_Mode input */ 1021 pci_read_config_dword(pdev, I5100_MS, &dw); 1022 ranksperch = !!(dw & (1 << 8)) * 2 + 4; 1023 1024 /* enable error reporting... */ 1025 pci_read_config_dword(pdev, I5100_EMASK_MEM, &dw); 1026 dw &= ~I5100_FERR_NF_MEM_ANY_MASK; 1027 pci_write_config_dword(pdev, I5100_EMASK_MEM, dw); 1028 1029 /* device 21, func 0, Channel 0 Memory Map, Error Flag/Mask, etc... */ 1030 ch0mm = pci_get_device_func(PCI_VENDOR_ID_INTEL, 1031 PCI_DEVICE_ID_INTEL_5100_21, 0); 1032 if (!ch0mm) { 1033 ret = -ENODEV; 1034 goto bail_pdev; 1035 } 1036 1037 rc = pci_enable_device(ch0mm); 1038 if (rc < 0) { 1039 ret = rc; 1040 goto bail_ch0; 1041 } 1042 1043 /* device 22, func 0, Channel 1 Memory Map, Error Flag/Mask, etc... */ 1044 ch1mm = pci_get_device_func(PCI_VENDOR_ID_INTEL, 1045 PCI_DEVICE_ID_INTEL_5100_22, 0); 1046 if (!ch1mm) { 1047 ret = -ENODEV; 1048 goto bail_disable_ch0; 1049 } 1050 1051 rc = pci_enable_device(ch1mm); 1052 if (rc < 0) { 1053 ret = rc; 1054 goto bail_ch1; 1055 } 1056 1057 layers[0].type = EDAC_MC_LAYER_CHANNEL; 1058 layers[0].size = 2; 1059 layers[0].is_virt_csrow = false; 1060 layers[1].type = EDAC_MC_LAYER_SLOT; 1061 layers[1].size = ranksperch; 1062 layers[1].is_virt_csrow = true; 1063 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 1064 sizeof(*priv)); 1065 if (!mci) { 1066 ret = -ENOMEM; 1067 goto bail_disable_ch1; 1068 } 1069 1070 1071 /* device 19, func 0, Error injection */ 1072 einj = pci_get_device_func(PCI_VENDOR_ID_INTEL, 1073 PCI_DEVICE_ID_INTEL_5100_19, 0); 1074 if (!einj) { 1075 ret = -ENODEV; 1076 goto bail_einj; 1077 } 1078 1079 rc = pci_enable_device(einj); 1080 if (rc < 0) { 1081 ret = rc; 1082 goto bail_disable_einj; 1083 } 1084 1085 1086 mci->pdev = &pdev->dev; 1087 1088 priv = mci->pvt_info; 1089 priv->ranksperchan = ranksperch; 1090 priv->mc = pdev; 1091 priv->ch0mm = ch0mm; 1092 priv->ch1mm = ch1mm; 1093 priv->einj = einj; 1094 1095 INIT_DELAYED_WORK(&(priv->i5100_scrubbing), i5100_refresh_scrubbing); 1096 1097 /* If scrubbing was already enabled by the bios, start maintaining it */ 1098 pci_read_config_dword(pdev, I5100_MC, &dw); 1099 if (i5100_mc_scrben(dw)) { 1100 priv->scrub_enable = 1; 1101 schedule_delayed_work(&(priv->i5100_scrubbing), 1102 I5100_SCRUB_REFRESH_RATE); 1103 } 1104 1105 i5100_init_dimm_layout(pdev, mci); 1106 i5100_init_interleaving(pdev, mci); 1107 1108 mci->mtype_cap = MEM_FLAG_FB_DDR2; 1109 mci->edac_ctl_cap = EDAC_FLAG_SECDED; 1110 mci->edac_cap = EDAC_FLAG_SECDED; 1111 mci->mod_name = "i5100_edac.c"; 1112 mci->mod_ver = "not versioned"; 1113 mci->ctl_name = "i5100"; 1114 mci->dev_name = pci_name(pdev); 1115 mci->ctl_page_to_phys = NULL; 1116 1117 mci->edac_check = i5100_check_error; 1118 mci->set_sdram_scrub_rate = i5100_set_scrub_rate; 1119 mci->get_sdram_scrub_rate = i5100_get_scrub_rate; 1120 1121 priv->inject_channel = 0; 1122 priv->inject_hlinesel = 0; 1123 priv->inject_deviceptr1 = 0; 1124 priv->inject_deviceptr2 = 0; 1125 priv->inject_eccmask1 = 0; 1126 priv->inject_eccmask2 = 0; 1127 1128 i5100_init_csrows(mci); 1129 1130 /* this strange construction seems to be in every driver, dunno why */ 1131 switch (edac_op_state) { 1132 case EDAC_OPSTATE_POLL: 1133 case EDAC_OPSTATE_NMI: 1134 break; 1135 default: 1136 edac_op_state = EDAC_OPSTATE_POLL; 1137 break; 1138 } 1139 1140 if (edac_mc_add_mc(mci)) { 1141 ret = -ENODEV; 1142 goto bail_scrub; 1143 } 1144 1145 i5100_setup_debugfs(mci); 1146 1147 return ret; 1148 1149 bail_scrub: 1150 priv->scrub_enable = 0; 1151 cancel_delayed_work_sync(&(priv->i5100_scrubbing)); 1152 edac_mc_free(mci); 1153 1154 bail_disable_einj: 1155 pci_disable_device(einj); 1156 1157 bail_einj: 1158 pci_dev_put(einj); 1159 1160 bail_disable_ch1: 1161 pci_disable_device(ch1mm); 1162 1163 bail_ch1: 1164 pci_dev_put(ch1mm); 1165 1166 bail_disable_ch0: 1167 pci_disable_device(ch0mm); 1168 1169 bail_ch0: 1170 pci_dev_put(ch0mm); 1171 1172 bail_pdev: 1173 pci_disable_device(pdev); 1174 1175 bail: 1176 return ret; 1177 } 1178 1179 static void i5100_remove_one(struct pci_dev *pdev) 1180 { 1181 struct mem_ctl_info *mci; 1182 struct i5100_priv *priv; 1183 1184 mci = edac_mc_del_mc(&pdev->dev); 1185 1186 if (!mci) 1187 return; 1188 1189 priv = mci->pvt_info; 1190 1191 edac_debugfs_remove_recursive(priv->debugfs); 1192 1193 priv->scrub_enable = 0; 1194 cancel_delayed_work_sync(&(priv->i5100_scrubbing)); 1195 1196 pci_disable_device(pdev); 1197 pci_disable_device(priv->ch0mm); 1198 pci_disable_device(priv->ch1mm); 1199 pci_disable_device(priv->einj); 1200 pci_dev_put(priv->ch0mm); 1201 pci_dev_put(priv->ch1mm); 1202 pci_dev_put(priv->einj); 1203 1204 edac_mc_free(mci); 1205 } 1206 1207 static const struct pci_device_id i5100_pci_tbl[] = { 1208 /* Device 16, Function 0, Channel 0 Memory Map, Error Flag/Mask, ... */ 1209 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5100_16) }, 1210 { 0, } 1211 }; 1212 MODULE_DEVICE_TABLE(pci, i5100_pci_tbl); 1213 1214 static struct pci_driver i5100_driver = { 1215 .name = KBUILD_BASENAME, 1216 .probe = i5100_init_one, 1217 .remove = i5100_remove_one, 1218 .id_table = i5100_pci_tbl, 1219 }; 1220 1221 static int __init i5100_init(void) 1222 { 1223 int pci_rc; 1224 1225 i5100_debugfs = edac_debugfs_create_dir_at("i5100_edac", NULL); 1226 1227 pci_rc = pci_register_driver(&i5100_driver); 1228 return (pci_rc < 0) ? pci_rc : 0; 1229 } 1230 1231 static void __exit i5100_exit(void) 1232 { 1233 edac_debugfs_remove(i5100_debugfs); 1234 1235 pci_unregister_driver(&i5100_driver); 1236 } 1237 1238 module_init(i5100_init); 1239 module_exit(i5100_exit); 1240 1241 MODULE_LICENSE("GPL"); 1242 MODULE_AUTHOR 1243 ("Arthur Jones <ajones@riverbed.com>"); 1244 MODULE_DESCRIPTION("MC Driver for Intel I5100 memory controllers"); 1245